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[mirror_edk2.git] / PcAtChipsetPkg / PcAtChipsetPkg.dec
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7b202cb0 1## @file\r
31ed75a9 2# Public definitions for PcAtChipset package.\r
3#\r
4# This package is designed to public interfaces and implementation which follows\r
5# PcAt defacto standard.\r
6#\r
6b9dd13d 7# Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>\r
e78aab9d 8# Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
015be407 9# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.<BR>\r
31ed75a9 10#\r
e1d302e5 11# SPDX-License-Identifier: BSD-2-Clause-Patent\r
31ed75a9 12#\r
7b202cb0 13##\r
31ed75a9 14\r
15[Defines]\r
16 DEC_SPECIFICATION = 0x00010005\r
17 PACKAGE_NAME = PcAtChipsetPkg\r
b414ac4d 18 PACKAGE_UNI_FILE = PcAtChipsetPkg.uni\r
31ed75a9 19 PACKAGE_GUID = B728689A-52D3-4b8c-AE89-2CE5514CC6DC\r
9325f684 20 PACKAGE_VERSION = 0.3\r
31ed75a9 21\r
986d1dfb 22[Includes]\r
23 Include\r
24\r
25[LibraryClasses]\r
26 ## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r
27 #\r
28 IoApicLib|Include/Library/IoApicLib.h\r
5a702acd 29\r
53705ed1 30[Guids]\r
31 gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r
32\r
f5f47471
RN
33#\r
34# [Error.gPcAtChipsetPkgTokenSpaceGuid]\r
35# 0x80000001 | Invalid value provided.\r
36#\r
37\r
986d1dfb 38[PcdsFeatureFlag]\r
b414ac4d
QS
39 ## Indicates the HPET Timer will be configured to use MSI interrupts if the HPET timer supports them, or use I/O APIC interrupts.<BR><BR>\r
40 # TRUE - Configures the HPET Timer to use MSI interrupts if the HPET Timer supports them.<BR>\r
41 # FALSE - Configures the HPET Timer to use I/O APIC interrupts.<BR>\r
42 # @Prompt Configure HPET to use MSI.\r
986d1dfb 43 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetMsiEnable|TRUE|BOOLEAN|0x00001000\r
b414ac4d 44\r
015be407
SM
45 ## Indicates the RTC port registers are in MMIO space, or in I/O space.\r
46 # Default is I/O space.<BR><BR>\r
47 # TRUE - RTC port registers are in MMIO space.<BR>\r
48 # FALSE - RTC port registers are in I/O space.<BR>\r
49 # @Prompt RTC port registers use MMIO.\r
50 gPcAtChipsetPkgTokenSpaceGuid.PcdRtcUseMmio|FALSE|BOOLEAN|0x00000021\r
51\r
856f592c 52[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r
986d1dfb 53 ## This PCD specifies the base address of the HPET timer.\r
b414ac4d 54 # @Prompt HPET base address.\r
986d1dfb 55 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT32|0x00000009\r
56\r
57 ## This PCD specifies the Local APIC Interrupt Vector for the HPET Timer.\r
b414ac4d 58 # @Prompt HPET local APIC vector.\r
986d1dfb 59 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r
60\r
53b1dd10 61 ## This PCD specifies the default period of the HPET Timer in 100 ns units.\r
986d1dfb 62 # The default value of 100000 100 ns units is the same as 10 ms.\r
b414ac4d 63 # @Prompt Default period of HPET timer.\r
986d1dfb 64 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r
5a702acd 65\r
b414ac4d
QS
66 ## This PCD specifies the base address of the IO APIC.\r
67 # @Prompt IO APIC base address.\r
986d1dfb 68 gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r
1e5fff63
EL
69\r
70 ## This PCD specifies the minimal valid year in RTC.\r
71 # @Prompt Minimal valid year in RTC.\r
72 gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1998|UINT16|0x0000000D\r
73\r
74 ## This PCD specifies the maximal valid year in RTC.\r
75 # @Prompt Maximal valid year in RTC.\r
f5f47471 76 # @Expression 0x80000001 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear < gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear + 100\r
fe320967 77 gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2097|UINT16|0x0000000E\r
5a702acd 78\r
015be407
SM
79 ## Specifies RTC Index Register address in MMIO space.\r
80 # @Prompt RTC Index Register address\r
81 gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister64|0x0|UINT64|0x00000022\r
82\r
83 ## Specifies RTC Target Register address in MMIO space.\r
84 # @Prompt RTC Target Register address\r
85 gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister64|0x0|UINT64|0x00000023\r
86\r
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LG
87[PcdsFixedAtBuild, PcdsPatchableInModule]\r
88 ## Defines the ACPI register set base address.\r
5a702acd 89 # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
90 # @Prompt ACPI Timer IO Port Address\r
91 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r
92\r
93 ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
94 # @Prompt ACPI Hardware PCI Bus Number\r
95 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r
96\r
97 ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
5a702acd 98 # The invalid 0xFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
99 # @Prompt ACPI Hardware PCI Device Number\r
100 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r
101\r
102 ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r
5a702acd 103 # The invalid 0xFF is as its default value. It must be configured to the real value.\r
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LG
104 # @Prompt ACPI Hardware PCI Function Number\r
105 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r
5a702acd 106\r
83d1ffb9 107 ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r
5a702acd 108 # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
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LG
109 # @Prompt ACPI Hardware PCI Register Offset\r
110 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r
5a702acd 111\r
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LG
112 ## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r
113 # @Prompt ACPI Hardware PCI Bar Enable BitMask\r
114 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r
5a702acd 115\r
83d1ffb9 116 ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r
5a702acd 117 # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r
83d1ffb9
LG
118 # @Prompt ACPI Hardware PCI Bar Register Offset\r
119 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r
120\r
121 ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.\r
122 # @Prompt Offset to 32-bit Timer register in ACPI BAR\r
123 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008|UINT16|0x00000017\r
b414ac4d 124\r
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LG
125 ## Defines the bit mask to retrieve ACPI IO Port Base Address\r
126 # @Prompt ACPI IO Port Base Address Mask\r
127 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFE|UINT16|0x00000018\r
128\r
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LG
129 ## Reset Control Register address in I/O space.\r
130 # @Prompt Reset Control Register address\r
131 gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlRegister|0x64|UINT64|0x00000019\r
132\r
133 ## 8bit Reset Control Register value for cold reset.\r
134 # @Prompt Reset Control Register value for cold reset\r
135 gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlValueColdReset|0xFE|UINT8|0x0000001A\r
136\r
e78aab9d
LD
137 ## Specifies the initial value for Register_A in RTC.\r
138 # @Prompt Initial value for Register_A in RTC.\r
139 gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x0000001B\r
140\r
141 ## Specifies the initial value for Register_B in RTC.\r
142 # @Prompt Initial value for Register_B in RTC.\r
143 gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x0000001C\r
144\r
145 ## Specifies the initial value for Register_D in RTC.\r
146 # @Prompt Initial value for Register_D in RTC.\r
147 gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0000001D\r
148\r
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RN
149 ## Specifies RTC Index Register address in I/O space.\r
150 # @Prompt RTC Index Register address\r
151 gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E\r
152\r
153 ## Specifies RTC Target Register address in I/O space.\r
154 # @Prompt RTC Target Register address\r
155 gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F\r
156\r
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RN
157 ## RTC Update Timeout Value(microsecond).\r
158 # @Prompt RTC Update Timeout Value.\r
159 gPcAtChipsetPkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|100000|UINT32|0x00000020\r
160\r
b414ac4d 161[UserExtensions.TianoCore."ExtraFiles"]\r
fe320967 162 PcAtChipsetPkgExtra.uni\r