Add generic HPET Timer DXE Driver and support libraries
[mirror_edk2.git] / PcAtChipsetPkg / PciHostBridgeDxe / PciHostBridge.h
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21b404d1 1/** @file\r
2 The Header file of the Pci Host Bridge Driver \r
3\r
cac2ab95 4 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r
95d48e82 5 This program and the accompanying materials are\r
21b404d1 6 licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9 \r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/ \r
14\r
15#ifndef _PCI_HOST_BRIDGE_H_\r
16#define _PCI_HOST_BRIDGE_H_\r
17\r
18#include <PiDxe.h>\r
19\r
20#include <IndustryStandard/Pci.h>\r
21#include <IndustryStandard/Acpi.h>\r
22\r
23#include <Protocol/PciHostBridgeResourceAllocation.h>\r
24#include <Protocol/PciRootBridgeIo.h>\r
21b404d1 25#include <Protocol/Metronome.h>\r
26#include <Protocol/DevicePath.h>\r
27\r
28\r
29#include <Library/BaseLib.h>\r
30#include <Library/DebugLib.h>\r
31#include <Library/BaseMemoryLib.h>\r
32#include <Library/MemoryAllocationLib.h>\r
33#include <Library/UefiLib.h>\r
34#include <Library/UefiBootServicesTableLib.h>\r
35#include <Library/DxeServicesTableLib.h>\r
36#include <Library/DevicePathLib.h>\r
cac2ab95 37#include <Library/IoLib.h>\r
38#include <Library/PciLib.h>\r
21b404d1 39\r
40//\r
41// Hard code the host bridge number in the platform.\r
42// In this chipset, there is only one host bridge.\r
43//\r
44#define HOST_BRIDGE_NUMBER 1\r
45\r
cac2ab95 46#define MAX_PCI_DEVICE_NUMBER 31\r
47#define MAX_PCI_FUNCTION_NUMBER 7\r
48#define MAX_PCI_REG_ADDRESS 0xFF\r
49\r
50typedef enum {\r
51 IoOperation,\r
52 MemOperation,\r
53 PciOperation\r
54} OPERATION_TYPE;\r
55\r
21b404d1 56#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r
57typedef struct {\r
58 UINTN Signature;\r
59 EFI_HANDLE HostBridgeHandle;\r
60 UINTN RootBridgeNumber;\r
61 LIST_ENTRY Head;\r
62 BOOLEAN ResourceSubmited; \r
63 BOOLEAN CanRestarted; \r
64 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r
65} PCI_HOST_BRIDGE_INSTANCE;\r
66\r
67#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
68 CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
21b404d1 69 \r
70//\r
71// HostBridge Resource Allocation interface\r
72//\r
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ED
73\r
74/**\r
75 These are the notifications from the PCI bus driver that it is about to enter a certain\r
76 phase of the PCI enumeration process.\r
77\r
78 This member function can be used to notify the host bridge driver to perform specific actions,\r
79 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r
80 Eight notification points are defined at this time. See belows:\r
81 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r
82 structures. The PCI enumerator should issue this notification\r
83 before starting a fresh enumeration process. Enumeration cannot\r
84 be restarted after sending any other notification such as\r
85 EfiPciHostBridgeBeginBusAllocation.\r
86 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r
87 required here. This notification can be used to perform any\r
88 chipset-specific programming.\r
89 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r
90 specific action is required here. This notification can be used to\r
91 perform any chipset-specific programming.\r
92 EfiPciHostBridgeBeginResourceAllocation\r
93 The resource allocation phase is about to begin. No specific\r
94 action is required here. This notification can be used to perform\r
95 any chipset-specific programming.\r
96 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r
97 root bridges. These resource settings are returned on the next call to\r
98 GetProposedResources(). Before calling NotifyPhase() with a Phase of\r
99 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r
100 for gathering I/O and memory requests for\r
101 all the PCI root bridges and submitting these requests using\r
102 SubmitResources(). This function pads the resource amount\r
103 to suit the root bridge hardware, takes care of dependencies between\r
104 the PCI root bridges, and calls the Global Coherency Domain (GCD)\r
105 with the allocation request. In the case of padding, the allocated range\r
106 could be bigger than what was requested.\r
107 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r
108 resources (proposed resources) for all the PCI root bridges. After the\r
109 hardware is programmed, reassigning resources will not be supported.\r
110 The bus settings are not affected.\r
111 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r
112 root bridges and resets the I/O and memory apertures to their initial\r
113 state. The bus settings are not affected. If the request to allocate\r
114 resources fails, the PCI enumerator can use this notification to\r
115 deallocate previous resources, adjust the requests, and retry\r
116 allocation.\r
117 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r
118 required here. This notification can be used to perform any chipsetspecific\r
119 programming.\r
120\r
121 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
122 @param[in] Phase The phase during enumeration\r
123\r
124 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r
125 is valid for a Phase of EfiPciHostBridgeAllocateResources if\r
126 SubmitResources() has not been called for one or more\r
127 PCI root bridges before this call\r
128 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r
129 for a Phase of EfiPciHostBridgeSetResources.\r
130 @retval EFI_INVALID_PARAMETER Invalid phase parameter\r
131 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
132 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r
133 previously submitted resource requests cannot be fulfilled or\r
134 were only partially fulfilled.\r
135 @retval EFI_SUCCESS The notification was accepted without any errors.\r
136\r
137**/\r
21b404d1 138EFI_STATUS\r
139EFIAPI\r
140NotifyPhase(\r
141 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
142 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
143 );\r
144\r
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ED
145/**\r
146 Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r
147\r
148 This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r
149 are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r
150 root bridges. On each call, the handle that was returned by the previous call is passed into the\r
151 interface, and on output the interface returns the device handle of the next PCI root bridge. The\r
152 caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
153 for that root bridge. When there are no more PCI root bridges to report, the interface returns\r
154 EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r
155 are returned by this function.\r
156 For D945 implementation, there is only one root bridge in PCI host bridge.\r
157\r
158 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
159 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r
160 \r
161 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r
162 specific Host bridge and return EFI_SUCCESS. \r
163 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.\r
164 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r
165 returned on a previous call to GetNextRootBridge().\r
166**/\r
21b404d1 167EFI_STATUS\r
168EFIAPI\r
169GetNextRootBridge(\r
170 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
171 IN OUT EFI_HANDLE *RootBridgeHandle\r
172 );\r
173 \r
24115e44
ED
174/**\r
175 Returns the allocation attributes of a PCI root bridge.\r
176\r
177 The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r
178 from one PCI root bridge to another. These attributes are different from the decode-related\r
179 attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r
180 RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r
181 handles of all the root bridges that are associated with this host bridge must be obtained by calling\r
182 GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r
183 after the enumeration process. The hardware may provide mechanisms to change the attributes on\r
184 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is \r
185 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r
186 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r
187 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to \r
188 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any \r
189 prefetchable memory.\r
190 Attribute Description\r
191 ------------------------------------ ----------------------------------------------------------------------\r
192 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate\r
193 windows for nonprefetchable and prefetchable memory. A PCI bus\r
194 driver needs to include requests for prefetchable memory in the\r
195 nonprefetchable memory pool.\r
196\r
197 EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory\r
198 windows. If this bit is not set, the PCI bus driver needs to include\r
199 requests for a 64-bit memory address in the corresponding 32-bit\r
200 memory pool.\r
201\r
202 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
203 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type\r
204 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
205 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter\r
206 \r
207 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r
208 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r
209 @retval EFI_SUCCESS Success to get attribute of interested root bridge.\r
210\r
211**/ \r
21b404d1 212EFI_STATUS\r
213EFIAPI\r
214GetAttributes(\r
215 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
216 IN EFI_HANDLE RootBridgeHandle,\r
217 OUT UINT64 *Attributes\r
218 );\r
219 \r
24115e44
ED
220/**\r
221 Sets up the specified PCI root bridge for the bus enumeration process.\r
222\r
223 This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r
224 over which the search should be performed in ACPI 2.0 resource descriptor format.\r
225\r
226 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
227 @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r
228 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r
229 \r
230 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r
231 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r
232 @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r
233\r
234**/\r
21b404d1 235EFI_STATUS\r
236EFIAPI\r
237StartBusEnumeration(\r
238 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
239 IN EFI_HANDLE RootBridgeHandle,\r
240 OUT VOID **Configuration\r
241 );\r
242 \r
24115e44
ED
243/**\r
244 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r
245\r
246 This member function programs the specified PCI root bridge to decode the bus range that is\r
247 specified by the input parameter Configuration.\r
248 The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r
249\r
250 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
251 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed\r
252 @param[in] Configuration The pointer to the PCI bus resource descriptor\r
253 \r
254 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
255 @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
256 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
257 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r
258 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than \r
259 bus descriptors.\r
260 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.\r
261 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r
262 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r
263 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
264 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r
265\r
266**/\r
21b404d1 267EFI_STATUS\r
268EFIAPI\r
269SetBusNumbers(\r
270 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
271 IN EFI_HANDLE RootBridgeHandle,\r
272 IN VOID *Configuration\r
273 );\r
274 \r
24115e44
ED
275/**\r
276 Submits the I/O and memory resource requirements for the specified PCI root bridge.\r
277\r
278 This function is used to submit all the I/O and memory resources that are required by the specified\r
279 PCI root bridge. The input parameter Configuration is used to specify the following:\r
280 - The various types of resources that are required\r
281 - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
282\r
283 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
284 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.\r
285 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r
286 \r
287 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.\r
288 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
289 @retval EFI_INVALID_PARAMETER Configuration is NULL.\r
290 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r
291 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are \r
292 not supported by this PCI root bridge. This error will happen if the caller \r
293 did not combine resources according to Attributes that were returned by\r
294 GetAllocAttributes().\r
295 @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r
296 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r
297 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r
298\r
299**/\r
21b404d1 300EFI_STATUS\r
301EFIAPI\r
302SubmitResources(\r
303 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
304 IN EFI_HANDLE RootBridgeHandle,\r
305 IN VOID *Configuration\r
306 );\r
307 \r
24115e44
ED
308/**\r
309 Returns the proposed resource settings for the specified PCI root bridge.\r
310\r
311 This member function returns the proposed resource settings for the specified PCI root bridge. The\r
312 proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r
313 EfiPciHostBridgeAllocateResources. The output parameter Configuration\r
314 specifies the following:\r
315 - The various types of resources, excluding bus resources, that are allocated\r
316 - The associated lengths in terms of ACPI 2.0 resource descriptor format\r
317\r
318 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
319 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r
320 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r
321 \r
322 @retval EFI_SUCCESS The requested parameters were returned.\r
323 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
324 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r
325 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
326\r
327**/\r
21b404d1 328EFI_STATUS\r
329EFIAPI\r
330GetProposedResources(\r
331 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
332 IN EFI_HANDLE RootBridgeHandle,\r
333 OUT VOID **Configuration\r
334 );\r
335\r
24115e44
ED
336/**\r
337 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r
338 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r
339 PCI controllers before enumeration.\r
340\r
341 This function is called during the PCI enumeration process. No specific action is expected from this\r
342 member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r
343 enumeration.\r
344\r
345 @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
346 @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r
347 InstallProtocolInterface() in the UEFI 2.0 Specification.\r
348 @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r
349 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r
350 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r
351 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r
352 @param Phase The phase of the PCI device enumeration. \r
353 \r
354 @retval EFI_SUCCESS The requested parameters were returned.\r
355 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r
356 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r
357 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r
358 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r
359 not enumerate this device, including its child devices if it is a PCI-to-PCI\r
360 bridge.\r
361\r
362**/\r
21b404d1 363EFI_STATUS\r
364EFIAPI\r
365PreprocessController (\r
366 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
367 IN EFI_HANDLE RootBridgeHandle,\r
368 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
369 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
370 );\r
371\r
372\r
373//\r
374// Define resource status constant \r
375//\r
376#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
377#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
378\r
379\r
380//\r
381// Driver Instance Data Prototypes\r
382//\r
383\r
384typedef struct {\r
385 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r
386 UINTN NumberOfBytes;\r
387 UINTN NumberOfPages;\r
388 EFI_PHYSICAL_ADDRESS HostAddress;\r
389 EFI_PHYSICAL_ADDRESS MappedHostAddress;\r
390} MAP_INFO;\r
391\r
392typedef struct {\r
393 ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
394 EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
395} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
396\r
397typedef struct {\r
398 UINT64 BusBase;\r
399 UINT64 BusLimit; \r
400 \r
401 UINT64 MemBase; \r
402 UINT64 MemLimit; \r
403 \r
404 UINT64 IoBase; \r
405 UINT64 IoLimit; \r
406} PCI_ROOT_BRIDGE_RESOURCE_APPETURE;\r
407\r
408typedef enum {\r
409 TypeIo = 0,\r
410 TypeMem32,\r
411 TypePMem32,\r
412 TypeMem64,\r
413 TypePMem64,\r
414 TypeBus,\r
415 TypeMax\r
416} PCI_RESOURCE_TYPE;\r
417\r
418typedef enum {\r
419 ResNone = 0,\r
420 ResSubmitted,\r
421 ResRequested,\r
422 ResAllocated,\r
423 ResStatusMax\r
424} RES_STATUS;\r
425\r
426typedef struct {\r
427 PCI_RESOURCE_TYPE Type;\r
428 UINT64 Base;\r
429 UINT64 Length;\r
430 UINT64 Alignment;\r
431 RES_STATUS Status;\r
432} PCI_RES_NODE;\r
433\r
434#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')\r
435\r
436typedef struct {\r
437 UINT32 Signature;\r
438 LIST_ENTRY Link;\r
439 EFI_HANDLE Handle;\r
440 UINT64 RootBridgeAttrib;\r
441 UINT64 Attributes;\r
442 UINT64 Supports;\r
443 \r
444 //\r
445 // Specific for this memory controller: Bus, I/O, Mem\r
446 //\r
447 PCI_RES_NODE ResAllocNode[6];\r
448 \r
449 //\r
450 // Addressing for Memory and I/O and Bus arrange\r
451 //\r
452 UINT64 BusBase;\r
453 UINT64 MemBase; \r
454 UINT64 IoBase; \r
455 UINT64 BusLimit; \r
456 UINT64 MemLimit; \r
457 UINT64 IoLimit; \r
458\r
21b404d1 459 UINTN PciAddress;\r
460 UINTN PciData;\r
461 \r
462 EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
463 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
464\r
465} PCI_ROOT_BRIDGE_INSTANCE;\r
466\r
467\r
468//\r
469// Driver Instance Data Macros\r
470//\r
471#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
472 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
473\r
474\r
475#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
476 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
477\r
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ED
478/**\r
479\r
480 Construct the Pci Root Bridge Io protocol\r
481\r
482 @param Protocol Point to protocol instance\r
483 @param HostBridgeHandle Handle of host bridge\r
484 @param Attri Attribute of host bridge\r
485 @param ResAppeture ResourceAppeture for host bridge\r
486\r
487 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
21b404d1 488\r
24115e44 489**/\r
21b404d1 490EFI_STATUS\r
491RootBridgeConstructor (\r
492 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
493 IN EFI_HANDLE HostBridgeHandle,\r
494 IN UINT64 Attri,\r
495 IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture\r
496 );\r
497\r
498#endif\r