Remove svn:executable on *.c, *.h, *.asm, *.S, *.inf and *.asl*

[mirror_edk2.git] / PcAtChipsetPkg / PciHostBridgeDxe / PciHostBridge.h

/** @file\r
  The Header file of the Pci Host Bridge Driver \r
\r
  Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
  reserved. This program and the accompanying materials are\r
  licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
  \r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/ \r
\r
#ifndef _PCI_HOST_BRIDGE_H_\r
#define _PCI_HOST_BRIDGE_H_\r
\r
#include <PiDxe.h>\r
\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
#include <Protocol/PciHostBridgeResourceAllocation.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/CpuIo2.h>\r
#include <Protocol/Metronome.h>\r
#include <Protocol/DevicePath.h>\r
\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
\r
//\r
// Hard code the host bridge number in the platform.\r
// In this chipset, there is only one host bridge.\r
//\r
#define HOST_BRIDGE_NUMBER  1\r
\r
#define PCI_HOST_BRIDGE_SIGNATURE  SIGNATURE_32('e', 'h', 's', 't')\r
typedef struct {\r
  UINTN                                             Signature;\r
  EFI_HANDLE                                        HostBridgeHandle;\r
  UINTN                                             RootBridgeNumber;\r
  LIST_ENTRY                                        Head;\r
  BOOLEAN                                           ResourceSubmited;  \r
  BOOLEAN                                           CanRestarted;  \r
  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  ResAlloc;\r
} PCI_HOST_BRIDGE_INSTANCE;\r
\r
#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r
  CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
\r
//\r
// Driver Entry Point\r
//\r
EFI_STATUS\r
EFIAPI\r
EfiMain (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  );\r
  \r
//\r
//  HostBridge Resource Allocation interface\r
//\r
EFI_STATUS\r
EFIAPI\r
NotifyPhase(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
GetNextRootBridge(\r
  IN       EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN OUT   EFI_HANDLE                                       *RootBridgeHandle\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
GetAttributes(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT UINT64                                           *Attributes\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
StartBusEnumeration(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT VOID                                             **Configuration\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
SetBusNumbers(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_HANDLE                                       RootBridgeHandle,\r
  IN VOID                                             *Configuration\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
SubmitResources(\r
  IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN EFI_HANDLE                                       RootBridgeHandle,\r
  IN VOID                                             *Configuration\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
GetProposedResources(\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
  IN  EFI_HANDLE                                       RootBridgeHandle,\r
  OUT VOID                                             **Configuration\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
PreprocessController (\r
  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *This,\r
  IN  EFI_HANDLE                                        RootBridgeHandle,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS       PciAddress,\r
  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE      Phase\r
  );\r
\r
\r
//\r
// Define resource status constant \r
//\r
#define EFI_RESOURCE_NONEXISTENT   0xFFFFFFFFFFFFFFFFULL\r
#define EFI_RESOURCE_LESS          0xFFFFFFFFFFFFFFFEULL\r
\r
\r
//\r
// Driver Instance Data Prototypes\r
//\r
\r
typedef struct {\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation;\r
  UINTN                                      NumberOfBytes;\r
  UINTN                                      NumberOfPages;\r
  EFI_PHYSICAL_ADDRESS                       HostAddress;\r
  EFI_PHYSICAL_ADDRESS                       MappedHostAddress;\r
} MAP_INFO;\r
\r
typedef struct {\r
  ACPI_HID_DEVICE_PATH              AcpiDevicePath;\r
  EFI_DEVICE_PATH_PROTOCOL          EndDevicePath;\r
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
\r
typedef struct {\r
  UINT64          BusBase;\r
  UINT64          BusLimit;     \r
  \r
  UINT64          MemBase;     \r
  UINT64          MemLimit;    \r
  \r
  UINT64          IoBase; \r
  UINT64          IoLimit;     \r
} PCI_ROOT_BRIDGE_RESOURCE_APPETURE;\r
\r
typedef enum {\r
  TypeIo = 0,\r
  TypeMem32,\r
  TypePMem32,\r
  TypeMem64,\r
  TypePMem64,\r
  TypeBus,\r
  TypeMax\r
} PCI_RESOURCE_TYPE;\r
\r
typedef enum {\r
  ResNone = 0,\r
  ResSubmitted,\r
  ResRequested,\r
  ResAllocated,\r
  ResStatusMax\r
} RES_STATUS;\r
\r
typedef struct {\r
  PCI_RESOURCE_TYPE Type;\r
  UINT64            Base;\r
  UINT64            Length;\r
  UINT64            Alignment;\r
  RES_STATUS        Status;\r
} PCI_RES_NODE;\r
\r
#define PCI_ROOT_BRIDGE_SIGNATURE  SIGNATURE_32('e', '2', 'p', 'b')\r
\r
typedef struct {\r
  UINT32                 Signature;\r
  LIST_ENTRY             Link;\r
  EFI_HANDLE             Handle;\r
  UINT64                 RootBridgeAttrib;\r
  UINT64                 Attributes;\r
  UINT64                 Supports;\r
  \r
  //\r
  // Specific for this memory controller: Bus, I/O, Mem\r
  //\r
  PCI_RES_NODE           ResAllocNode[6];\r
  \r
  //\r
  // Addressing for Memory and I/O and Bus arrange\r
  //\r
  UINT64                 BusBase;\r
  UINT64                 MemBase;     \r
  UINT64                 IoBase; \r
  UINT64                 BusLimit;     \r
  UINT64                 MemLimit;    \r
  UINT64                 IoLimit;     \r
\r
  EFI_LOCK               PciLock;\r
  UINTN                  PciAddress;\r
  UINTN                  PciData;\r
  \r
  EFI_DEVICE_PATH_PROTOCOL                *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         Io;\r
\r
} PCI_ROOT_BRIDGE_INSTANCE;\r
\r
\r
//\r
// Driver Instance Data Macros\r
//\r
#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
  CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
\r
\r
#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r
  CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
\r
\r
EFI_STATUS\r
RootBridgeConstructor (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,\r
  IN EFI_HANDLE                         HostBridgeHandle,\r
  IN UINT64                             Attri,\r
  IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE  *ResAppeture\r
  );\r
\r
#endif\r