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21b404d1 1/** @file\r
2 PCI Root Bridge Io Protocol implementation\r
3\r
3d78c020 4Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
18c97f53 5This program and the accompanying materials are\r
6licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
21b404d1 12\r
13**/ \r
14\r
15#include "PciHostBridge.h"\r
1fd376d9 16#include "IoFifo.h"\r
21b404d1 17\r
18typedef struct {\r
19 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];\r
20 EFI_ACPI_END_TAG_DESCRIPTOR EndDesp;\r
21} RESOURCE_CONFIGURATION;\r
22\r
23RESOURCE_CONFIGURATION Configuration = {\r
24 {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},\r
25 {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0}, \r
26 {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},\r
27 {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},\r
28 {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},\r
29 {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},\r
30 {0x79, 0}\r
31};\r
32\r
33//\r
34// Protocol Member Function Prototypes\r
35//\r
36\r
18c97f53 37/**\r
38 Polls an address in memory mapped I/O space until an exit condition is met, or \r
39 a timeout occurs. \r
40\r
41 This function provides a standard way to poll a PCI memory location. A PCI memory read\r
42 operation is performed at the PCI memory address specified by Address for the width specified\r
43 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
44 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
45 Mask) is equal to Value.\r
46\r
47 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
48 @param[in] Width Signifies the width of the memory operations.\r
49 @param[in] Address The base address of the memory operations. The caller is\r
50 responsible for aligning Address if required.\r
51 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
52 are ignored. The bits in the bytes below Width which are zero in\r
53 Mask are ignored when polling the memory address.\r
54 @param[in] Value The comparison value used for the polling exit criteria.\r
55 @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
56 be of poorer granularity.\r
57 @param[out] Result Pointer to the last value read from the memory location.\r
58 \r
59 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
60 @retval EFI_INVALID_PARAMETER Width is invalid.\r
61 @retval EFI_INVALID_PARAMETER Result is NULL.\r
62 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
63 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
64\r
65**/\r
21b404d1 66EFI_STATUS\r
67EFIAPI\r
68RootBridgeIoPollMem ( \r
69 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
70 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
71 IN UINT64 Address,\r
72 IN UINT64 Mask,\r
73 IN UINT64 Value,\r
74 IN UINT64 Delay,\r
75 OUT UINT64 *Result\r
76 );\r
77 \r
18c97f53 78/**\r
79 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
80 satisfied or after a defined duration.\r
81\r
82 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
83 performed at the PCI I/O address specified by Address for the width specified by Width.\r
84 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
85 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
86 to Value.\r
87\r
88 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
89 @param[in] Width Signifies the width of the I/O operations.\r
90 @param[in] Address The base address of the I/O operations. The caller is responsible\r
91 for aligning Address if required.\r
92 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
93 are ignored. The bits in the bytes below Width which are zero in\r
94 Mask are ignored when polling the I/O address.\r
95 @param[in] Value The comparison value used for the polling exit criteria.\r
96 @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
97 be of poorer granularity.\r
98 @param[out] Result Pointer to the last value read from the memory location.\r
99 \r
100 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
101 @retval EFI_INVALID_PARAMETER Width is invalid.\r
102 @retval EFI_INVALID_PARAMETER Result is NULL.\r
103 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
104 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
105\r
106**/\r
21b404d1 107EFI_STATUS\r
108EFIAPI\r
109RootBridgeIoPollIo ( \r
110 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
111 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
112 IN UINT64 Address,\r
113 IN UINT64 Mask,\r
114 IN UINT64 Value,\r
115 IN UINT64 Delay,\r
116 OUT UINT64 *Result\r
117 );\r
118 \r
18c97f53 119/**\r
120 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
121\r
122 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
123 registers in the PCI root bridge memory space.\r
124 The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
125 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
126\r
127 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
128 @param[in] Width Signifies the width of the memory operation.\r
129 @param[in] Address The base address of the memory operation. The caller is\r
130 responsible for aligning the Address if required.\r
131 @param[in] Count The number of memory operations to perform. Bytes moved is\r
132 Width size * Count, starting at Address.\r
133 @param[out] Buffer For read operations, the destination buffer to store the results. For\r
134 write operations, the source buffer to write data from.\r
135 \r
136 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
137 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
138 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
139 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
140\r
141**/\r
21b404d1 142EFI_STATUS\r
143EFIAPI\r
144RootBridgeIoMemRead (\r
145 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
146 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
147 IN UINT64 Address,\r
148 IN UINTN Count,\r
24115e44 149 OUT VOID *Buffer\r
21b404d1 150 );\r
151\r
18c97f53 152/**\r
153 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
154\r
155 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
156 registers in the PCI root bridge memory space.\r
157 The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
158 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
159\r
160 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
161 @param[in] Width Signifies the width of the memory operation.\r
162 @param[in] Address The base address of the memory operation. The caller is\r
163 responsible for aligning the Address if required.\r
164 @param[in] Count The number of memory operations to perform. Bytes moved is\r
165 Width size * Count, starting at Address.\r
24115e44 166 @param[in] Buffer For read operations, the destination buffer to store the results. For\r
18c97f53 167 write operations, the source buffer to write data from.\r
168 \r
169 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
170 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
171 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
172 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
173**/\r
21b404d1 174EFI_STATUS\r
175EFIAPI\r
176RootBridgeIoMemWrite (\r
177 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
178 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
179 IN UINT64 Address,\r
180 IN UINTN Count,\r
24115e44 181 IN VOID *Buffer\r
21b404d1 182 );\r
183\r
18c97f53 184/**\r
185 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
186\r
187 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
188 @param[in] Width Signifies the width of the memory operations.\r
24115e44 189 @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
18c97f53 190 aligning the Address if required.\r
191 @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
192 size * Count, starting at Address.\r
24115e44 193 @param[out] UserBuffer For read operations, the destination buffer to store the results. For\r
18c97f53 194 write operations, the source buffer to write data from.\r
195 \r
196 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
197 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
198 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
199 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
200\r
201**/\r
21b404d1 202EFI_STATUS\r
203EFIAPI\r
204RootBridgeIoIoRead (\r
205 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
206 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
207 IN UINT64 UserAddress,\r
208 IN UINTN Count,\r
24115e44 209 OUT VOID *UserBuffer\r
21b404d1 210 );\r
211\r
18c97f53 212/**\r
213 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
214\r
215 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
216 @param[in] Width Signifies the width of the memory operations.\r
24115e44 217 @param[in] UserAddress The base address of the I/O operation. The caller is responsible for\r
18c97f53 218 aligning the Address if required.\r
219 @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
220 size * Count, starting at Address.\r
24115e44 221 @param[in] UserBuffer For read operations, the destination buffer to store the results. For\r
18c97f53 222 write operations, the source buffer to write data from.\r
223 \r
224 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
225 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
226 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
227 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
228\r
229**/\r
21b404d1 230EFI_STATUS\r
231EFIAPI\r
232RootBridgeIoIoWrite (\r
233 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
234 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
235 IN UINT64 UserAddress,\r
236 IN UINTN Count,\r
24115e44 237 IN VOID *UserBuffer\r
21b404d1 238 );\r
239\r
18c97f53 240/**\r
241 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
242 root bridge memory space.\r
243\r
244 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
245 space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
246 operation on a memory mapped video buffer.\r
247 The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
248 any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
249\r
250 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
251 @param[in] Width Signifies the width of the memory operations.\r
252 @param[in] DestAddress The destination address of the memory operation. The caller is\r
253 responsible for aligning the DestAddress if required.\r
254 @param[in] SrcAddress The source address of the memory operation. The caller is\r
255 responsible for aligning the SrcAddress if required.\r
256 @param[in] Count The number of memory operations to perform. Bytes moved is\r
257 Width size * Count, starting at DestAddress and SrcAddress.\r
258 \r
259 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
260 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
261 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
262\r
263**/\r
21b404d1 264EFI_STATUS\r
265EFIAPI\r
266RootBridgeIoCopyMem (\r
267 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
268 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
269 IN UINT64 DestAddress,\r
270 IN UINT64 SrcAddress,\r
271 IN UINTN Count\r
272 );\r
273\r
18c97f53 274/**\r
275 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
276\r
277 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
278 registers for a PCI controller.\r
279 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
280 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
281 require.\r
282\r
283 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
284 @param[in] Width Signifies the width of the memory operations.\r
285 @param[in] Address The address within the PCI configuration space for the PCI controller.\r
286 @param[in] Count The number of PCI configuration operations to perform. Bytes\r
287 moved is Width size * Count, starting at Address.\r
288 @param[out] Buffer For read operations, the destination buffer to store the results. For\r
289 write operations, the source buffer to write data from.\r
290 \r
291 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
292 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
293 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
294 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
295\r
296**/\r
21b404d1 297EFI_STATUS\r
298EFIAPI\r
299RootBridgeIoPciRead (\r
300 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
301 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
302 IN UINT64 Address,\r
303 IN UINTN Count,\r
24115e44 304 OUT VOID *Buffer\r
21b404d1 305 );\r
306\r
18c97f53 307/**\r
308 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
309\r
310 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
311 registers for a PCI controller.\r
312 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
313 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
314 require.\r
315\r
316 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
317 @param[in] Width Signifies the width of the memory operations.\r
318 @param[in] Address The address within the PCI configuration space for the PCI controller.\r
319 @param[in] Count The number of PCI configuration operations to perform. Bytes\r
320 moved is Width size * Count, starting at Address.\r
24115e44 321 @param[in] Buffer For read operations, the destination buffer to store the results. For\r
18c97f53 322 write operations, the source buffer to write data from.\r
323 \r
324 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
325 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
326 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
327 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
328\r
329**/\r
21b404d1 330EFI_STATUS\r
331EFIAPI\r
332RootBridgeIoPciWrite (\r
333 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
334 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
335 IN UINT64 Address,\r
336 IN UINTN Count,\r
24115e44 337 IN VOID *Buffer\r
21b404d1 338 );\r
339\r
18c97f53 340/**\r
341 Provides the PCI controller-specific addresses required to access system memory from a\r
342 DMA bus master.\r
343\r
344 The Map() function provides the PCI controller specific addresses needed to access system\r
345 memory. This function is used to map system memory for PCI bus master DMA accesses.\r
346\r
347 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
348 @param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
349 @param[in] HostAddress The system memory address to map to the PCI controller.\r
24115e44 350 @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
18c97f53 351 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
352 to access the system memory's HostAddress.\r
353 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
354 \r
355 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
356 @retval EFI_INVALID_PARAMETER Operation is invalid.\r
357 @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
358 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
359 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
360 @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
361 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
362 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
363 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
364\r
365**/\r
21b404d1 366EFI_STATUS\r
367EFIAPI\r
368RootBridgeIoMap (\r
369 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
370 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
371 IN VOID *HostAddress,\r
372 IN OUT UINTN *NumberOfBytes,\r
373 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
374 OUT VOID **Mapping\r
375 );\r
376\r
18c97f53 377/**\r
378 Completes the Map() operation and releases any corresponding resources.\r
379\r
380 The Unmap() function completes the Map() operation and releases any corresponding resources.\r
381 If the operation was an EfiPciOperationBusMasterWrite or\r
382 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
383 Any resources used for the mapping are freed. \r
384\r
385 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
386 @param[in] Mapping The mapping value returned from Map().\r
387 \r
388 @retval EFI_SUCCESS The range was unmapped.\r
389 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
390 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
391\r
392**/\r
21b404d1 393EFI_STATUS\r
394EFIAPI\r
395RootBridgeIoUnmap (\r
396 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
397 IN VOID *Mapping\r
398 );\r
399\r
18c97f53 400/**\r
401 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
402 EfiPciOperationBusMasterCommonBuffer64 mapping.\r
403 \r
404 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
405 @param Type This parameter is not used and must be ignored.\r
406 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
407 @param Pages The number of pages to allocate.\r
408 @param HostAddress A pointer to store the base system memory address of the allocated range.\r
409 @param Attributes The requested bit mask of attributes for the allocated range. Only\r
410 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, \r
411 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
412 \r
413 @retval EFI_SUCCESS The requested memory pages were allocated.\r
414 @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
415 @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
416 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
417 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
418 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
419\r
420**/\r
21b404d1 421EFI_STATUS\r
422EFIAPI\r
423RootBridgeIoAllocateBuffer (\r
424 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
425 IN EFI_ALLOCATE_TYPE Type,\r
426 IN EFI_MEMORY_TYPE MemoryType,\r
427 IN UINTN Pages,\r
428 OUT VOID **HostAddress,\r
429 IN UINT64 Attributes\r
430 );\r
431\r
18c97f53 432/**\r
433 Frees memory that was allocated with AllocateBuffer().\r
434\r
435 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
436\r
437 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
438 @param Pages The number of pages to free.\r
439 @param HostAddress The base system memory address of the allocated range.\r
440 \r
441 @retval EFI_SUCCESS The requested memory pages were freed.\r
442 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
443 was not allocated with AllocateBuffer().\r
444\r
445**/\r
21b404d1 446EFI_STATUS\r
447EFIAPI\r
448RootBridgeIoFreeBuffer (\r
449 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
450 IN UINTN Pages,\r
451 OUT VOID *HostAddress\r
452 );\r
453\r
18c97f53 454/**\r
455 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
456\r
457 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
458 memory. Posted write transactions are generated by PCI bus masters when they perform write\r
459 transactions to target addresses in system memory.\r
460 This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
461 specific action must be taken to guarantee that the posted write transactions have been flushed from\r
462 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
463 a PCI read transaction from the PCI controller prior to calling Flush().\r
464\r
465 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
466 \r
467 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
468 bridge to system memory.\r
469 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
470 host bridge due to a hardware error.\r
471\r
472**/\r
21b404d1 473EFI_STATUS\r
474EFIAPI\r
475RootBridgeIoFlush (\r
476 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
477 );\r
478\r
18c97f53 479/**\r
480 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
481 attributes that a PCI root bridge is currently using. \r
482\r
483 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
484 and the mask of attributes that the PCI root bridge is currently using.\r
485\r
486 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
487 @param Supported A pointer to the mask of attributes that this PCI root bridge\r
488 supports setting with SetAttributes().\r
489 @param Attributes A pointer to the mask of attributes that this PCI root bridge is\r
490 currently using.\r
491 \r
492 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root\r
493 bridge supports is returned in Supports. If Attributes is\r
494 not NULL, then the attributes that the PCI root bridge is currently\r
495 using is returned in Attributes.\r
496 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
497\r
498**/\r
21b404d1 499EFI_STATUS\r
500EFIAPI\r
501RootBridgeIoGetAttributes (\r
502 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
503 OUT UINT64 *Supported,\r
504 OUT UINT64 *Attributes\r
505 );\r
506\r
18c97f53 507/**\r
508 Sets attributes for a resource range on a PCI root bridge.\r
509\r
510 The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
511 bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
512 granularity of setting these attributes may vary from resource type to resource type, and from\r
513 platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
514 result, this function may set the attributes specified by Attributes on a larger resource range\r
515 than the caller requested. The actual range is returned in ResourceBase and\r
516 ResourceLength. The caller is responsible for verifying that the actual range for which the\r
517 attributes were set is acceptable.\r
518\r
519 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
520 @param[in] Attributes The mask of attributes to set. If the attribute bit\r
521 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
522 MEMORY_DISABLE is set, then the resource range is specified by\r
523 ResourceBase and ResourceLength. If\r
524 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
525 MEMORY_DISABLE are not set, then ResourceBase and\r
526 ResourceLength are ignored, and may be NULL.\r
24115e44 527 @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
18c97f53 528 by the attributes specified by Attributes.\r
24115e44 529 @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
18c97f53 530 attributes specified by Attributes.\r
531 \r
532 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
533 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
534 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
535\r
536**/\r
21b404d1 537EFI_STATUS\r
538EFIAPI\r
539RootBridgeIoSetAttributes (\r
540 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
541 IN UINT64 Attributes,\r
542 IN OUT UINT64 *ResourceBase,\r
543 IN OUT UINT64 *ResourceLength \r
544 ); \r
545\r
18c97f53 546/**\r
547 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
548 resource descriptors.\r
549\r
550 There are only two resource descriptor types from the ACPI Specification that may be used to\r
551 describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
552 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
553 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
554 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
555 Address Space Descriptors followed by an End Tag.\r
556\r
557 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
558 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the\r
559 current configuration of this PCI root bridge. The storage for the\r
560 ACPI 2.0 resource descriptors is allocated by this function. The\r
561 caller must treat the return buffer as read-only data, and the buffer\r
562 must not be freed by the caller.\r
563 \r
564 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
565 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
566 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
567\r
568**/\r
21b404d1 569EFI_STATUS\r
570EFIAPI\r
571RootBridgeIoConfiguration (\r
572 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
573 OUT VOID **Resources\r
574 );\r
575\r
576//\r
cac2ab95 577// Memory Controller Pci Root Bridge Io Module Variables\r
21b404d1 578//\r
cac2ab95 579EFI_METRONOME_ARCH_PROTOCOL *mMetronome;\r
18c97f53 580\r
cac2ab95 581//\r
582// Lookup table for increment values based on transfer widths\r
583//\r
584UINT8 mInStride[] = {\r
585 1, // EfiPciWidthUint8\r
586 2, // EfiPciWidthUint16\r
587 4, // EfiPciWidthUint32\r
588 8, // EfiPciWidthUint64\r
589 0, // EfiPciWidthFifoUint8\r
590 0, // EfiPciWidthFifoUint16\r
591 0, // EfiPciWidthFifoUint32\r
592 0, // EfiPciWidthFifoUint64\r
593 1, // EfiPciWidthFillUint8\r
594 2, // EfiPciWidthFillUint16\r
595 4, // EfiPciWidthFillUint32\r
596 8 // EfiPciWidthFillUint64\r
597};\r
21b404d1 598\r
599//\r
cac2ab95 600// Lookup table for increment values based on transfer widths\r
21b404d1 601//\r
cac2ab95 602UINT8 mOutStride[] = {\r
603 1, // EfiPciWidthUint8\r
604 2, // EfiPciWidthUint16\r
605 4, // EfiPciWidthUint32\r
606 8, // EfiPciWidthUint64\r
607 1, // EfiPciWidthFifoUint8\r
608 2, // EfiPciWidthFifoUint16\r
609 4, // EfiPciWidthFifoUint32\r
610 8, // EfiPciWidthFifoUint64\r
611 0, // EfiPciWidthFillUint8\r
612 0, // EfiPciWidthFillUint16\r
613 0, // EfiPciWidthFillUint32\r
614 0 // EfiPciWidthFillUint64\r
615};\r
21b404d1 616\r
18c97f53 617/**\r
618\r
619 Construct the Pci Root Bridge Io protocol\r
620\r
621 @param Protocol Point to protocol instance\r
622 @param HostBridgeHandle Handle of host bridge\r
623 @param Attri Attribute of host bridge\r
0b7c6cd4 624 @param ResAperture ResourceAperture for host bridge\r
18c97f53 625\r
626 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
627\r
628**/\r
21b404d1 629EFI_STATUS\r
630RootBridgeConstructor (\r
631 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
632 IN EFI_HANDLE HostBridgeHandle,\r
633 IN UINT64 Attri,\r
0b7c6cd4 634 IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r
21b404d1 635 )\r
21b404d1 636{\r
637 EFI_STATUS Status;\r
638 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
639 PCI_RESOURCE_TYPE Index;\r
640\r
641 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
642\r
643 //\r
644 // The host to pci bridge, the host memory and io addresses are\r
645 // direct mapped to pci addresses, so no need translate, set bases to 0.\r
646 //\r
0b7c6cd4
LE		 647 PrivateData->MemBase = ResAperture->MemBase;\r
648 PrivateData->IoBase = ResAperture->IoBase;\r
21b404d1 649\r
650 //\r
651 // The host bridge only supports 32bit addressing for memory\r
652 // and standard IA32 16bit io\r
653 //\r
0b7c6cd4
LE		 654 PrivateData->MemLimit = ResAperture->MemLimit;\r
655 PrivateData->IoLimit = ResAperture->IoLimit;\r
21b404d1 656\r
657 //\r
0b7c6cd4 658 // Bus Aperture for this Root Bridge (Possible Range)\r
21b404d1 659 //\r
0b7c6cd4
LE		 660 PrivateData->BusBase = ResAperture->BusBase;\r
661 PrivateData->BusLimit = ResAperture->BusLimit;\r
21b404d1 662 \r
663 //\r
664 // Specific for this chipset\r
665 //\r
666 for (Index = TypeIo; Index < TypeMax; Index++) {\r
667 PrivateData->ResAllocNode[Index].Type = Index;\r
668 PrivateData->ResAllocNode[Index].Base = 0;\r
669 PrivateData->ResAllocNode[Index].Length = 0;\r
670 PrivateData->ResAllocNode[Index].Status = ResNone;\r
671 }\r
672 \r
21b404d1 673 PrivateData->PciAddress = 0xCF8;\r
674 PrivateData->PciData = 0xCFC;\r
675\r
676 PrivateData->RootBridgeAttrib = Attri;\r
677 \r
e0ee9d93 678 PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \\r
679 EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \\r
680 EFI_PCI_ATTRIBUTE_VGA_MEMORY | \\r
681 EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
682 PrivateData->Attributes = PrivateData->Supports;\r
21b404d1 683\r
684 Protocol->ParentHandle = HostBridgeHandle;\r
685 \r
686 Protocol->PollMem = RootBridgeIoPollMem;\r
687 Protocol->PollIo = RootBridgeIoPollIo;\r
688\r
689 Protocol->Mem.Read = RootBridgeIoMemRead;\r
690 Protocol->Mem.Write = RootBridgeIoMemWrite;\r
691\r
692 Protocol->Io.Read = RootBridgeIoIoRead;\r
693 Protocol->Io.Write = RootBridgeIoIoWrite;\r
694\r
695 Protocol->CopyMem = RootBridgeIoCopyMem;\r
696\r
697 Protocol->Pci.Read = RootBridgeIoPciRead;\r
698 Protocol->Pci.Write = RootBridgeIoPciWrite;\r
699\r
700 Protocol->Map = RootBridgeIoMap;\r
701 Protocol->Unmap = RootBridgeIoUnmap;\r
702\r
703 Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;\r
704 Protocol->FreeBuffer = RootBridgeIoFreeBuffer;\r
705\r
706 Protocol->Flush = RootBridgeIoFlush;\r
707\r
708 Protocol->GetAttributes = RootBridgeIoGetAttributes;\r
709 Protocol->SetAttributes = RootBridgeIoSetAttributes;\r
710\r
711 Protocol->Configuration = RootBridgeIoConfiguration;\r
712\r
713 Protocol->SegmentNumber = 0;\r
714\r
21b404d1 715 Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);\r
716 ASSERT_EFI_ERROR (Status);\r
717\r
718 return EFI_SUCCESS;\r
719}\r
720\r
cac2ab95 721/**\r
722 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r
723\r
724 The I/O operations are carried out exactly as requested. The caller is responsible \r
725 for satisfying any alignment and I/O width restrictions that a PI System on a \r
726 platform might require. For example on some platforms, width requests of \r
727 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
728 be handled by the driver.\r
729 \r
730 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
731 @param[in] OperationType I/O operation type: IO/MMIO/PCI.\r
732 @param[in] Width Signifies the width of the I/O or Memory operation.\r
733 @param[in] Address The base address of the I/O operation. \r
734 @param[in] Count The number of I/O operations to perform. The number of \r
735 bytes moved is Width size * Count, starting at Address.\r
736 @param[in] Buffer For read operations, the destination buffer to store the results.\r
737 For write operations, the source buffer from which to write data.\r
738\r
739 @retval EFI_SUCCESS The parameters for this request pass the checks.\r
740 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r
741 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
742 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r
743 @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r
744 and Count is not valid for this PI system.\r
745\r
746**/\r
747EFI_STATUS\r
748RootBridgeIoCheckParameter (\r
749 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
750 IN OPERATION_TYPE OperationType,\r
751 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
752 IN UINT64 Address,\r
753 IN UINTN Count,\r
754 IN VOID *Buffer\r
755 )\r
756{\r
757 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
758 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
759 UINT64 MaxCount;\r
760 UINT64 Base;\r
761 UINT64 Limit;\r
762\r
763 //\r
764 // Check to see if Buffer is NULL\r
765 //\r
766 if (Buffer == NULL) {\r
767 return EFI_INVALID_PARAMETER;\r
768 }\r
769\r
770 //\r
771 // Check to see if Width is in the valid range\r
772 //\r
3d78c020 773 if ((UINT32)Width >= EfiPciWidthMaximum) {\r
cac2ab95 774 return EFI_INVALID_PARAMETER;\r
775 }\r
776\r
777 //\r
778 // For FIFO type, the target address won't increase during the access,\r
779 // so treat Count as 1\r
780 //\r
781 if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
782 Count = 1;\r
783 }\r
784\r
785 //\r
786 // Check to see if Width is in the valid range for I/O Port operations\r
787 //\r
788 Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
789 if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {\r
790 ASSERT (FALSE);\r
791 return EFI_INVALID_PARAMETER;\r
792 }\r
793\r
794 //\r
795 // Check to see if Address is aligned\r
796 //\r
797 if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {\r
798 return EFI_UNSUPPORTED;\r
799 }\r
800\r
801 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
802\r
803 //\r
804 // Check to see if any address associated with this transfer exceeds the maximum \r
805 // allowed address. The maximum address implied by the parameters passed in is\r
806 // Address + Size * Count. If the following condition is met, then the transfer\r
807 // is not supported.\r
808 //\r
809 // Address + Size * Count > Limit + 1\r
810 //\r
811 // Since Limit can be the maximum integer value supported by the CPU and Count \r
812 // can also be the maximum integer value supported by the CPU, this range\r
813 // check must be adjusted to avoid all oveflow conditions.\r
814 // \r
815 // The following form of the range check is equivalent but assumes that \r
816 // Limit is of the form (2^n - 1).\r
817 //\r
818 if (OperationType == IoOperation) {\r
819 Base = PrivateData->IoBase;\r
820 Limit = PrivateData->IoLimit;\r
821 } else if (OperationType == MemOperation) {\r
822 Base = PrivateData->MemBase;\r
823 Limit = PrivateData->MemLimit;\r
824 } else {\r
825 PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
826 if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {\r
827 return EFI_INVALID_PARAMETER;\r
828 }\r
829\r
830 if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {\r
831 return EFI_INVALID_PARAMETER;\r
832 }\r
833\r
834 if (PciRbAddr->ExtendedRegister != 0) {\r
835 Address = PciRbAddr->ExtendedRegister;\r
836 } else {\r
837 Address = PciRbAddr->Register;\r
838 }\r
839 Base = 0;\r
840 Limit = MAX_PCI_REG_ADDRESS;\r
841 }\r
842\r
843 if (Address < Base) {\r
844 return EFI_INVALID_PARAMETER;\r
845 }\r
846\r
847 if (Count == 0) {\r
848 if (Address > Limit) {\r
849 return EFI_UNSUPPORTED;\r
850 }\r
851 } else { \r
852 MaxCount = RShiftU64 (Limit, Width);\r
853 if (MaxCount < (Count - 1)) {\r
854 return EFI_UNSUPPORTED;\r
855 }\r
856 if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
857 return EFI_UNSUPPORTED;\r
858 }\r
859 }\r
860\r
861 return EFI_SUCCESS;\r
862}\r
863\r
864/**\r
865 Internal help function for read and write memory space.\r
866\r
867 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
868 @param[in] Write Switch value for Read or Write.\r
869 @param[in] Width Signifies the width of the memory operations.\r
870 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
871 @param[in] Count The number of PCI configuration operations to perform. Bytes\r
872 moved is Width size * Count, starting at Address.\r
24115e44 873 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
cac2ab95 874 write operations, the source buffer to write data from.\r
875 \r
876 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
877 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
878 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
879 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
880\r
881**/\r
882EFI_STATUS\r
883RootBridgeIoMemRW (\r
884 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
885 IN BOOLEAN Write,\r
886 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
887 IN UINT64 Address,\r
888 IN UINTN Count,\r
889 IN OUT VOID *Buffer\r
890 )\r
891{\r
892 EFI_STATUS Status;\r
893 UINT8 InStride;\r
894 UINT8 OutStride;\r
895 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
896 UINT8 *Uint8Buffer;\r
897\r
898 Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);\r
899 if (EFI_ERROR (Status)) {\r
900 return Status;\r
901 }\r
902\r
903 InStride = mInStride[Width];\r
904 OutStride = mOutStride[Width];\r
905 OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
906 for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
907 if (Write) {\r
908 switch (OperationWidth) {\r
909 case EfiPciWidthUint8:\r
910 MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
911 break;\r
912 case EfiPciWidthUint16:\r
913 MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
914 break;\r
915 case EfiPciWidthUint32:\r
916 MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
917 break;\r
918 case EfiPciWidthUint64:\r
919 MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
920 break;\r
daaad270 921 default:\r
922 //\r
923 // The RootBridgeIoCheckParameter call above will ensure that this\r
924 // path is not taken.\r
925 //\r
926 ASSERT (FALSE);\r
927 break;\r
cac2ab95 928 }\r
929 } else {\r
930 switch (OperationWidth) {\r
931 case EfiPciWidthUint8:\r
932 *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
933 break;\r
934 case EfiPciWidthUint16:\r
935 *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
936 break;\r
937 case EfiPciWidthUint32:\r
938 *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
939 break;\r
940 case EfiPciWidthUint64:\r
941 *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
942 break;\r
daaad270 943 default:\r
944 //\r
945 // The RootBridgeIoCheckParameter call above will ensure that this\r
946 // path is not taken.\r
947 //\r
948 ASSERT (FALSE);\r
949 break;\r
cac2ab95 950 }\r
951 }\r
952 }\r
953 return EFI_SUCCESS; \r
954}\r
955\r
956/**\r
957 Internal help function for read and write IO space.\r
958\r
959 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
960 @param[in] Write Switch value for Read or Write.\r
961 @param[in] Width Signifies the width of the memory operations.\r
962 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
963 @param[in] Count The number of PCI configuration operations to perform. Bytes\r
964 moved is Width size * Count, starting at Address.\r
24115e44 965 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
cac2ab95 966 write operations, the source buffer to write data from.\r
967 \r
968 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
969 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
970 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
971 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
972\r
973**/\r
974EFI_STATUS\r
975RootBridgeIoIoRW (\r
976 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
977 IN BOOLEAN Write,\r
978 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
979 IN UINT64 Address,\r
980 IN UINTN Count,\r
981 IN OUT VOID *Buffer\r
982 )\r
983{\r
984 EFI_STATUS Status;\r
985 UINT8 InStride;\r
986 UINT8 OutStride;\r
987 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
988 UINT8 *Uint8Buffer;\r
989\r
990 Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);\r
991 if (EFI_ERROR (Status)) {\r
992 return Status;\r
993 }\r
994\r
995 InStride = mInStride[Width];\r
996 OutStride = mOutStride[Width];\r
997 OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
1fd376d9 998\r
999#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
1000 if (InStride == 0) {\r
1001 if (Write) {\r
1002 switch (OperationWidth) {\r
1003 case EfiPciWidthUint8:\r
1004 IoWriteFifo8 ((UINTN) Address, Count, Buffer);\r
1005 return EFI_SUCCESS;\r
1006 case EfiPciWidthUint16:\r
1007 IoWriteFifo16 ((UINTN) Address, Count, Buffer);\r
1008 return EFI_SUCCESS;\r
1009 case EfiPciWidthUint32:\r
1010 IoWriteFifo32 ((UINTN) Address, Count, Buffer);\r
1011 return EFI_SUCCESS;\r
1012 default:\r
1013 //\r
1014 // The RootBridgeIoCheckParameter call above will ensure that this\r
1015 // path is not taken.\r
1016 //\r
1017 ASSERT (FALSE);\r
1018 break;\r
1019 }\r
1020 } else {\r
1021 switch (OperationWidth) {\r
1022 case EfiPciWidthUint8:\r
1023 IoReadFifo8 ((UINTN) Address, Count, Buffer);\r
1024 return EFI_SUCCESS;\r
1025 case EfiPciWidthUint16:\r
1026 IoReadFifo16 ((UINTN) Address, Count, Buffer);\r
1027 return EFI_SUCCESS;\r
1028 case EfiPciWidthUint32:\r
1029 IoReadFifo32 ((UINTN) Address, Count, Buffer);\r
1030 return EFI_SUCCESS;\r
1031 default:\r
1032 //\r
1033 // The RootBridgeIoCheckParameter call above will ensure that this\r
1034 // path is not taken.\r
1035 //\r
1036 ASSERT (FALSE);\r
1037 break;\r
1038 }\r
1039 }\r
1040 }\r
1041#endif\r
1042\r
cac2ab95 1043 for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
1044 if (Write) {\r
1045 switch (OperationWidth) {\r
1046 case EfiPciWidthUint8:\r
1047 IoWrite8 ((UINTN)Address, *Uint8Buffer);\r
1048 break;\r
1049 case EfiPciWidthUint16:\r
1050 IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
1051 break;\r
1052 case EfiPciWidthUint32:\r
1053 IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
1054 break;\r
daaad270 1055 default:\r
1056 //\r
1057 // The RootBridgeIoCheckParameter call above will ensure that this\r
1058 // path is not taken.\r
1059 //\r
1060 ASSERT (FALSE);\r
1061 break;\r
cac2ab95 1062 }\r
1063 } else {\r
1064 switch (OperationWidth) {\r
1065 case EfiPciWidthUint8:\r
1066 *Uint8Buffer = IoRead8 ((UINTN)Address);\r
1067 break;\r
1068 case EfiPciWidthUint16:\r
1069 *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);\r
1070 break;\r
1071 case EfiPciWidthUint32:\r
1072 *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);\r
1073 break;\r
daaad270 1074 default:\r
1075 //\r
1076 // The RootBridgeIoCheckParameter call above will ensure that this\r
1077 // path is not taken.\r
1078 //\r
1079 ASSERT (FALSE);\r
1080 break;\r
cac2ab95 1081 }\r
1082 }\r
1083 }\r
1084 return EFI_SUCCESS;\r
1085}\r
1086\r
1087/**\r
1088 Internal help function for read and write PCI configuration space.\r
1089\r
1090 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1091 @param[in] Write Switch value for Read or Write.\r
1092 @param[in] Width Signifies the width of the memory operations.\r
1093 @param[in] UserAddress The address within the PCI configuration space for the PCI controller.\r
1094 @param[in] Count The number of PCI configuration operations to perform. Bytes\r
1095 moved is Width size * Count, starting at Address.\r
24115e44 1096 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
cac2ab95 1097 write operations, the source buffer to write data from.\r
1098 \r
1099 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
1100 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1101 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
1102 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1103\r
1104**/\r
1105EFI_STATUS\r
1106RootBridgeIoPciRW (\r
1107 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1108 IN BOOLEAN Write,\r
1109 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1110 IN UINT64 Address,\r
1111 IN UINTN Count,\r
1112 IN OUT VOID *Buffer\r
1113 )\r
1114{\r
1115 EFI_STATUS Status;\r
1116 UINT8 InStride;\r
1117 UINT8 OutStride;\r
1118 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;\r
1119 UINT8 *Uint8Buffer;\r
1120 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;\r
1121 UINTN PcieRegAddr;\r
1122\r
1123 Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r
1124 if (EFI_ERROR (Status)) {\r
1125 return Status;\r
1126 }\r
1127\r
1128 PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
1129\r
1130 PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (\r
1131 PciRbAddr->Bus,\r
1132 PciRbAddr->Device,\r
1133 PciRbAddr->Function,\r
1134 (PciRbAddr->ExtendedRegister != 0) ? \\r
1135 PciRbAddr->ExtendedRegister :\r
1136 PciRbAddr->Register\r
1137 );\r
1138\r
1139 InStride = mInStride[Width];\r
1140 OutStride = mOutStride[Width];\r
1141 OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
1142 for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {\r
1143 if (Write) {\r
1144 switch (OperationWidth) {\r
1145 case EfiPciWidthUint8:\r
1146 PciWrite8 (PcieRegAddr, *Uint8Buffer);\r
1147 break;\r
1148 case EfiPciWidthUint16:\r
1149 PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));\r
1150 break;\r
1151 case EfiPciWidthUint32:\r
1152 PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));\r
1153 break;\r
daaad270 1154 default:\r
1155 //\r
1156 // The RootBridgeIoCheckParameter call above will ensure that this\r
1157 // path is not taken.\r
1158 //\r
1159 ASSERT (FALSE);\r
1160 break;\r
cac2ab95 1161 }\r
1162 } else {\r
1163 switch (OperationWidth) {\r
1164 case EfiPciWidthUint8:\r
1165 *Uint8Buffer = PciRead8 (PcieRegAddr);\r
1166 break;\r
1167 case EfiPciWidthUint16:\r
1168 *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);\r
1169 break;\r
1170 case EfiPciWidthUint32:\r
1171 *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);\r
1172 break;\r
daaad270 1173 default:\r
1174 //\r
1175 // The RootBridgeIoCheckParameter call above will ensure that this\r
1176 // path is not taken.\r
1177 //\r
1178 ASSERT (FALSE);\r
1179 break;\r
cac2ab95 1180 }\r
1181 }\r
1182 }\r
1183\r
1184 return EFI_SUCCESS;\r
1185}\r
1186\r
18c97f53 1187/**\r
1188 Polls an address in memory mapped I/O space until an exit condition is met, or \r
1189 a timeout occurs. \r
1190\r
1191 This function provides a standard way to poll a PCI memory location. A PCI memory read\r
1192 operation is performed at the PCI memory address specified by Address for the width specified\r
1193 by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
1194 read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
1195 Mask) is equal to Value.\r
1196\r
1197 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1198 @param[in] Width Signifies the width of the memory operations.\r
1199 @param[in] Address The base address of the memory operations. The caller is\r
1200 responsible for aligning Address if required.\r
1201 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
1202 are ignored. The bits in the bytes below Width which are zero in\r
1203 Mask are ignored when polling the memory address.\r
1204 @param[in] Value The comparison value used for the polling exit criteria.\r
1205 @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
1206 be of poorer granularity.\r
1207 @param[out] Result Pointer to the last value read from the memory location.\r
1208 \r
1209 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
1210 @retval EFI_INVALID_PARAMETER Width is invalid.\r
1211 @retval EFI_INVALID_PARAMETER Result is NULL.\r
1212 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
1213 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1214\r
1215**/\r
21b404d1 1216EFI_STATUS\r
1217EFIAPI\r
1218RootBridgeIoPollMem ( \r
1219 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1220 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1221 IN UINT64 Address,\r
1222 IN UINT64 Mask,\r
1223 IN UINT64 Value,\r
1224 IN UINT64 Delay,\r
1225 OUT UINT64 *Result\r
1226 )\r
21b404d1 1227{\r
1228 EFI_STATUS Status;\r
1229 UINT64 NumberOfTicks;\r
1230 UINT32 Remainder;\r
1231\r
1232 if (Result == NULL) {\r
1233 return EFI_INVALID_PARAMETER;\r
1234 }\r
1235\r
3d78c020 1236 if ((UINT32)Width > EfiPciWidthUint64) {\r
21b404d1 1237 return EFI_INVALID_PARAMETER;\r
1238 }\r
1239\r
1240 //\r
1241 // No matter what, always do a single poll.\r
1242 //\r
1243 Status = This->Mem.Read (This, Width, Address, 1, Result);\r
1244 if (EFI_ERROR (Status)) {\r
1245 return Status;\r
1246 } \r
1247 if ((*Result & Mask) == Value) {\r
1248 return EFI_SUCCESS;\r
1249 }\r
1250\r
1251 if (Delay == 0) {\r
1252 return EFI_SUCCESS;\r
1253 \r
1254 } else {\r
1255\r
1256 //\r
1257 // Determine the proper # of metronome ticks to wait for polling the\r
1258 // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
1259 // The "+1" to account for the possibility of the first tick being short\r
1260 // because we started in the middle of a tick.\r
1261 //\r
1262 // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
1263 // protocol definition is updated.\r
1264 //\r
1265 NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);\r
1266 if (Remainder != 0) {\r
1267 NumberOfTicks += 1;\r
1268 }\r
1269 NumberOfTicks += 1;\r
1270 \r
24115e44 1271 while (NumberOfTicks != 0) {\r
21b404d1 1272\r
1273 mMetronome->WaitForTick (mMetronome, 1);\r
1274 \r
1275 Status = This->Mem.Read (This, Width, Address, 1, Result);\r
1276 if (EFI_ERROR (Status)) {\r
1277 return Status;\r
1278 }\r
1279 \r
1280 if ((*Result & Mask) == Value) {\r
1281 return EFI_SUCCESS;\r
1282 }\r
1283\r
1284 NumberOfTicks -= 1;\r
1285 }\r
1286 }\r
1287 return EFI_TIMEOUT;\r
1288}\r
1289 \r
18c97f53 1290/**\r
1291 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
1292 satisfied or after a defined duration.\r
1293\r
1294 This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
1295 performed at the PCI I/O address specified by Address for the width specified by Width.\r
1296 The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
1297 repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
1298 to Value.\r
1299\r
1300 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1301 @param[in] Width Signifies the width of the I/O operations.\r
1302 @param[in] Address The base address of the I/O operations. The caller is responsible\r
1303 for aligning Address if required.\r
1304 @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask\r
1305 are ignored. The bits in the bytes below Width which are zero in\r
1306 Mask are ignored when polling the I/O address.\r
1307 @param[in] Value The comparison value used for the polling exit criteria.\r
1308 @param[in] Delay The number of 100 ns units to poll. Note that timer available may\r
1309 be of poorer granularity.\r
1310 @param[out] Result Pointer to the last value read from the memory location.\r
1311 \r
1312 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
1313 @retval EFI_INVALID_PARAMETER Width is invalid.\r
1314 @retval EFI_INVALID_PARAMETER Result is NULL.\r
1315 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
1316 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1317\r
1318**/\r
21b404d1 1319EFI_STATUS\r
1320EFIAPI\r
1321RootBridgeIoPollIo ( \r
1322 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1323 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1324 IN UINT64 Address,\r
1325 IN UINT64 Mask,\r
1326 IN UINT64 Value,\r
1327 IN UINT64 Delay,\r
1328 OUT UINT64 *Result\r
1329 )\r
21b404d1 1330{\r
1331 EFI_STATUS Status;\r
1332 UINT64 NumberOfTicks;\r
1333 UINT32 Remainder;\r
1334\r
1335 //\r
1336 // No matter what, always do a single poll.\r
1337 //\r
1338\r
1339 if (Result == NULL) {\r
1340 return EFI_INVALID_PARAMETER;\r
1341 }\r
1342\r
3d78c020 1343 if ((UINT32)Width > EfiPciWidthUint64) {\r
21b404d1 1344 return EFI_INVALID_PARAMETER;\r
1345 }\r
1346 \r
1347 Status = This->Io.Read (This, Width, Address, 1, Result);\r
1348 if (EFI_ERROR (Status)) {\r
1349 return Status;\r
1350 } \r
1351 if ((*Result & Mask) == Value) {\r
1352 return EFI_SUCCESS;\r
1353 }\r
1354\r
1355 if (Delay == 0) {\r
1356 return EFI_SUCCESS;\r
1357 \r
1358 } else {\r
1359\r
1360 //\r
1361 // Determine the proper # of metronome ticks to wait for polling the\r
1362 // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
1363 // The "+1" to account for the possibility of the first tick being short\r
1364 // because we started in the middle of a tick.\r
1365 //\r
1366 NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);\r
1367 if (Remainder != 0) {\r
1368 NumberOfTicks += 1;\r
1369 }\r
1370 NumberOfTicks += 1;\r
1371 \r
24115e44 1372 while (NumberOfTicks != 0) {\r
21b404d1 1373\r
1374 mMetronome->WaitForTick (mMetronome, 1);\r
1375 \r
1376 Status = This->Io.Read (This, Width, Address, 1, Result);\r
1377 if (EFI_ERROR (Status)) {\r
1378 return Status;\r
1379 }\r
1380 \r
1381 if ((*Result & Mask) == Value) {\r
1382 return EFI_SUCCESS;\r
1383 }\r
1384\r
1385 NumberOfTicks -= 1;\r
1386 }\r
1387 }\r
1388 return EFI_TIMEOUT;\r
1389}\r
1390\r
18c97f53 1391/**\r
1392 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
1393\r
1394 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
1395 registers in the PCI root bridge memory space.\r
1396 The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
1397 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
1398\r
1399 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1400 @param[in] Width Signifies the width of the memory operation.\r
1401 @param[in] Address The base address of the memory operation. The caller is\r
1402 responsible for aligning the Address if required.\r
1403 @param[in] Count The number of memory operations to perform. Bytes moved is\r
1404 Width size * Count, starting at Address.\r
1405 @param[out] Buffer For read operations, the destination buffer to store the results. For\r
1406 write operations, the source buffer to write data from.\r
1407 \r
1408 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
1409 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1410 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
1411 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1412\r
1413**/\r
21b404d1 1414EFI_STATUS\r
1415EFIAPI\r
1416RootBridgeIoMemRead (\r
1417 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1418 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1419 IN UINT64 Address,\r
1420 IN UINTN Count,\r
24115e44 1421 OUT VOID *Buffer\r
21b404d1 1422 )\r
21b404d1 1423{\r
cac2ab95 1424 return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r
21b404d1 1425}\r
1426\r
18c97f53 1427/**\r
1428 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
1429\r
1430 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
1431 registers in the PCI root bridge memory space.\r
1432 The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
1433 any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
1434\r
1435 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1436 @param[in] Width Signifies the width of the memory operation.\r
1437 @param[in] Address The base address of the memory operation. The caller is\r
1438 responsible for aligning the Address if required.\r
1439 @param[in] Count The number of memory operations to perform. Bytes moved is\r
1440 Width size * Count, starting at Address.\r
24115e44 1441 @param[in] Buffer For read operations, the destination buffer to store the results. For\r
18c97f53 1442 write operations, the source buffer to write data from.\r
1443 \r
1444 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
1445 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1446 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
1447 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1448**/\r
21b404d1 1449EFI_STATUS\r
1450EFIAPI\r
1451RootBridgeIoMemWrite (\r
1452 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1453 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1454 IN UINT64 Address,\r
1455 IN UINTN Count,\r
24115e44 1456 IN VOID *Buffer\r
21b404d1 1457 )\r
21b404d1 1458{\r
cac2ab95 1459 return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); \r
21b404d1 1460}\r
1461\r
18c97f53 1462/**\r
1463 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
1464\r
1465 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1466 @param[in] Width Signifies the width of the memory operations.\r
1467 @param[in] Address The base address of the I/O operation. The caller is responsible for\r
1468 aligning the Address if required.\r
1469 @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
1470 size * Count, starting at Address.\r
1471 @param[out] Buffer For read operations, the destination buffer to store the results. For\r
1472 write operations, the source buffer to write data from.\r
1473 \r
1474 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
1475 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1476 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
1477 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1478\r
1479**/\r
21b404d1 1480EFI_STATUS\r
1481EFIAPI\r
1482RootBridgeIoIoRead (\r
1483 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1484 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1485 IN UINT64 Address,\r
1486 IN UINTN Count,\r
24115e44 1487 OUT VOID *Buffer\r
21b404d1 1488 )\r
21b404d1 1489{\r
cac2ab95 1490 return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); \r
21b404d1 1491}\r
1492\r
18c97f53 1493/**\r
1494 Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
1495\r
1496 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1497 @param[in] Width Signifies the width of the memory operations.\r
1498 @param[in] Address The base address of the I/O operation. The caller is responsible for\r
1499 aligning the Address if required.\r
1500 @param[in] Count The number of I/O operations to perform. Bytes moved is Width\r
1501 size * Count, starting at Address.\r
24115e44 1502 @param[in] Buffer For read operations, the destination buffer to store the results. For\r
18c97f53 1503 write operations, the source buffer to write data from.\r
1504 \r
1505 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
1506 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1507 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
1508 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1509\r
1510**/\r
21b404d1 1511EFI_STATUS\r
1512EFIAPI\r
1513RootBridgeIoIoWrite (\r
1514 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1515 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1516 IN UINT64 Address,\r
1517 IN UINTN Count,\r
24115e44 1518 IN VOID *Buffer\r
21b404d1 1519 )\r
21b404d1 1520{\r
cac2ab95 1521 return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); \r
21b404d1 1522}\r
1523\r
18c97f53 1524/**\r
1525 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
1526 root bridge memory space.\r
1527\r
1528 The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
1529 space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
1530 operation on a memory mapped video buffer.\r
1531 The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
1532 any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
1533\r
1534 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
1535 @param[in] Width Signifies the width of the memory operations.\r
1536 @param[in] DestAddress The destination address of the memory operation. The caller is\r
1537 responsible for aligning the DestAddress if required.\r
1538 @param[in] SrcAddress The source address of the memory operation. The caller is\r
1539 responsible for aligning the SrcAddress if required.\r
1540 @param[in] Count The number of memory operations to perform. Bytes moved is\r
1541 Width size * Count, starting at DestAddress and SrcAddress.\r
1542 \r
1543 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
1544 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1545 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1546\r
1547**/\r
21b404d1 1548EFI_STATUS\r
1549EFIAPI\r
1550RootBridgeIoCopyMem (\r
24115e44 1551 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
21b404d1 1552 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1553 IN UINT64 DestAddress,\r
1554 IN UINT64 SrcAddress,\r
1555 IN UINTN Count\r
1556 )\r
21b404d1 1557{\r
1558 EFI_STATUS Status;\r
1559 BOOLEAN Direction;\r
1560 UINTN Stride;\r
1561 UINTN Index;\r
1562 UINT64 Result;\r
1563\r
3d78c020 1564 if ((UINT32)Width > EfiPciWidthUint64) {\r
21b404d1 1565 return EFI_INVALID_PARAMETER;\r
1566 } \r
1567\r
1568 if (DestAddress == SrcAddress) {\r
1569 return EFI_SUCCESS;\r
1570 }\r
1571\r
1572 Stride = (UINTN)(1 << Width);\r
1573\r
1574 Direction = TRUE;\r
1575 if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
1576 Direction = FALSE;\r
1577 SrcAddress = SrcAddress + (Count-1) * Stride;\r
1578 DestAddress = DestAddress + (Count-1) * Stride;\r
1579 }\r
1580\r
1581 for (Index = 0;Index < Count;Index++) {\r
1582 Status = RootBridgeIoMemRead (\r
1583 This,\r
1584 Width,\r
1585 SrcAddress,\r
1586 1,\r
1587 &Result\r
1588 );\r
1589 if (EFI_ERROR (Status)) {\r
1590 return Status;\r
1591 }\r
1592 Status = RootBridgeIoMemWrite (\r
1593 This,\r
1594 Width,\r
1595 DestAddress,\r
1596 1,\r
1597 &Result\r
1598 );\r
1599 if (EFI_ERROR (Status)) {\r
1600 return Status;\r
1601 }\r
1602 if (Direction) {\r
1603 SrcAddress += Stride;\r
1604 DestAddress += Stride;\r
1605 } else {\r
1606 SrcAddress -= Stride;\r
1607 DestAddress -= Stride;\r
1608 }\r
1609 }\r
1610 return EFI_SUCCESS;\r
1611}\r
1612\r
18c97f53 1613/**\r
1614 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
1615\r
1616 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
1617 registers for a PCI controller.\r
1618 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
1619 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
1620 require.\r
1621\r
1622 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1623 @param[in] Width Signifies the width of the memory operations.\r
1624 @param[in] Address The address within the PCI configuration space for the PCI controller.\r
1625 @param[in] Count The number of PCI configuration operations to perform. Bytes\r
1626 moved is Width size * Count, starting at Address.\r
1627 @param[out] Buffer For read operations, the destination buffer to store the results. For\r
1628 write operations, the source buffer to write data from.\r
1629 \r
1630 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
1631 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1632 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
1633 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1634\r
1635**/\r
21b404d1 1636EFI_STATUS\r
1637EFIAPI\r
1638RootBridgeIoPciRead (\r
1639 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1640 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1641 IN UINT64 Address,\r
1642 IN UINTN Count,\r
24115e44 1643 OUT VOID *Buffer\r
21b404d1 1644 )\r
21b404d1 1645{\r
21b404d1 1646 return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
1647}\r
1648\r
18c97f53 1649/**\r
1650 Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
1651\r
1652 The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
1653 registers for a PCI controller.\r
1654 The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
1655 any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
1656 require.\r
1657\r
1658 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1659 @param[in] Width Signifies the width of the memory operations.\r
1660 @param[in] Address The address within the PCI configuration space for the PCI controller.\r
1661 @param[in] Count The number of PCI configuration operations to perform. Bytes\r
1662 moved is Width size * Count, starting at Address.\r
24115e44 1663 @param[in] Buffer For read operations, the destination buffer to store the results. For\r
18c97f53 1664 write operations, the source buffer to write data from.\r
1665 \r
1666 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
1667 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
1668 @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
1669 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1670\r
1671**/\r
21b404d1 1672EFI_STATUS\r
1673EFIAPI\r
1674RootBridgeIoPciWrite (\r
1675 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1676 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
1677 IN UINT64 Address,\r
1678 IN UINTN Count,\r
24115e44 1679 IN VOID *Buffer\r
21b404d1 1680 )\r
21b404d1 1681{\r
21b404d1 1682 return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
1683}\r
1684\r
18c97f53 1685/**\r
1686 Provides the PCI controller-specific addresses required to access system memory from a\r
1687 DMA bus master.\r
1688\r
1689 The Map() function provides the PCI controller specific addresses needed to access system\r
1690 memory. This function is used to map system memory for PCI bus master DMA accesses.\r
1691\r
1692 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1693 @param[in] Operation Indicates if the bus master is going to read or write to system memory.\r
1694 @param[in] HostAddress The system memory address to map to the PCI controller.\r
24115e44 1695 @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.\r
18c97f53 1696 @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use\r
1697 to access the system memory's HostAddress.\r
1698 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.\r
1699 \r
1700 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
1701 @retval EFI_INVALID_PARAMETER Operation is invalid.\r
1702 @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
1703 @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.\r
1704 @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.\r
1705 @retval EFI_INVALID_PARAMETER Mapping is NULL.\r
1706 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
1707 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
1708 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
1709\r
1710**/\r
21b404d1 1711EFI_STATUS\r
1712EFIAPI\r
1713RootBridgeIoMap (\r
1714 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1715 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
1716 IN VOID *HostAddress,\r
1717 IN OUT UINTN *NumberOfBytes,\r
1718 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
1719 OUT VOID **Mapping\r
1720 )\r
21b404d1 1721{\r
1722 EFI_STATUS Status;\r
1723 EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
1724 MAP_INFO *MapInfo;\r
1725\r
1726 if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
1727 return EFI_INVALID_PARAMETER;\r
1728 }\r
1729 \r
1730 //\r
1731 // Initialize the return values to their defaults\r
1732 //\r
1733 *Mapping = NULL;\r
1734\r
1735 //\r
1736 // Make sure that Operation is valid\r
1737 //\r
3d78c020 1738 if ((UINT32)Operation >= EfiPciOperationMaximum) {\r
21b404d1 1739 return EFI_INVALID_PARAMETER;\r
1740 }\r
1741\r
1742 //\r
1743 // Most PCAT like chipsets can not handle performing DMA above 4GB.\r
1744 // If any part of the DMA transfer being mapped is above 4GB, then\r
1745 // map the DMA transfer to a buffer below 4GB.\r
1746 //\r
1747 PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
1748 if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {\r
1749\r
1750 //\r
1751 // Common Buffer operations can not be remapped. If the common buffer\r
1752 // if above 4GB, then it is not possible to generate a mapping, so return \r
1753 // an error.\r
1754 //\r
1755 if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
1756 return EFI_UNSUPPORTED;\r
1757 }\r
1758\r
1759 //\r
1760 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
1761 // called later.\r
1762 //\r
1763 Status = gBS->AllocatePool (\r
1764 EfiBootServicesData, \r
1765 sizeof(MAP_INFO), \r
1766 (VOID **)&MapInfo\r
1767 );\r
1768 if (EFI_ERROR (Status)) {\r
1769 *NumberOfBytes = 0;\r
1770 return Status;\r
1771 }\r
1772\r
1773 //\r
1774 // Return a pointer to the MAP_INFO structure in Mapping\r
1775 //\r
1776 *Mapping = MapInfo;\r
1777\r
1778 //\r
1779 // Initialize the MAP_INFO structure\r
1780 //\r
1781 MapInfo->Operation = Operation;\r
1782 MapInfo->NumberOfBytes = *NumberOfBytes;\r
1783 MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES(*NumberOfBytes);\r
1784 MapInfo->HostAddress = PhysicalAddress;\r
1785 MapInfo->MappedHostAddress = 0x00000000ffffffff;\r
1786\r
1787 //\r
1788 // Allocate a buffer below 4GB to map the transfer to.\r
1789 //\r
1790 Status = gBS->AllocatePages (\r
1791 AllocateMaxAddress, \r
1792 EfiBootServicesData, \r
1793 MapInfo->NumberOfPages,\r
1794 &MapInfo->MappedHostAddress\r
1795 );\r
1796 if (EFI_ERROR (Status)) {\r
1797 gBS->FreePool (MapInfo);\r
1798 *NumberOfBytes = 0;\r
1799 return Status;\r
1800 }\r
1801\r
1802 //\r
1803 // If this is a read operation from the Bus Master's point of view,\r
1804 // then copy the contents of the real buffer into the mapped buffer\r
1805 // so the Bus Master can read the contents of the real buffer.\r
1806 //\r
1807 if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {\r
1808 CopyMem (\r
1809 (VOID *)(UINTN)MapInfo->MappedHostAddress, \r
1810 (VOID *)(UINTN)MapInfo->HostAddress,\r
1811 MapInfo->NumberOfBytes\r
1812 );\r
1813 }\r
1814\r
1815 //\r
1816 // The DeviceAddress is the address of the maped buffer below 4GB\r
1817 //\r
1818 *DeviceAddress = MapInfo->MappedHostAddress;\r
1819 } else {\r
1820 //\r
1821 // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress\r
1822 //\r
1823 *DeviceAddress = PhysicalAddress;\r
1824 }\r
1825\r
1826 return EFI_SUCCESS;\r
1827}\r
1828\r
18c97f53 1829/**\r
1830 Completes the Map() operation and releases any corresponding resources.\r
1831\r
1832 The Unmap() function completes the Map() operation and releases any corresponding resources.\r
1833 If the operation was an EfiPciOperationBusMasterWrite or\r
1834 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
1835 Any resources used for the mapping are freed. \r
1836\r
1837 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1838 @param[in] Mapping The mapping value returned from Map().\r
1839 \r
1840 @retval EFI_SUCCESS The range was unmapped.\r
1841 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
1842 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
1843\r
1844**/\r
21b404d1 1845EFI_STATUS\r
1846EFIAPI\r
1847RootBridgeIoUnmap (\r
1848 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1849 IN VOID *Mapping\r
1850 )\r
21b404d1 1851{\r
1852 MAP_INFO *MapInfo;\r
1853\r
1854 //\r
1855 // See if the Map() operation associated with this Unmap() required a mapping buffer.\r
1856 // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.\r
1857 //\r
1858 if (Mapping != NULL) {\r
1859 //\r
1860 // Get the MAP_INFO structure from Mapping\r
1861 //\r
1862 MapInfo = (MAP_INFO *)Mapping;\r
1863\r
1864 //\r
1865 // If this is a write operation from the Bus Master's point of view,\r
1866 // then copy the contents of the mapped buffer into the real buffer\r
1867 // so the processor can read the contents of the real buffer.\r
1868 //\r
1869 if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
1870 CopyMem (\r
1871 (VOID *)(UINTN)MapInfo->HostAddress, \r
1872 (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
1873 MapInfo->NumberOfBytes\r
1874 );\r
1875 }\r
1876\r
1877 //\r
1878 // Free the mapped buffer and the MAP_INFO structure.\r
1879 //\r
1880 gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
1881 gBS->FreePool (Mapping);\r
1882 }\r
1883 return EFI_SUCCESS;\r
1884}\r
1885\r
18c97f53 1886/**\r
1887 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
1888 EfiPciOperationBusMasterCommonBuffer64 mapping.\r
1889 \r
1890 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1891 @param Type This parameter is not used and must be ignored.\r
1892 @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
1893 @param Pages The number of pages to allocate.\r
1894 @param HostAddress A pointer to store the base system memory address of the allocated range.\r
1895 @param Attributes The requested bit mask of attributes for the allocated range. Only\r
1896 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, \r
1897 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
1898 \r
1899 @retval EFI_SUCCESS The requested memory pages were allocated.\r
1900 @retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
1901 @retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
1902 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
1903 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
1904 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
1905\r
1906**/\r
21b404d1 1907EFI_STATUS\r
1908EFIAPI\r
1909RootBridgeIoAllocateBuffer (\r
1910 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1911 IN EFI_ALLOCATE_TYPE Type,\r
1912 IN EFI_MEMORY_TYPE MemoryType,\r
1913 IN UINTN Pages,\r
1914 OUT VOID **HostAddress,\r
1915 IN UINT64 Attributes\r
1916 )\r
21b404d1 1917{\r
1918 EFI_STATUS Status;\r
1919 EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
1920\r
1921 //\r
1922 // Validate Attributes\r
1923 //\r
24115e44 1924 if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
21b404d1 1925 return EFI_UNSUPPORTED;\r
1926 }\r
1927\r
1928 //\r
1929 // Check for invalid inputs\r
1930 //\r
1931 if (HostAddress == NULL) {\r
1932 return EFI_INVALID_PARAMETER;\r
1933 }\r
1934 \r
1935 //\r
1936 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
1937 //\r
1938 if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {\r
1939 return EFI_INVALID_PARAMETER;\r
1940 }\r
1941\r
1942 //\r
1943 // Limit allocations to memory below 4GB\r
1944 //\r
1945 PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);\r
1946\r
1947 Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);\r
1948 if (EFI_ERROR (Status)) {\r
1949 return Status;\r
1950 }\r
1951\r
1952 *HostAddress = (VOID *)(UINTN)PhysicalAddress;\r
1953\r
1954 return EFI_SUCCESS;\r
1955}\r
1956\r
18c97f53 1957/**\r
1958 Frees memory that was allocated with AllocateBuffer().\r
1959\r
1960 The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
1961\r
1962 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1963 @param Pages The number of pages to free.\r
1964 @param HostAddress The base system memory address of the allocated range.\r
1965 \r
1966 @retval EFI_SUCCESS The requested memory pages were freed.\r
1967 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
1968 was not allocated with AllocateBuffer().\r
1969\r
1970**/\r
21b404d1 1971EFI_STATUS\r
1972EFIAPI\r
1973RootBridgeIoFreeBuffer (\r
1974 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
1975 IN UINTN Pages,\r
1976 OUT VOID *HostAddress\r
1977 )\r
21b404d1 1978{\r
1979 return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
1980}\r
1981\r
18c97f53 1982/**\r
1983 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
1984\r
1985 The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
1986 memory. Posted write transactions are generated by PCI bus masters when they perform write\r
1987 transactions to target addresses in system memory.\r
1988 This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
1989 specific action must be taken to guarantee that the posted write transactions have been flushed from\r
1990 the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
1991 a PCI read transaction from the PCI controller prior to calling Flush().\r
1992\r
1993 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
1994 \r
1995 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
1996 bridge to system memory.\r
1997 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
1998 host bridge due to a hardware error.\r
1999\r
2000**/\r
21b404d1 2001EFI_STATUS\r
2002EFIAPI\r
2003RootBridgeIoFlush (\r
2004 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
2005 )\r
21b404d1 2006{\r
2007 //\r
2008 // not supported yet\r
2009 //\r
2010 return EFI_SUCCESS;\r
2011}\r
2012\r
18c97f53 2013/**\r
2014 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
2015 attributes that a PCI root bridge is currently using. \r
2016\r
2017 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
2018 and the mask of attributes that the PCI root bridge is currently using.\r
2019\r
2020 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
2021 @param Supported A pointer to the mask of attributes that this PCI root bridge\r
2022 supports setting with SetAttributes().\r
2023 @param Attributes A pointer to the mask of attributes that this PCI root bridge is\r
2024 currently using.\r
2025 \r
2026 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root\r
2027 bridge supports is returned in Supports. If Attributes is\r
2028 not NULL, then the attributes that the PCI root bridge is currently\r
2029 using is returned in Attributes.\r
2030 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
2031\r
2032**/\r
21b404d1 2033EFI_STATUS\r
2034EFIAPI\r
2035RootBridgeIoGetAttributes (\r
2036 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
2037 OUT UINT64 *Supported,\r
2038 OUT UINT64 *Attributes\r
2039 )\r
21b404d1 2040{\r
2041 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
2042\r
2043 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
2044\r
2045 if (Attributes == NULL && Supported == NULL) {\r
2046 return EFI_INVALID_PARAMETER;\r
2047 }\r
2048\r
2049 //\r
2050 // Set the return value for Supported and Attributes\r
2051 //\r
24115e44 2052 if (Supported != NULL) {\r
21b404d1 2053 *Supported = PrivateData->Supports; \r
2054 }\r
2055\r
24115e44 2056 if (Attributes != NULL) {\r
21b404d1 2057 *Attributes = PrivateData->Attributes;\r
2058 }\r
2059 \r
2060 return EFI_SUCCESS;\r
2061}\r
2062\r
18c97f53 2063/**\r
2064 Sets attributes for a resource range on a PCI root bridge.\r
2065\r
2066 The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
2067 bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
2068 granularity of setting these attributes may vary from resource type to resource type, and from\r
2069 platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
2070 result, this function may set the attributes specified by Attributes on a larger resource range\r
2071 than the caller requested. The actual range is returned in ResourceBase and\r
2072 ResourceLength. The caller is responsible for verifying that the actual range for which the\r
2073 attributes were set is acceptable.\r
2074\r
2075 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
2076 @param[in] Attributes The mask of attributes to set. If the attribute bit\r
2077 MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
2078 MEMORY_DISABLE is set, then the resource range is specified by\r
2079 ResourceBase and ResourceLength. If\r
2080 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
2081 MEMORY_DISABLE are not set, then ResourceBase and\r
2082 ResourceLength are ignored, and may be NULL.\r
24115e44 2083 @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified\r
18c97f53 2084 by the attributes specified by Attributes.\r
24115e44 2085 @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the\r
18c97f53 2086 attributes specified by Attributes.\r
2087 \r
2088 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
2089 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
2090 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
2091\r
2092**/\r
21b404d1 2093EFI_STATUS\r
2094EFIAPI\r
2095RootBridgeIoSetAttributes (\r
2096 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
2097 IN UINT64 Attributes,\r
2098 IN OUT UINT64 *ResourceBase,\r
2099 IN OUT UINT64 *ResourceLength \r
2100 )\r
21b404d1 2101{\r
2102 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
2103 \r
2104 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
2105 \r
24115e44 2106 if (Attributes != 0) {\r
21b404d1 2107 if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
2108 return EFI_UNSUPPORTED;\r
2109 }\r
2110 }\r
2111 \r
2112 //\r
2113 // This is a generic driver for a PC-AT class system. It does not have any\r
2114 // chipset specific knowlegde, so none of the attributes can be set or \r
2115 // cleared. Any attempt to set attribute that are already set will succeed, \r
2116 // and any attempt to set an attribute that is not supported will fail.\r
2117 //\r
2118 if (Attributes & (~PrivateData->Attributes)) {\r
2119 return EFI_UNSUPPORTED;\r
2120 }\r
2121\r
2122 return EFI_SUCCESS;\r
2123}\r
2124\r
18c97f53 2125/**\r
2126 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
2127 resource descriptors.\r
2128\r
2129 There are only two resource descriptor types from the ACPI Specification that may be used to\r
2130 describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
2131 Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
2132 QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
2133 or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
2134 Address Space Descriptors followed by an End Tag.\r
2135\r
2136 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
2137 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the\r
2138 current configuration of this PCI root bridge. The storage for the\r
2139 ACPI 2.0 resource descriptors is allocated by this function. The\r
2140 caller must treat the return buffer as read-only data, and the buffer\r
2141 must not be freed by the caller.\r
2142 \r
2143 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.\r
2144 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
2145 @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
2146\r
2147**/\r
21b404d1 2148EFI_STATUS\r
2149EFIAPI\r
2150RootBridgeIoConfiguration (\r
2151 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
2152 OUT VOID **Resources\r
2153 )\r
21b404d1 2154{\r
2155 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
2156 UINTN Index;\r
2157\r
2158 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
2159 \r
2160 for (Index = 0; Index < TypeMax; Index++) {\r
2161 if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {\r
2162 Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
2163 Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;\r
2164 Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;\r
2165 } \r
2166 } \r
2167 \r
2168 *Resources = &Configuration; \r
2169 return EFI_SUCCESS;\r
2170}\r
2171\r
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