[mirror_edk2.git] / PcAtChipsetPkg / PciHostBridgeDxe / PciRootBridgeIo.c

/** @file\r
  PCI Root Bridge Io Protocol implementation\r
\r
  Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
  reserved. This program and the accompanying materials are\r
  licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
  \r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/ \r
\r
#include "PciHostBridge.h"\r
\r
typedef struct {\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     SpaceDesp[TypeMax];\r
  EFI_ACPI_END_TAG_DESCRIPTOR           EndDesp;\r
} RESOURCE_CONFIGURATION;\r
\r
RESOURCE_CONFIGURATION Configuration = {\r
  {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0}, \r
  {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},\r
  {0x79, 0}\r
};\r
\r
//\r
// Protocol Member Function Prototypes\r
//\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollMem ( \r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollIo ( \r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  );\r
  \r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 UserAddress,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *UserBuffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 UserAddress,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *UserBuffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoCopyMem (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 DestAddress,\r
  IN     UINT64                                 SrcAddress,\r
  IN     UINTN                                  Count\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMap (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoUnmap (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  VOID                             *Mapping\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoAllocateBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  EFI_ALLOCATE_TYPE                Type,\r
  IN  EFI_MEMORY_TYPE                  MemoryType,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             **HostAddress,\r
  IN  UINT64                           Attributes\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFreeBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             *HostAddress\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFlush (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoGetAttributes (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  OUT UINT64                           *Supported,\r
  OUT UINT64                           *Attributes\r
  );\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoSetAttributes (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN     UINT64                           Attributes,\r
  IN OUT UINT64                           *ResourceBase,\r
  IN OUT UINT64                           *ResourceLength \r
  ); \r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoConfiguration (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  OUT    VOID                             **Resources\r
  );\r
\r
//\r
// Sub Function Prototypes\r
//\r
EFI_STATUS\r
RootBridgeIoPciRW (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     BOOLEAN                                Write,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 UserAddress,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *UserBuffer\r
  );\r
\r
//\r
// Memory Controller Pci Root Bridge Io Module Variables\r
//\r
EFI_METRONOME_ARCH_PROTOCOL *mMetronome;\r
EFI_CPU_IO2_PROTOCOL *mCpuIo;\r
\r
EFI_STATUS\r
RootBridgeConstructor (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,\r
  IN EFI_HANDLE                         HostBridgeHandle,\r
  IN UINT64                             Attri,\r
  IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE  *ResAppeture\r
  )\r
/*++\r
\r
Routine Description:\r
\r
    Construct the Pci Root Bridge Io protocol\r
\r
Arguments:\r
\r
    Protocol - protocol to initialize\r
    \r
Returns:\r
\r
    None\r
\r
--*/\r
{\r
  EFI_STATUS                        Status;\r
  PCI_ROOT_BRIDGE_INSTANCE          *PrivateData;\r
  PCI_RESOURCE_TYPE                 Index;\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
\r
  //\r
  // The host to pci bridge, the host memory and io addresses are\r
  // direct mapped to pci addresses, so no need translate, set bases to 0.\r
  //\r
  PrivateData->MemBase = ResAppeture->MemBase;\r
  PrivateData->IoBase  = ResAppeture->IoBase;\r
\r
  //\r
  // The host bridge only supports 32bit addressing for memory\r
  // and standard IA32 16bit io\r
  //\r
  PrivateData->MemLimit = ResAppeture->MemLimit;\r
  PrivateData->IoLimit  = ResAppeture->IoLimit;\r
\r
  //\r
  // Bus Appeture for this Root Bridge (Possible Range)\r
  //\r
  PrivateData->BusBase  = ResAppeture->BusBase;\r
  PrivateData->BusLimit = ResAppeture->BusLimit;\r
  \r
  //\r
  // Specific for this chipset\r
  //\r
  for (Index = TypeIo; Index < TypeMax; Index++) {\r
    PrivateData->ResAllocNode[Index].Type      = Index;\r
    PrivateData->ResAllocNode[Index].Base      = 0;\r
    PrivateData->ResAllocNode[Index].Length    = 0;\r
    PrivateData->ResAllocNode[Index].Status    = ResNone;\r
  }\r
  \r
\r
  EfiInitializeLock (&PrivateData->PciLock, TPL_HIGH_LEVEL);\r
  PrivateData->PciAddress = 0xCF8;\r
  PrivateData->PciData    = 0xCFC;\r
\r
  PrivateData->RootBridgeAttrib = Attri;\r
  \r
  PrivateData->Attributes  = 0;\r
  PrivateData->Supports    = 0;\r
\r
  Protocol->ParentHandle   = HostBridgeHandle;\r
  \r
  Protocol->PollMem        = RootBridgeIoPollMem;\r
  Protocol->PollIo         = RootBridgeIoPollIo;\r
\r
  Protocol->Mem.Read       = RootBridgeIoMemRead;\r
  Protocol->Mem.Write      = RootBridgeIoMemWrite;\r
\r
  Protocol->Io.Read        = RootBridgeIoIoRead;\r
  Protocol->Io.Write       = RootBridgeIoIoWrite;\r
\r
  Protocol->CopyMem        = RootBridgeIoCopyMem;\r
\r
  Protocol->Pci.Read       = RootBridgeIoPciRead;\r
  Protocol->Pci.Write      = RootBridgeIoPciWrite;\r
\r
  Protocol->Map            = RootBridgeIoMap;\r
  Protocol->Unmap          = RootBridgeIoUnmap;\r
\r
  Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;\r
  Protocol->FreeBuffer     = RootBridgeIoFreeBuffer;\r
\r
  Protocol->Flush          = RootBridgeIoFlush;\r
\r
  Protocol->GetAttributes  = RootBridgeIoGetAttributes;\r
  Protocol->SetAttributes  = RootBridgeIoSetAttributes;\r
\r
  Protocol->Configuration  = RootBridgeIoConfiguration;\r
\r
  Protocol->SegmentNumber  = 0;\r
\r
  Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&mCpuIo);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollMem ( \r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  )\r
/*++\r
\r
Routine Description:\r
  Memory Poll\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  EFI_STATUS  Status;\r
  UINT64      NumberOfTicks;\r
  UINT32      Remainder;\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width < 0 || Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // No matter what, always do a single poll.\r
  //\r
  Status = This->Mem.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }    \r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
  \r
  } else {\r
\r
    //\r
    // Determine the proper # of metronome ticks to wait for polling the\r
    // location.  The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
    // The "+1" to account for the possibility of the first tick being short\r
    // because we started in the middle of a tick.\r
    //\r
    // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
    // protocol definition is updated.\r
    //\r
    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);\r
    if (Remainder != 0) {\r
      NumberOfTicks += 1;\r
    }\r
    NumberOfTicks += 1;\r
  \r
    while (NumberOfTicks) {\r
\r
      mMetronome->WaitForTick (mMetronome, 1);\r
    \r
      Status = This->Mem.Read (This, Width, Address, 1, Result);\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
    \r
      if ((*Result & Mask) == Value) {\r
        return EFI_SUCCESS;\r
      }\r
\r
      NumberOfTicks -= 1;\r
    }\r
  }\r
  return EFI_TIMEOUT;\r
}\r
  \r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollIo ( \r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  )\r
/*++\r
\r
Routine Description:\r
  Io Poll\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  EFI_STATUS  Status;\r
  UINT64      NumberOfTicks;\r
  UINT32      Remainder;\r
\r
  //\r
  // No matter what, always do a single poll.\r
  //\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width < 0 || Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  Status = This->Io.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }    \r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
  \r
  } else {\r
\r
    //\r
    // Determine the proper # of metronome ticks to wait for polling the\r
    // location.  The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
    // The "+1" to account for the possibility of the first tick being short\r
    // because we started in the middle of a tick.\r
    //\r
    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);\r
    if (Remainder != 0) {\r
      NumberOfTicks += 1;\r
    }\r
    NumberOfTicks += 1;\r
  \r
    while (NumberOfTicks) {\r
\r
      mMetronome->WaitForTick (mMetronome, 1);\r
    \r
      Status = This->Io.Read (This, Width, Address, 1, Result);\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
    \r
      if ((*Result & Mask) == Value) {\r
        return EFI_SUCCESS;\r
      }\r
\r
      NumberOfTicks -= 1;\r
    }\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  )\r
/*++\r
\r
Routine Description:\r
  Memory read\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  PCI_ROOT_BRIDGE_INSTANCE                 *PrivateData;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    OldWidth;\r
  UINTN                                    OldCount;\r
  \r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  //\r
  // Check memory access limit\r
  //\r
  if (Address < PrivateData->MemBase) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  OldWidth = Width;\r
  OldCount = Count;\r
\r
  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
    Count = 1;\r
  }\r
\r
  Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
\r
  if (Address + (((UINTN)1 << Width) * Count) - 1 > PrivateData->MemLimit) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, \r
                       Address, OldCount, Buffer);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  )\r
/*++\r
\r
Routine Description:\r
  Memory write\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  PCI_ROOT_BRIDGE_INSTANCE                    *PrivateData;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH       OldWidth;\r
  UINTN                                       OldCount;\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  //\r
  // Check memory access limit\r
  //\r
  if (Address < PrivateData->MemBase) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  OldWidth = Width;\r
  OldCount = Count;\r
  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
    Count = 1;\r
  }\r
\r
  Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
\r
  if (Address + (((UINTN)1 << Width) * Count) - 1 > PrivateData->MemLimit) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, \r
                       Address, OldCount, Buffer);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  )\r
/*++\r
\r
Routine Description:\r
  Io read\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  \r
  \r
  UINTN                                    AlignMask;\r
  PCI_ROOT_BRIDGE_INSTANCE                 *PrivateData;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH    OldWidth;\r
  UINTN                                    OldCount;\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  //AlignMask = (1 << Width) - 1;\r
  AlignMask = (1 << (Width & 0x03)) - 1;\r
\r
  //\r
  // check Io access limit\r
  //\r
  if (Address < PrivateData->IoBase) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  OldWidth = Width;\r
  OldCount = Count;\r
  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
    Count = 1;\r
  }\r
\r
  Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
  \r
  if (Address + (((UINTN)1 << Width) * Count) - 1 >= PrivateData->IoLimit) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Address & AlignMask) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, \r
                      Address, OldCount, Buffer);\r
\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoWrite (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,\r
  IN       UINT64                                  Address,\r
  IN       UINTN                                   Count,\r
  IN OUT   VOID                                    *Buffer\r
  )\r
/*++\r
\r
Routine Description:\r
  Io write\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  UINTN                                         AlignMask;\r
  PCI_ROOT_BRIDGE_INSTANCE                      *PrivateData;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH         OldWidth;\r
  UINTN                                         OldCount;\r
\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  //AlignMask = (1 << Width) - 1;\r
  AlignMask = (1 << (Width & 0x03)) - 1;\r
\r
  //\r
  // Check Io access limit\r
  //\r
  if (Address < PrivateData->IoBase) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  OldWidth = Width;\r
  OldCount = Count;\r
  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
    Count = 1;\r
  }\r
\r
  Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
  \r
  if (Address + (((UINTN)1 << Width) * Count) - 1 >= PrivateData->IoLimit) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Address & AlignMask) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, \r
                      Address, OldCount, Buffer);\r
\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoCopyMem (\r
  IN struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL      *This,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,\r
  IN UINT64                                       DestAddress,\r
  IN UINT64                                       SrcAddress,\r
  IN UINTN                                        Count\r
  )\r
/*++\r
\r
Routine Description:\r
  Memory copy\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/\r
{\r
  EFI_STATUS  Status;\r
  BOOLEAN     Direction;\r
  UINTN       Stride;\r
  UINTN       Index;\r
  UINT64      Result;\r
\r
  if (Width < 0 || Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }    \r
\r
  if (DestAddress == SrcAddress) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  Stride = (UINTN)(1 << Width);\r
\r
  Direction = TRUE;\r
  if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
    Direction   = FALSE;\r
    SrcAddress  = SrcAddress  + (Count-1) * Stride;\r
    DestAddress = DestAddress + (Count-1) * Stride;\r
  }\r
\r
  for (Index = 0;Index < Count;Index++) {\r
    Status = RootBridgeIoMemRead (\r
               This,\r
               Width,\r
               SrcAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    Status = RootBridgeIoMemWrite (\r
               This,\r
               Width,\r
               DestAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    if (Direction) {\r
      SrcAddress  += Stride;\r
      DestAddress += Stride;\r
    } else {\r
      SrcAddress  -= Stride;\r
      DestAddress -= Stride;\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciRead (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN       UINT64                                 Address,\r
  IN       UINTN                                  Count,\r
  IN OUT   VOID                                   *Buffer\r
  )\r
/*++\r
\r
Routine Description:\r
  Pci read\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  \r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  //\r
  // Read Pci configuration space\r
  //\r
  return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciWrite (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN       UINT64                                 Address,\r
  IN       UINTN                                  Count,\r
  IN OUT   VOID                                   *Buffer\r
  )\r
/*++\r
\r
Routine Description:\r
  Pci write\r
  \r
Arguments:\r
    \r
Returns:\r
\r
--*/  \r
{\r
  \r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  //\r
  // Write Pci configuration space\r
  //\r
  return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMap (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  )\r
\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  PhysicalAddress;\r
  MAP_INFO              *MapInfo;\r
\r
  if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  //\r
  // Initialize the return values to their defaults\r
  //\r
  *Mapping = NULL;\r
\r
  //\r
  // Make sure that Operation is valid\r
  //\r
  if (Operation < 0 || Operation >= EfiPciOperationMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Most PCAT like chipsets can not handle performing DMA above 4GB.\r
  // If any part of the DMA transfer being mapped is above 4GB, then\r
  // map the DMA transfer to a buffer below 4GB.\r
  //\r
  PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
  if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {\r
\r
    //\r
    // Common Buffer operations can not be remapped.  If the common buffer\r
    // if above 4GB, then it is not possible to generate a mapping, so return \r
    // an error.\r
    //\r
    if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
      return EFI_UNSUPPORTED;\r
    }\r
\r
    //\r
    // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
    // called later.\r
    //\r
    Status = gBS->AllocatePool (\r
                    EfiBootServicesData, \r
                    sizeof(MAP_INFO), \r
                    (VOID **)&MapInfo\r
                    );\r
    if (EFI_ERROR (Status)) {\r
      *NumberOfBytes = 0;\r
      return Status;\r
    }\r
\r
    //\r
    // Return a pointer to the MAP_INFO structure in Mapping\r
    //\r
    *Mapping = MapInfo;\r
\r
    //\r
    // Initialize the MAP_INFO structure\r
    //\r
    MapInfo->Operation         = Operation;\r
    MapInfo->NumberOfBytes     = *NumberOfBytes;\r
    MapInfo->NumberOfPages     = EFI_SIZE_TO_PAGES(*NumberOfBytes);\r
    MapInfo->HostAddress       = PhysicalAddress;\r
    MapInfo->MappedHostAddress = 0x00000000ffffffff;\r
\r
    //\r
    // Allocate a buffer below 4GB to map the transfer to.\r
    //\r
    Status = gBS->AllocatePages (\r
                    AllocateMaxAddress, \r
                    EfiBootServicesData, \r
                    MapInfo->NumberOfPages,\r
                    &MapInfo->MappedHostAddress\r
                    );\r
    if (EFI_ERROR (Status)) {\r
      gBS->FreePool (MapInfo);\r
      *NumberOfBytes = 0;\r
      return Status;\r
    }\r
\r
    //\r
    // If this is a read operation from the Bus Master's point of view,\r
    // then copy the contents of the real buffer into the mapped buffer\r
    // so the Bus Master can read the contents of the real buffer.\r
    //\r
    if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {\r
      CopyMem (\r
        (VOID *)(UINTN)MapInfo->MappedHostAddress, \r
        (VOID *)(UINTN)MapInfo->HostAddress,\r
        MapInfo->NumberOfBytes\r
        );\r
    }\r
\r
    //\r
    // The DeviceAddress is the address of the maped buffer below 4GB\r
    //\r
    *DeviceAddress = MapInfo->MappedHostAddress;\r
  } else {\r
    //\r
    // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress\r
    //\r
    *DeviceAddress = PhysicalAddress;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoUnmap (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN VOID                             *Mapping\r
  )\r
\r
{\r
  MAP_INFO    *MapInfo;\r
\r
  //\r
  // See if the Map() operation associated with this Unmap() required a mapping buffer.\r
  // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.\r
  //\r
  if (Mapping != NULL) {\r
    //\r
    // Get the MAP_INFO structure from Mapping\r
    //\r
    MapInfo = (MAP_INFO *)Mapping;\r
\r
    //\r
    // If this is a write operation from the Bus Master's point of view,\r
    // then copy the contents of the mapped buffer into the real buffer\r
    // so the processor can read the contents of the real buffer.\r
    //\r
    if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
      CopyMem (\r
        (VOID *)(UINTN)MapInfo->HostAddress, \r
        (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
        MapInfo->NumberOfBytes\r
        );\r
    }\r
\r
    //\r
    // Free the mapped buffer and the MAP_INFO structure.\r
    //\r
    gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
    gBS->FreePool (Mapping);\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoAllocateBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  EFI_ALLOCATE_TYPE                Type,\r
  IN  EFI_MEMORY_TYPE                  MemoryType,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             **HostAddress,\r
  IN  UINT64                           Attributes\r
  )\r
\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  PhysicalAddress;\r
\r
  //\r
  // Validate Attributes\r
  //\r
  if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Check for invalid inputs\r
  //\r
  if (HostAddress == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
 \r
  //\r
  // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
  //\r
  if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Limit allocations to memory below 4GB\r
  //\r
  PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);\r
\r
  Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  *HostAddress = (VOID *)(UINTN)PhysicalAddress;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFreeBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             *HostAddress\r
  )\r
\r
{\r
  return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFlush (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This\r
  )\r
/*++\r
\r
Routine Description:\r
\r
Arguments:\r
    \r
Returns:\r
\r
--*/\r
{\r
  //\r
  // not supported yet\r
  //\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoGetAttributes (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  OUT UINT64                           *Supported,\r
  OUT UINT64                           *Attributes\r
  )\r
/*++\r
\r
Routine Description:\r
\r
Arguments:\r
    \r
Returns:\r
\r
--*/\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  if (Attributes == NULL && Supported == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Set the return value for Supported and Attributes\r
  //\r
  if (Supported) {\r
    *Supported  = PrivateData->Supports; \r
  }\r
\r
  if (Attributes) {\r
    *Attributes = PrivateData->Attributes;\r
  }\r
  \r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoSetAttributes (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN     UINT64                           Attributes,\r
  IN OUT UINT64                           *ResourceBase,\r
  IN OUT UINT64                           *ResourceLength \r
  )\r
/*++\r
\r
Routine Description:\r
\r
Arguments:\r
    \r
Returns:\r
\r
--*/\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE            *PrivateData;\r
  \r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
  \r
  if (Attributes) {\r
    if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
      return EFI_UNSUPPORTED;\r
    }\r
  }\r
  \r
  //\r
  // This is a generic driver for a PC-AT class system.  It does not have any\r
  // chipset specific knowlegde, so none of the attributes can be set or \r
  // cleared.  Any attempt to set attribute that are already set will succeed, \r
  // and any attempt to set an attribute that is not supported will fail.\r
  //\r
  if (Attributes & (~PrivateData->Attributes)) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoConfiguration (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *This,\r
  OUT VOID                                **Resources\r
  )\r
/*++\r
\r
Routine Description:\r
\r
Arguments:\r
    \r
Returns:\r
\r
--*/\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;\r
  UINTN                                 Index;\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
  \r
  for (Index = 0; Index < TypeMax; Index++) {\r
    if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {\r
      Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
      Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;\r
      Configuration.SpaceDesp[Index].AddrLen      = PrivateData->ResAllocNode[Index].Length;\r
    }  \r
  }  \r
    \r
  *Resources = &Configuration;      \r
  return EFI_SUCCESS;\r
}\r
\r
//\r
// Internal function\r
//\r
EFI_STATUS\r
RootBridgeIoPciRW (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN BOOLEAN                                Write,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                                 UserAddress,\r
  IN UINTN                                  Count,\r
  IN OUT VOID                               *UserBuffer\r
  )\r
{\r
  PCI_CONFIG_ACCESS_CF8             Pci;\r
  PCI_CONFIG_ACCESS_CF8             PciAligned;\r
  UINT32                            InStride;\r
  UINT32                            OutStride;\r
  UINTN                             PciData;\r
  UINTN                             PciDataStride;\r
  PCI_ROOT_BRIDGE_INSTANCE     *PrivateData;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  PciAddress;\r
\r
  if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  if ((Width & 0x03) >= EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  InStride    = 1 << (Width & 0x03);\r
  OutStride   = InStride;\r
  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
    InStride = 0;\r
  }\r
\r
  if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {\r
    OutStride = 0;\r
  }\r
\r
  CopyMem (&PciAddress, &UserAddress, sizeof(UINT64));\r
\r
  if (PciAddress.ExtendedRegister > 0xFF) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  if (PciAddress.ExtendedRegister != 0) {\r
    Pci.Bits.Reg = PciAddress.ExtendedRegister & 0xFF;\r
  } else {\r
    Pci.Bits.Reg = PciAddress.Register;\r
  }\r
\r
  Pci.Bits.Func     = PciAddress.Function;\r
  Pci.Bits.Dev      = PciAddress.Device;\r
  Pci.Bits.Bus      = PciAddress.Bus;\r
  Pci.Bits.Reserved = 0;\r
  Pci.Bits.Enable   = 1;\r
\r
  //\r
  // PCI Config access are all 32-bit alligned, but by accessing the\r
  //  CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types\r
  //  are possible on PCI.\r
  //\r
  // To read a byte of PCI config space you load 0xcf8 and \r
  //  read 0xcfc, 0xcfd, 0xcfe, 0xcff\r
  //\r
  PciDataStride = Pci.Bits.Reg & 0x03;\r
\r
  while (Count) {\r
    CopyMem (&PciAligned, &Pci, sizeof (PciAligned));\r
    PciAligned.Bits.Reg &= 0xfc;\r
    PciData = (UINTN)PrivateData->PciData + PciDataStride;\r
    EfiAcquireLock(&PrivateData->PciLock);\r
    This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned);\r
    if (Write) {\r
      This->Io.Write (This, Width, PciData, 1, UserBuffer);\r
    } else {\r
      This->Io.Read (This, Width, PciData, 1, UserBuffer);\r
    }\r
    EfiReleaseLock(&PrivateData->PciLock);\r
    UserBuffer = ((UINT8 *)UserBuffer) + OutStride;\r
    PciDataStride = (PciDataStride + InStride) % 4;\r
    Pci.Bits.Reg += InStride;\r
    Count -= 1;\r
  }\r
  \r
  return EFI_SUCCESS;\r
}\r