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[mirror_edk2.git] / PerformancePkg / Library / TscTimerLib / TscTimerLib.c

/** @file\r
  A Timer Library implementation which uses the Time Stamp Counter in the processor.\r
\r
  For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);\r
    for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);\r
    for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);\r
    for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);\r
    for Intel Atom processors (family [06H], display_model [1CH]):\r
  the time-stamp counter increments at a constant rate.\r
  That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by\r
  the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may\r
  differ from the maximum qualified frequency of the processor.\r
\r
  The specific processor configuration determines the behavior. Constant TSC behavior ensures that the\r
  duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if\r
  the processor core changes frequency.  This is the architectural behavior moving forward.\r
\r