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c06ad33e | 1 | /** @file\r |
2 | A Timer Library implementation which uses the Time Stamp Counter in the processor.\r | |
3 | \r | |
4 | For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);\r | |
5 | for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);\r | |
6 | for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);\r | |
7 | for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);\r | |
8 | for Intel Atom processors (family [06H], display_model [1CH]):\r | |
9 | the time-stamp counter increments at a constant rate.\r | |
10 | That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by\r | |
11 | the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may\r | |
12 | differ from the maximum qualified frequency of the processor.\r | |
13 | \r | |
14 | The specific processor configuration determines the behavior. Constant TSC behavior ensures that the\r | |
15 | duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if\r | |
16 | the processor core changes frequency. This is the architectural behavior moving forward.\r | |
17 | \r | |
18 |