projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | Board config definitions for each of the boards supported by this platform\r | |
| 3 | package.\r | |
| 4 | \r | |
| 5 | Copyright (c) 2013 Intel Corporation.\r | |
| 6 | \r | |
| 0eb3de2e | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| b303605e MK |
8 | \r |
| 9 | \r | |
| 10 | **/\r | |
| 11 | #include "Platform.h"\r | |
| 12 | \r | |
| 13 | #ifndef __PLATFORM_BOARDS_H__\r | |
| 14 | #define __PLATFORM_BOARDS_H__\r | |
| 15 | \r | |
| 16 | //\r | |
| 17 | // Constant definition\r | |
| 18 | //\r | |
| 19 | \r | |
| 20 | //\r | |
| 21 | // Default resume well TPM reset.\r | |
| 22 | //\r | |
| 23 | #define PLATFORM_RESUMEWELL_TPM_RST_GPIO 5\r | |
| 24 | \r | |
| 25 | //\r | |
| 26 | // Basic Configs for GPIO table definitions.\r | |
| 27 | //\r | |
| 28 | #define NULL_LEGACY_GPIO_INITIALIZER {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\r | |
| 29 | #define ALL_INPUT_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}\r | |
| 30 | #define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER ALL_INPUT_LEGACY_GPIO_INITIALIZER\r | |
| 31 | #define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}\r | |
| 32 | #define KIPS_BAY_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}\r | |
| 33 | #define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}\r | |
| 34 | #define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}\r | |
| 35 | #define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}\r | |
| 36 | #define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}\r | |
| 37 | \r | |
| 38 | #define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0}\r | |
| 39 | #define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r | |
| 40 | #define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r | |
| 41 | #define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r | |
| 42 | #define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r | |
| 43 | #define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER {0x0D,0x2D,0,0,0,0,0,0}\r | |
| 44 | #define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0}\r | |
| 45 | #define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0}\r | |
| 46 | #define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r | |
| 47 | \r | |
| 48 | //\r | |
| 49 | // Legacy Gpio to be used to assert / deassert PCI express PERST# signal\r | |
| 50 | // on Galileo Gen 2 platform.\r | |
| 51 | //\r | |
| 52 | #define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0\r | |
| 53 | \r | |
| 54 | //\r | |
| 55 | // Io expander slave address.\r | |
| 56 | //\r | |
| 57 | \r | |
| 58 | //\r | |
| 59 | // On Galileo value of Jumper J2 determines slave address of io expander.\r | |
| 60 | //\r | |
| 61 | #define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5\r | |
| 62 | #define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20\r | |
| 63 | #define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21\r | |
| 64 | \r | |
| 65 | //\r | |
| 66 | // Three IO Expmanders at fixed addresses on Galileo Gen2.\r | |
| 67 | //\r | |
| 68 | #define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25\r | |
| 69 | #define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26\r | |
| 70 | #define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27\r | |
| 71 | \r | |
| 72 | //\r | |
| 73 | // Led GPIOs for flash update / recovery.\r | |
| 74 | //\r | |
| 75 | #define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1\r | |
| 76 | #define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5\r | |
| 77 | \r | |
| 78 | //\r | |
| 79 | // Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.\r | |
| 80 | //\r | |
| 81 | typedef struct {\r | |
| 82 | UINT32 CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.\r | |
| 83 | UINT32 CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.\r | |
| 84 | UINT32 CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.\r | |
| 85 | UINT32 CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.\r | |
| 86 | UINT32 CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.\r | |
| 87 | UINT32 CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.\r | |
| 88 | UINT32 CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.\r | |
| 89 | UINT32 CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.\r | |
| 90 | UINT32 CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.\r | |
| 91 | UINT32 ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.\r | |
| 92 | UINT32 ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.\r | |
| 93 | UINT32 ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.\r | |
| 94 | UINT32 ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.\r | |
| 95 | UINT32 ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.\r | |
| 96 | UINT32 ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.\r | |
| 97 | UINT32 ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.\r | |
| 98 | UINT32 ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.\r | |
| 99 | UINT32 ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.\r | |
| 100 | } BOARD_LEGACY_GPIO_CONFIG;\r | |
| 101 | \r | |
| 102 | //\r | |
| 103 | // GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.\r | |
| 104 | //\r | |
| 105 | typedef struct {\r | |
| 106 | UINT32 PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR.\r | |
| 107 | UINT32 PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR.\r | |
| 108 | UINT32 IntEn; ///< Value for IOH REG GPIO_INTEN.\r | |
| 109 | UINT32 IntMask; ///< Value for IOH REG GPIO_INTMASK.\r | |
| 110 | UINT32 IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.\r | |
| 111 | UINT32 IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY.\r | |
| 112 | UINT32 Debounce; ///< Value for IOH REG GPIO_DEBOUNCE.\r | |
| 113 | UINT32 LsSync; ///< Value for IOH REG GPIO_LS_SYNC.\r | |
| 114 | } BOARD_GPIO_CONTROLLER_CONFIG;\r | |
| 115 | \r | |
| 116 | ///\r | |
| 117 | /// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported\r | |
| 118 | /// by this platform package.\r | |
| 119 | /// Table indexed with EFI_PLATFORM_TYPE enum value.\r | |
| 120 | ///\r | |
| 121 | #define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \\r | |
| 122 | /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r | |
| 123 | NULL_LEGACY_GPIO_INITIALIZER,\\r | |
| 124 | /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r | |
| 125 | QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\\r | |
| 126 | /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r | |
| 127 | CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\\r | |
| 128 | /* EFI_PLATFORM_TYPE - KipsBay*/\\r | |
| 129 | KIPS_BAY_LEGACY_GPIO_INITIALIZER,\\r | |
| 130 | /* EFI_PLATFORM_TYPE - CrossHill*/\\r | |
| 131 | CROSS_HILL_LEGACY_GPIO_INITIALIZER,\\r | |
| 132 | /* EFI_PLATFORM_TYPE - ClantonHill*/\\r | |
| 133 | CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\\r | |
| 134 | /* EFI_PLATFORM_TYPE - Galileo*/\\r | |
| 135 | GALILEO_LEGACY_GPIO_INITIALIZER,\\r | |
| 136 | /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\\r | |
| 137 | NULL_LEGACY_GPIO_INITIALIZER,\\r | |
| 138 | /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r | |
| 139 | GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\\r | |
| 140 | \r | |
| 141 | ///\r | |
| 142 | /// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board\r | |
| 143 | /// supported by this platform package.\r | |
| 144 | /// Table indexed with EFI_PLATFORM_TYPE enum value.\r | |
| 145 | ///\r | |
| 146 | #define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \\r | |
| 147 | /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r | |
| 148 | NULL_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 149 | /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r | |
| 150 | QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 151 | /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r | |
| 152 | CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 153 | /* EFI_PLATFORM_TYPE - KipsBay*/\\r | |
| 154 | KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 155 | /* EFI_PLATFORM_TYPE - CrossHill*/\\r | |
| 156 | CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 157 | /* EFI_PLATFORM_TYPE - ClantonHill*/\\r | |
| 158 | CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 159 | /* EFI_PLATFORM_TYPE - Galileo*/\\r | |
| 160 | GALILEO_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 161 | /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\\r | |
| 162 | NULL_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 163 | /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r | |
| 164 | GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\\r | |
| 165 | \r | |
| 166 | #endif\r |