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QuarkPlatformPkg: Add new package for Galileo boards
[mirror_edk2.git] / QuarkPlatformPkg / Library / PlatformHelperLib / PlatformHelperLib.c
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b303605e
MK		 1/** @file\r
2Helper routines with common PEI / DXE implementation.\r
3\r
4Copyright (c) 2013-2015 Intel Corporation.\r
5\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "CommonHeader.h"\r
17\r
18CHAR16 *mPlatTypeNameTable[] = { EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION };\r
19UINTN mPlatTypeNameTableLen = ((sizeof(mPlatTypeNameTable)) / sizeof (CHAR16 *));\r
20\r
21//\r
22// Routines defined in other source modules of this component.\r
23//\r
24\r
25//\r
26// Routines local to this source module.\r
27//\r
28\r
29//\r
30// Routines shared with other souce modules in this component.\r
31//\r
32\r
33EFI_STATUS\r
34WriteFirstFreeSpiProtect (\r
35 IN CONST UINT32 PchRootComplexBar,\r
36 IN CONST UINT32 DirectValue,\r
37 IN CONST UINT32 BaseAddress,\r
38 IN CONST UINT32 Length,\r
39 OUT UINT32 *OffsetPtr\r
40 )\r
41{\r
42 UINT32 RegVal;\r
43 UINT32 Offset;\r
44 UINT32 StepLen;\r
45\r
46 ASSERT (PchRootComplexBar > 0);\r
47\r
48 Offset = 0;\r
49 if (OffsetPtr != NULL) {\r
50 *OffsetPtr = Offset;\r
51 }\r
52 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) == 0) {\r
53 Offset = R_QNC_RCRB_SPIPBR0;\r
54 } else {\r
55 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1) == 0) {\r
56 Offset = R_QNC_RCRB_SPIPBR1;\r
57 } else {\r
58 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2) == 0) {\r
59 Offset = R_QNC_RCRB_SPIPBR2;\r
60 }\r
61 }\r
62 }\r
63 if (Offset != 0) {\r
64 if (DirectValue == 0) {\r
65 StepLen = ALIGN_VALUE (Length,SIZE_4KB); // Bring up to 4K boundary.\r
66 RegVal = BaseAddress + StepLen - 1;\r
67 RegVal &= 0x00FFF000; // Set EDS Protected Range Limit (PRL).\r
68 RegVal |= ((BaseAddress >> 12) & 0xfff); // or in EDS Protected Range Base (PRB).\r
69 } else {\r
70 RegVal = DirectValue;\r
71 }\r
72 //\r
73 // Enable protection.\r
74 //\r
75 RegVal |= B_QNC_RCRB_SPIPBRn_WPE;\r
76 MmioWrite32 (PchRootComplexBar + Offset, RegVal);\r
77 if (RegVal == MmioRead32 (PchRootComplexBar + Offset)) {\r
78 if (OffsetPtr != NULL) {\r
79 *OffsetPtr = Offset;\r
80 }\r
81 return EFI_SUCCESS;\r
82 }\r
83 return EFI_DEVICE_ERROR;\r
84 }\r
85 return EFI_NOT_FOUND;\r
86}\r
87\r
88//\r
89// Routines exported by this component.\r
90//\r
91\r
92/**\r
93 Read 8bit character from debug stream.\r
94\r
95 Block until character is read.\r
96\r
97 @return 8bit character read from debug stream.\r
98\r
99**/\r
100CHAR8\r
101EFIAPI\r
102PlatformDebugPortGetChar8 (\r
103 VOID\r
104 )\r
105{\r
106 CHAR8 Got;\r
107\r
108 do {\r
109 if (SerialPortPoll ()) {\r
110 if (SerialPortRead ((UINT8 *) &Got, 1) == 1) {\r
111 break;\r
112 }\r
113 }\r
114 } while (TRUE);\r
115\r
116 return Got;\r
117}\r
118\r
119/**\r
120 Clear SPI Protect registers.\r
121\r
122 @retval EFI_SUCCESS SPI protect registers cleared.\r
123 @retval EFI_ACCESS_DENIED Unable to clear SPI protect registers.\r
124**/\r
125\r
126EFI_STATUS\r
127EFIAPI\r
128PlatformClearSpiProtect (\r
129 VOID\r
130 )\r
131{\r
132 UINT32 PchRootComplexBar;\r
133\r
134 PchRootComplexBar = QNC_RCRB_BASE;\r
135 //\r
136 // Check if the SPI interface has been locked-down.\r
137 //\r
138 if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {\r
139 return EFI_ACCESS_DENIED;\r
140 }\r
141 MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0, 0);\r
142 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {\r
143 return EFI_ACCESS_DENIED;\r
144 }\r
145 MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1, 0);\r
146 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {\r
147 return EFI_ACCESS_DENIED;\r
148 }\r
149 MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2, 0);\r
150 if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {\r
151 return EFI_ACCESS_DENIED;\r
152 }\r
153 return EFI_SUCCESS;\r
154}\r
155\r
156/**\r
157 Determine if an SPI address range is protected.\r
158\r
159 @param SpiBaseAddress Base of SPI range.\r
160 @param Length Length of SPI range.\r
161\r
162 @retval TRUE Range is protected.\r
163 @retval FALSE Range is not protected.\r
164**/\r
165BOOLEAN\r
166EFIAPI\r
167PlatformIsSpiRangeProtected (\r
168 IN CONST UINT32 SpiBaseAddress,\r
169 IN CONST UINT32 Length\r
170 )\r
171{\r
172 UINT32 RegVal;\r
173 UINT32 Offset;\r
174 UINT32 Limit;\r
175 UINT32 ProtectedBase;\r
176 UINT32 ProtectedLimit;\r
177 UINT32 PchRootComplexBar;\r
178\r
179 PchRootComplexBar = QNC_RCRB_BASE;\r
180\r
181 if (Length > 0) {\r
182 Offset = R_QNC_RCRB_SPIPBR0;\r
183 Limit = SpiBaseAddress + (Length - 1);\r
184 do {\r
185 RegVal = MmioRead32 (PchRootComplexBar + Offset);\r
186 if ((RegVal & B_QNC_RCRB_SPIPBRn_WPE) != 0) {\r
187 ProtectedBase = (RegVal & 0xfff) << 12;\r
188 ProtectedLimit = (RegVal & 0x00fff000) + 0xfff;\r
189 if (SpiBaseAddress >= ProtectedBase && Limit <= ProtectedLimit) {\r
190 return TRUE;\r
191 }\r
192 }\r
193 if (Offset == R_QNC_RCRB_SPIPBR0) {\r
194 Offset = R_QNC_RCRB_SPIPBR1;\r
195 } else if (Offset == R_QNC_RCRB_SPIPBR1) {\r
196 Offset = R_QNC_RCRB_SPIPBR2;\r
197 } else {\r
198 break;\r
199 }\r
200 } while (TRUE);\r
201 }\r
202 return FALSE;\r
203}\r
204\r
205/**\r
206 Set Legacy GPIO Level\r
207\r
208 @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
209 @param GpioNum GPIO bit to change.\r
210 @param HighLevel If TRUE set GPIO High else Set GPIO low.\r
211\r
212**/\r
213VOID\r
214EFIAPI\r
215PlatformLegacyGpioSetLevel (\r
216 IN CONST UINT32 LevelRegOffset,\r
217 IN CONST UINT32 GpioNum,\r
218 IN CONST BOOLEAN HighLevel\r
219 )\r
220{\r
221 UINT32 RegValue;\r
222 UINT32 GpioBaseAddress;\r
223 UINT32 GpioNumMask;\r
224\r
225 GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r
226 ASSERT (GpioBaseAddress > 0);\r
227\r
228 RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);\r
229 GpioNumMask = (1 << GpioNum);\r
230 if (HighLevel) {\r
231 RegValue |= (GpioNumMask);\r
232 } else {\r
233 RegValue &= ~(GpioNumMask);\r
234 }\r
235 IoWrite32 (GpioBaseAddress + LevelRegOffset, RegValue);\r
236}\r
237\r
238/**\r
239 Get Legacy GPIO Level\r
240\r
241 @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
242 @param GpioNum GPIO bit to check.\r
243\r
244 @retval TRUE If bit is SET.\r
245 @retval FALSE If bit is CLEAR.\r
246\r
247**/\r
248BOOLEAN\r
249EFIAPI\r
250PlatformLegacyGpioGetLevel (\r
251 IN CONST UINT32 LevelRegOffset,\r
252 IN CONST UINT32 GpioNum\r
253 )\r
254{\r
255 UINT32 RegValue;\r
256 UINT32 GpioBaseAddress;\r
257 UINT32 GpioNumMask;\r
258\r
259 GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r
260 RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);\r
261 GpioNumMask = (1 << GpioNum);\r
262 return ((RegValue & GpioNumMask) != 0);\r
263}\r
EFI Development Kit II mirror for PVE