QuarkPlatformPkg/PlatformInit: Fix recovery detection issues
[mirror_edk2.git] / QuarkPlatformPkg / Platform / Pei / PlatformInit / MrcWrapper.h
CommitLineData
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1/** @file\r
2Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.\r
3\r
8b43c84e 4Copyright (c) 2013 - 2016 Intel Corporation.\r
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5\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _MRC_WRAPPER_H\r
17#define _MRC_WRAPPER_H\r
18\r
19#include <Ppi/QNCMemoryInit.h>\r
20#include "PlatformEarlyInit.h"\r
21\r
22//\r
23// Define the default memory areas required\r
24//\r
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25#define EDKII_RESERVED_SIZE_PAGES 0x20\r
26#define ACPI_NVS_SIZE_PAGES 0x60\r
b303605e 27#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20\r
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28#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x80\r
29#define ACPI_RECLAIM_SIZE_PAGES 0x20\r
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30#define EDKII_DXE_MEM_SIZE_PAGES 0x20\r
31\r
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32//\r
33// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
34// DIMM's from the various channels\r
35//\r
36#define MAX_SOCKET_SETS 2\r
37\r
38//\r
39// Maximum number of memory ranges supported by the memory controller\r
40//\r
41#define MAX_RANGES (MAX_ROWS + 5)\r
42\r
43//\r
44// Min. of 48MB PEI phase\r
45//\r
46#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)\r
47#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)\r
48\r
49#define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r
50#define PEI_MR_OPTION_ROM_NONE 0x00000000\r
51\r
52//\r
53// SMRAM Memory Range\r
54//\r
55#define PEI_MEMORY_RANGE_SMRAM UINT32\r
56#define PEI_MR_SMRAM_ALL 0xFFFFFFFF\r
57#define PEI_MR_SMRAM_NONE 0x00000000\r
58#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r
59#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000\r
60#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000\r
61#define PEI_MR_SMRAM_HSEG_MASK 0x00020000\r
62#define PEI_MR_SMRAM_TSEG_MASK 0x00040000\r
63//\r
64// SMRAM Size is a multiple of 128KB.\r
65//\r
66#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF\r
67\r
68//\r
69// Pci Memory Hole\r
70//\r
71#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32\r
72\r
73typedef enum {\r
74 Ignore,\r
75 Quick,\r
76 Sparse,\r
77 Extensive\r
78} PEI_MEMORY_TEST_OP;\r
79\r
80//\r
81// MRC Params Variable structure.\r
82//\r
83\r
84typedef struct {\r
85 MrcTimings_t timings; // Actual MRC config values saved in variable store.\r
86 UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.\r
87} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;\r
88\r
89///\r
90/// MRC Params Platform Data Flags bits\r
91///\r
92#define PDAT_MRC_FLAG_ECC_EN BIT0\r
93#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1\r
94#define PDAT_MRC_FLAG_MEMTEST_EN BIT2\r
95#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.\r
96#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.\r
97\r
98///\r
99/// MRC Params Platform Data.\r
100///\r
101typedef struct {\r
102 UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.\r
103 UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.\r
104 UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.\r
105 UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.\r
106 UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.\r
107 UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.\r
108 UINT8 ChanWidth; ///< 1=x16, others=RESERVED.\r
109 UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.\r
110 UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.\r
111 UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.\r
112 UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.\r
113 UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.\r
114 UINT8 DramRttWrVal; ///< 0=off others=RESERVED.\r
115 UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.\r
116 UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.\r
117 UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.\r
118 UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.\r
119 UINT32 tRAS; ///< ACT to PRE command period in picoseconds.\r
120 UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.\r
121 UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.\r
122 UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.\r
123 UINT8 tCL; ///< DRAM CAS Latency in clocks.\r
124} PDAT_MRC_ITEM;\r
125\r
126//\r
127// Memory range types\r
128//\r
129typedef enum {\r
130 DualChannelDdrMainMemory,\r
131 DualChannelDdrSmramCacheable,\r
132 DualChannelDdrSmramNonCacheable,\r
133 DualChannelDdrGraphicsMemoryCacheable,\r
134 DualChannelDdrGraphicsMemoryNonCacheable,\r
135 DualChannelDdrReservedMemory,\r
136 DualChannelDdrMaxMemoryRangeType\r
137} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
138\r
139//\r
140// Memory map range information\r
141//\r
142typedef struct {\r
143 EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
144 EFI_PHYSICAL_ADDRESS CpuAddress;\r
145 EFI_PHYSICAL_ADDRESS RangeLength;\r
146 PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r
147} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
148\r
149//\r
150// Function prototypes.\r
151//\r
152\r
153EFI_STATUS\r
154InstallEfiMemory (\r
155 IN EFI_PEI_SERVICES **PeiServices,\r
156 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
157 IN EFI_BOOT_MODE BootMode,\r
158 IN UINT32 TotalMemorySize\r
159 );\r
160\r
161EFI_STATUS\r
162InstallS3Memory (\r
163 IN EFI_PEI_SERVICES **PeiServices,\r
164 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
165 IN UINT32 TotalMemorySize\r
166 );\r
167\r
168EFI_STATUS\r
169MemoryInit (\r
170 IN EFI_PEI_SERVICES **PeiServices\r
171 );\r
172\r
173\r
174EFI_STATUS\r
175LoadConfig (\r
176 IN EFI_PEI_SERVICES **PeiServices,\r
177 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
178 IN OUT MRCParams_t *MrcData\r
179 );\r
180\r
181EFI_STATUS\r
182SaveConfig (\r
183 IN MRCParams_t *MrcData\r
184 );\r
185\r
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186EFI_STATUS\r
187GetMemoryMap (\r
188 IN EFI_PEI_SERVICES **PeiServices,\r
189 IN UINT32 TotalMemorySize,\r
190 IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,\r
191 IN OUT UINT8 *NumRanges\r
192 );\r
193\r
194EFI_STATUS\r
195ChooseRanges (\r
196 IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,\r
197 IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,\r
198 IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask\r
199 );\r
200\r
201EFI_STATUS\r
202GetPlatformMemorySize (\r
203 IN EFI_PEI_SERVICES **PeiServices,\r
204 IN EFI_BOOT_MODE BootMode,\r
205 IN OUT UINT64 *MemorySize\r
206 );\r
207\r
208EFI_STATUS\r
209BaseMemoryTest (\r
210 IN EFI_PEI_SERVICES **PeiServices,\r
211 IN EFI_PHYSICAL_ADDRESS BeginAddress,\r
212 IN UINT64 MemoryLength,\r
213 IN PEI_MEMORY_TEST_OP Operation,\r
214 OUT EFI_PHYSICAL_ADDRESS *ErrorAddress\r
215 );\r
216\r
217EFI_STATUS\r
218SetPlatformImrPolicy (\r
219 IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,\r
69a0854b 220 IN UINT64 PeiMemoryLength\r
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221 );\r
222\r
223VOID\r
224EFIAPI\r
225InfoPostInstallMemory (\r
226 OUT UINT32 *RmuBaseAddressPtr OPTIONAL,\r
227 OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,\r
228 OUT UINTN *NumSmramRegionsPtr OPTIONAL\r
229 );\r
230\r
231#endif\r