projects / mirror_edk2.git / blame
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| b303605e MK |
1 | /** @file\r |
| 2 | Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013 Intel Corporation.\r | |
| 5 | \r | |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef _MRC_WRAPPER_H\r | |
| 17 | #define _MRC_WRAPPER_H\r | |
| 18 | \r | |
| 19 | #include <Ppi/QNCMemoryInit.h>\r | |
| 20 | #include "PlatformEarlyInit.h"\r | |
| 21 | \r | |
| 22 | //\r | |
| 23 | // Define the default memory areas required\r | |
| 24 | //\r | |
| 25 | #define EDKII_RESERVED_SIZE_PAGES 0x40\r | |
| 26 | #define ACPI_NVS_SIZE_PAGES 0x40\r | |
| 27 | #define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20\r | |
| 28 | #define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x60\r | |
| 29 | #define ACPI_RECLAIM_SIZE_PAGES 0x10\r | |
| 30 | #define EDKII_DXE_MEM_SIZE_PAGES 0x20\r | |
| 31 | \r | |
| 32 | #define AP_STARTUP_VECTOR 0x00097000\r | |
| 33 | \r | |
| 34 | //\r | |
| 35 | // Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r | |
| 36 | // DIMM's from the various channels\r | |
| 37 | //\r | |
| 38 | #define MAX_SOCKET_SETS 2\r | |
| 39 | \r | |
| 40 | //\r | |
| 41 | // Maximum number of memory ranges supported by the memory controller\r | |
| 42 | //\r | |
| 43 | #define MAX_RANGES (MAX_ROWS + 5)\r | |
| 44 | \r | |
| 45 | //\r | |
| 46 | // Min. of 48MB PEI phase\r | |
| 47 | //\r | |
| 48 | #define PEI_MIN_MEMORY_SIZE (6 * 0x800000)\r | |
| 49 | #define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)\r | |
| 50 | \r | |
| 51 | #define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r | |
| 52 | #define PEI_MR_OPTION_ROM_NONE 0x00000000\r | |
| 53 | \r | |
| 54 | //\r | |
| 55 | // SMRAM Memory Range\r | |
| 56 | //\r | |
| 57 | #define PEI_MEMORY_RANGE_SMRAM UINT32\r | |
| 58 | #define PEI_MR_SMRAM_ALL 0xFFFFFFFF\r | |
| 59 | #define PEI_MR_SMRAM_NONE 0x00000000\r | |
| 60 | #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r | |
| 61 | #define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000\r | |
| 62 | #define PEI_MR_SMRAM_ABSEG_MASK 0x00010000\r | |
| 63 | #define PEI_MR_SMRAM_HSEG_MASK 0x00020000\r | |
| 64 | #define PEI_MR_SMRAM_TSEG_MASK 0x00040000\r | |
| 65 | //\r | |
| 66 | // SMRAM Size is a multiple of 128KB.\r | |
| 67 | //\r | |
| 68 | #define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF\r | |
| 69 | \r | |
| 70 | //\r | |
| 71 | // Pci Memory Hole\r | |
| 72 | //\r | |
| 73 | #define PEI_MEMORY_RANGE_PCI_MEMORY UINT32\r | |
| 74 | \r | |
| 75 | typedef enum {\r | |
| 76 | Ignore,\r | |
| 77 | Quick,\r | |
| 78 | Sparse,\r | |
| 79 | Extensive\r | |
| 80 | } PEI_MEMORY_TEST_OP;\r | |
| 81 | \r | |
| 82 | //\r | |
| 83 | // MRC Params Variable structure.\r | |
| 84 | //\r | |
| 85 | \r | |
| 86 | typedef struct {\r | |
| 87 | MrcTimings_t timings; // Actual MRC config values saved in variable store.\r | |
| 88 | UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.\r | |
| 89 | } PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;\r | |
| 90 | \r | |
| 91 | ///\r | |
| 92 | /// MRC Params Platform Data Flags bits\r | |
| 93 | ///\r | |
| 94 | #define PDAT_MRC_FLAG_ECC_EN BIT0\r | |
| 95 | #define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1\r | |
| 96 | #define PDAT_MRC_FLAG_MEMTEST_EN BIT2\r | |
| 97 | #define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.\r | |
| 98 | #define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.\r | |
| 99 | \r | |
| 100 | ///\r | |
| 101 | /// MRC Params Platform Data.\r | |
| 102 | ///\r | |
| 103 | typedef struct {\r | |
| 104 | UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.\r | |
| 105 | UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.\r | |
| 106 | UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.\r | |
| 107 | UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.\r | |
| 108 | UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.\r | |
| 109 | UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.\r | |
| 110 | UINT8 ChanWidth; ///< 1=x16, others=RESERVED.\r | |
| 111 | UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.\r | |
| 112 | UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.\r | |
| 113 | UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.\r | |
| 114 | UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.\r | |
| 115 | UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.\r | |
| 116 | UINT8 DramRttWrVal; ///< 0=off others=RESERVED.\r | |
| 117 | UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.\r | |
| 118 | UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.\r | |
| 119 | UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.\r | |
| 120 | UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.\r | |
| 121 | UINT32 tRAS; ///< ACT to PRE command period in picoseconds.\r | |
| 122 | UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.\r | |
| 123 | UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.\r | |
| 124 | UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.\r | |
| 125 | UINT8 tCL; ///< DRAM CAS Latency in clocks.\r | |
| 126 | } PDAT_MRC_ITEM;\r | |
| 127 | \r | |
| 128 | //\r | |
| 129 | // Memory range types\r | |
| 130 | //\r | |
| 131 | typedef enum {\r | |
| 132 | DualChannelDdrMainMemory,\r | |
| 133 | DualChannelDdrSmramCacheable,\r | |
| 134 | DualChannelDdrSmramNonCacheable,\r | |
| 135 | DualChannelDdrGraphicsMemoryCacheable,\r | |
| 136 | DualChannelDdrGraphicsMemoryNonCacheable,\r | |
| 137 | DualChannelDdrReservedMemory,\r | |
| 138 | DualChannelDdrMaxMemoryRangeType\r | |
| 139 | } PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r | |
| 140 | \r | |
| 141 | //\r | |
| 142 | // Memory map range information\r | |
| 143 | //\r | |
| 144 | typedef struct {\r | |
| 145 | EFI_PHYSICAL_ADDRESS PhysicalAddress;\r | |
| 146 | EFI_PHYSICAL_ADDRESS CpuAddress;\r | |
| 147 | EFI_PHYSICAL_ADDRESS RangeLength;\r | |
| 148 | PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r | |
| 149 | } PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r | |
| 150 | \r | |
| 151 | //\r | |
| 152 | // Function prototypes.\r | |
| 153 | //\r | |
| 154 | \r | |
| 155 | EFI_STATUS\r | |
| 156 | InstallEfiMemory (\r | |
| 157 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 158 | IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r | |
| 159 | IN EFI_BOOT_MODE BootMode,\r | |
| 160 | IN UINT32 TotalMemorySize\r | |
| 161 | );\r | |
| 162 | \r | |
| 163 | EFI_STATUS\r | |
| 164 | InstallS3Memory (\r | |
| 165 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 166 | IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r | |
| 167 | IN UINT32 TotalMemorySize\r | |
| 168 | );\r | |
| 169 | \r | |
| 170 | EFI_STATUS\r | |
| 171 | MemoryInit (\r | |
| 172 | IN EFI_PEI_SERVICES **PeiServices\r | |
| 173 | );\r | |
| 174 | \r | |
| 175 | \r | |
| 176 | EFI_STATUS\r | |
| 177 | LoadConfig (\r | |
| 178 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 179 | IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r | |
| 180 | IN OUT MRCParams_t *MrcData\r | |
| 181 | );\r | |
| 182 | \r | |
| 183 | EFI_STATUS\r | |
| 184 | SaveConfig (\r | |
| 185 | IN MRCParams_t *MrcData\r | |
| 186 | );\r | |
| 187 | \r | |
| 188 | VOID\r | |
| 189 | RetriveRequiredMemorySize (\r | |
| 190 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 191 | OUT UINTN *Size\r | |
| 192 | );\r | |
| 193 | \r | |
| 194 | EFI_STATUS\r | |
| 195 | GetMemoryMap (\r | |
| 196 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 197 | IN UINT32 TotalMemorySize,\r | |
| 198 | IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,\r | |
| 199 | IN OUT UINT8 *NumRanges\r | |
| 200 | );\r | |
| 201 | \r | |
| 202 | EFI_STATUS\r | |
| 203 | ChooseRanges (\r | |
| 204 | IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,\r | |
| 205 | IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,\r | |
| 206 | IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask\r | |
| 207 | );\r | |
| 208 | \r | |
| 209 | EFI_STATUS\r | |
| 210 | GetPlatformMemorySize (\r | |
| 211 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 212 | IN EFI_BOOT_MODE BootMode,\r | |
| 213 | IN OUT UINT64 *MemorySize\r | |
| 214 | );\r | |
| 215 | \r | |
| 216 | EFI_STATUS\r | |
| 217 | BaseMemoryTest (\r | |
| 218 | IN EFI_PEI_SERVICES **PeiServices,\r | |
| 219 | IN EFI_PHYSICAL_ADDRESS BeginAddress,\r | |
| 220 | IN UINT64 MemoryLength,\r | |
| 221 | IN PEI_MEMORY_TEST_OP Operation,\r | |
| 222 | OUT EFI_PHYSICAL_ADDRESS *ErrorAddress\r | |
| 223 | );\r | |
| 224 | \r | |
| 225 | EFI_STATUS\r | |
| 226 | SetPlatformImrPolicy (\r | |
| 227 | IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,\r | |
| 228 | IN UINT64 PeiMemoryLength,\r | |
| 229 | IN UINTN RequiredMemSize\r | |
| 230 | );\r | |
| 231 | \r | |
| 232 | VOID\r | |
| 233 | EFIAPI\r | |
| 234 | InfoPostInstallMemory (\r | |
| 235 | OUT UINT32 *RmuBaseAddressPtr OPTIONAL,\r | |
| 236 | OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,\r | |
| 237 | OUT UINTN *NumSmramRegionsPtr OPTIONAL\r | |
| 238 | );\r | |
| 239 | \r | |
| 240 | #endif\r |