[mirror_edk2.git] / QuarkPlatformPkg / Platform / Pei / PlatformInit / PlatformEarlyInit.c

/** @file\r
This PEIM initialize platform for MRC, following action is performed,\r
1. Initizluize GMCH\r
2. Detect boot mode\r
3. Detect video adapter to determine whether we need pre allocated memory\r
4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.\r
This file contains the main entrypoint of the PEIM.\r
\r
Copyright (c) 2013 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#include "CommonHeader.h"\r
#include "PlatformEarlyInit.h"\r
#include "PeiFvSecurity.h"\r
\r
EFI_STATUS\r
EFIAPI\r
EndOfPeiSignalPpiNotifyCallback (\r
  IN EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  );\r
\r
//\r
// Function prototypes to routines implemented in other source modules\r
// within this component.\r
//\r
\r
EFI_STATUS\r
EFIAPI\r
PlatformErratasPostMrc (\r
  VOID\r
  );\r
\r
//\r
// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory\r
//\r
BOOLEAN ImageInMemory = FALSE;\r
\r
BOARD_LEGACY_GPIO_CONFIG      mBoardLegacyGpioConfigTable[]  = { PLATFORM_LEGACY_GPIO_TABLE_DEFINITION };\r
UINTN                         mBoardLegacyGpioConfigTableLen = (sizeof(mBoardLegacyGpioConfigTable) / sizeof(BOARD_LEGACY_GPIO_CONFIG));\r
BOARD_GPIO_CONTROLLER_CONFIG  mBoardGpioControllerConfigTable[]  = { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION };\r
UINTN                         mBoardGpioControllerConfigTableLen = (sizeof(mBoardGpioControllerConfigTable) / sizeof(BOARD_GPIO_CONTROLLER_CONFIG));\r
UINT8                         ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};\r
\r
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[1] = {\r
  {\r
    (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
    &gEfiPeiMasterBootModePpiGuid,\r
    NULL\r
  }\r
};\r
\r
EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {\r
  {\r
    (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
    &gEfiPeiMemoryDiscoveredPpiGuid,\r
    MemoryDiscoveredPpiNotifyCallback\r
  }\r
};\r
\r
EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiSignalPpiNotifyList[1] = {\r
  {\r
    (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
    &gEfiEndOfPeiSignalPpiGuid,\r
    EndOfPeiSignalPpiNotifyCallback\r
  }\r
};\r
\r
EFI_PEI_STALL_PPI mStallPpi = {\r
  PEI_STALL_RESOLUTION,\r
  Stall\r
};\r
\r
EFI_PEI_PPI_DESCRIPTOR mPpiStall[1] = {\r
  {\r
    (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
    &gEfiPeiStallPpiGuid,\r
    &mStallPpi\r
  }\r
};\r
\r
/**\r
  Set Mac address on chipset ethernet device.\r
\r
  @param  Bus      PCI Bus number of chipset ethernet device.\r
  @param  Device   Device number of chipset ethernet device.\r
  @param  Func     PCI Function number of chipset ethernet device.\r
  @param  MacAddr  MAC Address to set.\r
\r
**/\r
VOID\r
EFIAPI\r
SetLanControllerMacAddr (\r
  IN CONST UINT8                          Bus,\r
  IN CONST UINT8                          Device,\r
  IN CONST UINT8                          Func,\r
  IN CONST UINT8                          *MacAddr,\r
  IN CONST UINT32                         Bar0\r
  )\r
{\r
  UINT32                            Data32;\r
  UINT16                            PciVid;\r
  UINT16                            PciDid;\r
  UINT32                            Addr;\r
  UINT32                            MacVer;\r
  volatile UINT8                    *Wrote;\r
  UINT32                            DevPcieAddr;\r
  UINT16                            SaveCmdReg;\r
  UINT32                            SaveBarReg;\r
\r
  DevPcieAddr = PCI_LIB_ADDRESS (\r
                  Bus,\r
                  Device,\r
                  Func,\r
                  0\r
                  );\r
\r
  //\r
  // Do nothing if not a supported device.\r
  //\r
  PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);\r
  PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);\r
  if((PciVid != V_IOH_MAC_VENDOR_ID) || (PciDid != V_IOH_MAC_DEVICE_ID)) {\r
    return;\r
  }\r
\r
  //\r
  // Save current settings for PCI CMD/BAR registers\r
  //\r
  SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);\r
  SaveBarReg = PciRead32 (DevPcieAddr + R_IOH_MAC_MEMBAR);\r
\r
  //\r
  // Use predefined tempory memory resource\r
  //\r
  PciWrite32 ( DevPcieAddr + R_IOH_MAC_MEMBAR, Bar0);\r
  PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);\r
\r
  Addr =  Bar0 + R_IOH_MAC_GMAC_REG_8;\r
  MacVer = *((volatile UINT32 *) (UINTN)(Addr));\r
\r
  DEBUG ((EFI_D_INFO, "Ioh MAC [B:%d, D:%d, F:%d] VER:%04x ADDR:",\r
    (UINTN) Bus,\r
    (UINTN) Device,\r
    (UINTN) Func,\r
    (UINTN) MacVer\r
    ));\r
\r
  //\r
  // Set MAC Address0 Low Register (GMAC_REG_17) ADDRLO bits.\r
  //\r
  Addr =  Bar0 + R_IOH_MAC_GMAC_REG_17;\r
  Data32 = *((UINT32 *) (UINTN)(&MacAddr[0]));\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
  Wrote = (volatile UINT8 *) (UINTN)(Addr);\r
  DEBUG ((EFI_D_INFO, "%02x-%02x-%02x-%02x-",\r
    (UINTN) Wrote[0],\r
    (UINTN) Wrote[1],\r
    (UINTN) Wrote[2],\r
    (UINTN) Wrote[3]\r
    ));\r
\r
  //\r
  // Set MAC Address0 High Register (GMAC_REG_16) ADDRHI bits\r
  // and Address Enable (AE) bit.\r
  //\r
  Addr =  Bar0 + R_IOH_MAC_GMAC_REG_16;\r
  Data32 =\r
    ((UINT32) MacAddr[4]) |\r
    (((UINT32)MacAddr[5]) << 8) |\r
    B_IOH_MAC_AE;\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
  Wrote = (volatile UINT8 *) (UINTN)(Addr);\r
\r
  DEBUG ((EFI_D_INFO, "%02x-%02x\n", (UINTN) Wrote[0], (UINTN) Wrote[1]));\r
\r
  //\r
  // Restore settings for PCI CMD/BAR registers\r
  //\r
  PciWrite32 ((DevPcieAddr + R_IOH_MAC_MEMBAR), SaveBarReg);\r
  PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);\r
}\r
\r
/**\r
  This is the entrypoint of PEIM\r
\r
  @param  FileHandle  Handle of the file being invoked.\r
  @param  PeiServices Describes the list of possible PEI Services.\r
\r
  @retval EFI_SUCCESS if it completed successfully.\r
**/\r
EFI_STATUS\r
EFIAPI\r
PeiInitPlatform (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  EFI_STATUS                              Status;\r
  EFI_BOOT_MODE                           BootMode;\r
  EFI_PEI_STALL_PPI                       *StallPpi;\r
  EFI_PEI_PPI_DESCRIPTOR                  *StallPeiPpiDescriptor;\r
  EFI_FV_FILE_INFO                        FileInfo;\r
  EFI_PLATFORM_TYPE                       PlatformType;\r
\r
  PlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);\r
\r
  //\r
  // Initialize Firmware Volume security.\r
  // This must be done before any firmware volume accesses (excl. BFV)\r
  //\r
  Status = PeiInitializeFvSecurity();\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Do any early platform specific initialization.\r
  //\r
  EarlyPlatformInit ();\r
\r
  //\r
  // This is a second path on entry, in recovery boot path the Stall PPI need to be memory-based\r
  // to improve recovery performance.\r
  //\r
  Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);\r
  ASSERT_EFI_ERROR (Status);\r
  //\r
  // The follow conditional check only works for memory-mapped FFS,\r
  // so we ASSERT that the file is really a MM FFS.\r
  //\r
  ASSERT (FileInfo.Buffer != NULL);\r
  if (!(((UINTN) FileInfo.Buffer <= (UINTN) PeiInitPlatform) &&\r
        ((UINTN) PeiInitPlatform <= (UINTN) FileInfo.Buffer + FileInfo.BufferSize))) {\r
    //\r
    // Now that module in memory, update the\r
    // PPI that describes the Stall to other modules\r
    //\r
    Status = PeiServicesLocatePpi (\r
               &gEfiPeiStallPpiGuid,\r
               0,\r
               &StallPeiPpiDescriptor,\r
               (VOID **) &StallPpi\r
               );\r
\r
    if (!EFI_ERROR (Status)) {\r
\r
      Status = PeiServicesReInstallPpi (\r
                 StallPeiPpiDescriptor,\r
                 &mPpiStall[0]\r
                 );\r
    } else {\r
\r
      Status = PeiServicesInstallPpi (&mPpiStall[0]);\r
    }\r
    return Status;\r
  }\r
\r
  //\r
  // Initialize System Phys\r
  //\r
\r
  // Program USB Phy\r
  InitializeUSBPhy();\r
\r
  //\r
  // Do platform specific logic to create a boot mode\r
  //\r
  Status = UpdateBootMode ((EFI_PEI_SERVICES**)PeiServices, &BootMode);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Signal possible dependent modules that there has been a\r
  // final boot mode determination\r
  //\r
  if (!EFI_ERROR(Status)) {\r
    Status = PeiServicesInstallPpi (&mPpiBootMode[0]);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  if (BootMode != BOOT_ON_S3_RESUME) {\r
    QNCClearSmiAndWake ();\r
  }\r
\r
  DEBUG ((EFI_D_INFO, "MRC Entry\n"));\r
  MemoryInit ((EFI_PEI_SERVICES**)PeiServices);\r
\r
  //\r
  // Do Early PCIe init.\r
  //\r
  DEBUG ((EFI_D_INFO, "Early PCIe controller initialization\n"));\r
  PlatformPciExpressEarlyInit (PlatformType);\r
\r
\r
  DEBUG ((EFI_D_INFO, "Platform Erratas After MRC\n"));\r
  PlatformErratasPostMrc ();\r
\r
  //\r
  // Now that all of the pre-permanent memory activities have\r
  // been taken care of, post a call-back for the permanent-memory\r
  // resident services, such as HOB construction.\r
  // PEI Core will switch stack after this PEIM exit.  After that the MTRR\r
  // can be set.\r
  //\r
  Status = PeiServicesNotifyPpi (&mMemoryDiscoveredNotifyList[0]);\r
  ASSERT_EFI_ERROR (Status);\r
/*\r
\r
  if (BootMode != BOOT_ON_S3_RESUME) {\r
    Status = PeiServicesNotifyPpi (mEndOfPeiSignalPpiNotifyList);\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
*/\r
  if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
    PeiServicesRegisterForShadow (FileHandle);\r
  }\r
\r
  return Status;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
EndOfPeiSignalPpiNotifyCallback (\r
  IN EFI_PEI_SERVICES           **PeiServices,\r
  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
  IN VOID                       *Ppi\r
  )\r
{\r
  EFI_STATUS                            Status;\r
\r
  DEBUG ((EFI_D_INFO, "End of PEI Signal Callback\n"));\r
\r
    //\r
  // Restore the flash region to be UC\r
  // for both normal boot as we build a Resource Hob to\r
  // describe this region as UC to DXE core.\r
  //\r
  WriteBackInvalidateDataCacheRange (\r
    (VOID *) (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),\r
    PcdGet32 (PcdFlashAreaSize)\r
  );\r
\r
  Status = MtrrSetMemoryAttribute (PcdGet32 (PcdFlashAreaBaseAddress), PcdGet32 (PcdFlashAreaSize), CacheUncacheable);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  This function will initialize USB Phy registers associated with QuarkSouthCluster.\r
\r
  @param  VOID                  No Argument\r
\r
  @retval EFI_SUCCESS           All registers have been initialized\r
**/\r
VOID\r
EFIAPI\r
InitializeUSBPhy (\r
    VOID\r
   )\r
{\r
    UINT32 RegData32;\r
\r
    /** In order to configure the PHY to use clk120 (ickusbcoreclk) as PLL reference clock\r
     *  and Port2 as a USB device port, the following sequence must be followed\r
     *\r
     **/\r
\r
    // Sideband register write to USB AFE (Phy)\r
    RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT);\r
    RegData32 &= ~(BIT1);\r
    //\r
    // Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.\r
    // For port 0 & 1 as host and port 2 as device.\r
    //\r
    RegData32 |= (BIT8 | BIT7);\r
    QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT, RegData32);\r
\r
    //\r
    // Sighting #4930653 Required BIOS change on Disconnect vref to change to 600mV.\r
    //\r
    RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG);\r
    RegData32 &= ~(BIT10 | BIT9 | BIT8 | BIT7);\r
    RegData32 |= (BIT10 | BIT7);\r
    QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG, RegData32);\r
\r
    // Sideband register write to USB AFE (Phy)\r
    // (pllbypass) to bypass/Disable PLL before switch\r
    RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);\r
    RegData32 |= BIT29;\r
    QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);\r
\r
    // Sideband register write to USB AFE (Phy)\r
    // (coreclksel) to select 120MHz (ickusbcoreclk) clk source.\r
    // (Default 0 to select 96MHz (ickusbclk96_npad/ppad))\r
    RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);\r
    RegData32 |= BIT1;\r
    QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);\r
\r
    // Sideband register write to USB AFE (Phy)\r
    // (divide by 8) to achieve internal 480MHz clock\r
    // for 120MHz input refclk.  (Default: 4'b1000 (divide by 10) for 96MHz)\r
    RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);\r
    RegData32 &= ~(BIT5 | BIT4 | BIT3);\r
    RegData32 |= BIT6;\r
    QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);\r
\r
    // Sideband register write to USB AFE (Phy)\r
    // Clear (pllbypass)\r
    RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);\r
    RegData32 &= ~BIT29;\r
    QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);\r
\r
    // Sideband register write to USB AFE (Phy)\r
    // Set (startlock) to force the PLL FSM to restart the lock\r
    // sequence due to input clock/freq switch.\r
    RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);\r
    RegData32 |= BIT24;\r
    QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);\r
\r
    // At this point the PLL FSM and COMP FSM will complete\r
\r
}\r
\r
/**\r
  This function provides early platform Thermal sensor initialisation.\r
**/\r
VOID\r
EFIAPI\r
EarlyPlatformThermalSensorInit (\r
  VOID\r
  )\r
{\r
  DEBUG ((EFI_D_INFO, "Early Platform Thermal Sensor Init\n"));\r
\r
  //\r
  // Set Thermal sensor mode.\r
  //\r
  QNCThermalSensorSetRatiometricMode ();\r
\r
  //\r
  // Enable RMU Thermal sensor with a Catastrophic Trip point.\r
  //\r
  QNCThermalSensorEnableWithCatastrophicTrip (PLATFORM_CATASTROPHIC_TRIP_CELSIUS);\r
\r
  //\r
  // Lock all RMU Thermal sensor control & trip point registers.\r
  //\r
  QNCThermalSensorLockAllRegisters ();\r
}\r
\r
/**\r
  Print early platform info messages includeing the Stage1 module that's\r
  running, MFH item list and platform data item list.\r
**/\r
VOID\r
EFIAPI\r
EarlyPlatformInfoMessages (\r
  VOID\r
  )\r
{\r
  DEBUG_CODE_BEGIN ();\r
  QUARK_EDKII_STAGE1_HEADER       *Edk2ImageHeader;\r
\r
  //\r
  // Find which 'Stage1' image we are running and print the details\r
  //\r
  Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base);\r
  DEBUG ((EFI_D_INFO, "\n************************************************************\n"));\r
\r
  switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) {\r
    case QUARK_STAGE1_BOOT_IMAGE_TYPE:\r
      DEBUG ((EFI_D_INFO, "****  Quark EDKII Stage 1 Boot Image %d                ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));\r
      break;\r
\r
    case QUARK_STAGE1_RECOVERY_IMAGE_TYPE:\r
      DEBUG ((EFI_D_INFO, "****  Quark EDKII Stage 1 Recovery Image %d            ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));\r
      break;\r
\r
    default:\r
      DEBUG ((EFI_D_INFO, "****  Quark EDKII Unknown Stage 1 Image !!!!           ****\n"));\r
      break;\r
  }\r
  DEBUG (\r
    (EFI_D_INFO,\r
    "****  Quark EDKII Stage 2 Image 0x%08X:0x%08X ****\n" ,\r
    (UINTN) PcdGet32 (PcdFlashFvMainBase),\r
    (UINTN) PcdGet32 (PcdFlashFvMainSize)\r
    ));\r
\r
  DEBUG (\r
    (EFI_D_INFO,\r
    "****  Quark EDKII Payload Image 0x%08X:0x%08X ****\n" ,\r
    (UINTN) PcdGet32 (PcdFlashFvPayloadBase),\r
    (UINTN) PcdGet32 (PcdFlashFvPayloadSize)\r
    ));\r
\r
  DEBUG ((EFI_D_INFO, "************************************************************\n\n"));\r
\r
  DEBUG_CODE_END ();\r
}\r
\r
/**\r
  Check if system reset due to error condition.\r
\r
  @param  ClearErrorBits  If TRUE clear error flags and value bits.\r
\r
  @retval TRUE  if system reset due to error condition.\r
  @retval FALSE if NO reset error conditions.\r
**/\r
BOOLEAN\r
CheckForResetDueToErrors (\r
  IN BOOLEAN                              ClearErrorBits\r
  )\r
{\r
  UINT32                            RegValue;\r
  BOOLEAN                           ResetDueToError;\r
\r
  ResetDueToError = FALSE;\r
\r
  //\r
  // Check if RMU reset system due to access violations.\r
  // RMU updates a SOC Unit register before reseting the system.\r
  //\r
  RegValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW);\r
  if ((RegValue & B_CFG_STICKY_RW_VIOLATION) != 0) {\r
    ResetDueToError = TRUE;\r
\r
    DEBUG (\r
      (EFI_D_ERROR,\r
      "\nReset due to access violation: %s %s %s %s\n",\r
      ((RegValue & B_CFG_STICKY_RW_IMR_VIOLATION) != 0) ? L"'IMR'" : L".",\r
      ((RegValue & B_CFG_STICKY_RW_DECC_VIOLATION) != 0) ? L"'DECC'" : L".",\r
      ((RegValue & B_CFG_STICKY_RW_SMM_VIOLATION) != 0) ? L"'SMM'" : L".",\r
      ((RegValue & B_CFG_STICKY_RW_HMB_VIOLATION) != 0) ? L"'HMB'" : L"."\r
      ));\r
\r
    //\r
    // Clear error bits.\r
    //\r
    if (ClearErrorBits) {\r
      RegValue &= ~(B_CFG_STICKY_RW_VIOLATION);\r
      QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, RegValue);\r
    }\r
  }\r
\r
  return ResetDueToError;\r
}\r
\r
/**\r
  This function provides early platform initialization.\r
\r
  @param  PlatformInfo  Pointer to platform Info structure.\r
\r
**/\r
VOID\r
EFIAPI\r
EarlyPlatformInit (\r
  VOID\r
  )\r
{\r
  EFI_PLATFORM_TYPE                 PlatformType;\r
\r
  PlatformType = (EFI_PLATFORM_TYPE) PcdGet16 (PcdPlatformType);\r
\r
  DEBUG ((EFI_D_INFO, "EarlyPlatformInit for PlatType=0x%02x\n", (UINTN) PlatformType));\r
\r
  //\r
  // Check if system reset due to error condition.\r
  //\r
  if (CheckForResetDueToErrors (TRUE)) {\r
    if(FeaturePcdGet (WaitIfResetDueToError)) {\r
      DEBUG ((EFI_D_ERROR, "Press any key to continue.\n"));\r
      PlatformDebugPortGetChar8 ();\r
    }\r
  }\r
\r
  //\r
  // Display platform info messages.\r
  //\r
  EarlyPlatformInfoMessages ();\r
\r
  //\r
  // Early Legacy Gpio Init.\r
  //\r
  EarlyPlatformLegacyGpioInit (PlatformType);\r
\r
  //\r
  // Early platform Legacy GPIO manipulation depending on GPIOs\r
  // setup by EarlyPlatformLegacyGpioInit.\r
  //\r
  EarlyPlatformLegacyGpioManipulation (PlatformType);\r
\r
  //\r
  // Early platform specific GPIO Controller init & manipulation.\r
  // Combined for sharing of temp. memory bar.\r
  //\r
  EarlyPlatformGpioCtrlerInitAndManipulation (PlatformType);\r
\r
  //\r
  // Early Thermal Sensor Init.\r
  //\r
  EarlyPlatformThermalSensorInit ();\r
\r
  //\r
  // Early Lan Ethernet Mac Init.\r
  //\r
  EarlyPlatformMacInit (\r
    PcdGetPtr (PcdIohEthernetMac0),\r
    PcdGetPtr (PcdIohEthernetMac1)\r
    );\r
}\r
\r
/**\r
  This function provides early platform Legacy GPIO initialisation.\r
\r
  @param  PlatformType  Platform type for GPIO init.\r
\r
**/\r
VOID\r
EFIAPI\r
EarlyPlatformLegacyGpioInit (\r
  IN CONST EFI_PLATFORM_TYPE              PlatformType\r
  )\r
{\r
  BOARD_LEGACY_GPIO_CONFIG          *LegacyGpioConfig;\r
  UINT32                            NewValue;\r
  UINT32                            GpioBaseAddress;\r
\r
  //\r
  // Assert if platform type outside table range.\r
  //\r
  ASSERT ((UINTN) PlatformType < mBoardLegacyGpioConfigTableLen);\r
  LegacyGpioConfig = &mBoardLegacyGpioConfigTable[(UINTN) PlatformType];\r
\r
  GpioBaseAddress = (UINT32)PcdGet16 (PcdGbaIoBaseAddress);\r
\r
  NewValue     = 0x0;\r
  //\r
  // Program QNC GPIO Registers.\r
  //\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL, NewValue );\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellIoSelect;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL, NewValue);\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellLvlForInputOrOutput;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL, NewValue);\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerPositiveEdge;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL, NewValue );\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerNegativeEdge;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL, NewValue);\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellGPEEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL, NewValue);\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellSMIEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL, NewValue );\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerStatus;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL, NewValue);\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellNMIEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL, NewValue);\r
\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL, NewValue );\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellIoSelect;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL, NewValue) ;\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellLvlForInputOrOutput;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, NewValue);\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerPositiveEdge;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL, NewValue );\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerNegativeEdge;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL, NewValue) ;\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellGPEEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL, NewValue);\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellSMIEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL, NewValue );\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerStatus;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL, NewValue) ;\r
  NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellNMIEnable;\r
  IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL, NewValue);\r
}\r
\r
/**\r
  Performs any early platform specific Legacy GPIO manipulation.\r
\r
  @param  PlatformType  Platform type GPIO manipulation.\r
\r
**/\r
VOID\r
EFIAPI\r
EarlyPlatformLegacyGpioManipulation (\r
  IN CONST EFI_PLATFORM_TYPE              PlatformType\r
  )\r
{\r
  if (PlatformType == CrossHill) {\r
\r
    //\r
    // Pull TPM reset low for 80us (equivalent to cold reset, Table 39\r
    // Infineon SLB9645 Databook), then pull TPM reset high and wait for\r
    // 150ms to give time for TPM to stabilise (Section 4.7.1 Infineon\r
    // SLB9645 Databook states TPM is ready to receive command after 30ms\r
    // but section 4.7 states some TPM commands may take longer to execute\r
    // upto 150ms after test).\r
    //\r
\r
    PlatformLegacyGpioSetLevel (\r
      R_QNC_GPIO_RGLVL_RESUME_WELL,\r
      PLATFORM_RESUMEWELL_TPM_RST_GPIO,\r
      FALSE\r
      );\r
    MicroSecondDelay (80);\r
\r
    PlatformLegacyGpioSetLevel (\r
      R_QNC_GPIO_RGLVL_RESUME_WELL,\r
      PLATFORM_RESUMEWELL_TPM_RST_GPIO,\r
      TRUE\r
      );\r
    MicroSecondDelay (150000);\r
  }\r
\r
}\r
\r
/**\r
  Performs any early platform specific GPIO Controller init & manipulation.\r
\r
  @param  PlatformType  Platform type for GPIO init & manipulation.\r
\r
**/\r
VOID\r
EFIAPI\r
EarlyPlatformGpioCtrlerInitAndManipulation (\r
  IN CONST EFI_PLATFORM_TYPE              PlatformType\r
  )\r
{\r
  UINT32                            IohGpioBase;\r
  UINT32                            Data32;\r
  UINT32                            Addr;\r
  BOARD_GPIO_CONTROLLER_CONFIG      *GpioConfig;\r
  UINT32                            DevPcieAddr;\r
  UINT16                            SaveCmdReg;\r
  UINT32                            SaveBarReg;\r
  UINT16                            PciVid;\r
  UINT16                            PciDid;\r
\r
  ASSERT ((UINTN) PlatformType < mBoardGpioControllerConfigTableLen);\r
  GpioConfig = &mBoardGpioControllerConfigTable[(UINTN) PlatformType];\r
\r
  IohGpioBase = (UINT32) PcdGet64 (PcdIohGpioMmioBase);\r
\r
  DevPcieAddr = PCI_LIB_ADDRESS (\r
                  PcdGet8 (PcdIohGpioBusNumber),\r
                  PcdGet8 (PcdIohGpioDevNumber),\r
                  PcdGet8 (PcdIohGpioFunctionNumber),\r
                  0\r
                  );\r
\r
  //\r
  // Do nothing if not a supported device.\r
  //\r
  PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);\r
  PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);\r
  if((PciVid != V_IOH_I2C_GPIO_VENDOR_ID) || (PciDid != V_IOH_I2C_GPIO_DEVICE_ID)) {\r
    return;\r
  }\r
\r
  //\r
  // Save current settings for PCI CMD/BAR registers.\r
  //\r
  SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);\r
  SaveBarReg = PciRead32 (DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister));\r
\r
  //\r
  // Use predefined tempory memory resource.\r
  //\r
  PciWrite32 ( DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister), IohGpioBase);\r
  PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);\r
\r
  //\r
  // Gpio Controller Init Tasks.\r
  //\r
\r
  //\r
  // IEN- Interrupt Enable Register\r
  //\r
  Addr =  IohGpioBase + GPIO_INTEN;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->IntEn & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // ISTATUS- Interrupt Status Register\r
  //\r
  Addr =  IohGpioBase + GPIO_INTSTATUS;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // GPIO SWPORTA Direction Register - GPIO_SWPORTA_DR\r
  //\r
  Addr =  IohGpioBase + GPIO_SWPORTA_DR;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->PortADR & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR - default input\r
  //\r
  Addr =  IohGpioBase + GPIO_SWPORTA_DDR;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->PortADir & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // Interrupt Mask Register - GPIO_INTMASK - default interrupts unmasked\r
  //\r
  Addr =  IohGpioBase + GPIO_INTMASK;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->IntMask & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL - default is level sensitive\r
  //\r
  Addr =  IohGpioBase + GPIO_INTTYPE_LEVEL;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->IntType & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // Interrupt Polarity Type Register - GPIO_INT_POLARITY - default is active low\r
  //\r
  Addr =  IohGpioBase + GPIO_INT_POLARITY;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->IntPolarity & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // Interrupt Debounce Type Register - GPIO_DEBOUNCE - default no debounce\r
  //\r
  Addr =  IohGpioBase + GPIO_DEBOUNCE;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->Debounce & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // Interrupt Clock Synchronisation Register - GPIO_LS_SYNC - default no sync with pclk_intr(APB bus clk)\r
  //\r
  Addr =  IohGpioBase + GPIO_LS_SYNC;\r
  Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
  Data32 |= (GpioConfig->LsSync & 0x000FFFFF);\r
  *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  //\r
  // Gpio Controller Manipulation Tasks.\r
  //\r
\r
  if (PlatformType == (EFI_PLATFORM_TYPE) Galileo) {\r
    //\r
    // Reset Cypress Expander on Galileo Platform\r
    //\r
    Addr = IohGpioBase + GPIO_SWPORTA_DR;\r
    Data32 = *((volatile UINT32 *) (UINTN)(Addr));\r
    Data32 |= BIT4;                                 // Cypress Reset line controlled by GPIO<4>\r
    *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
    Data32 = *((volatile UINT32 *) (UINTN)(Addr));\r
    Data32 &= ~BIT4;                                // Cypress Reset line controlled by GPIO<4>\r
    *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
\r
  }\r
\r
  //\r
  // Restore settings for PCI CMD/BAR registers\r
  //\r
  PciWrite32 ((DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);\r
  PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);\r
}\r
\r
/**\r
  Performs any early platform init of SoC Ethernet Mac devices.\r
\r
  @param  IohMac0Address  Mac address to program into Mac0 device.\r
  @param  IohMac1Address  Mac address to program into Mac1 device.\r
\r
**/\r
VOID\r
EFIAPI\r
EarlyPlatformMacInit (\r
  IN CONST UINT8                          *IohMac0Address,\r
  IN CONST UINT8                          *IohMac1Address\r
  )\r
{\r
  BOOLEAN                           SetMacAddr;\r
\r
  //\r
  // Set chipset MAC0 address if configured.\r
  //\r
  SetMacAddr =\r
    (CompareMem (ChipsetDefaultMac, IohMac0Address, sizeof (ChipsetDefaultMac))) != 0;\r
  if (SetMacAddr) {\r
    if ((*(IohMac0Address) & BIT0) != 0) {\r
      DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",\r
        (UINTN) IOH_MAC0_BUS_NUMBER,\r
        (UINTN) IOH_MAC0_DEVICE_NUMBER,\r
        (UINTN) IOH_MAC0_FUNCTION_NUMBER\r
        ));\r
      ASSERT (FALSE);\r
    } else {\r
      SetLanControllerMacAddr (\r
        IOH_MAC0_BUS_NUMBER,\r
        IOH_MAC0_DEVICE_NUMBER,\r
        IOH_MAC0_FUNCTION_NUMBER,\r
        IohMac0Address,\r
        (UINT32) PcdGet64(PcdIohMac0MmioBase)\r
        );\r
    }\r
  } else {\r
    DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",\r
      (UINTN) IOH_MAC0_BUS_NUMBER,\r
      (UINTN) IOH_MAC0_DEVICE_NUMBER,\r
      (UINTN) IOH_MAC0_FUNCTION_NUMBER\r
      ));\r
  }\r
\r
  //\r
  // Set chipset MAC1 address if configured.\r
  //\r
  SetMacAddr =\r
    (CompareMem (ChipsetDefaultMac, IohMac1Address, sizeof (ChipsetDefaultMac))) != 0;\r
  if (SetMacAddr) {\r
    if ((*(IohMac1Address) & BIT0) != 0) {\r
      DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",\r
        (UINTN) IOH_MAC1_BUS_NUMBER,\r
        (UINTN) IOH_MAC1_DEVICE_NUMBER,\r
        (UINTN) IOH_MAC1_FUNCTION_NUMBER\r
        ));\r
      ASSERT (FALSE);\r
    } else {\r
        SetLanControllerMacAddr (\r
          IOH_MAC1_BUS_NUMBER,\r
          IOH_MAC1_DEVICE_NUMBER,\r
          IOH_MAC1_FUNCTION_NUMBER,\r
          IohMac1Address,\r
          (UINT32) PcdGet64(PcdIohMac1MmioBase)\r
          );\r
    }\r
  } else {\r
    DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",\r
      (UINTN) IOH_MAC1_BUS_NUMBER,\r
      (UINTN) IOH_MAC1_DEVICE_NUMBER,\r
      (UINTN) IOH_MAC1_FUNCTION_NUMBER\r
      ));\r
  }\r
}\r
\r