[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / DdrMemoryController.h

/** @file\r
Memory controller configuration.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#ifndef __DDR_MEMORY_CONTROLLER_H__\r
#define __DDR_MEMORY_CONTROLLER_H__\r
\r
//\r
// DDR timing data definitions.\r
// These are used to create bitmaps of valid timing configurations.\r
//\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN    0xFF\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20    0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25    0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30    0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL   0x03\r
\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02   0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03   0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04   0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL  0x03\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02    0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03    0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04    0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL   0x03\r
\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05   0x05\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06   0x04\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07   0x03\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08   0x02\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09   0x01\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10   0x00\r
#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL  0x07\r
\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED    0x01\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED  0x02\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED      0x04\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED    0x08\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR           0x10\r
#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR           0x20\r
\r
\r
//\r
// Maximum number of SDRAM channels supported by the memory controller\r
//\r
#define MAX_CHANNELS 1\r
\r
//\r
// Maximum number of DIMM sockets supported by the memory controller\r
//\r
#define MAX_SOCKETS 1\r
\r
//\r
// Maximum number of sides supported per DIMM\r
//\r
#define   MAX_SIDES                         2\r
\r
//\r
// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
// DIMM's from the various channels\r
//\r
#define   MAX_SOCKET_SETS                   2\r
\r
//\r
// Maximum number of rows supported by the memory controller\r
//\r
#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)\r
\r
//\r
// Maximum number of memory ranges supported by the memory controller\r
//\r
#define MAX_RANGES (MAX_ROWS + 5)\r
\r
//\r
// Maximum Number of Log entries\r
//\r
#define   MEMORY_LOG_MAX_INDEX          16\r
\r
\r
typedef struct _MEMORY_LOG_ENTRY {\r
  EFI_STATUS_CODE_VALUE                     Event;\r
  EFI_STATUS_CODE_TYPE                      Severity;\r
  UINT8                                     Data;\r
} MEMORY_LOG_ENTRY;\r
\r
typedef struct _MEMORY_LOG {\r
  UINT8                                     Index;\r
  MEMORY_LOG_ENTRY                      Entry[MEMORY_LOG_MAX_INDEX];\r
} MEMORY_LOG;\r
\r
\r
\r
//\r
// Defined ECC types\r
//\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE             0x01   // No error checking\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_EC               0x02   // Error checking only\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC             0x04   // Software Scrubbing ECC\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC             0x08   // Hardware Scrubbing ECC\r
#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC            0x10   // Chip Kill ECC\r
\r
//\r
// Row configuration status values\r
//\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS        0x00  // No error\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN        0x01  // Pattern mismatch, no memory\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED    0x02  // Memory type not supported\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR  0x03  // Row/Col/Bnk mismatch\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR      0x04  // Received ECC error\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT    0x05  // Row is not present\r
#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED       0x06  // Row is disabled\r
\r
\r
//\r
// Memory range types\r
//\r
typedef enum {\r
  DualChannelDdrMainMemory,\r
  DualChannelDdrSmramCacheable,\r
  DualChannelDdrSmramNonCacheable,\r
  DualChannelDdrGraphicsMemoryCacheable,\r
  DualChannelDdrGraphicsMemoryNonCacheable,\r
  DualChannelDdrReservedMemory,\r
  DualChannelDdrMaxMemoryRangeType\r
} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
\r
//\r
// Memory map range information\r
//\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS                          PhysicalAddress;\r
  EFI_PHYSICAL_ADDRESS                          CpuAddress;\r
  EFI_PHYSICAL_ADDRESS                          RangeLength;\r
  DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE                 Type;\r
} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
typedef struct {\r
    unsigned    dramType        :1;                 /**< Type: 0 = RESERVED; 1 = DDR2 */\r
    unsigned    dramWidth       :1;                 /**< Width: 0 = x8; 1 = x16 */\r
    unsigned    dramDensity     :2;                 /**< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb */\r
    unsigned    dramSpeed       :1;                 /**< Speed Grade: 0 = RESERVED; 1 = 800MT/s;*/\r
    unsigned    dramTimings     :3;                 /**< Timings: 4-4-4, 5-5-5, 6-6-6 */\r
    unsigned    dramRanks       :1;                 /**< Ranks: 0 = Single Rank; 1 = Dual Rank */\r
} DramGeometry;                                     /**< DRAM Geometry Descriptor */\r
\r
typedef union _RegDRP {\r
    UINT32    raw;\r
    struct {\r
        unsigned rank0Enabled       :1;     /**< Rank 0 Enable */\r
        unsigned rank0DevWidth      :2;     /**< DRAM Device Width (x8,x16) */\r
        unsigned rank0DevDensity    :2;     /**< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) */\r
        unsigned reserved2          :1;\r
        unsigned rank1Enabled       :1;     /**< Rank 1 Enable */\r
        unsigned reserved3          :5;\r
        unsigned dramType           :1;     /**< DRAM Type (0=DDR2) */\r
        unsigned reserved4          :5;\r
        unsigned reserved5          :14;\r
      } field;\r
} RegDRP;                                   /**< DRAM Rank Population and Interface Register */\r
\r
\r
typedef union {\r
    UINT32    raw;\r
    struct {\r
        unsigned dramFrequency      :3;     /**< DRAM Frequency (000=RESERVED,010=667,011=800) */\r
        unsigned tRP                :2;     /**< Precharge to Activate Delay (3,4,5,6) */\r
        unsigned reserved1          :1;\r
        unsigned tRCD               :2;     /**< Activate to CAS Delay (3,4,5,6) */\r
        unsigned reserved2          :1;\r
        unsigned tCL                :2;     /**< CAS Latency (3,4,5,6) */\r
        unsigned reserved3          :21;\r
      } field;\r
} RegDTR0;                                  /**< DRAM Timing Register 0 */\r
\r
typedef union {\r
    UINT32    raw;\r
    struct {\r
        unsigned tWRRD_dly          :2;     /**< Additional Write to Read Delay (0,1,2,3) */\r
        unsigned reserved1          :1;\r
        unsigned tRDWR_dly          :2;     /**< Additional Read to Write Delay (0,1,2,3) */\r
        unsigned reserved2          :1;\r
        unsigned tRDRD_dr_dly       :1;     /**< Additional Read to Read Delay (1,2) */\r
        unsigned reserved3          :1;\r
        unsigned tRD_dly            :3;     /**< Additional Read Data Sampling Delay (0-7) */\r
        unsigned reserved4          :1;\r
        unsigned tRCVEN_halfclk_dly :4;     /**< Additional RCVEN Half Clock Delay Control */\r
        unsigned reserved5          :1;\r
        unsigned readDqDelay        :2;     /**< Read DQ Delay */\r
        unsigned reserved6          :13;\r
      } field;\r
} RegDTR1;                                  /**< DRAM Timing Register 1 */\r
\r
typedef union {\r
    UINT32    raw;\r
    struct {\r
        unsigned ckStaticDisable    :1;     /**< CK/CK# Static Disable */\r
        unsigned reserved1          :3;\r
        unsigned ckeStaticDisable   :2;     /**< CKE Static Disable */\r
        unsigned reserved2          :8;\r
        unsigned refreshPeriod      :2;     /**< Refresh Period (disabled,128clks,3.9us,7.8us) */\r
        unsigned refreshQueueDepth  :2;     /**< Refresh Queue Depth (1,2,4,8) */\r
        unsigned reserved5          :13;\r
        unsigned initComplete       :1;     /**< Initialization Complete */\r
      } field;\r
} RegDCO;\r
\r
//\r
// MRC Data Structure\r
//\r
typedef struct {\r
    RegDRP          drp;\r
    RegDTR0         dtr0;\r
    RegDTR1         dtr1;\r
    RegDCO          dco;\r
    UINT32          reg0104;\r
    UINT32          reg0120;\r
    UINT32          reg0121;\r
    UINT32          reg0123;\r
    UINT32          reg0111;\r
    UINT32          reg0130;\r
    UINT8           refreshPeriod;      /**< Placeholder for the chosen refresh\r
                                         *   period.  This value will NOT be\r
                                         *   programmed into DCO until all\r
                                         *   initialization is done.\r
                                         */\r
    UINT8           ddr2Odt;            /**< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm */\r
    UINT8           sku;                /**< Detected QuarkNcSocId SKU */\r
    UINT8           capabilities;       /**< Capabilities Available on this part */\r
    UINT8           state;              /**< NORMAL_BOOT, S3_RESUME */\r
    UINT32          memSize;            /**< Memory size */\r
    UINT16          pmBase;             /**< PM Base */\r
    UINT16          mrcVersion;         /**< MRC Version */\r
    UINT32          hecbase;            /**< HECBASE shifted left 16 bits */\r
    DramGeometry    geometry;          /**< DRAM Geometry */\r
} MRC_DATA_STRUCTURE;             /**< QuarkNcSocId Memory Parameters for MRC */\r
\r
typedef struct _EFI_MEMINIT_CONFIG_DATA {\r
  MRC_DATA_STRUCTURE                        MrcData;\r
} EFI_MEMINIT_CONFIG_DATA;\r
\r
\r
\r
#endif\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	Memory controller configuration.\r
	3	\r
	4	Copyright (c) 2013-2015 Intel Corporation.\r
	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	#ifndef __DDR_MEMORY_CONTROLLER_H__\r
	16	#define __DDR_MEMORY_CONTROLLER_H__\r
	17	\r
	18	//\r
	19	// DDR timing data definitions.\r
	20	// These are used to create bitmaps of valid timing configurations.\r
	21	//\r
	22	\r
	23	#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN 0xFF\r
	24	#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF\r
	25	\r
	26	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20 0x01\r
	27	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25 0x00\r
	28	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30 0x02\r
	29	#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL 0x03\r
	30	\r
	31	\r
	32	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02 0x02\r
	33	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03 0x01\r
	34	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04 0x00\r
	35	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL 0x03\r
	36	\r
	37	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02 0x02\r
	38	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03 0x01\r
	39	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04 0x00\r
	40	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL 0x03\r
	41	\r
	42	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05 0x05\r
	43	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06 0x04\r
	44	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07 0x03\r
	45	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08 0x02\r
	46	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09 0x01\r
	47	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10 0x00\r
	48	#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL 0x07\r
	49	\r
	50	#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED 0x01\r
	51	#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED 0x02\r
	52	#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED 0x04\r
	53	#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED 0x08\r
	54	#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR 0x10\r
	55	#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR 0x20\r
	56	\r
	57	\r
	58	//\r
	59	// Maximum number of SDRAM channels supported by the memory controller\r
	60	//\r
	61	#define MAX_CHANNELS 1\r
	62	\r
	63	//\r
	64	// Maximum number of DIMM sockets supported by the memory controller\r
65	//\r
66	#define MAX_SOCKETS 1\r
67	\r
68	//\r
69	// Maximum number of sides supported per DIMM\r
70	//\r
71	#define MAX_SIDES 2\r
72	\r
73	//\r
74	// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
75	// DIMM's from the various channels\r
76	//\r
77	#define MAX_SOCKET_SETS 2\r
78	\r
79	//\r
80	// Maximum number of rows supported by the memory controller\r
81	//\r
82	#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)\r
83	\r
84	//\r
85	// Maximum number of memory ranges supported by the memory controller\r
86	//\r
87	#define MAX_RANGES (MAX_ROWS + 5)\r
88	\r
89	//\r
90	// Maximum Number of Log entries\r
91	//\r
92	#define MEMORY_LOG_MAX_INDEX 16\r
93	\r
94	\r
95	typedef struct _MEMORY_LOG_ENTRY {\r
96	EFI_STATUS_CODE_VALUE Event;\r
97	EFI_STATUS_CODE_TYPE Severity;\r
98	UINT8 Data;\r
99	} MEMORY_LOG_ENTRY;\r
100	\r
101	typedef struct _MEMORY_LOG {\r
102	UINT8 Index;\r
103	MEMORY_LOG_ENTRY Entry[MEMORY_LOG_MAX_INDEX];\r
104	} MEMORY_LOG;\r
105	\r
106	\r
107	\r
108	//\r
109	// Defined ECC types\r
110	//\r
111	#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE 0x01 // No error checking\r
112	#define DUAL_CHANNEL_DDR_ECC_TYPE_EC 0x02 // Error checking only\r
113	#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC 0x04 // Software Scrubbing ECC\r
114	#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC 0x08 // Hardware Scrubbing ECC\r
115	#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC 0x10 // Chip Kill ECC\r
116	\r
117	//\r
118	// Row configuration status values\r
119	//\r
120	#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS 0x00 // No error\r
121	#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN 0x01 // Pattern mismatch, no memory\r
122	#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED 0x02 // Memory type not supported\r
123	#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR 0x03 // Row/Col/Bnk mismatch\r
124	#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR 0x04 // Received ECC error\r
125	#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT 0x05 // Row is not present\r
126	#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED 0x06 // Row is disabled\r
127	\r
128	\r
129	//\r
130	// Memory range types\r
131	//\r
132	typedef enum {\r
133	DualChannelDdrMainMemory,\r
134	DualChannelDdrSmramCacheable,\r
135	DualChannelDdrSmramNonCacheable,\r
136	DualChannelDdrGraphicsMemoryCacheable,\r
137	DualChannelDdrGraphicsMemoryNonCacheable,\r
138	DualChannelDdrReservedMemory,\r
139	DualChannelDdrMaxMemoryRangeType\r
140	} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
141	\r
142	//\r
143	// Memory map range information\r
144	//\r
145	typedef struct {\r
146	EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
147	EFI_PHYSICAL_ADDRESS CpuAddress;\r
148	EFI_PHYSICAL_ADDRESS RangeLength;\r
149	DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r
150	} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
151	typedef struct {\r
152	unsigned dramType :1; /*< Type: 0 = RESERVED; 1 = DDR2 /\r
153	unsigned dramWidth :1; /*< Width: 0 = x8; 1 = x16 /\r
154	unsigned dramDensity :2; /*< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb /\r
155	unsigned dramSpeed :1; /*< Speed Grade: 0 = RESERVED; 1 = 800MT/s;/\r
156	unsigned dramTimings :3; /*< Timings: 4-4-4, 5-5-5, 6-6-6 /\r
157	unsigned dramRanks :1; /*< Ranks: 0 = Single Rank; 1 = Dual Rank /\r
158	} DramGeometry; /*< DRAM Geometry Descriptor /\r
159	\r
160	typedef union _RegDRP {\r
161	UINT32 raw;\r
162	struct {\r
163	unsigned rank0Enabled :1; /*< Rank 0 Enable /\r
164	unsigned rank0DevWidth :2; /*< DRAM Device Width (x8,x16) /\r
165	unsigned rank0DevDensity :2; /*< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) /\r
166	unsigned reserved2 :1;\r
167	unsigned rank1Enabled :1; /*< Rank 1 Enable /\r
168	unsigned reserved3 :5;\r
169	unsigned dramType :1; /*< DRAM Type (0=DDR2) /\r
170	unsigned reserved4 :5;\r
171	unsigned reserved5 :14;\r
172	} field;\r
173	} RegDRP; /*< DRAM Rank Population and Interface Register /\r
174	\r
175	\r
176	typedef union {\r
177	UINT32 raw;\r
178	struct {\r
179	unsigned dramFrequency :3; /*< DRAM Frequency (000=RESERVED,010=667,011=800) /\r
180	unsigned tRP :2; /*< Precharge to Activate Delay (3,4,5,6) /\r
181	unsigned reserved1 :1;\r
182	unsigned tRCD :2; /*< Activate to CAS Delay (3,4,5,6) /\r
183	unsigned reserved2 :1;\r
184	unsigned tCL :2; /*< CAS Latency (3,4,5,6) /\r
185	unsigned reserved3 :21;\r
186	} field;\r
187	} RegDTR0; /*< DRAM Timing Register 0 /\r
188	\r
189	typedef union {\r
190	UINT32 raw;\r
191	struct {\r
192	unsigned tWRRD_dly :2; /*< Additional Write to Read Delay (0,1,2,3) /\r
193	unsigned reserved1 :1;\r
194	unsigned tRDWR_dly :2; /*< Additional Read to Write Delay (0,1,2,3) /\r
195	unsigned reserved2 :1;\r
196	unsigned tRDRD_dr_dly :1; /*< Additional Read to Read Delay (1,2) /\r
197	unsigned reserved3 :1;\r
198	unsigned tRD_dly :3; /*< Additional Read Data Sampling Delay (0-7) /\r
199	unsigned reserved4 :1;\r
200	unsigned tRCVEN_halfclk_dly :4; /*< Additional RCVEN Half Clock Delay Control /\r
201	unsigned reserved5 :1;\r
202	unsigned readDqDelay :2; /*< Read DQ Delay /\r
203	unsigned reserved6 :13;\r
204	} field;\r
205	} RegDTR1; /*< DRAM Timing Register 1 /\r
206	\r
207	typedef union {\r
208	UINT32 raw;\r
209	struct {\r
210	unsigned ckStaticDisable :1; /*< CK/CK# Static Disable /\r
211	unsigned reserved1 :3;\r
212	unsigned ckeStaticDisable :2; /*< CKE Static Disable /\r
213	unsigned reserved2 :8;\r
214	unsigned refreshPeriod :2; /*< Refresh Period (disabled,128clks,3.9us,7.8us) /\r
215	unsigned refreshQueueDepth :2; /*< Refresh Queue Depth (1,2,4,8) /\r
216	unsigned reserved5 :13;\r
217	unsigned initComplete :1; /*< Initialization Complete /\r
218	} field;\r
219	} RegDCO;\r
220	\r
221	//\r
222	// MRC Data Structure\r
223	//\r
224	typedef struct {\r
225	RegDRP drp;\r
226	RegDTR0 dtr0;\r
227	RegDTR1 dtr1;\r
228	RegDCO dco;\r
229	UINT32 reg0104;\r
230	UINT32 reg0120;\r
231	UINT32 reg0121;\r
232	UINT32 reg0123;\r
233	UINT32 reg0111;\r
234	UINT32 reg0130;\r
235	UINT8 refreshPeriod; /**< Placeholder for the chosen refresh\r
236	* period. This value will NOT be\r
237	* programmed into DCO until all\r
238	* initialization is done.\r
239	*/\r
240	UINT8 ddr2Odt; /*< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm /\r
241	UINT8 sku; /*< Detected QuarkNcSocId SKU /\r
242	UINT8 capabilities; /*< Capabilities Available on this part /\r
243	UINT8 state; /*< NORMAL_BOOT, S3_RESUME /\r
244	UINT32 memSize; /*< Memory size /\r
245	UINT16 pmBase; /*< PM Base /\r
246	UINT16 mrcVersion; /*< MRC Version /\r
247	UINT32 hecbase; /*< HECBASE shifted left 16 bits /\r
248	DramGeometry geometry; /*< DRAM Geometry /\r
249	} MRC_DATA_STRUCTURE; /*< QuarkNcSocId Memory Parameters for MRC /\r
250	\r
251	typedef struct _EFI_MEMINIT_CONFIG_DATA {\r
252	MRC_DATA_STRUCTURE MrcData;\r
253	} EFI_MEMINIT_CONFIG_DATA;\r
254	\r
255	\r
256	\r
257	#endif\r