projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 9b6bbcdb MK |
1 | /** @file\r |
| 2 | Some configuration of QNC Package\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 5 | \r | |
| c9f231d0 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 9b6bbcdb MK |
7 | \r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | #ifndef __INTEL_QNC_CONFIG_H__\r | |
| 11 | #define __INTEL_QNC_CONFIG_H__\r | |
| 12 | \r | |
| 13 | //\r | |
| 14 | // QNC Fixed configurations.\r | |
| 15 | //\r | |
| 16 | \r | |
| 17 | //\r | |
| 18 | // Memory arbiter fixed config values.\r | |
| 19 | //\r | |
| 20 | #define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\\r | |
| 21 | (ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \\r | |
| 22 | (ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \\r | |
| 23 | (ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \\r | |
| 24 | (ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \\r | |
| 25 | ))\r | |
| 26 | \r | |
| 27 | //\r | |
| 28 | // Memory Manager fixed config values.\r | |
| 29 | //\r | |
| 30 | #define V_DRAM_NON_HOST_RQ_LIMIT 2\r | |
| 31 | \r | |
| 32 | //\r | |
| 33 | // RMU Thermal config fixed config values for TS in Vref Mode.\r | |
| 34 | //\r | |
| 35 | #define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04\r | |
| 36 | #define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01\r | |
| 37 | #define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1\r | |
| 38 | #define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b\r | |
| 39 | #define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34\r | |
| 40 | \r | |
| 41 | //\r | |
| 42 | // RMU Thermal config fixed config values for TS in Ratiometric mode.\r | |
| 43 | //\r | |
| 44 | #define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04\r | |
| 45 | #define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02\r | |
| 46 | #define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1\r | |
| 47 | #define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f\r | |
| 48 | #define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001\r | |
| 49 | #define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01\r | |
| 50 | #define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00\r | |
| 51 | #define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0\r | |
| 52 | #define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0\r | |
| 53 | #define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8\r | |
| 54 | #define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17\r | |
| 55 | \r | |
| 56 | //\r | |
| 57 | // iCLK fixed config values.\r | |
| 58 | //\r | |
| 59 | #define V_MUXTOP_FLEX2 3\r | |
| 60 | #define V_MUXTOP_FLEX1 1\r | |
| 61 | \r | |
| 62 | //\r | |
| 63 | // PCIe Root Port fixed config values.\r | |
| 64 | //\r | |
| 65 | #define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)\r | |
| 66 | \r | |
| 67 | //\r | |
| 68 | // QNC structures for configuration.\r | |
| 69 | //\r | |
| 70 | \r | |
| 71 | typedef union {\r | |
| 72 | struct {\r | |
| 73 | UINT32 PortErrorMask :8;\r | |
| 74 | UINT32 SlotImplemented :1;\r | |
| 75 | UINT32 Reserved1 :1;\r | |
| 76 | UINT32 AspmEnable :1;\r | |
| 77 | UINT32 AspmAutoEnable :1;\r | |
| 78 | UINT32 AspmL0sEnable :2;\r | |
| 79 | UINT32 AspmL1Enable :1;\r | |
| 80 | UINT32 PmeInterruptEnable :1;\r | |
| 81 | UINT32 PhysicalSlotNumber :13;\r | |
| 82 | UINT32 Reserved2 :1;\r | |
| 83 | UINT32 PmSciEnable :1;\r | |
| 84 | UINT32 HotplugSciEnable :1;\r | |
| 85 | } Bits;\r | |
| 86 | UINT32 Uint32;\r | |
| 87 | } PCIEXP_ROOT_PORT_CONFIGURATION;\r | |
| 88 | \r | |
| 89 | typedef union {\r | |
| 90 | UINT32 Uint32;\r | |
| 91 | struct {\r | |
| 92 | UINT32 Pcie_0 :1; // 0: Disabled; 1: Enabled*\r | |
| 93 | UINT32 Pcie_1 :1; // 0: Disabled; 1: Enabled*\r | |
| 94 | UINT32 Smbus :1; // 0: Disabled; 1: Enabled*\r | |
| 95 | UINT32 Rsvd :29; // 0\r | |
| 96 | } Bits;\r | |
| 97 | } QNC_DEVICE_ENABLES;\r | |
| 98 | \r | |
| 99 | #endif\r | |
| 100 | \r |