[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / Protocol / Spi.h

/** @file\r
This file defines the EFI SPI Protocol which implements the\r
Intel(R) ICH SPI Host Controller Compatibility Interface.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
\r
**/\r
#ifndef _SPI_H_\r
#define _SPI_H_\r
\r
//\r
// Define the SPI protocol GUID\r
//\r
// EDK and EDKII have different GUID formats\r
//\r
#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)\r
#define EFI_SPI_PROTOCOL_GUID \\r
  { \\r
    0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
  }\r
#define EFI_SMM_SPI_PROTOCOL_GUID \\r
  { \\r
    0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
  }\r
#else\r
#define EFI_SPI_PROTOCOL_GUID \\r
  { \\r
    0x1156efc6, 0xea32, 0x4396, \\r
    { \\r
      0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
    } \\r
  }\r
#define EFI_SMM_SPI_PROTOCOL_GUID \\r
  { \\r
    0xD9072C35, 0xEB8F, 0x43ad, \\r
    { \\r
      0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
    } \\r
  }\r
#endif\r
//\r
// Extern the GUID for protocol users.\r
//\r
extern EFI_GUID                   gEfiSpiProtocolGuid;\r
extern EFI_GUID                   gEfiSmmSpiProtocolGuid;\r
\r
//\r
// Forward reference for ANSI C compatibility\r
//\r
typedef struct _EFI_SPI_PROTOCOL  EFI_SPI_PROTOCOL;\r
\r
//\r
// SPI protocol data structures and definitions\r
//\r
//\r
// Number of Prefix Opcodes allowed on the SPI interface\r
//\r
#define SPI_NUM_PREFIX_OPCODE 2\r
\r
//\r
// Number of Opcodes in the Opcode Menu\r
//\r
#define SPI_NUM_OPCODE  8\r
\r
#ifdef SERVER_BIOS_FLAG\r
//\r
// SPI default opcode slots\r
//\r
#define SPI_OPCODE_JEDEC_ID_INDEX        0\r
#endif // SERVER_BIOS_FLAG\r
\r
//\r
// Opcode Type\r
//    EnumSpiOpcodeCommand: Command without address\r
//    EnumSpiOpcodeRead: Read with address\r
//    EnumSpiOpcodeWrite: Write with address\r
//\r
typedef enum {\r
  EnumSpiOpcodeReadNoAddr,\r
  EnumSpiOpcodeWriteNoAddr,\r
  EnumSpiOpcodeRead,\r
  EnumSpiOpcodeWrite,\r
  EnumSpiOpcodeMax\r
} SPI_OPCODE_TYPE;\r
\r
typedef enum {\r
  EnumSpiCycle20MHz,\r
  EnumSpiCycle33MHz,\r
  EnumSpiCycle66MHz,  // not supported by PCH\r
  EnumSpiCycle50MHz,\r
  EnumSpiCycleMax\r
} SPI_CYCLE_FREQUENCY;\r
\r
typedef enum {\r
  EnumSpiRegionAll,\r
  EnumSpiRegionBios,\r
  EnumSpiRegionMe,\r
  EnumSpiRegionGbE,\r
  EnumSpiRegionDescriptor,\r
  EnumSpiRegionPlatformData,\r
  EnumSpiRegionMax\r
} SPI_REGION_TYPE;\r
\r
//\r
// Hardware Sequencing required operations (as listed in CougarPoint EDS Table 5-55: "Hardware\r
// Sequencing Commands and Opcode Requirements"\r
//\r
typedef enum {\r
  EnumSpiOperationWriteStatus,\r
  EnumSpiOperationProgramData_1_Byte,\r
  EnumSpiOperationProgramData_64_Byte,\r
  EnumSpiOperationReadData,\r
  EnumSpiOperationWriteDisable,\r
  EnumSpiOperationReadStatus,\r
  EnumSpiOperationWriteEnable,\r
  EnumSpiOperationFastRead,\r
  EnumSpiOperationEnableWriteStatus,\r
  EnumSpiOperationErase_256_Byte,\r
  EnumSpiOperationErase_4K_Byte,\r
  EnumSpiOperationErase_8K_Byte,\r
  EnumSpiOperationErase_64K_Byte,\r
  EnumSpiOperationFullChipErase,\r
  EnumSpiOperationJedecId,\r
  EnumSpiOperationDualOutputFastRead,\r
  EnumSpiOperationDiscoveryParameters,\r
  EnumSpiOperationOther,\r
  EnumSpiOperationMax\r
} SPI_OPERATION;\r
\r
//\r
// Opcode menu entries\r
//   Type            Operation Type (value to be programmed to the OPTYPE register)\r
//   Code            The opcode (value to be programmed to the OPMENU register)\r
//   Frequency       The expected frequency to be used (value to be programmed to the SSFC\r
//                   Register)\r
//   Operation       Which Hardware Sequencing required operation this opcode respoinds to.\r
//                   The required operations are listed in EDS Table 5-55: "Hardware\r
//                   Sequencing Commands and Opcode Requirements"\r
//                   If the opcode does not corresponds to any operation listed, use\r
//                   EnumSpiOperationOther\r
//\r
typedef struct _SPI_OPCODE_MENU_ENTRY {\r
  SPI_OPCODE_TYPE     Type;\r
  UINT8               Code;\r
  SPI_CYCLE_FREQUENCY Frequency;\r
  SPI_OPERATION       Operation;\r
} SPI_OPCODE_MENU_ENTRY;\r
\r
//\r
// Initialization data table loaded to the SPI host controller\r
//    VendorId        Vendor ID of the SPI device\r
//    DeviceId0       Device ID0 of the SPI device\r
//    DeviceId1       Device ID1 of the SPI device\r
//    PrefixOpcode    Prefix opcodes which are loaded into the SPI host controller\r
//    OpcodeMenu      Opcodes which are loaded into the SPI host controller Opcode Menu\r
//    BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
//                    Please note this is a Flash Linear Address, NOT a memory space address.\r
//                    This value is platform specific and depends on the system flash map.\r
//                    This value is only used on non Descriptor mode.\r
//    BiosSize        The the BIOS Image size in flash. This value is platform specific\r
//                    and depends on the system flash map. Please note BIOS Image size may\r
//                    be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
//                    (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
//                    placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
//                    (in Non Descriptor Mode)\r
//\r
typedef struct _SPI_INIT_TABLE {\r
  UINT8                 VendorId;\r
  UINT8                 DeviceId0;\r
  UINT8                 DeviceId1;\r
  UINT8                 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
  SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
  UINTN                 BiosStartOffset;\r
  UINTN                 BiosSize;\r
} SPI_INIT_TABLE;\r
\r
//\r
// Public Info struct to show current initialized state of the spi interface.\r
// OpcodeIndex must be less then SPI_NUM_OPCODE for operation to be supported.\r
//\r
typedef struct _SPI_INIT_INFO {\r
  SPI_INIT_TABLE        *InitTable;\r
  UINT8                 JedecIdOpcodeIndex;\r
  UINT8                 OtherOpcodeIndex;\r
  UINT8                 WriteStatusOpcodeIndex;\r
  UINT8                 ProgramOpcodeIndex;\r
  UINT8                 ReadOpcodeIndex;\r
  UINT8                 EraseOpcodeIndex;\r
  UINT8                 ReadStatusOpcodeIndex;\r
  UINT8                 FullChipEraseOpcodeIndex;\r
} SPI_INIT_INFO;\r
\r
//\r
// Protocol member functions\r
//\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_INIT) (\r
  IN EFI_SPI_PROTOCOL     * This,\r
  IN SPI_INIT_TABLE       * InitTable\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Initializes the host controller to execute SPI commands.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitTable               Pointer to caller-allocated buffer containing the SPI\r
                          interface initialization table.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Opcode initialization on the SPI host controller completed.\r
  EFI_ACCESS_DENIED       The SPI configuration interface is locked.\r
  EFI_OUT_OF_RESOURCES    Not enough resource available to initialize the device.\r
  EFI_DEVICE_ERROR        Device error, operation failed.\r
\r
--*/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_LOCK) (\r
  IN EFI_SPI_PROTOCOL     * This\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Lock the SPI Static Configuration Interface.\r
  Once locked, the interface is no longer open for configuration changes.\r
  The lock state automatically clears on next system reset.\r
\r
Arguments:\r
\r
  This      Pointer to the EFI_SPI_PROTOCOL instance.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Lock operation succeed.\r
  EFI_DEVICE_ERROR        Device error, operation failed.\r
  EFI_ACCESS_DENIED       The interface has already been locked.\r
\r
--*/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_EXECUTE) (\r
  IN     EFI_SPI_PROTOCOL   * This,\r
  IN     UINT8              OpcodeIndex,\r
  IN     UINT8              PrefixOpcodeIndex,\r
  IN     BOOLEAN            DataCycle,\r
  IN     BOOLEAN            Atomic,\r
  IN     BOOLEAN            ShiftOut,\r
  IN     UINTN              Address,\r
  IN     UINT32             DataByteCount,\r
  IN OUT UINT8              *Buffer,\r
  IN     SPI_REGION_TYPE    SpiRegionType\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Execute SPI commands from the host controller.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  OpcodeIndex             Index of the command in the OpCode Menu.\r
  PrefixOpcodeIndex       Index of the first command to run when in an atomic cycle sequence.\r
  DataCycle               TRUE if the SPI cycle contains data\r
  Atomic                  TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
  ShiftOut                If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
  Address                 In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                          Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                          this value specifies the offset from the start of the BIOS Image. In Non\r
                          Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                          Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                          Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                          supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                          the flash (in Non Descriptor Mode)\r
  DataByteCount           Number of bytes in the data portion of the SPI cycle.\r
  Buffer                  Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
  SpiRegionType           SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                          EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                          Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                          and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                          to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
\r
Returns:\r
\r
  EFI_SUCCESS             Command succeed.\r
  EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
  EFI_UNSUPPORTED         Command not supported.\r
  EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
\r
--*/\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SPI_INFO) (\r
  IN EFI_SPI_PROTOCOL     *This,\r
  OUT SPI_INIT_INFO      **InitInfoPtr\r
  );\r
/*++\r
\r
Routine Description:\r
\r
  Return info about SPI host controller, to help callers usage of Execute\r
  service.\r
\r
  If 0xff is returned as an opcode index in init info struct\r
  then device does not support the operation.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitInfoPtr             Pointer to init info written to this memory location.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Information returned.\r
  EFI_INVALID_PARAMETER   Invalid parameter.\r
  EFI_NOT_READY           Required resources not setup.\r
  Others                  Unexpected error happened.\r
\r
--*/\r
\r
//\r
// Protocol definition\r
//\r
struct _EFI_SPI_PROTOCOL {\r
  EFI_SPI_INIT    Init;\r
  EFI_SPI_LOCK    Lock;\r
  EFI_SPI_EXECUTE Execute;\r
  EFI_SPI_INFO    Info;\r
};\r
\r
#endif\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	This file defines the EFI SPI Protocol which implements the\r
	3	Intel(R) ICH SPI Host Controller Compatibility Interface.\r
	4	\r
	5	Copyright (c) 2013-2015 Intel Corporation.\r
	6	\r
	7	This program and the accompanying materials\r
	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	\r
	16	**/\r
	17	#ifndef _SPI_H_\r
	18	#define _SPI_H_\r
	19	\r
	20	//\r
	21	// Define the SPI protocol GUID\r
	22	//\r
	23	// EDK and EDKII have different GUID formats\r
	24	//\r
	25	#if !defined(EDK_RELEASE_VERSION) \|\| (EDK_RELEASE_VERSION < 0x00020000)\r
	26	#define EFI_SPI_PROTOCOL_GUID \\r
	27	{ \\r
	28	0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
	29	}\r
	30	#define EFI_SMM_SPI_PROTOCOL_GUID \\r
	31	{ \\r
	32	0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
	33	}\r
	34	#else\r
	35	#define EFI_SPI_PROTOCOL_GUID \\r
	36	{ \\r
	37	0x1156efc6, 0xea32, 0x4396, \\r
	38	{ \\r
	39	0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
	40	} \\r
	41	}\r
	42	#define EFI_SMM_SPI_PROTOCOL_GUID \\r
	43	{ \\r
	44	0xD9072C35, 0xEB8F, 0x43ad, \\r
	45	{ \\r
	46	0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
	47	} \\r
	48	}\r
	49	#endif\r
	50	//\r
	51	// Extern the GUID for protocol users.\r
	52	//\r
	53	extern EFI_GUID gEfiSpiProtocolGuid;\r
	54	extern EFI_GUID gEfiSmmSpiProtocolGuid;\r
	55	\r
	56	//\r
	57	// Forward reference for ANSI C compatibility\r
	58	//\r
	59	typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;\r
	60	\r
	61	//\r
	62	// SPI protocol data structures and definitions\r
	63	//\r
	64	//\r
65	// Number of Prefix Opcodes allowed on the SPI interface\r
66	//\r
67	#define SPI_NUM_PREFIX_OPCODE 2\r
68	\r
69	//\r
70	// Number of Opcodes in the Opcode Menu\r
71	//\r
72	#define SPI_NUM_OPCODE 8\r
73	\r
74	#ifdef SERVER_BIOS_FLAG\r
75	//\r
76	// SPI default opcode slots\r
77	//\r
78	#define SPI_OPCODE_JEDEC_ID_INDEX 0\r
79	#endif // SERVER_BIOS_FLAG\r
80	\r
81	//\r
82	// Opcode Type\r
83	// EnumSpiOpcodeCommand: Command without address\r
84	// EnumSpiOpcodeRead: Read with address\r
85	// EnumSpiOpcodeWrite: Write with address\r
86	//\r
87	typedef enum {\r
88	EnumSpiOpcodeReadNoAddr,\r
89	EnumSpiOpcodeWriteNoAddr,\r
90	EnumSpiOpcodeRead,\r
91	EnumSpiOpcodeWrite,\r
92	EnumSpiOpcodeMax\r
93	} SPI_OPCODE_TYPE;\r
94	\r
95	typedef enum {\r
96	EnumSpiCycle20MHz,\r
97	EnumSpiCycle33MHz,\r
98	EnumSpiCycle66MHz, // not supported by PCH\r
99	EnumSpiCycle50MHz,\r
100	EnumSpiCycleMax\r
101	} SPI_CYCLE_FREQUENCY;\r
102	\r
103	typedef enum {\r
104	EnumSpiRegionAll,\r
105	EnumSpiRegionBios,\r
106	EnumSpiRegionMe,\r
107	EnumSpiRegionGbE,\r
108	EnumSpiRegionDescriptor,\r
109	EnumSpiRegionPlatformData,\r
110	EnumSpiRegionMax\r
111	} SPI_REGION_TYPE;\r
112	\r
113	//\r
114	// Hardware Sequencing required operations (as listed in CougarPoint EDS Table 5-55: "Hardware\r
115	// Sequencing Commands and Opcode Requirements"\r
116	//\r
117	typedef enum {\r
118	EnumSpiOperationWriteStatus,\r
119	EnumSpiOperationProgramData_1_Byte,\r
120	EnumSpiOperationProgramData_64_Byte,\r
121	EnumSpiOperationReadData,\r
122	EnumSpiOperationWriteDisable,\r
123	EnumSpiOperationReadStatus,\r
124	EnumSpiOperationWriteEnable,\r
125	EnumSpiOperationFastRead,\r
126	EnumSpiOperationEnableWriteStatus,\r
127	EnumSpiOperationErase_256_Byte,\r
128	EnumSpiOperationErase_4K_Byte,\r
129	EnumSpiOperationErase_8K_Byte,\r
130	EnumSpiOperationErase_64K_Byte,\r
131	EnumSpiOperationFullChipErase,\r
132	EnumSpiOperationJedecId,\r
133	EnumSpiOperationDualOutputFastRead,\r
134	EnumSpiOperationDiscoveryParameters,\r
135	EnumSpiOperationOther,\r
136	EnumSpiOperationMax\r
137	} SPI_OPERATION;\r
138	\r
139	//\r
140	// Opcode menu entries\r
141	// Type Operation Type (value to be programmed to the OPTYPE register)\r
142	// Code The opcode (value to be programmed to the OPMENU register)\r
143	// Frequency The expected frequency to be used (value to be programmed to the SSFC\r
144	// Register)\r
145	// Operation Which Hardware Sequencing required operation this opcode respoinds to.\r
146	// The required operations are listed in EDS Table 5-55: "Hardware\r
147	// Sequencing Commands and Opcode Requirements"\r
148	// If the opcode does not corresponds to any operation listed, use\r
149	// EnumSpiOperationOther\r
150	//\r
151	typedef struct _SPI_OPCODE_MENU_ENTRY {\r
152	SPI_OPCODE_TYPE Type;\r
153	UINT8 Code;\r
154	SPI_CYCLE_FREQUENCY Frequency;\r
155	SPI_OPERATION Operation;\r
156	} SPI_OPCODE_MENU_ENTRY;\r
157	\r
158	//\r
159	// Initialization data table loaded to the SPI host controller\r
160	// VendorId Vendor ID of the SPI device\r
161	// DeviceId0 Device ID0 of the SPI device\r
162	// DeviceId1 Device ID1 of the SPI device\r
163	// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller\r
164	// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu\r
165	// BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
166	// Please note this is a Flash Linear Address, NOT a memory space address.\r
167	// This value is platform specific and depends on the system flash map.\r
168	// This value is only used on non Descriptor mode.\r
169	// BiosSize The the BIOS Image size in flash. This value is platform specific\r
170	// and depends on the system flash map. Please note BIOS Image size may\r
171	// be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
172	// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
173	// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
174	// (in Non Descriptor Mode)\r
175	//\r
176	typedef struct _SPI_INIT_TABLE {\r
177	UINT8 VendorId;\r
178	UINT8 DeviceId0;\r
179	UINT8 DeviceId1;\r
180	UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
181	SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
182	UINTN BiosStartOffset;\r
183	UINTN BiosSize;\r
184	} SPI_INIT_TABLE;\r
185	\r
186	//\r
187	// Public Info struct to show current initialized state of the spi interface.\r
188	// OpcodeIndex must be less then SPI_NUM_OPCODE for operation to be supported.\r
189	//\r
190	typedef struct _SPI_INIT_INFO {\r
191	SPI_INIT_TABLE *InitTable;\r
192	UINT8 JedecIdOpcodeIndex;\r
193	UINT8 OtherOpcodeIndex;\r
194	UINT8 WriteStatusOpcodeIndex;\r
195	UINT8 ProgramOpcodeIndex;\r
196	UINT8 ReadOpcodeIndex;\r
197	UINT8 EraseOpcodeIndex;\r
198	UINT8 ReadStatusOpcodeIndex;\r
199	UINT8 FullChipEraseOpcodeIndex;\r
200	} SPI_INIT_INFO;\r
201	\r
202	//\r
203	// Protocol member functions\r
204	//\r
205	\r
206	typedef\r
207	EFI_STATUS\r
208	(EFIAPI *EFI_SPI_INIT) (\r
209	IN EFI_SPI_PROTOCOL * This,\r
210	IN SPI_INIT_TABLE * InitTable\r
211	);\r
212	/*++\r
213	\r
214	Routine Description:\r
215	\r
216	Initializes the host controller to execute SPI commands.\r
217	\r
218	Arguments:\r
219	\r
220	This Pointer to the EFI_SPI_PROTOCOL instance.\r
221	InitTable Pointer to caller-allocated buffer containing the SPI\r
222	interface initialization table.\r
223	\r
224	Returns:\r
225	\r
226	EFI_SUCCESS Opcode initialization on the SPI host controller completed.\r
227	EFI_ACCESS_DENIED The SPI configuration interface is locked.\r
228	EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.\r
229	EFI_DEVICE_ERROR Device error, operation failed.\r
230	\r
231	--*/\r
232	\r
233	typedef\r
234	EFI_STATUS\r
235	(EFIAPI *EFI_SPI_LOCK) (\r
236	IN EFI_SPI_PROTOCOL * This\r
237	);\r
238	/*++\r
239	\r
240	Routine Description:\r
241	\r
242	Lock the SPI Static Configuration Interface.\r
243	Once locked, the interface is no longer open for configuration changes.\r
244	The lock state automatically clears on next system reset.\r
245	\r
246	Arguments:\r
247	\r
248	This Pointer to the EFI_SPI_PROTOCOL instance.\r
249	\r
250	Returns:\r
251	\r
252	EFI_SUCCESS Lock operation succeed.\r
253	EFI_DEVICE_ERROR Device error, operation failed.\r
254	EFI_ACCESS_DENIED The interface has already been locked.\r
255	\r
256	--*/\r
257	\r
258	typedef\r
259	EFI_STATUS\r
260	(EFIAPI *EFI_SPI_EXECUTE) (\r
261	IN EFI_SPI_PROTOCOL * This,\r
262	IN UINT8 OpcodeIndex,\r
263	IN UINT8 PrefixOpcodeIndex,\r
264	IN BOOLEAN DataCycle,\r
265	IN BOOLEAN Atomic,\r
266	IN BOOLEAN ShiftOut,\r
267	IN UINTN Address,\r
268	IN UINT32 DataByteCount,\r
269	IN OUT UINT8 *Buffer,\r
270	IN SPI_REGION_TYPE SpiRegionType\r
271	);\r
272	/*++\r
273	\r
274	Routine Description:\r
275	\r
276	Execute SPI commands from the host controller.\r
277	\r
278	Arguments:\r
279	\r
280	This Pointer to the EFI_SPI_PROTOCOL instance.\r
281	OpcodeIndex Index of the command in the OpCode Menu.\r
282	PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
283	DataCycle TRUE if the SPI cycle contains data\r
284	Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
285	ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
286	Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
287	Region, this value specifies the offset from the Region Base; for BIOS Region,\r
288	this value specifies the offset from the start of the BIOS Image. In Non\r
289	Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
290	Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
291	Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
292	supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
293	the flash (in Non Descriptor Mode)\r
294	DataByteCount Number of bytes in the data portion of the SPI cycle.\r
295	Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
296	SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
297	EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
298	Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
299	and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
300	to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
301	\r
302	Returns:\r
303	\r
304	EFI_SUCCESS Command succeed.\r
305	EFI_INVALID_PARAMETER The parameters specified are not valid.\r
306	EFI_UNSUPPORTED Command not supported.\r
307	EFI_DEVICE_ERROR Device error, command aborts abnormally.\r
308	\r
309	--*/\r
310	\r
311	typedef\r
312	EFI_STATUS\r
313	(EFIAPI *EFI_SPI_INFO) (\r
314	IN EFI_SPI_PROTOCOL *This,\r
315	OUT SPI_INIT_INFO **InitInfoPtr\r
316	);\r
317	/*++\r
318	\r
319	Routine Description:\r
320	\r
321	Return info about SPI host controller, to help callers usage of Execute\r
322	service.\r
323	\r
324	If 0xff is returned as an opcode index in init info struct\r
325	then device does not support the operation.\r
326	\r
327	Arguments:\r
328	\r
329	This Pointer to the EFI_SPI_PROTOCOL instance.\r
330	InitInfoPtr Pointer to init info written to this memory location.\r
331	\r
332	Returns:\r
333	\r
334	EFI_SUCCESS Information returned.\r
335	EFI_INVALID_PARAMETER Invalid parameter.\r
336	EFI_NOT_READY Required resources not setup.\r
337	Others Unexpected error happened.\r
338	\r
339	--*/\r
340	\r
341	//\r
342	// Protocol definition\r
343	//\r
344	struct _EFI_SPI_PROTOCOL {\r
345	EFI_SPI_INIT Init;\r
346	EFI_SPI_LOCK Lock;\r
347	EFI_SPI_EXECUTE Execute;\r
348	EFI_SPI_INFO Info;\r
349	};\r
350	\r
351	#endif\r