[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / QNCAccess.h

/** @file\r
Macros to simplify and abstract the interface to PCI configuration.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
**/\r
\r
#ifndef _QNC_ACCESS_H_\r
#define _QNC_ACCESS_H_\r
\r
#include "QuarkNcSocId.h"\r
#include "QNCCommonDefinitions.h"\r
\r
#define EFI_LPC_PCI_ADDRESS( Register ) \\r
  EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register)\r
\r
//\r
// QNC Controller PCI access macros\r
//\r
#define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0, PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK)\r
\r
//\r
// Device 0x1f, Function 0\r
//\r
\r
#define LpcPciCfg32( Register ) \\r
  QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
\r
#define LpcPciCfg32Or( Register, OrData ) \\r
  QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
\r
#define LpcPciCfg32And( Register, AndData ) \\r
  QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
\r
#define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \\r
  QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
\r
#define LpcPciCfg16( Register ) \\r
  QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
\r
#define LpcPciCfg16Or( Register, OrData ) \\r
  QNCMmPci16Or(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
\r
#define LpcPciCfg16And( Register, AndData ) \\r
  QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
\r
#define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \\r
  QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
\r
#define LpcPciCfg8( Register ) \\r
  QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
\r
#define LpcPciCfg8Or( Register, OrData ) \\r
  QNCMmPci8Or(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
\r
#define LpcPciCfg8And( Register, AndData ) \\r
  QNCMmPci8And(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
\r
#define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \\r
  QNCMmPci8AndThenOr(  0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
\r
//\r
// Root Complex Register Block\r
//\r
\r
#define MmRcrb32( Register ) \\r
  QNCMmio32( QNC_RCRB_BASE, Register )\r
\r
#define MmRcrb32Or( Register, OrData ) \\r
  QNCMmio32Or( QNC_RCRB_BASE, Register, OrData )\r
\r
#define MmRcrb32And( Register, AndData ) \\r
  QNCMmio32And( QNC_RCRB_BASE, Register, AndData )\r
\r
#define MmRcrb32AndThenOr( Register, AndData, OrData ) \\r
  QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
\r
#define MmRcrb16( Register ) \\r
  QNCMmio16( QNC_RCRB_BASE, Register )\r
\r
#define MmRcrb16Or( Register, OrData ) \\r
  QNCMmio16Or( QNC_RCRB_BASE, Register, OrData )\r
\r
#define MmRcrb16And( Register, AndData ) \\r
  QNCMmio16And( QNC_RCRB_BASE, Register, AndData )\r
\r
#define MmRcrb16AndThenOr( Register, AndData, OrData ) \\r
  QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
\r
#define MmRcrb8( Register ) \\r
  QNCMmio8( QNC_RCRB_BASE, Register )\r
\r
#define MmRcrb8Or( Register, OrData ) \\r
  QNCMmio8Or( QNC_RCRB_BASE, Register, OrData )\r
\r
#define MmRcrb8And( Register, AndData ) \\r
  QNCMmio8And( QNC_RCRB_BASE, Register, AndData )\r
\r
#define MmRcrb8AndThenOr( Register, AndData, OrData ) \\r
  QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
\r
//\r
// Memory Controller PCI access macros\r
//\r
\r
//\r
// Device 0, Function 0\r
//\r
\r
#define McD0PciCfg64(Register)                              QNCMmPci32           (0, MC_BUS, 0, 0, Register)\r
#define McD0PciCfg64Or(Register, OrData)                    QNCMmPci32Or         (0, MC_BUS, 0, 0, Register, OrData)\r
#define McD0PciCfg64And(Register, AndData)                  QNCMmPci32And        (0, MC_BUS, 0, 0, Register, AndData)\r
#define McD0PciCfg64AndThenOr(Register, AndData, OrData)    QNCMmPci32AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
\r
#define McD0PciCfg32(Register)                              QNCMmPci32           (0, MC_BUS, 0, 0, Register)\r
#define McD0PciCfg32Or(Register, OrData)                    QNCMmPci32Or         (0, MC_BUS, 0, 0, Register, OrData)\r
#define McD0PciCfg32And(Register, AndData)                  QNCMmPci32And        (0, MC_BUS, 0, 0, Register, AndData)\r
#define McD0PciCfg32AndThenOr(Register, AndData, OrData)    QNCMmPci32AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
\r
#define McD0PciCfg16(Register)                              QNCMmPci16           (0, MC_BUS, 0, 0, Register)\r
#define McD0PciCfg16Or(Register, OrData)                    QNCMmPci16Or         (0, MC_BUS, 0, 0, Register, OrData)\r
#define McD0PciCfg16And(Register, AndData)                  QNCMmPci16And        (0, MC_BUS, 0, 0, Register, AndData)\r
#define McD0PciCfg16AndThenOr(Register, AndData, OrData)    QNCMmPci16AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
\r
#define McD0PciCfg8(Register)                               QNCMmPci8            (0, MC_BUS, 0, 0, Register)\r
#define McD0PciCfg8Or(Register, OrData)                     QNCMmPci8Or          (0, MC_BUS, 0, 0, Register, OrData)\r
#define McD0PciCfg8And(Register, AndData)                   QNCMmPci8And         (0, MC_BUS, 0, 0, Register, AndData)\r
#define McD0PciCfg8AndThenOr( Register, AndData, OrData )   QNCMmPci8AndThenOr   (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
\r
\r
//\r
// Memory Controller Hub Memory Mapped IO register access ???\r
//\r
#define MCH_REGION_BASE                     (McD0PciCfg64 (MC_MCHBAR_OFFSET) & ~BIT0)\r
#define McMmioAddress(Register)             ((UINTN) MCH_REGION_BASE + (UINTN) (Register))\r
\r
#define McMmio32Ptr(Register)               ((volatile UINT32*) McMmioAddress (Register))\r
#define McMmio64Ptr(Register)               ((volatile UINT64*) McMmioAddress (Register))\r
\r
#define McMmio64(Register)                            *McMmio64Ptr( Register )\r
#define McMmio64Or(Register, OrData)                  (McMmio64 (Register) |= (UINT64)(OrData))\r
#define McMmio64And(Register, AndData)                (McMmio64 (Register) &= (UINT64)(AndData))\r
#define McMmio64AndThenOr(Register, AndData, OrData)  (McMmio64 ( Register ) = (McMmio64( Register ) & (UINT64)(AndData)) | (UINT64)(OrData))\r
\r
#define McMmio32(Register)                            *McMmio32Ptr (Register)\r
#define McMmio32Or(Register, OrData)                  (McMmio32 (Register) |= (UINT32)(OrData))\r
#define McMmio32And(Register, AndData)                (McMmio32 (Register) &= (UINT32)(AndData))\r
#define McMmio32AndThenOr(Register, AndData, OrData)  (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
\r
#define McMmio16Ptr(Register)                         ((volatile UINT16*) McMmioAddress (Register))\r
#define McMmio16(Register)                            *McMmio16Ptr (Register)\r
#define McMmio16Or(Register, OrData)                  (McMmio16 (Register) |= (UINT16) (OrData))\r
#define McMmio16And(Register, AndData)                (McMmio16 (Register) &= (UINT16) (AndData))\r
#define McMmio16AndThenOr(Register, AndData, OrData)  (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
\r
#define McMmio8Ptr(Register)                          ((volatile UINT8 *)McMmioAddress (Register))\r
#define McMmio8(Register)                             *McMmio8Ptr (Register)\r
#define McMmio8Or(Register, OrData)                   (McMmio8 (Register) |= (UINT8) (OrData))\r
#define McMmio8And(Register, AndData)                 (McMmio8 (Register) &= (UINT8) (AndData))\r
#define McMmio8AndThenOr(Register, AndData, OrData)   (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
\r
//\r
// QNC memory mapped related data structure deifinition\r
//\r
typedef enum {\r
  QNCMmioWidthUint8  = 0,\r
  QNCMmioWidthUint16 = 1,\r
  QNCMmioWidthUint32 = 2,\r
  QNCMmioWidthUint64 = 3,\r
  QNCMmioWidthMaximum\r
} QNC_MEM_IO_WIDTH;\r
\r
#endif\r
\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	Macros to simplify and abstract the interface to PCI configuration.\r
	3	\r
	4	Copyright (c) 2013-2015 Intel Corporation.\r
	5	\r
c9f231d0	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
9b6bbcdb MK	7	\r
	8	\r
	9	**/\r
	10	\r
	11	#ifndef _QNC_ACCESS_H_\r
	12	#define _QNC_ACCESS_H_\r
	13	\r
	14	#include "QuarkNcSocId.h"\r
	15	#include "QNCCommonDefinitions.h"\r
	16	\r
	17	#define EFI_LPC_PCI_ADDRESS( Register ) \\r
	18	EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register)\r
	19	\r
	20	//\r
	21	// QNC Controller PCI access macros\r
	22	//\r
	23	#define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0, PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK)\r
	24	\r
	25	//\r
	26	// Device 0x1f, Function 0\r
	27	//\r
	28	\r
	29	#define LpcPciCfg32( Register ) \\r
	30	QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
	31	\r
	32	#define LpcPciCfg32Or( Register, OrData ) \\r
	33	QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
	34	\r
	35	#define LpcPciCfg32And( Register, AndData ) \\r
	36	QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
	37	\r
	38	#define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \\r
	39	QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
	40	\r
	41	#define LpcPciCfg16( Register ) \\r
	42	QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
	43	\r
	44	#define LpcPciCfg16Or( Register, OrData ) \\r
	45	QNCMmPci16Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
	46	\r
	47	#define LpcPciCfg16And( Register, AndData ) \\r
	48	QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
	49	\r
	50	#define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \\r
	51	QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
	52	\r
	53	#define LpcPciCfg8( Register ) \\r
	54	QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )\r
	55	\r
	56	#define LpcPciCfg8Or( Register, OrData ) \\r
	57	QNCMmPci8Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )\r
	58	\r
	59	#define LpcPciCfg8And( Register, AndData ) \\r
	60	QNCMmPci8And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )\r
	61	\r
	62	#define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \\r
	63	QNCMmPci8AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )\r
	64	\r
	65	//\r
	66	// Root Complex Register Block\r
	67	//\r
	68	\r
	69	#define MmRcrb32( Register ) \\r
	70	QNCMmio32( QNC_RCRB_BASE, Register )\r
71	\r
72	#define MmRcrb32Or( Register, OrData ) \\r
73	QNCMmio32Or( QNC_RCRB_BASE, Register, OrData )\r
74	\r
75	#define MmRcrb32And( Register, AndData ) \\r
76	QNCMmio32And( QNC_RCRB_BASE, Register, AndData )\r
77	\r
78	#define MmRcrb32AndThenOr( Register, AndData, OrData ) \\r
79	QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
80	\r
81	#define MmRcrb16( Register ) \\r
82	QNCMmio16( QNC_RCRB_BASE, Register )\r
83	\r
84	#define MmRcrb16Or( Register, OrData ) \\r
85	QNCMmio16Or( QNC_RCRB_BASE, Register, OrData )\r
86	\r
87	#define MmRcrb16And( Register, AndData ) \\r
88	QNCMmio16And( QNC_RCRB_BASE, Register, AndData )\r
89	\r
90	#define MmRcrb16AndThenOr( Register, AndData, OrData ) \\r
91	QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
92	\r
93	#define MmRcrb8( Register ) \\r
94	QNCMmio8( QNC_RCRB_BASE, Register )\r
95	\r
96	#define MmRcrb8Or( Register, OrData ) \\r
97	QNCMmio8Or( QNC_RCRB_BASE, Register, OrData )\r
98	\r
99	#define MmRcrb8And( Register, AndData ) \\r
100	QNCMmio8And( QNC_RCRB_BASE, Register, AndData )\r
101	\r
102	#define MmRcrb8AndThenOr( Register, AndData, OrData ) \\r
103	QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )\r
104	\r
105	//\r
106	// Memory Controller PCI access macros\r
107	//\r
108	\r
109	//\r
110	// Device 0, Function 0\r
111	//\r
112	\r
113	#define McD0PciCfg64(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)\r
114	#define McD0PciCfg64Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)\r
115	#define McD0PciCfg64And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)\r
116	#define McD0PciCfg64AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
117	\r
118	#define McD0PciCfg32(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)\r
119	#define McD0PciCfg32Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)\r
120	#define McD0PciCfg32And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)\r
121	#define McD0PciCfg32AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
122	\r
123	#define McD0PciCfg16(Register) QNCMmPci16 (0, MC_BUS, 0, 0, Register)\r
124	#define McD0PciCfg16Or(Register, OrData) QNCMmPci16Or (0, MC_BUS, 0, 0, Register, OrData)\r
125	#define McD0PciCfg16And(Register, AndData) QNCMmPci16And (0, MC_BUS, 0, 0, Register, AndData)\r
126	#define McD0PciCfg16AndThenOr(Register, AndData, OrData) QNCMmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
127	\r
128	#define McD0PciCfg8(Register) QNCMmPci8 (0, MC_BUS, 0, 0, Register)\r
129	#define McD0PciCfg8Or(Register, OrData) QNCMmPci8Or (0, MC_BUS, 0, 0, Register, OrData)\r
130	#define McD0PciCfg8And(Register, AndData) QNCMmPci8And (0, MC_BUS, 0, 0, Register, AndData)\r
131	#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) QNCMmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
132	\r
133	\r
134	//\r
135	// Memory Controller Hub Memory Mapped IO register access ???\r
136	//\r
137	#define MCH_REGION_BASE (McD0PciCfg64 (MC_MCHBAR_OFFSET) & ~BIT0)\r
138	#define McMmioAddress(Register) ((UINTN) MCH_REGION_BASE + (UINTN) (Register))\r
139	\r
140	#define McMmio32Ptr(Register) ((volatile UINT32*) McMmioAddress (Register))\r
141	#define McMmio64Ptr(Register) ((volatile UINT64*) McMmioAddress (Register))\r
142	\r
143	#define McMmio64(Register) *McMmio64Ptr( Register )\r
144	#define McMmio64Or(Register, OrData) (McMmio64 (Register) \|= (UINT64)(OrData))\r
145	#define McMmio64And(Register, AndData) (McMmio64 (Register) &= (UINT64)(AndData))\r
146	#define McMmio64AndThenOr(Register, AndData, OrData) (McMmio64 ( Register ) = (McMmio64( Register ) & (UINT64)(AndData)) \| (UINT64)(OrData))\r
147	\r
148	#define McMmio32(Register) *McMmio32Ptr (Register)\r
149	#define McMmio32Or(Register, OrData) (McMmio32 (Register) \|= (UINT32)(OrData))\r
150	#define McMmio32And(Register, AndData) (McMmio32 (Register) &= (UINT32)(AndData))\r
151	#define McMmio32AndThenOr(Register, AndData, OrData) (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) \| (UINT32) (OrData))\r
152	\r
153	#define McMmio16Ptr(Register) ((volatile UINT16*) McMmioAddress (Register))\r
154	#define McMmio16(Register) *McMmio16Ptr (Register)\r
155	#define McMmio16Or(Register, OrData) (McMmio16 (Register) \|= (UINT16) (OrData))\r
156	#define McMmio16And(Register, AndData) (McMmio16 (Register) &= (UINT16) (AndData))\r
157	#define McMmio16AndThenOr(Register, AndData, OrData) (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) \| (UINT16) (OrData))\r
158	\r
159	#define McMmio8Ptr(Register) ((volatile UINT8 *)McMmioAddress (Register))\r
160	#define McMmio8(Register) *McMmio8Ptr (Register)\r
161	#define McMmio8Or(Register, OrData) (McMmio8 (Register) \|= (UINT8) (OrData))\r
162	#define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8) (AndData))\r
163	#define McMmio8AndThenOr(Register, AndData, OrData) (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) \| (UINT8) (OrData))\r
164	\r
165	//\r
166	// QNC memory mapped related data structure deifinition\r
167	//\r
168	typedef enum {\r
169	QNCMmioWidthUint8 = 0,\r
170	QNCMmioWidthUint16 = 1,\r
171	QNCMmioWidthUint32 = 2,\r
172	QNCMmioWidthUint64 = 3,\r
173	QNCMmioWidthMaximum\r
174	} QNC_MEM_IO_WIDTH;\r
175	\r
176	#endif\r
177	\r