QuarkSocPkg/QncSmmDispatcher: Fix context passed to SMI handlers
[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Include / QNCCommonDefinitions.h
CommitLineData
9b6bbcdb
MK
1/** @file\r
2This header file provides common definitions just for MCH using to avoid including extra module's file.\r
3\r
4Copyright (c) 2013-2015 Intel Corporation.\r
5\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions of the BSD License\r
8which accompanies this distribution. The full text of the license may be found at\r
9http://opensource.org/licenses/bsd-license.php\r
10\r
11THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#ifndef _QNC_COMMON_DEFINITIONS_H_\r
17#define _QNC_COMMON_DEFINITIONS_H_\r
18\r
19//\r
20// PCI CONFIGURATION MAP REGISTER OFFSETS\r
21//\r
22#ifndef PCI_VID\r
23#define PCI_VID 0x0000 // Vendor ID Register\r
24#define PCI_DID 0x0002 // Device ID Register\r
25#define PCI_CMD 0x0004 // PCI Command Register\r
26#define PCI_STS 0x0006 // PCI Status Register\r
27#define PCI_RID 0x0008 // Revision ID Register\r
28#define PCI_IFT 0x0009 // Interface Type\r
29#define PCI_SCC 0x000A // Sub Class Code Register\r
30#define PCI_BCC 0x000B // Base Class Code Register\r
31#define PCI_CLS 0x000C // Cache Line Size\r
32#define PCI_PMLT 0x000D // Primary Master Latency Timer\r
33#define PCI_HDR 0x000E // Header Type Register\r
34#define PCI_BIST 0x000F // Built in Self Test Register\r
35#define PCI_BAR0 0x0010 // Base Address Register 0\r
36#define PCI_BAR1 0x0014 // Base Address Register 1\r
37#define PCI_BAR2 0x0018 // Base Address Register 2\r
38#define PCI_PBUS 0x0018 // Primary Bus Number Register\r
39#define PCI_SBUS 0x0019 // Secondary Bus Number Register\r
40#define PCI_SUBUS 0x001A // Subordinate Bus Number Register\r
41#define PCI_SMLT 0x001B // Secondary Master Latency Timer\r
42#define PCI_BAR3 0x001C // Base Address Register 3\r
43#define PCI_IOBASE 0x001C // I/O base Register\r
44#define PCI_IOLIMIT 0x001D // I/O Limit Register\r
45#define PCI_SECSTATUS 0x001E // Secondary Status Register\r
46#define PCI_BAR4 0x0020 // Base Address Register 4\r
47#define PCI_MEMBASE 0x0020 // Memory Base Register\r
48#define PCI_MEMLIMIT 0x0022 // Memory Limit Register\r
49#define PCI_BAR5 0x0024 // Base Address Register 5\r
50#define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register\r
51#define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register\r
52#define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits\r
53#define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits\r
54#define PCI_SVID 0x002C // Subsystem Vendor ID\r
55#define PCI_SID 0x002E // Subsystem ID\r
56#define PCI_IOBASE_U 0x0030 // I/O base Upper Register\r
57#define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register\r
58#define PCI_CAPP 0x0034 // Capabilities Pointer\r
59#define PCI_EROM 0x0038 // Expansion ROM Base Address\r
60#define PCI_INTLINE 0x003C // Interrupt Line Register\r
61#define PCI_INTPIN 0x003D // Interrupt Pin Register\r
62#define PCI_MAXGNT 0x003E // Max Grant Register\r
63#define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register\r
64#define PCI_MAXLAT 0x003F // Max Latency Register\r
65#endif\r
66//\r
67// Bit Difinitions\r
68//\r
69#ifndef BIT0\r
70#define BIT0 0x0001\r
71#define BIT1 0x0002\r
72#define BIT2 0x0004\r
73#define BIT3 0x0008\r
74#define BIT4 0x0010\r
75#define BIT5 0x0020\r
76#define BIT6 0x0040\r
77#define BIT7 0x0080\r
78#define BIT8 0x0100\r
79#define BIT9 0x0200\r
80#define BIT10 0x0400\r
81#define BIT11 0x0800\r
82#define BIT12 0x1000\r
83#define BIT13 0x2000\r
84#define BIT14 0x4000\r
85#define BIT15 0x8000\r
86#define BIT16 0x00010000\r
87#define BIT17 0x00020000\r
88#define BIT18 0x00040000\r
89#define BIT19 0x00080000\r
90#define BIT20 0x00100000\r
91#define BIT21 0x00200000\r
92#define BIT22 0x00400000\r
93#define BIT23 0x00800000\r
94#define BIT24 0x01000000\r
95#define BIT25 0x02000000\r
96#define BIT26 0x04000000\r
97#define BIT27 0x08000000\r
98#define BIT28 0x10000000\r
99#define BIT29 0x20000000\r
100#define BIT30 0x40000000\r
101#define BIT31 0x80000000\r
102#endif\r
103\r
104\r
105//\r
106// Common Memory mapped Io access macros ------------------------------------------\r
107//\r
108#define QNCMmioAddress( BaseAddr, Register ) \\r
109 ( (UINTN)BaseAddr + \\r
110 (UINTN)(Register) \\r
111 )\r
112\r
113//\r
114// UINT64\r
115//\r
116#define QNCMmio64Ptr( BaseAddr, Register ) \\r
117 ( (volatile UINT64 *)QNCMmioAddress( BaseAddr, Register ) )\r
118\r
119#define QNCMmio64( BaseAddr, Register ) \\r
120 *QNCMmio64Ptr( BaseAddr, Register )\r
121\r
122#define QNCMmio64Or( BaseAddr, Register, OrData ) \\r
123 QNCMmio64( BaseAddr, Register ) = \\r
124 (UINT64) ( \\r
125 QNCMmio64( BaseAddr, Register ) | \\r
126 (UINT64)(OrData) \\r
127 )\r
128\r
129#define QNCMmio64And( BaseAddr, Register, AndData ) \\r
130 QNCMmio64( BaseAddr, Register ) = \\r
131 (UINT64) ( \\r
132 QNCMmio64( BaseAddr, Register ) & \\r
133 (UINT64)(AndData) \\r
134 )\r
135\r
136#define QNCMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
137 QNCMmio64( BaseAddr, Register ) = \\r
138 (UINT64) ( \\r
139 ( QNCMmio64( BaseAddr, Register ) & \\r
140 (UINT64)(AndData) \\r
141 ) | \\r
142 (UINT64)(OrData) \\r
143 )\r
144\r
145//\r
146// UINT32\r
147//\r
148#define QNCMmio32Ptr( BaseAddr, Register ) \\r
149 ( (volatile UINT32 *)QNCMmioAddress( BaseAddr, Register ) )\r
150\r
151#define QNCMmio32( BaseAddr, Register ) \\r
152 *QNCMmio32Ptr( BaseAddr, Register )\r
153\r
154#define QNCMmio32Or( BaseAddr, Register, OrData ) \\r
155 QNCMmio32( BaseAddr, Register ) = \\r
156 (UINT32) ( \\r
157 QNCMmio32( BaseAddr, Register ) | \\r
158 (UINT32)(OrData) \\r
159 )\r
160\r
161#define QNCMmio32And( BaseAddr, Register, AndData ) \\r
162 QNCMmio32( BaseAddr, Register ) = \\r
163 (UINT32) ( \\r
164 QNCMmio32( BaseAddr, Register ) & \\r
165 (UINT32)(AndData) \\r
166 )\r
167\r
168#define QNCMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
169 QNCMmio32( BaseAddr, Register ) = \\r
170 (UINT32) ( \\r
171 ( QNCMmio32( BaseAddr, Register ) & \\r
172 (UINT32)(AndData) \\r
173 ) | \\r
174 (UINT32)(OrData) \\r
175 )\r
176//\r
177// UINT16\r
178//\r
179\r
180#define QNCMmio16Ptr( BaseAddr, Register ) \\r
181 ( (volatile UINT16 *)QNCMmioAddress( BaseAddr, Register ) )\r
182\r
183#define QNCMmio16( BaseAddr, Register ) \\r
184 *QNCMmio16Ptr( BaseAddr, Register )\r
185\r
186#define QNCMmio16Or( BaseAddr, Register, OrData ) \\r
187 QNCMmio16( BaseAddr, Register ) = \\r
188 (UINT16) ( \\r
189 QNCMmio16( BaseAddr, Register ) | \\r
190 (UINT16)(OrData) \\r
191 )\r
192\r
193#define QNCMmio16And( BaseAddr, Register, AndData ) \\r
194 QNCMmio16( BaseAddr, Register ) = \\r
195 (UINT16) ( \\r
196 QNCMmio16( BaseAddr, Register ) & \\r
197 (UINT16)(AndData) \\r
198 )\r
199\r
200#define QNCMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
201 QNCMmio16( BaseAddr, Register ) = \\r
202 (UINT16) ( \\r
203 ( QNCMmio16( BaseAddr, Register ) & \\r
204 (UINT16)(AndData) \\r
205 ) | \\r
206 (UINT16)(OrData) \\r
207 )\r
208//\r
209// UINT8\r
210//\r
211#define QNCMmio8Ptr( BaseAddr, Register ) \\r
212 ( (volatile UINT8 *)QNCMmioAddress( BaseAddr, Register ) )\r
213\r
214#define QNCMmio8( BaseAddr, Register ) \\r
215 *QNCMmio8Ptr( BaseAddr, Register )\r
216\r
217#define QNCMmio8Or( BaseAddr, Register, OrData ) \\r
218 QNCMmio8( BaseAddr, Register ) = \\r
219 (UINT8) ( \\r
220 QNCMmio8( BaseAddr, Register ) | \\r
221 (UINT8)(OrData) \\r
222 )\r
223\r
224#define QNCMmio8And( BaseAddr, Register, AndData ) \\r
225 QNCMmio8( BaseAddr, Register ) = \\r
226 (UINT8) ( \\r
227 QNCMmio8( BaseAddr, Register ) & \\r
228 (UINT8)(AndData) \\r
229 )\r
230\r
231#define QNCMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
232 QNCMmio8( BaseAddr, Register ) = \\r
233 (UINT8) ( \\r
234 ( QNCMmio8( BaseAddr, Register ) & \\r
235 (UINT8)(AndData) \\r
236 ) | \\r
237 (UINT8)(OrData) \\r
238 )\r
239\r
240//\r
241// Common Memory mapped Pci access macros ------------------------------------------\r
242//\r
243\r
244#define QNCMmPciAddress( Segment, Bus, Device, Function, Register ) \\r
245 ( (UINTN) QncGetPciExpressBaseAddress() + \\r
246 (UINTN)(Bus << 20) + \\r
247 (UINTN)(Device << 15) + \\r
248 (UINTN)(Function << 12) + \\r
249 (UINTN)(Register) \\r
250 )\r
251\r
252//\r
253// Macro to calculate the Pci device's base memory mapped address\r
254//\r
255#define PciDeviceMmBase( Bus, Device, Function) \\r
256 ( (UINTN) QncGetPciExpressBaseAddress () + \\r
257 (UINTN)(Bus << 20) + \\r
258 (UINTN)(Device << 15) + \\r
259 (UINTN)(Function << 12) \\r
260 )\r
261\r
262//\r
263// UINT32\r
264//\r
265#define QNCMmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r
266 ( (volatile UINT32 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )\r
267\r
268#define QNCMmPci32( Segment, Bus, Device, Function, Register ) \\r
269 *QNCMmPci32Ptr( Segment, Bus, Device, Function, Register )\r
270\r
271#define QNCMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r
272 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \\r
273 (UINT32) ( \\r
274 QNCMmPci32( Segment, Bus, Device, Function, Register ) | \\r
275 (UINT32)(OrData) \\r
276 )\r
277\r
278#define QNCMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r
279 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \\r
280 (UINT32) ( \\r
281 QNCMmPci32( Segment, Bus, Device, Function, Register ) & \\r
282 (UINT32)(AndData) \\r
283 )\r
284\r
285#define QNCMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
286 QNCMmPci32( Segment, Bus, Device, Function, Register ) = \\r
287 (UINT32) ( \\r
288 ( QNCMmPci32( Segment, Bus, Device, Function, Register ) & \\r
289 (UINT32)(AndData) \\r
290 ) | \\r
291 (UINT32)(OrData) \\r
292 )\r
293//\r
294// UINT16\r
295//\r
296#define QNCMmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r
297 ( (volatile UINT16 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )\r
298\r
299#define QNCMmPci16( Segment, Bus, Device, Function, Register ) \\r
300 *QNCMmPci16Ptr( Segment, Bus, Device, Function, Register )\r
301\r
302#define QNCMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r
303 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \\r
304 (UINT16) ( \\r
305 QNCMmPci16( Segment, Bus, Device, Function, Register ) | \\r
306 (UINT16)(OrData) \\r
307 )\r
308\r
309#define QNCMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r
310 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \\r
311 (UINT16) ( \\r
312 QNCMmPci16( Segment, Bus, Device, Function, Register ) & \\r
313 (UINT16)(AndData) \\r
314 )\r
315\r
316#define QNCMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
317 QNCMmPci16( Segment, Bus, Device, Function, Register ) = \\r
318 (UINT16) ( \\r
319 ( QNCMmPci16( Segment, Bus, Device, Function, Register ) & \\r
320 (UINT16)(AndData) \\r
321 ) | \\r
322 (UINT16)(OrData) \\r
323 )\r
324//\r
325// UINT8\r
326//\r
327#define QNCMmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r
328 ( (volatile UINT8 *)QNCMmPciAddress( Segment, Bus, Device, Function, Register ) )\r
329\r
330#define QNCMmPci8( Segment, Bus, Device, Function, Register ) \\r
331 *QNCMmPci8Ptr( Segment, Bus, Device, Function, Register )\r
332\r
333#define QNCMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r
334 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \\r
335 (UINT8) ( \\r
336 QNCMmPci8( Segment, Bus, Device, Function, Register ) | \\r
337 (UINT8)(OrData) \\r
338 )\r
339\r
340#define QNCMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r
341 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \\r
342 (UINT8) ( \\r
343 QNCMmPci8( Segment, Bus, Device, Function, Register ) & \\r
344 (UINT8)(AndData) \\r
345 )\r
346\r
347#define QNCMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
348 QNCMmPci8( Segment, Bus, Device, Function, Register ) = \\r
349 (UINT8) ( \\r
350 ( QNCMmPci8( Segment, Bus, Device, Function, Register ) & \\r
351 (UINT8)(AndData) \\r
352 ) | \\r
353 (UINT8)(OrData) \\r
354 )\r
355\r
356#endif\r