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1 | /** @file\r |
| 2 | QuarkNcSocId Register Definitions\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 5 | \r | |
| 6 | This program and the accompanying materials\r | |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 8 | which accompanies this distribution. The full text of the license may be found at\r | |
| 9 | http://opensource.org/licenses/bsd-license.php\r | |
| 10 | \r | |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | Definitions beginning with "R_" are registers\r | |
| 15 | Definitions beginning with "B_" are bits within registers\r | |
| 16 | Definitions beginning with "V_" are meaningful values of bits within the registers\r | |
| 17 | Definitions beginning with "S_" are register sizes\r | |
| 18 | Definitions beginning with "N_" are the bit position\r | |
| 19 | \r | |
| 20 | **/\r | |
| 21 | \r | |
| 22 | #ifndef _QUARK_NC_SOC_ID_H_\r | |
| 23 | #define _QUARK_NC_SOC_ID_H_\r | |
| 24 | \r | |
| 25 | //\r | |
| 26 | // QNC GMCH Equates\r | |
| 27 | //\r | |
| 28 | \r | |
| 29 | //\r | |
| 30 | // DEVICE 0 (Memroy Controller Hub)\r | |
| 31 | //\r | |
| 32 | #define MC_BUS PCI_BUS_NUMBER_QNC\r | |
| 33 | #define MC_DEV 0x00\r | |
| 34 | #define MC_FUN 0x00\r | |
| 35 | \r | |
| 36 | #define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID\r | |
| 37 | #define QUARK_MC_DEVICE_ID 0x0958\r | |
| 38 | #define QUARK2_MC_DEVICE_ID 0x12C0\r | |
| 39 | #define QNC_MC_REV_ID_A0 0x00\r | |
| 40 | \r | |
| 41 | \r | |
| 42 | //\r | |
| 43 | // MCR - B0:D0:F0:RD0h (WO)- Message control register\r | |
| 44 | // [31:24] Message opcode - D0 read; E0 write;\r | |
| 45 | // [23:16] Message port\r | |
| 46 | // [15:8 ] Message target register address\r | |
| 47 | // [ 7:4 ] Message write byte enable : F is enable\r | |
| 48 | // [ 3:0 ] Reserved\r | |
| 49 | //\r | |
| 50 | #define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register\r | |
| 51 | // Always Set to 0xF0\r | |
| 52 | \r | |
| 53 | //\r | |
| 54 | //MDR - B0:D0:F0:RD4h (RW)- Message data register\r | |
| 55 | //\r | |
| 56 | #define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register\r | |
| 57 | \r | |
| 58 | //\r | |
| 59 | //MEA - B0:D0:F0:RD8h (RW)- Message extended address register\r | |
| 60 | //\r | |
| 61 | #define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register\r | |
| 62 | \r | |
| 63 | #define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR\r | |
| 64 | #define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR\r | |
| 65 | #define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR\r | |
| 66 | \r | |
| 67 | //\r | |
| 68 | // Misc Useful Macros\r | |
| 69 | //\r | |
| 70 | \r | |
| 71 | #define LShift16(value) (value << 16)\r | |
| 72 | \r | |
| 73 | //\r | |
| 74 | // QNC Message OpCodes and Attributes\r | |
| 75 | //\r | |
| 76 | #define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode\r | |
| 77 | #define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode\r | |
| 78 | \r | |
| 79 | //\r | |
| 80 | // Alternative opcodes for the SCSS block\r | |
| 81 | //\r | |
| 82 | #define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode\r | |
| 83 | #define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode\r | |
| 84 | \r | |
| 85 | //\r | |
| 86 | // QNC Message OpCodes and Attributes for IO\r | |
| 87 | //\r | |
| 88 | #define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode\r | |
| 89 | #define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode\r | |
| 90 | \r | |
| 91 | \r | |
| 92 | #define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode\r | |
| 93 | \r | |
| 94 | #define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode\r | |
| 95 | #define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode\r | |
| 96 | \r | |
| 97 | //\r | |
| 98 | // QNC Message Ports and Registers\r | |
| 99 | //\r | |
| 100 | // Start of SB Port IDs\r | |
| 101 | #define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00\r | |
| 102 | #define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01\r | |
| 103 | #define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03\r | |
| 104 | #define QUARK_NC_RMU_SB_PORT_ID 0x04\r | |
| 105 | #define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05\r | |
| 106 | #define QUARK_SC_USB_AFE_SB_PORT_ID 0x14\r | |
| 107 | #define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16\r | |
| 108 | #define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31\r | |
| 109 | #define QUARK_SCSS_FUSE_SB_PORT_ID 0x33\r | |
| 110 | #define QUARK_ICLK_SB_PORT_ID 0x32\r | |
| 111 | #define QUARK_SCSS_CRU_SB_PORT_ID 0x34\r | |
| 112 | \r | |
| 113 | //\r | |
| 114 | // Quark Memory Arbiter Registers.\r | |
| 115 | //\r | |
| 116 | #define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register.\r | |
| 117 | #define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient\r | |
| 118 | #define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh.\r | |
| 119 | #define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing.\r | |
| 120 | #define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing.\r | |
| 121 | #define ASTATUS1_RASISED_BP (10)\r | |
| 122 | #define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r | |
| 123 | #define ASTATUS0_RASISED_BP (8)\r | |
| 124 | #define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r | |
| 125 | #define ASTATUS1_DEFAULT_BP (2)\r | |
| 126 | #define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r | |
| 127 | #define ASTATUS0_DEFAULT_BP (0)\r | |
| 128 | #define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)\r | |
| 129 | \r | |
| 130 | //\r | |
| 131 | // Quark Memory Controller Registers.\r | |
| 132 | //\r | |
| 133 | #define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register.\r | |
| 134 | #define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC.\r | |
| 135 | \r | |
| 136 | //\r | |
| 137 | // Quark Remote Management Unit Registers.\r | |
| 138 | //\r | |
| 139 | #define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address\r | |
| 140 | \r | |
| 141 | #define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register.\r | |
| 142 | #define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)\r | |
| 143 | #define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)\r | |
| 144 | \r | |
| 145 | #define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1.\r | |
| 146 | #define OPTIONS_1_DMA_DISABLE (BIT0)\r | |
| 147 | \r | |
| 148 | #define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register.\r | |
| 149 | #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)\r | |
| 150 | #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18\r | |
| 151 | #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r | |
| 152 | #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r | |
| 153 | #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r | |
| 154 | #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)\r | |
| 155 | \r | |
| 156 | #define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register.\r | |
| 157 | #define TS_ENABLE (BIT15)\r | |
| 158 | #define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register.\r | |
| 159 | #define TS_HOT_TRIP_CLEAR_THOLD_BP 24\r | |
| 160 | #define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)\r | |
| 161 | #define TS_CAT_TRIP_CLEAR_THOLD_BP 16\r | |
| 162 | #define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)\r | |
| 163 | #define TS_HOT_TRIP_SET_THOLD_BP 8\r | |
| 164 | #define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)\r | |
| 165 | #define TS_CAT_TRIP_SET_THOLD_BP 0\r | |
| 166 | #define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)\r | |
| 167 | \r | |
| 168 | #define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50\r | |
| 169 | #define SCRUB_CFG_INTERVAL_SHIFT 0x00\r | |
| 170 | #define SCRUB_CFG_INTERVAL_MASK 0xFF\r | |
| 171 | #define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08\r | |
| 172 | #define SCRUB_CFG_BLOCKSIZE_MASK 0x1F\r | |
| 173 | #define SCRUB_CFG_ACTIVE (BIT13)\r | |
| 174 | #define SCRUB_CFG_INVALID 0x00000FFF\r | |
| 175 | \r | |
| 176 | #define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76\r | |
| 177 | #define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77\r | |
| 178 | #define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C\r | |
| 179 | \r | |
| 180 | #define SCRUB_RESUME_MSG() ((UINT32)( \\r | |
| 181 | (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \\r | |
| 182 | (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \\r | |
| 183 | 0xF0))\r | |
| 184 | \r | |
| 185 | #define SCRUB_PAUSE_MSG() ((UINT32)( \\r | |
| 186 | (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \\r | |
| 187 | (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \\r | |
| 188 | 0xF0))\r | |
| 189 | \r | |
| 190 | //\r | |
| 191 | // Quark Memory Manager Registers\r | |
| 192 | //\r | |
| 193 | #define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82\r | |
| 194 | #define BLOCK_ENABLE_PG (1 << 28)\r | |
| 195 | #define BLOCK_DISABLE_PG (1 << 29)\r | |
| 196 | #define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19\r | |
| 197 | #define EnableIMRInt BIT31\r | |
| 198 | #define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C\r | |
| 199 | #define EnableSMMInt BIT31\r | |
| 200 | #define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20\r | |
| 201 | #define DRAM_NON_HOST_RQ_LIMIT_BP 0\r | |
| 202 | #define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)\r | |
| 203 | \r | |
| 204 | #define QUARK_NC_TOTAL_IMR_SET 0x8\r | |
| 205 | #define QUARK_NC_MEMORY_MANAGER_IMR0 0x40\r | |
| 206 | #define QUARK_NC_MEMORY_MANAGER_IMR1 0x44\r | |
| 207 | #define QUARK_NC_MEMORY_MANAGER_IMR2 0x48\r | |
| 208 | #define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C\r | |
| 209 | #define QUARK_NC_MEMORY_MANAGER_IMR4 0x50\r | |
| 210 | #define QUARK_NC_MEMORY_MANAGER_IMR5 0x54\r | |
| 211 | #define QUARK_NC_MEMORY_MANAGER_IMR6 0x58\r | |
| 212 | #define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C\r | |
| 213 | #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00\r | |
| 214 | #define IMR_LOCK BIT31\r | |
| 215 | #define IMR_EN BIT30\r | |
| 216 | #define IMRL_MASK 0x00FFFFFC\r | |
| 217 | #define IMRL_RESET 0x00000000\r | |
| 218 | #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01\r | |
| 219 | #define IMRH_MASK 0x00FFFFFC\r | |
| 220 | #define IMRH_RESET 0x00000000\r | |
| 221 | #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02\r | |
| 222 | #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03\r | |
| 223 | #define IMRX_ALL_ACCESS 0xFFFFFFFF\r | |
| 224 | #define CPU_SNOOP BIT30\r | |
| 225 | #define RMU BIT29\r | |
| 226 | #define CPU0_NON_SMM BIT0\r | |
| 227 | \r | |
| 228 | //\r | |
| 229 | // Quark Host Bridge Registers\r | |
| 230 | //\r | |
| 231 | #define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls\r | |
| 232 | #define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge)\r | |
| 233 | #define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control\r | |
| 234 | #define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN\r | |
| 235 | #define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN\r | |
| 236 | #define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN\r | |
| 237 | #define SMM_CTL_EN (BIT3) // SMM enable\r | |
| 238 | #define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN\r | |
| 239 | #define SMM_READ_OPEN (BIT1) // SMM Reads OPEN\r | |
| 240 | #define SMM_LOCKED (BIT0) // SMM Locked\r | |
| 241 | #define SMM_START_MASK 0x0000FFF0\r | |
| 242 | #define SMM_END_MASK 0xFFF00000\r | |
| 243 | #define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08\r | |
| 244 | #define HMBOUND_MASK 0x0FFFFF000\r | |
| 245 | #define HMBOUND_LOCK BIT0\r | |
| 246 | #define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A\r | |
| 247 | #define HLEGACY_SMI_PIN_VALUE BIT12\r | |
| 248 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40\r | |
| 249 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41\r | |
| 250 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42\r | |
| 251 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44\r | |
| 252 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46\r | |
| 253 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48\r | |
| 254 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A\r | |
| 255 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C\r | |
| 256 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E\r | |
| 257 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50\r | |
| 258 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52\r | |
| 259 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54\r | |
| 260 | #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56\r | |
| 261 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58\r | |
| 262 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59\r | |
| 263 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A\r | |
| 264 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B\r | |
| 265 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C\r | |
| 266 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D\r | |
| 267 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E\r | |
| 268 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F\r | |
| 269 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60\r | |
| 270 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61\r | |
| 271 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62\r | |
| 272 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63\r | |
| 273 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64\r | |
| 274 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65\r | |
| 275 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66\r | |
| 276 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67\r | |
| 277 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68\r | |
| 278 | #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69\r | |
| 279 | \r | |
| 280 | //\r | |
| 281 | // System On Chip Unit (SOCUnit) Registers.\r | |
| 282 | //\r | |
| 283 | #define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00\r | |
| 284 | #define B_STPDDRCFG_FORCE_RECOVERY BIT0\r | |
| 285 | #define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25\r | |
| 286 | #define B_ROM_FUSE_IN_SECURE_SKU BIT6\r | |
| 287 | \r | |
| 288 | #define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31\r | |
| 289 | #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)\r | |
| 290 | #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3\r | |
| 291 | #define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8)\r | |
| 292 | #define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8\r | |
| 293 | #define B_TSCGF1_CONFIG_IBGEN BIT17\r | |
| 294 | #define B_TSCGF1_CONFIG_IBGEN_BP 17\r | |
| 295 | #define B_TSCGF1_CONFIG_IBGCHOPEN BIT18\r | |
| 296 | #define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18\r | |
| 297 | #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14\r | |
| 298 | #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14\r | |
| 299 | \r | |
| 300 | #define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32\r | |
| 301 | #define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF\r | |
| 302 | #define B_TSCGF2_CONFIG_IDSCONTROL_BP 0\r | |
| 303 | #define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000\r | |
| 304 | #define B_TSCGF2_CONFIG_IDSTIMING_BP 16\r | |
| 305 | \r | |
| 306 | #define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33\r | |
| 307 | #define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000\r | |
| 308 | #define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24\r | |
| 309 | #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8)\r | |
| 310 | #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8\r | |
| 311 | #define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF\r | |
| 312 | #define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0\r | |
| 313 | \r | |
| 314 | #define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34\r | |
| 315 | #define B_TSCGF3_CONFIG_ITSRST BIT0\r | |
| 316 | #define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11\r | |
| 317 | #define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)\r | |
| 318 | \r | |
| 319 | #define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36\r | |
| 320 | #define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20\r | |
| 321 | #define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19\r | |
| 322 | #define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18\r | |
| 323 | #define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17\r | |
| 324 | #define SOCCLKEN_CONFIG_BB_RST_B BIT16\r | |
| 325 | \r | |
| 326 | #define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36\r | |
| 327 | \r | |
| 328 | #define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51\r | |
| 329 | #define B_CFG_STICKY_RW_SMM_VIOLATION BIT0\r | |
| 330 | #define B_CFG_STICKY_RW_HMB_VIOLATION BIT1\r | |
| 331 | #define B_CFG_STICKY_RW_IMR_VIOLATION BIT2\r | |
| 332 | #define B_CFG_STICKY_RW_DECC_VIOLATION BIT3\r | |
| 333 | #define B_CFG_STICKY_RW_WARM_RST BIT4\r | |
| 334 | #define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9\r | |
| 335 | #define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION)\r | |
| 336 | #define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST)\r | |
| 337 | \r | |
| 338 | //\r | |
| 339 | // iCLK Registers.\r | |
| 340 | //\r | |
| 341 | #define QUARK_ICLK_MUXTOP 0x0140\r | |
| 342 | #define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23)\r | |
| 343 | #define B_MUXTOP_FLEX2_BP 23\r | |
| 344 | #define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20)\r | |
| 345 | #define B_MUXTOP_FLEX1_BP 20\r | |
| 346 | \r | |
| 347 | #define QUARK_ICLK_SSC1 0x0314\r | |
| 348 | #define QUARK_ICLK_SSC2 0x0414\r | |
| 349 | #define QUARK_ICLK_SSC3 0x0514\r | |
| 350 | #define QUARK_ICLK_REF2_DBUFF0 0x2000\r | |
| 351 | \r | |
| 352 | //\r | |
| 353 | // PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID).\r | |
| 354 | //\r | |
| 355 | #define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080\r | |
| 356 | #define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180\r | |
| 357 | #define OCFGPIMIXLOAD_1_0 BIT6\r | |
| 358 | #define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F\r | |
| 359 | \r | |
| 360 | //\r | |
| 361 | // QNC ICH Equates\r | |
| 362 | //\r | |
| 363 | #define V_INTEL_VENDOR_ID 0x8086\r | |
| 364 | \r | |
| 365 | #define PCI_BUS_NUMBER_QNC 0x00\r | |
| 366 | \r | |
| 367 | //\r | |
| 368 | // PCI to LPC Bridge Registers (D31:F0)\r | |
| 369 | //\r | |
| 370 | #define PCI_DEVICE_NUMBER_QNC_LPC 31\r | |
| 371 | #define PCI_FUNCTION_NUMBER_QNC_LPC 0\r | |
| 372 | \r | |
| 373 | #define R_QNC_LPC_VENDOR_ID 0x00\r | |
| 374 | #define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID\r | |
| 375 | #define R_QNC_LPC_DEVICE_ID 0x02\r | |
| 376 | #define QUARK_V_LPC_DEVICE_ID_0 0x095E\r | |
| 377 | #define R_QNC_LPC_REV_ID 0x08\r | |
| 378 | \r | |
| 379 | #define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43\r | |
| 380 | #define B_QNC_LPC_SMBUS_BASE_EN (BIT31)\r | |
| 381 | #define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6]\r | |
| 382 | //\r | |
| 383 | // SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h)\r | |
| 384 | // Suggested Value for SMBA = 0x1040\r | |
| 385 | //\r | |
| 386 | #define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W\r | |
| 387 | #define B_QNC_SMBUS_START (BIT4) // Start/Stop\r | |
| 388 | #define V_QNC_SMBUS_HCTL_CMD_QUICK 0\r | |
| 389 | #define V_QNC_SMBUS_HCTL_CMD_BYTE 1\r | |
| 390 | #define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2\r | |
| 391 | #define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3\r | |
| 392 | #define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4\r | |
| 393 | #define V_QNC_SMBUS_HCTL_CMD_BLOCK 5\r | |
| 394 | \r | |
| 395 | #define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W\r | |
| 396 | #define B_QNC_SMBUS_BERR (BIT2) // BUS Error\r | |
| 397 | #define B_QNC_SMBUS_DERR (BIT1) // Device Error\r | |
| 398 | #define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status\r | |
| 399 | #define B_QNC_SMBUS_HSTS_ALL 0x07\r | |
| 400 | \r | |
| 401 | #define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W\r | |
| 402 | #define V_QNC_SMBUS_HCLK_100KHZ 0x0054\r | |
| 403 | \r | |
| 404 | #define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W\r | |
| 405 | #define V_QNC_SMBUS_RW_SEL_READ 1\r | |
| 406 | #define V_QNC_SMBUS_RW_SEL_WRITE 0\r | |
| 407 | \r | |
| 408 | #define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W\r | |
| 409 | #define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W\r | |
| 410 | #define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W\r | |
| 411 | #define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh\r | |
| 412 | \r | |
| 413 | #define R_QNC_LPC_GBA_BASE 0x44\r | |
| 414 | #define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0\r | |
| 415 | //\r | |
| 416 | // GPIO register offsets from GBA - "GPIO" (D31:F0:R44h)\r | |
| 417 | // Suggested Value for GBA = 0x1080\r | |
| 418 | //\r | |
| 419 | #define R_QNC_GPIO_CGEN_CORE_WELL 0x00\r | |
| 420 | #define R_QNC_GPIO_CGIO_CORE_WELL 0x04\r | |
| 421 | #define R_QNC_GPIO_CGLVL_CORE_WELL 0x08\r | |
| 422 | #define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable\r | |
| 423 | #define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable\r | |
| 424 | #define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable\r | |
| 425 | #define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable\r | |
| 426 | #define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status\r | |
| 427 | #define R_QNC_GPIO_RGEN_RESUME_WELL 0x20\r | |
| 428 | #define R_QNC_GPIO_RGIO_RESUME_WELL 0x24\r | |
| 429 | #define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28\r | |
| 430 | #define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable\r | |
| 431 | #define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable\r | |
| 432 | #define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable\r | |
| 433 | #define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable\r | |
| 434 | #define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status\r | |
| 435 | #define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable\r | |
| 436 | #define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable\r | |
| 437 | \r | |
| 438 | #define R_QNC_LPC_PM1BLK 0x48\r | |
| 439 | #define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0\r | |
| 440 | //\r | |
| 441 | // ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h)\r | |
| 442 | // Suggested Value for PM1BLK = 0x1000\r | |
| 443 | //\r | |
| 444 | #define R_QNC_PM1BLK_PM1S 0x00\r | |
| 445 | #define S_QNC_PM1BLK_PM1S 2\r | |
| 446 | #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)\r | |
| 447 | #define B_QNC_PM1BLK_PM1S_WAKE (BIT15)\r | |
| 448 | #define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14)\r | |
| 449 | #define B_QNC_PM1BLK_PM1S_RTC (BIT10)\r | |
| 450 | #define B_QNC_PM1BLK_PM1S_GLOB (BIT5)\r | |
| 451 | #define B_QNC_PM1BLK_PM1S_TO (BIT0)\r | |
| 452 | #define N_QNC_PM1BLK_PM1S_RTC 10\r | |
| 453 | \r | |
| 454 | \r | |
| 455 | #define R_QNC_PM1BLK_PM1E 0x02\r | |
| 456 | #define S_QNC_PM1BLK_PM1E 2\r | |
| 457 | #define B_QNC_PM1BLK_PM1E_PWAKED (BIT14)\r | |
| 458 | #define B_QNC_PM1BLK_PM1E_RTC (BIT10)\r | |
| 459 | #define B_QNC_PM1BLK_PM1E_GLOB (BIT5)\r | |
| 460 | #define N_QNC_PM1BLK_PM1E_RTC 10\r | |
| 461 | \r | |
| 462 | #define R_QNC_PM1BLK_PM1C 0x04\r | |
| 463 | #define B_QNC_PM1BLK_PM1C_SLPEN (BIT13)\r | |
| 464 | #define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10)\r | |
| 465 | #define V_S0 0x00000000\r | |
| 466 | #define V_S3 0x00001400\r | |
| 467 | #define V_S4 0x00001800\r | |
| 468 | #define V_S5 0x00001C00\r | |
| 469 | #define B_QNC_PM1BLK_PM1C_SCIEN (BIT0)\r | |
| 470 | \r | |
| 471 | #define R_QNC_PM1BLK_PM1T 0x08\r | |
| 472 | \r | |
| 473 | #define R_QNC_LPC_GPE0BLK 0x4C\r | |
| 474 | #define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0\r | |
| 475 | // Suggested Value for GPE0BLK = 0x10C0\r | |
| 476 | //\r | |
| 477 | #define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status\r | |
| 478 | #define S_QNC_GPE0BLK_GPE0S 4\r | |
| 479 | #define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg\r | |
| 480 | #define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE\r | |
| 481 | #define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO\r | |
| 482 | #define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE\r | |
| 483 | #define N_QNC_GPE0BLK_GPE0S_THRM 12\r | |
| 484 | \r | |
| 485 | #define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable\r | |
| 486 | #define S_QNC_GPE0BLK_GPE0E 4\r | |
| 487 | #define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE\r | |
| 488 | #define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO\r | |
| 489 | #define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE\r | |
| 490 | #define N_QNC_GPE0BLK_GPE0E_THRM 12\r | |
| 491 | \r | |
| 492 | #define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable\r | |
| 493 | #define S_QNC_GPE0BLK_SMIE 4\r | |
| 494 | #define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F\r | |
| 495 | #define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM\r | |
| 496 | #define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep\r | |
| 497 | #define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer\r | |
| 498 | #define N_QNC_GPE0BLK_SMIE_GPIO 9\r | |
| 499 | #define N_QNC_GPE0BLK_SMIE_ESMI 8\r | |
| 500 | #define N_QNC_GPE0BLK_SMIE_APM 4\r | |
| 501 | #define N_QNC_GPE0BLK_SMIE_SPI 3\r | |
| 502 | #define N_QNC_GPE0BLK_SMIE_SLP 2\r | |
| 503 | #define N_QNC_GPE0BLK_SMIE_SWT 1\r | |
| 504 | \r | |
| 505 | #define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register.\r | |
| 506 | #define S_QNC_GPE0BLK_SMIS 4\r | |
| 507 | #define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F\r | |
| 508 | #define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI\r | |
| 509 | #define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM\r | |
| 510 | #define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI\r | |
| 511 | #define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep\r | |
| 512 | #define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer\r | |
| 513 | #define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS\r | |
| 514 | #define N_QNC_GPE0BLK_SMIS_GPIO 9\r | |
| 515 | #define N_QNC_GPE0BLK_SMIS_APM 4\r | |
| 516 | #define N_QNC_GPE0BLK_SMIS_SPI 3\r | |
| 517 | #define N_QNC_GPE0BLK_SMIS_SLP 2\r | |
| 518 | #define N_QNC_GPE0BLK_SMIS_SWT 1\r | |
| 519 | \r | |
| 520 | #define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well\r | |
| 521 | #define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable\r | |
| 522 | \r | |
| 523 | #define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well\r | |
| 524 | #define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad\r | |
| 525 | \r | |
| 526 | #define R_QNC_LPC_ACTL 0x58\r | |
| 527 | #define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00\r | |
| 528 | \r | |
| 529 | //\r | |
| 530 | // Number of PIRQs supported. PIRQA~PIRQH\r | |
| 531 | //\r | |
| 532 | #define QNC_NUMBER_PIRQS 8\r | |
| 533 | #define R_QNC_LPC_PIRQA_ROUT 0x60\r | |
| 534 | #define R_QNC_LPC_PIRQB_ROUT 0x61\r | |
| 535 | #define R_QNC_LPC_PIRQC_ROUT 0x62\r | |
| 536 | #define R_QNC_LPC_PIRQD_ROUT 0x63\r | |
| 537 | #define R_QNC_LPC_PIRQE_ROUT 0x64\r | |
| 538 | #define R_QNC_LPC_PIRQF_ROUT 0x65\r | |
| 539 | #define R_QNC_LPC_PIRQG_ROUT 0x66\r | |
| 540 | #define R_QNC_LPC_PIRQH_ROUT 0x67\r | |
| 541 | \r | |
| 542 | //\r | |
| 543 | // Bit values are the same for R_TNC_LPC_PIRQA_ROUT to\r | |
| 544 | // R_TNC_LPC_PIRQH_ROUT\r | |
| 545 | #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)\r | |
| 546 | \r | |
| 547 | #define R_QNC_LPC_WDTBA 0x84\r | |
| 548 | // Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN\r | |
| 549 | #define R_QNC_LPC_WDT_WDTCR 0x10\r | |
| 550 | #define R_QNC_LPC_WDT_WDTLR 0x18\r | |
| 551 | // Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END\r | |
| 552 | \r | |
| 553 | #define R_QNC_LPC_FWH_BIOS_DEC 0xD4\r | |
| 554 | #define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)\r | |
| 555 | #define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)\r | |
| 556 | #define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29)\r | |
| 557 | #define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28)\r | |
| 558 | #define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27)\r | |
| 559 | #define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26)\r | |
| 560 | #define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25)\r | |
| 561 | #define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24)\r | |
| 562 | \r | |
| 563 | #define R_QNC_LPC_BIOS_CNTL 0xD8\r | |
| 564 | #define S_QNC_LPC_BIOS_CNTL 4\r | |
| 565 | #define B_QNC_LPC_BIOS_CNTL_PFE (BIT8)\r | |
| 566 | #define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5)\r | |
| 567 | #define B_QNC_LPC_BIOS_CNTL_BCD (BIT2)\r | |
| 568 | #define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)\r | |
| 569 | #define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0)\r | |
| 570 | #define N_QNC_LPC_BIOS_CNTL_BLE 1\r | |
| 571 | #define N_QNC_LPC_BIOS_CNTL_BIOSWE 0\r | |
| 572 | \r | |
| 573 | #define R_QNC_LPC_RCBA 0xF0\r | |
| 574 | #define B_QNC_LPC_RCBA_MASK 0xFFFFC000\r | |
| 575 | #define B_QNC_LPC_RCBA_EN (BIT0)\r | |
| 576 | \r | |
| 577 | //---------------------------------------------------------------------------\r | |
| 578 | // Fixed IO Decode on QuarkNcSocId\r | |
| 579 | //\r | |
| 580 | // 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master\r | |
| 581 | // 40h(3B): R/W 8254\r | |
| 582 | // 43h(1B): W 8254\r | |
| 583 | // 50h(3B): R/W 8254\r | |
| 584 | // 53h(1B): W 8254\r | |
| 585 | // 61h(1B): R/W NMI Controller\r | |
| 586 | // 63h(1B): R/W NMI Controller - can be disabled\r | |
| 587 | // 65h(1B): R/W NMI Controller - can be disabled\r | |
| 588 | // 67h(1B): R/W NMI Controller - can be disabled\r | |
| 589 | // 70h(1B): W NMI & RTC\r | |
| 590 | // 71h(1B): R/W RTC\r | |
| 591 | // 72h(1B): R RTC; W NMI&RTC\r | |
| 592 | // 73h(1B): R/W RTC\r | |
| 593 | // 74h(1B): R RTC; W NMI&RTC\r | |
| 594 | // 75h(1B): R/W RTC\r | |
| 595 | // 76h(1B): R RTC; W NMI&RTC\r | |
| 596 | // 77h(1B): R/W RTC\r | |
| 597 | // 84h(3B): R/W Internal/LPC\r | |
| 598 | // 88h(1B): R/W Internal/LPC\r | |
| 599 | // 8Ch(3B): R/W Internal/LPC\r | |
| 600 | // A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave\r | |
| 601 | // B2h(1B) B3h(1B): R/W Power management\r | |
| 602 | // 3B0h-3BBh: R/W VGA\r | |
| 603 | // 3C0h-3DFh: R/W VGA\r | |
| 604 | // CF8h(4B): R/W Internal\r | |
| 605 | // CF9h(1B): R/W LPC\r | |
| 606 | // CFCh(4B): R/W Internal\r | |
| 607 | //---------------------------------------------------------------------------\r | |
| 608 | \r | |
| 609 | #define R_APM_CNT 0xB2\r | |
| 610 | \r | |
| 611 | //\r | |
| 612 | // Reset Generator I/O Port\r | |
| 613 | //\r | |
| 614 | #define RST_CNT 0xCF9\r | |
| 615 | #define B_RST_CNT_COLD_RST (BIT3) // Cold reset\r | |
| 616 | #define B_RST_CNT_WARM_RST (BIT1) // Warm reset\r | |
| 617 | \r | |
| 618 | //\r | |
| 619 | // Processor interface registers (NMI)\r | |
| 620 | //\r | |
| 621 | \r | |
| 622 | #define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20\r | |
| 623 | #define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21\r | |
| 624 | #define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0\r | |
| 625 | \r | |
| 626 | //\r | |
| 627 | // Pci Express Root Ports (D23:F0/F1)\r | |
| 628 | //\r | |
| 629 | #define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23\r | |
| 630 | #define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0\r | |
| 631 | #define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1\r | |
| 632 | \r | |
| 633 | #define MAX_PCI_EXPRESS_ROOT_PORTS 2\r | |
| 634 | \r | |
| 635 | #define R_QNC_PCIE_BNUM 0x18\r | |
| 636 | #define R_QNC_PCIE_CAP_PTR 0x34\r | |
| 637 | \r | |
| 638 | #define PCIE_CAPID 0x10 //PCIE Capability ID\r | |
| 639 | #define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID\r | |
| 640 | #define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset\r | |
| 641 | #define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset\r | |
| 642 | #define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset\r | |
| 643 | #define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset\r | |
| 644 | #define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset\r | |
| 645 | \r | |
| 646 | #define R_QNC_PCIE_XCAP 0x42 //~ 43h\r | |
| 647 | #define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented\r | |
| 648 | #define R_QNC_PCIE_DCAP 0x44 //~ 47h\r | |
| 649 | #define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency\r | |
| 650 | #define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency\r | |
| 651 | #define R_QNC_PCIE_DCTL 0x48 //~ 49h\r | |
| 652 | #define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable\r | |
| 653 | #define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable\r | |
| 654 | #define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable\r | |
| 655 | #define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable\r | |
| 656 | #define R_QNC_PCIE_LCAP 0x4C //~ 4Fh\r | |
| 657 | #define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported\r | |
| 658 | #define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask\r | |
| 659 | #define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask\r | |
| 660 | #define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask\r | |
| 661 | #define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask\r | |
| 662 | #define R_QNC_PCIE_LCTL 0x50 //~ 51h\r | |
| 663 | #define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration\r | |
| 664 | #define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link\r | |
| 665 | #define R_QNC_PCIE_LSTS 0x52 //~ 53h\r | |
| 666 | #define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration\r | |
| 667 | #define B_QNC_PCIE_LSTS_LT (BIT11) //Link training\r | |
| 668 | #define R_QNC_PCIE_SLCAP 0x54 //~ 57h\r | |
| 669 | #define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F\r | |
| 670 | #define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7]\r | |
| 671 | #define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7]\r | |
| 672 | #define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19]\r | |
| 673 | #define R_QNC_PCIE_SLCTL 0x58 //~ 59h\r | |
| 674 | #define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable\r | |
| 675 | #define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable\r | |
| 676 | #define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable\r | |
| 677 | #define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh\r | |
| 678 | #define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected\r | |
| 679 | #define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed\r | |
| 680 | #define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed\r | |
| 681 | #define R_QNC_PCIE_RCTL 0x5C //~ 5Dh\r | |
| 682 | #define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable\r | |
| 683 | #define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable\r | |
| 684 | #define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable\r | |
| 685 | #define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable\r | |
| 686 | #define R_QNC_PCIE_SVID 0x94 //~ 97h\r | |
| 687 | #define R_QNC_PCIE_CCFG 0xD0 //~ D3h\r | |
| 688 | #define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable\r | |
| 689 | #define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size\r | |
| 690 | #define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size\r | |
| 691 | #define R_QNC_PCIE_MPC2 0xD4 //~ D7h\r | |
| 692 | #define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode\r | |
| 693 | #define R_QNC_PCIE_MPC 0xD8 //~ DBh\r | |
| 694 | #define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable\r | |
| 695 | #define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable\r | |
| 696 | \r | |
| 697 | #define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable\r | |
| 698 | #define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable\r | |
| 699 | #define R_QNC_PCIE_IOSFSBCTL 0xF6\r | |
| 700 | #define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter.\r | |
| 701 | #define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE.\r | |
| 702 | \r | |
| 703 | #define V_PCIE_MAX_TRY_TIMES 200\r | |
| 704 | \r | |
| 705 | //\r | |
| 706 | // Misc PCI register offsets and sizes\r | |
| 707 | //\r | |
| 708 | #define R_EFI_PCI_SVID 0x2C\r | |
| 709 | \r | |
| 710 | //\r | |
| 711 | // IO_APIC\r | |
| 712 | //\r | |
| 713 | #define IOAPIC_BASE 0xFEC00000\r | |
| 714 | #define IOAPIC_SIZE 0x1000\r | |
| 715 | \r | |
| 716 | //\r | |
| 717 | // Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h)\r | |
| 718 | // Suggested Value for RCBA = 0xFED1C000\r | |
| 719 | //\r | |
| 720 | \r | |
| 721 | #define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB\r | |
| 722 | #define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status\r | |
| 723 | #define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown\r | |
| 724 | #define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status\r | |
| 725 | #define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status\r | |
| 726 | #define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress\r | |
| 727 | \r | |
| 728 | #define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control\r | |
| 729 | #define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable\r | |
| 730 | #define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64)\r | |
| 731 | #define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer\r | |
| 732 | #define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer\r | |
| 733 | #define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence\r | |
| 734 | #define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go\r | |
| 735 | \r | |
| 736 | #define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address\r | |
| 737 | #define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask\r | |
| 738 | #define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0\r | |
| 739 | #define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration\r | |
| 740 | #define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration\r | |
| 741 | #define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0\r | |
| 742 | #define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)\r | |
| 743 | #define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)\r | |
| 744 | #define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1)\r | |
| 745 | #define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU\r | |
| 746 | \r | |
| 747 | #define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0.\r | |
| 748 | #define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1.\r | |
| 749 | #define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2.\r | |
| 750 | #define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers.\r | |
| 751 | \r | |
| 752 | #define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route\r | |
| 753 | #define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route\r | |
| 754 | #define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route\r | |
| 755 | #define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route\r | |
| 756 | \r | |
| 757 | #endif\r |