QuarkSocPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / io.h

/** @file\r
Declaration of IO handling routines.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#ifndef __IO_H\r
#define __IO_H\r
\r
#include "core_types.h"\r
\r
#include "general_definitions.h"\r
#include "gen5_iosf_sb_definitions.h"\r
\r
// Instruction not present on Quark\r
#define SFENCE()\r
\r
#define DEAD_LOOP()   for(;;);\r
\r
////\r
// Define each of the IOSF_SB ports used by MRC\r
//\r
\r
//\r
// Has to be 0 because of emulation static data\r
// initialisation:\r
//   Space_t EmuSpace[ SPACE_COUNT] = {0};\r
//\r
#define FREE                0x000\r
\r
// Pseudo side-band ports for access abstraction\r
// See Wr32/Rd32 functions\r
#define MEM                 0x101\r
#define MMIO                0x102\r
#define DCMD                0x0A0\r
\r
// Real side-band ports\r
// See Wr32/Rd32 functions\r
#define MCU                 0x001\r
#define HOST_BRIDGE               0x003\r
#define MEMORY_MANAGER               0x005\r
#define HTE                0x011\r
#define DDRPHY              0x012\r
#define FUSE                0x033\r
\r
// End of IOSF_SB ports\r
////\r
\r
// Pciexbar address\r
#define EC_BASE          0xE0000000\r
\r
#define PCIADDR(bus,dev,fn,reg) ( \\r
        (EC_BASE) + \\r
    ((bus) << 20) + \\r
    ((dev) << 15) + \\r
    ((fn)  << 12) + \\r
    (reg))\r
\r
// Various offsets used in the building sideband commands.\r
#define SB_OPCODE_OFFSET      24\r
#define SB_PORT_OFFSET        16\r
#define SB_REG_OFFEST          8\r
\r
// Sideband opcodes\r
#define SB_REG_READ_OPCODE        0x10\r
#define SB_REG_WRITE_OPCODE       0x11\r
\r
#define SB_FUSE_REG_READ_OPCODE    0x06\r
#define SB_FUSE_REG_WRITE_OPCODE  0x07\r
\r
#define SB_DDRIO_REG_READ_OPCODE  0x06\r
#define SB_DDRIO_REG_WRITE_OPCODE 0x07\r
\r
#define SB_DRAM_CMND_OPCODE       0x68\r
#define SB_WAKE_CMND_OPCODE       0xCA\r
#define SB_SUSPEND_CMND_OPCODE    0xCC\r
\r
// Register addresses for sideband command and data.\r
#define SB_PACKET_REG        0x00D0\r
#define SB_DATA_REG          0x00D4\r
#define SB_HADR_REG          0x00D8\r
\r
// We always flag all 4 bytes in the register reads/writes as required.\r
#define SB_ALL_BYTES_ENABLED  0xF0\r
\r
#define SB_COMMAND(Opcode, Port, Reg)  \\r
 ((Opcode << SB_OPCODE_OFFSET) |  \\r
  (Port   << SB_PORT_OFFSET) |  \\r
  (Reg    << SB_REG_OFFEST) |  \\r
   SB_ALL_BYTES_ENABLED)\r
\r
// iosf\r
#define isbM32m   WrMask32\r
#define isbW32m   Wr32\r
#define isbR32m   Rd32\r
\r
// pci\r
\r
void pciwrite32(\r
    uint32_t bus,\r
    uint32_t dev,\r
    uint32_t fn,\r
    uint32_t reg,\r
    uint32_t data);\r
\r
uint32_t pciread32(\r
    uint32_t bus,\r
    uint32_t dev,\r
    uint32_t fn,\r
    uint32_t reg);\r
\r
// general\r
\r
uint32_t Rd32(\r
    uint32_t unit,\r
    uint32_t addr);\r
\r
void Wr32(\r
    uint32_t unit,\r
    uint32_t addr,\r
    uint32_t data);\r
\r
void WrMask32(\r
    uint32_t unit,\r
    uint32_t addr,\r
    uint32_t data,\r
    uint32_t mask);\r
\r
\r
#endif\r