[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / mrc.h

/************************************************************************\r
 *\r
 * Copyright (c) 2013-2015 Intel Corporation.\r
 *\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
* which accompanies this distribution.  The full text of the license may be found at\r
* http://opensource.org/licenses/bsd-license.php\r
*\r
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 ************************************************************************/\r
#ifndef _MRC_H_\r
#define _MRC_H_\r
\r
#include "core_types.h"\r
\r
// define the MRC Version\r
#define MRC_VERSION 0x0112\r
\r
\r
// architectural definitions\r
#define NUM_CHANNELS   1 // number of channels\r
#define NUM_RANKS      2 // number of ranks per channel\r
#define NUM_BYTE_LANES 4 // number of byte lanes per channel\r
\r
// software limitations\r
#define MAX_CHANNELS   1\r
#define MAX_RANKS      2\r
#define MAX_BYTE_LANES 4\r
\r
// only to mock MrcWrapper\r
#define MAX_SOCKETS    1\r
#define MAX_SIDES      1\r
#define MAX_ROWS       (MAX_SIDES * MAX_SOCKETS)\r
// end\r
\r
\r
// Specify DRAM of nenory channel width\r
enum {\r
  x8,   // DRAM width\r
  x16,  // DRAM width & Channel Width\r
  x32   // Channel Width\r
};\r
\r
// Specify DRAM speed\r
enum {\r
  DDRFREQ_800,\r
  DDRFREQ_1066\r
};\r
\r
// Specify DRAM type\r
enum {\r
  DDR3,\r
  DDR3L\r
};\r
\r
// Delay configuration for individual signals\r
// Vref setting\r
// Scrambler seed\r
typedef struct MrcTimings_s\r
{\r
  uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t wdq [NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];\r
  uint32_t wctl[NUM_CHANNELS][NUM_RANKS];\r
  uint32_t wcmd[NUM_CHANNELS];\r
\r
  uint32_t scrambler_seed;\r
  uint8_t  ddr_speed;            // need to save for the case of frequency change\r
} MrcTimings_t;\r
\r
\r
// DENSITY: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb\r
// tCL is DRAM CAS Latency in clocks.\r
// All other timings are in picoseconds.\r
// Refer to JEDEC spec (or DRAM datasheet) when changing these values.\r
typedef struct DRAMParams_s {\r
  uint8_t  DENSITY;\r
  uint8_t  tCL;   // CAS latency in clocks\r
  uint32_t tRAS;  // ACT to PRE command period\r
  uint32_t tWTR;  // Delay from start of internal write transaction to internal read command\r
  uint32_t tRRD;  // ACT to ACT command period (JESD79 specific to page size 1K/2K)\r
  uint32_t tFAW;  // Four activate window (JESD79 specific to page size 1K/2K)\r
} DRAMParams_t;\r
\r
\r
// Boot mode defined as bit mask (1<<n)\r
#define bmCold     1    // full training\r
#define bmFast     2    // restore timing parameters\r
#define bmS3       4    // resume from S3\r
#define bmWarm     8\r
#define bmUnknown  0\r
\r
\r
// MRC execution status\r
#define MRC_SUCCESS     0      // initialization ok\r
#define MRC_E_MEMTEST   1      // memtest failed\r
\r
\r
//\r
// Input/output/context parameters for Memory Reference Code\r
//\r
typedef struct MRCParams_s\r
{\r
  //\r
  // Global settings\r
  //\r
\r
  uint32_t boot_mode;           // bmCold, bmFast, bmWarm, bmS3\r
  uint32_t uart_mmio_base;      // pcie serial port base address (force 0 to disable debug)\r
\r
  uint8_t  dram_width;          // x8, x16\r
  uint8_t  ddr_speed;           // DDRFREQ_800, DDRFREQ_1066\r
  uint8_t  ddr_type;            // DDR3, DDR3L\r
  uint8_t  ecc_enables;         // 0, 1 (memory size reduced to 7/8)\r
  uint8_t  scrambling_enables;  // 0, 1\r
  uint32_t rank_enables;        // 1, 3 (1'st rank has to be populated if 2'nd rank present)\r
  uint32_t channel_enables;     // 1 only\r
  uint32_t channel_width;       // x16 only\r
  uint32_t address_mode;        // 0, 1, 2 (mode 2 forced if ecc enabled)\r
\r
  // memConfig_t begin\r
  uint8_t refresh_rate;         // REFRESH_RATE       : 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED\r
  uint8_t sr_temp_range;        // SR_TEMP_RANGE      : 0=normal, 1=extended, others=RESERVED\r
  uint8_t ron_value;            // RON_VALUE          : 0=34ohm, 1=40ohm, others=RESERVED (select MRS1.DIC driver impedance control)\r
  uint8_t rtt_nom_value;        // RTT_NOM_VALUE      : 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED\r
  uint8_t rd_odt_value;         // RD_ODT_VALUE       : 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED\r
  // memConfig_t end\r
\r
  DRAMParams_t params;\r
\r
  //\r
  // Internally used\r
  //\r
\r
  uint32_t board_id;            // internally used for board layout (use x8 or x16 memory)\r
  uint32_t hte_setup : 1;       // when set hte reconfiguration requested\r
  uint32_t menu_after_mrc : 1;\r
  uint32_t power_down_disable :1;\r
  uint32_t tune_rcvn :1;\r
\r
  uint32_t channel_size[NUM_CHANNELS];\r
  uint32_t column_bits[NUM_CHANNELS];\r
  uint32_t row_bits[NUM_CHANNELS];\r
\r
  uint32_t mrs1;                // register content saved during training\r
\r
  //\r
  // Output\r
  //\r
\r
  uint32_t status;              // initialization result (non zero specifies error code)\r
  uint32_t mem_size;            // total memory size in bytes (excludes ECC banks)\r
\r
  MrcTimings_t timings;         // training results (also used on input)\r
\r
} MRCParams_t;\r
\r
// Alternative type name for consistent naming convention\r
#define MRC_PARAMS    MRCParams_t\r
\r
#endif // _MRC_H_\r
Commit	Line	Data
9b6bbcdb MK	1	/************************************************************************\r
	2	*\r
	3	* Copyright (c) 2013-2015 Intel Corporation.\r
	4	*\r
	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	*\r
	13	************************************************************************/\r
	14	#ifndef _MRC_H_\r
	15	#define _MRC_H_\r
	16	\r
	17	#include "core_types.h"\r
	18	\r
	19	// define the MRC Version\r
	20	#define MRC_VERSION 0x0112\r
	21	\r
	22	\r
	23	// architectural definitions\r
	24	#define NUM_CHANNELS 1 // number of channels\r
	25	#define NUM_RANKS 2 // number of ranks per channel\r
	26	#define NUM_BYTE_LANES 4 // number of byte lanes per channel\r
	27	\r
	28	// software limitations\r
	29	#define MAX_CHANNELS 1\r
	30	#define MAX_RANKS 2\r
	31	#define MAX_BYTE_LANES 4\r
	32	\r
	33	// only to mock MrcWrapper\r
	34	#define MAX_SOCKETS 1\r
	35	#define MAX_SIDES 1\r
	36	#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)\r
	37	// end\r
	38	\r
	39	\r
	40	// Specify DRAM of nenory channel width\r
	41	enum {\r
	42	x8, // DRAM width\r
	43	x16, // DRAM width & Channel Width\r
	44	x32 // Channel Width\r
	45	};\r
	46	\r
	47	// Specify DRAM speed\r
	48	enum {\r
	49	DDRFREQ_800,\r
	50	DDRFREQ_1066\r
	51	};\r
	52	\r
	53	// Specify DRAM type\r
	54	enum {\r
	55	DDR3,\r
	56	DDR3L\r
	57	};\r
	58	\r
	59	// Delay configuration for individual signals\r
	60	// Vref setting\r
	61	// Scrambler seed\r
	62	typedef struct MrcTimings_s\r
	63	{\r
	64	uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
65	uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
66	uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
67	uint32_t wdq [NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
68	uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];\r
69	uint32_t wctl[NUM_CHANNELS][NUM_RANKS];\r
70	uint32_t wcmd[NUM_CHANNELS];\r
71	\r
72	uint32_t scrambler_seed;\r
73	uint8_t ddr_speed; // need to save for the case of frequency change\r
74	} MrcTimings_t;\r
75	\r
76	\r
77	// DENSITY: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb\r
78	// tCL is DRAM CAS Latency in clocks.\r
79	// All other timings are in picoseconds.\r
80	// Refer to JEDEC spec (or DRAM datasheet) when changing these values.\r
81	typedef struct DRAMParams_s {\r
82	uint8_t DENSITY;\r
83	uint8_t tCL; // CAS latency in clocks\r
84	uint32_t tRAS; // ACT to PRE command period\r
85	uint32_t tWTR; // Delay from start of internal write transaction to internal read command\r
86	uint32_t tRRD; // ACT to ACT command period (JESD79 specific to page size 1K/2K)\r
87	uint32_t tFAW; // Four activate window (JESD79 specific to page size 1K/2K)\r
88	} DRAMParams_t;\r
89	\r
90	\r
91	// Boot mode defined as bit mask (1<<n)\r
92	#define bmCold 1 // full training\r
93	#define bmFast 2 // restore timing parameters\r
94	#define bmS3 4 // resume from S3\r
95	#define bmWarm 8\r
96	#define bmUnknown 0\r
97	\r
98	\r
99	// MRC execution status\r
100	#define MRC_SUCCESS 0 // initialization ok\r
101	#define MRC_E_MEMTEST 1 // memtest failed\r
102	\r
103	\r
104	//\r
105	// Input/output/context parameters for Memory Reference Code\r
106	//\r
107	typedef struct MRCParams_s\r
108	{\r
109	//\r
110	// Global settings\r
111	//\r
112	\r
113	uint32_t boot_mode; // bmCold, bmFast, bmWarm, bmS3\r
114	uint32_t uart_mmio_base; // pcie serial port base address (force 0 to disable debug)\r
115	\r
116	uint8_t dram_width; // x8, x16\r
117	uint8_t ddr_speed; // DDRFREQ_800, DDRFREQ_1066\r
118	uint8_t ddr_type; // DDR3, DDR3L\r
119	uint8_t ecc_enables; // 0, 1 (memory size reduced to 7/8)\r
120	uint8_t scrambling_enables; // 0, 1\r
121	uint32_t rank_enables; // 1, 3 (1'st rank has to be populated if 2'nd rank present)\r
122	uint32_t channel_enables; // 1 only\r
123	uint32_t channel_width; // x16 only\r
124	uint32_t address_mode; // 0, 1, 2 (mode 2 forced if ecc enabled)\r
125	\r
126	// memConfig_t begin\r
127	uint8_t refresh_rate; // REFRESH_RATE : 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED\r
128	uint8_t sr_temp_range; // SR_TEMP_RANGE : 0=normal, 1=extended, others=RESERVED\r
129	uint8_t ron_value; // RON_VALUE : 0=34ohm, 1=40ohm, others=RESERVED (select MRS1.DIC driver impedance control)\r
130	uint8_t rtt_nom_value; // RTT_NOM_VALUE : 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED\r
131	uint8_t rd_odt_value; // RD_ODT_VALUE : 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED\r
132	// memConfig_t end\r
133	\r
134	DRAMParams_t params;\r
135	\r
136	//\r
137	// Internally used\r
138	//\r
139	\r
140	uint32_t board_id; // internally used for board layout (use x8 or x16 memory)\r
141	uint32_t hte_setup : 1; // when set hte reconfiguration requested\r
142	uint32_t menu_after_mrc : 1;\r
143	uint32_t power_down_disable :1;\r
144	uint32_t tune_rcvn :1;\r
145	\r
146	uint32_t channel_size[NUM_CHANNELS];\r
147	uint32_t column_bits[NUM_CHANNELS];\r
148	uint32_t row_bits[NUM_CHANNELS];\r
149	\r
150	uint32_t mrs1; // register content saved during training\r
151	\r
152	//\r
153	// Output\r
154	//\r
155	\r
156	uint32_t status; // initialization result (non zero specifies error code)\r
157	uint32_t mem_size; // total memory size in bytes (excludes ECC banks)\r
158	\r
159	MrcTimings_t timings; // training results (also used on input)\r
160	\r
161	} MRCParams_t;\r
162	\r
163	// Alternative type name for consistent naming convention\r
164	#define MRC_PARAMS MRCParams_t\r
165	\r
166	#endif // _MRC_H_\r