QuarkSocPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / mrc.h

/************************************************************************\r
 *\r
 * Copyright (c) 2013-2015 Intel Corporation.\r
 *\r
* SPDX-License-Identifier: BSD-2-Clause-Patent\r
 *\r
 ************************************************************************/\r
#ifndef _MRC_H_\r
#define _MRC_H_\r
\r
#include "core_types.h"\r
\r
// define the MRC Version\r
#define MRC_VERSION 0x0112\r
\r
\r
// architectural definitions\r
#define NUM_CHANNELS   1 // number of channels\r
#define NUM_RANKS      2 // number of ranks per channel\r
#define NUM_BYTE_LANES 4 // number of byte lanes per channel\r
\r
// software limitations\r
#define MAX_CHANNELS   1\r
#define MAX_RANKS      2\r
#define MAX_BYTE_LANES 4\r
\r
// only to mock MrcWrapper\r
#define MAX_SOCKETS    1\r
#define MAX_SIDES      1\r
#define MAX_ROWS       (MAX_SIDES * MAX_SOCKETS)\r
// end\r
\r
\r
// Specify DRAM of nenory channel width\r
enum {\r
  x8,   // DRAM width\r
  x16,  // DRAM width & Channel Width\r
  x32   // Channel Width\r
};\r
\r
// Specify DRAM speed\r
enum {\r
  DDRFREQ_800,\r
  DDRFREQ_1066\r
};\r
\r
// Specify DRAM type\r
enum {\r
  DDR3,\r
  DDR3L\r
};\r
\r
// Delay configuration for individual signals\r
// Vref setting\r
// Scrambler seed\r
typedef struct MrcTimings_s\r
{\r
  uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t wdq [NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];\r
  uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];\r
  uint32_t wctl[NUM_CHANNELS][NUM_RANKS];\r
  uint32_t wcmd[NUM_CHANNELS];\r
\r
  uint32_t scrambler_seed;\r
  uint8_t  ddr_speed;            // need to save for the case of frequency change\r
} MrcTimings_t;\r
\r
\r
// DENSITY: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb\r
// tCL is DRAM CAS Latency in clocks.\r
// All other timings are in picoseconds.\r
// Refer to JEDEC spec (or DRAM datasheet) when changing these values.\r
typedef struct DRAMParams_s {\r
  uint8_t  DENSITY;\r
  uint8_t  tCL;   // CAS latency in clocks\r
  uint32_t tRAS;  // ACT to PRE command period\r
  uint32_t tWTR;  // Delay from start of internal write transaction to internal read command\r
  uint32_t tRRD;  // ACT to ACT command period (JESD79 specific to page size 1K/2K)\r
  uint32_t tFAW;  // Four activate window (JESD79 specific to page size 1K/2K)\r
} DRAMParams_t;\r
\r
\r
// Boot mode defined as bit mask (1<<n)\r
#define bmCold     1    // full training\r
#define bmFast     2    // restore timing parameters\r
#define bmS3       4    // resume from S3\r
#define bmWarm     8\r
#define bmUnknown  0\r
\r
\r
// MRC execution status\r
#define MRC_SUCCESS     0      // initialization ok\r
#define MRC_E_MEMTEST   1      // memtest failed\r
\r
\r
//\r
// Input/output/context parameters for Memory Reference Code\r
//\r
typedef struct MRCParams_s\r
{\r
  //\r
  // Global settings\r
  //\r
\r
  uint32_t boot_mode;           // bmCold, bmFast, bmWarm, bmS3\r
  uint32_t uart_mmio_base;      // pcie serial port base address (force 0 to disable debug)\r
\r
  uint8_t  dram_width;          // x8, x16\r
  uint8_t  ddr_speed;           // DDRFREQ_800, DDRFREQ_1066\r
  uint8_t  ddr_type;            // DDR3, DDR3L\r
  uint8_t  ecc_enables;         // 0, 1 (memory size reduced to 7/8)\r
  uint8_t  scrambling_enables;  // 0, 1\r
  uint32_t rank_enables;        // 1, 3 (1'st rank has to be populated if 2'nd rank present)\r
  uint32_t channel_enables;     // 1 only\r
  uint32_t channel_width;       // x16 only\r
  uint32_t address_mode;        // 0, 1, 2 (mode 2 forced if ecc enabled)\r
\r
  // memConfig_t begin\r
  uint8_t refresh_rate;         // REFRESH_RATE       : 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED\r
  uint8_t sr_temp_range;        // SR_TEMP_RANGE      : 0=normal, 1=extended, others=RESERVED\r
  uint8_t ron_value;            // RON_VALUE          : 0=34ohm, 1=40ohm, others=RESERVED (select MRS1.DIC driver impedance control)\r
  uint8_t rtt_nom_value;        // RTT_NOM_VALUE      : 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED\r
  uint8_t rd_odt_value;         // RD_ODT_VALUE       : 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED\r
  // memConfig_t end\r
\r
  DRAMParams_t params;\r
\r
  //\r
  // Internally used\r
  //\r
\r
  uint32_t board_id;            // internally used for board layout (use x8 or x16 memory)\r
  uint32_t hte_setup : 1;       // when set hte reconfiguration requested\r
  uint32_t menu_after_mrc : 1;\r
  uint32_t power_down_disable :1;\r
  uint32_t tune_rcvn :1;\r
\r
  uint32_t channel_size[NUM_CHANNELS];\r
  uint32_t column_bits[NUM_CHANNELS];\r
  uint32_t row_bits[NUM_CHANNELS];\r
\r
  uint32_t mrs1;                // register content saved during training\r
\r
  //\r
  // Output\r
  //\r
\r
  uint32_t status;              // initialization result (non zero specifies error code)\r
  uint32_t mem_size;            // total memory size in bytes (excludes ECC banks)\r
\r
  MrcTimings_t timings;         // training results (also used on input)\r
\r
} MRCParams_t;\r
\r
// Alternative type name for consistent naming convention\r
#define MRC_PARAMS    MRCParams_t\r
\r
#endif // _MRC_H_\r