QuarkSocPkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / MemoryInit / Pei / prememinit.c

/************************************************************************\r
 *\r
 * Copyright (c) 2013-2015 Intel Corporation.\r
 *\r
* SPDX-License-Identifier: BSD-2-Clause-Patent\r
 *\r
 ************************************************************************/\r
\r
#include "mrc.h"\r
#include "memory_options.h"\r
\r
#include "meminit_utils.h"\r
#include "prememinit.h"\r
#include "io.h"\r
\r
// Read character from serial console\r
uint8_t mgetc(void);\r
\r
extern uint32_t DpfPrintMask;\r
\r
// Adjust configuration parameters before initialisation\r
// sequence.\r
void PreMemInit(\r
    MRCParams_t *mrc_params)\r
{\r
  const DRAMParams_t *dram_params;\r
\r
  uint8_t dram_width;\r
  uint32_t dram_cfg_index;\r
  uint32_t channel_i;\r
\r
  ENTERFN();\r
\r
#ifdef MRC_SV\r
  {\r
    uint8_t ch;\r
\r
    myloop:\r
\r
    DPF(D_INFO, "- c - continue\n");\r
    DPF(D_INFO, "- f - boot mode [%d]\n", mrc_params->boot_mode);\r
    DPF(D_INFO, "- r - rank enable [%d]\n", mrc_params->rank_enables);\r
    DPF(D_INFO, "- e - ecc switch [%d]\n", mrc_params->ecc_enables);\r
    DPF(D_INFO, "- b - scrambling switch [%d]\n", mrc_params->scrambling_enables);\r
    DPF(D_INFO, "- a - adr mode [%d]\n", mrc_params->address_mode);\r
    DPF(D_INFO, "- m - menu after mrc [%d]\n", mrc_params->menu_after_mrc);\r
    DPF(D_INFO, "- t - tune to rcvn [%d]\n", mrc_params->tune_rcvn);\r
    DPF(D_INFO, "- o - odt switch [%d]\n", mrc_params->rd_odt_value);\r
    DPF(D_INFO, "- d - dram density [%d]\n", mrc_params->params.DENSITY);\r
    DPF(D_INFO, "- p - power down disable [%d]\n", mrc_params->power_down_disable);\r
    DPF(D_INFO, "- l - log switch 0x%x\n", DpfPrintMask);\r
    ch = mgetc();\r
\r
    switch (ch)\r
    {\r
    case 'f':\r
      mrc_params->boot_mode >>= 1;\r
      if(mrc_params->boot_mode == bmUnknown)\r
      {\r
         mrc_params->boot_mode = bmWarm;\r
      }\r
      DPF(D_INFO, "Boot mode %d\n", mrc_params->boot_mode);\r
      break;\r
\r
    case 'p':\r
      mrc_params->power_down_disable ^= 1;\r
      DPF(D_INFO, "Power down disable %d\n", mrc_params->power_down_disable);\r
      break;\r
\r
    case 'r':\r
      mrc_params->rank_enables ^= 2;\r
      DPF(D_INFO, "Rank enable %d\n", mrc_params->rank_enables);\r
      break;\r
\r
    case 'e':\r
      mrc_params->ecc_enables ^= 1;\r
      DPF(D_INFO, "Ecc enable %d\n", mrc_params->ecc_enables);\r
      break;\r
\r
    case 'b':\r
      mrc_params->scrambling_enables ^= 1;\r
      DPF(D_INFO, "Scrambler enable %d\n", mrc_params->scrambling_enables);\r
      break;\r
\r
    case 'a':\r
      mrc_params->address_mode = (mrc_params->address_mode + 1) % 3;\r
      DPF(D_INFO, "Adr mode %d\n", mrc_params->address_mode);\r
      break;\r
\r
    case 'm':\r
       mrc_params->menu_after_mrc ^= 1;\r
      DPF(D_INFO, "Menu after mrc %d\n", mrc_params->menu_after_mrc);\r
      break;\r
\r
    case 't':\r
      mrc_params->tune_rcvn ^= 1;\r
      DPF(D_INFO, "Tune to rcvn %d\n", mrc_params->tune_rcvn);\r
      break;\r
\r
    case 'o':\r
      mrc_params->rd_odt_value = (mrc_params->rd_odt_value + 1) % 4;\r
      DPF(D_INFO, "Rd_odt_value %d\n", mrc_params->rd_odt_value);\r
      break;\r
\r
    case 'd':\r
      mrc_params->params.DENSITY = (mrc_params->params.DENSITY + 1) % 4;\r
      DPF(D_INFO, "Dram density %d\n", mrc_params->params.DENSITY);\r
      break;\r
\r
    case 'l':\r
      DpfPrintMask ^= 0x30;\r
      DPF(D_INFO, "Log mask %x\n", DpfPrintMask);\r
      break;\r
\r
    default:\r
      break;\r
    }\r
\r
    if (ch != 'c')\r
      goto myloop;\r
\r
  }\r
#endif\r
\r
  // initially expect success\r
  mrc_params->status = MRC_SUCCESS;\r
\r
  // todo!!! Setup board layout (must be reviewed as is selecting static timings)\r
  // 0 == R0 (DDR3 x16), 1 == R1 (DDR3 x16), 2 == DV (DDR3 x8), 3 == SV (DDR3 x8)\r
  if (mrc_params->dram_width == x8)\r
  {\r
    mrc_params->board_id = 2;  // select x8 layout\r
  }\r
  else\r
  {\r
    mrc_params->board_id = 0;  // select x16 layout\r
  }\r
\r
  // initially no memory\r
  mrc_params->mem_size = 0;\r
  channel_i = 0;\r
\r
  // begin of channel settings\r
  dram_width = mrc_params->dram_width;\r
  dram_params = &mrc_params->params;\r
  dram_cfg_index = 0;\r
\r
  // Determine Column & Row Bits:\r
  // Column:\r
  // 11 for 8Gbx8, else 10\r
  mrc_params->column_bits[channel_i] = ((dram_params[dram_cfg_index].DENSITY == 4) && (dram_width == x8)) ? (11) : (10);\r
\r
  // Row:\r
  // 512Mbx16=12 512Mbx8=13\r
  //   1Gbx16=13   1Gbx8=14\r
  //   2Gbx16=14   2Gbx8=15\r
  //   4Gbx16=15   4Gbx8=16\r
  //   8Gbx16=16   8Gbx8=16\r
  mrc_params->row_bits[channel_i] = 12 + (dram_params[dram_cfg_index].DENSITY)\r
      + (((dram_params[dram_cfg_index].DENSITY < 4) && (dram_width == x8)) ? (1) : (0));\r
\r
  // Determine Per Channel Memory Size:\r
  // (For 2 RANKs, multiply by 2)\r
  // (For 16 bit data bus, divide by 2)\r
  // DENSITY  WIDTH   MEM_AVAILABLE\r
  // 512Mb    x16     0x008000000 ( 128MB)\r
  // 512Mb    x8      0x010000000 ( 256MB)\r
  // 1Gb      x16     0x010000000 ( 256MB)\r
  // 1Gb      x8      0x020000000 ( 512MB)\r
  // 2Gb      x16     0x020000000 ( 512MB)\r
  // 2Gb      x8      0x040000000 (1024MB)\r
  // 4Gb      x16     0x040000000 (1024MB)\r
  // 4Gb      x8      0x080000000 (2048MB)\r
  mrc_params->channel_size[channel_i] = (1 << dram_params[dram_cfg_index].DENSITY);\r
  mrc_params->channel_size[channel_i] *= ((dram_width == x8) ? (2) : (1));\r
  mrc_params->channel_size[channel_i] *= (mrc_params->rank_enables == 0x3) ? (2) : (1);\r
  mrc_params->channel_size[channel_i] *= (mrc_params->channel_width == x16) ? (1) : (2);\r
\r
  // Determine memory size (convert number of 64MB/512Mb units)\r
  mrc_params->mem_size += mrc_params->channel_size[channel_i] << 26;\r
\r
  // end of channel settings\r
\r
  LEAVEFN();\r
  return;\r
}\r
\r