[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Smm / Dxe / SmmControlDxe / SmmControlDriver.c

/** @file\r
This module produces the SMM COntrol2 Protocol for QNC\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <PiDxe.h>\r
#include <Protocol/SmmControl2.h>\r
#include <IndustryStandard/Pci.h>\r
#include <Library/DebugLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UefiRuntimeServicesTableLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
#include <IntelQNCDxe.h>\r
#include <Library/QNCAccessLib.h>\r
#include <Uefi/UefiBaseType.h>\r
\r
#define EFI_INTERNAL_POINTER  0x00000004\r
\r
extern EFI_GUID gEfiEventVirtualAddressChangeGuid;\r
\r
/**\r
  Generates an SMI using the parameters passed in.\r
\r
  @param  This                A pointer to an instance of\r
                              EFI_SMM_CONTROL2_PROTOCOL\r
  @param  ArgumentBuffer      The argument buffer\r
  @param  ArgumentBufferSize  The size of the argument buffer\r
  @param  Periodic            TRUE to indicate a periodical SMI\r
  @param  ActivationInterval  Interval of the periodical SMI\r
\r
  @retval EFI_INVALID_PARAMETER Periodic is TRUE or ArgumentBufferSize > 1\r
  @return Return value from SmmTrigger().\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
Activate (\r
  IN CONST EFI_SMM_CONTROL2_PROTOCOL     *This,\r
  IN OUT  UINT8                          *CommandPort       OPTIONAL,\r
  IN OUT  UINT8                          *DataPort          OPTIONAL,\r
  IN      BOOLEAN                        Periodic           OPTIONAL,\r
  IN      EFI_SMM_PERIOD                 ActivationInterval OPTIONAL\r
                  );\r
\r
/**\r
  Clears an SMI.\r
\r
  @param  This      Pointer to an instance of EFI_SMM_CONTROL2_PROTOCOL\r
  @param  Periodic  TRUE to indicate a periodical SMI\r
\r
  @return Return value from SmmClear()\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
Deactivate (\r
  IN CONST     EFI_SMM_CONTROL2_PROTOCOL  *This,\r
  IN      BOOLEAN                         Periodic OPTIONAL\r
  );\r
\r
///\r
/// Handle for the SMM Control2 Protocol\r
///\r
EFI_HANDLE  mSmmControl2Handle = NULL;\r
\r
///\r
/// SMM COntrol2 Protocol instance\r
///\r
EFI_SMM_CONTROL2_PROTOCOL mSmmControl2 = {\r
  Activate,\r
  Deactivate,\r
  0\r
};\r
\r
VOID\r
EFIAPI\r
SmmControlVirtualddressChangeEvent (\r
  IN EFI_EVENT                  Event,\r
  IN VOID                       *Context\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Fixup internal data pointers so that the services can be called in virtual mode.\r
\r
Arguments:\r
\r
  Event                         The event registered.\r
  Context                       Event context.\r
\r
Returns:\r
\r
  None.\r
\r
--*/\r
{\r
  gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl2.Trigger));\r
  gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl2.Clear));\r
}\r
\r
/**\r
  Clear SMI related chipset status and re-enable SMI by setting the EOS bit.\r
\r
  @retval EFI_SUCCESS The requested operation has been carried out successfully\r
  @retval EFI_DEVICE_ERROR  The EOS bit could not be set.\r
\r
**/\r
EFI_STATUS\r
SmmClear (\r
  VOID\r
  )\r
{\r
  UINT16                       PM1BLK_Base;\r
  UINT16                       GPE0BLK_Base;\r
\r
  //\r
  // Get PM1BLK_Base & GPE0BLK_Base\r
  //\r
  PM1BLK_Base  = PcdGet16 (PcdPm1blkIoBaseAddress);\r
  GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);\r
\r
  //\r
  // Clear the Power Button Override Status Bit, it gates EOS from being set.\r
  // In QuarkNcSocId - Bit is read only. Handled by external SMC, do nothing.\r
  //\r
\r
  //\r
  // Clear the APM SMI Status Bit\r
  //\r
  IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_APM);\r
\r
  //\r
  // Set the EOS Bit\r
  //\r
  IoOr32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_EOS);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Generates an SMI using the parameters passed in.\r
\r
  @param  This                A pointer to an instance of\r
                              EFI_SMM_CONTROL_PROTOCOL\r
  @param  ArgumentBuffer      The argument buffer\r
  @param  ArgumentBufferSize  The size of the argument buffer\r
  @param  Periodic            TRUE to indicate a periodical SMI\r
  @param  ActivationInterval  Interval of the periodical SMI\r
\r
  @retval EFI_INVALID_PARAMETER Periodic is TRUE or ArgumentBufferSize > 1\r
  @retval EFI_SUCCESS            SMI generated\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
Activate (\r
  IN CONST EFI_SMM_CONTROL2_PROTOCOL     *This,\r
  IN OUT  UINT8                          *CommandPort       OPTIONAL,\r
  IN OUT  UINT8                          *DataPort          OPTIONAL,\r
  IN      BOOLEAN                        Periodic           OPTIONAL,\r
  IN      EFI_SMM_PERIOD                 ActivationInterval OPTIONAL\r
  )\r
{\r
  UINT16        GPE0BLK_Base;\r
  UINT32        NewValue;\r
\r
  //\r
  // Get GPE0BLK_Base\r
  //\r
  GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);\r
\r
  if (Periodic) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Clear any pending the APM SMI\r
  //\r
  if (EFI_ERROR (SmmClear())) {\r
    return EFI_DEVICE_ERROR;\r
    }\r
\r
  //\r
  // Enable the APMC SMI\r
  //\r
  IoOr32 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIE, B_QNC_GPE0BLK_SMIE_APM);\r
\r
  //\r
  // Enable SMI globally\r
  //\r
  NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);\r
  NewValue |= SMI_EN;\r
  QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);\r
\r
\r
  //\r
  // Set APMC_STS\r
  //\r
  if (DataPort == NULL) {\r
    IoWrite8 (PcdGet16 (PcdSmmDataPort), 0xFF);\r
  } else {\r
    IoWrite8 (PcdGet16 (PcdSmmDataPort), *DataPort);\r
  }\r
\r
  //\r
  // Generate the APMC SMI\r
  //\r
  if (CommandPort == NULL) {\r
    IoWrite8 (PcdGet16 (PcdSmmActivationPort), 0xFF);\r
  } else {\r
    IoWrite8 (PcdGet16 (PcdSmmActivationPort), *CommandPort);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Clears an SMI.\r
\r
  @param  This      Pointer to an instance of EFI_SMM_CONTROL_PROTOCOL\r
  @param  Periodic  TRUE to indicate a periodical SMI\r
\r
  @return Return value from SmmClear()\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
Deactivate (\r
  IN CONST EFI_SMM_CONTROL2_PROTOCOL     *This,\r
  IN      BOOLEAN                   Periodic\r
  )\r
{\r
  if (Periodic) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return SmmClear();\r
}\r
\r
/**\r
  This is the constructor for the SMM Control protocol.\r
\r
  This function installs EFI_SMM_CONTROL2_PROTOCOL.\r
\r
  @param  ImageHandle Handle for the image of this driver\r
  @param  SystemTable Pointer to the EFI System Table\r
\r
  @retval EFI_UNSUPPORTED There's no Intel ICH on this platform\r
  @return The status returned from InstallProtocolInterface().\r
\r
--*/\r
EFI_STATUS\r
SmmControl2Init (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS  Status;\r
  EFI_EVENT   Event;\r
  UINT16      PM1BLK_Base;\r
  UINT16      GPE0BLK_Base;\r
  BOOLEAN     SciEn;\r
  UINT32      NewValue;\r
\r
  //\r
  // Get PM1BLK_Base & GPE0BLK_Base\r
  //\r
  PM1BLK_Base  = PcdGet16 (PcdPm1blkIoBaseAddress);\r
  GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);\r
\r
  //\r
  // Install our protocol interfaces on the device's handle\r
  //\r
  Status = gBS->InstallMultipleProtocolInterfaces (\r
                  &mSmmControl2Handle,\r
                  &gEfiSmmControl2ProtocolGuid,  &mSmmControl2,\r
                  NULL\r
                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  //\r
  // Determine whether an ACPI OS is present (via the SCI_EN bit)\r
  //\r
  SciEn = (BOOLEAN)((IoRead16 (PM1BLK_Base + R_QNC_PM1BLK_PM1C) & B_QNC_PM1BLK_PM1C_SCIEN) != 0);\r
  if (!SciEn) {\r
    //\r
    // Clear any SMIs that double as SCIs (when SCI_EN==0)\r
    //\r
    IoWrite16 ((PM1BLK_Base + R_QNC_PM1BLK_PM1S), B_QNC_PM1BLK_PM1S_ALL);\r
    IoWrite16 ((PM1BLK_Base + R_QNC_PM1BLK_PM1E), 0x00000000);\r
    IoWrite32 ((PM1BLK_Base + R_QNC_PM1BLK_PM1C),  0x00000000);\r
    IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_GPE0S), B_QNC_GPE0BLK_GPE0S_ALL);\r
    IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_GPE0E), 0x00000000);\r
  }\r
\r
  //\r
  // Clear and disable all SMIs that are unaffected by SCI_EN\r
  // Set EOS\r
  //\r
  IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIE), 0x00000000);\r
  IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), (B_QNC_GPE0BLK_SMIS_EOS + B_QNC_GPE0BLK_SMIS_ALL));\r
\r
  //\r
  // Enable SMI globally\r
  //\r
  NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);\r
  NewValue |= SMI_EN;\r
  QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);\r
\r
  //\r
  // Make sure to write this register last -- EOS re-enables SMIs for the QNC\r
  //\r
  IoAndThenOr32 (\r
    GPE0BLK_Base + R_QNC_GPE0BLK_SMIE,\r
    (UINT32)(~B_QNC_GPE0BLK_SMIE_ALL),\r
    B_QNC_GPE0BLK_SMIE_APM\r
    );\r
\r
  //\r
  // Make sure EOS bit cleared\r
  //\r
  DEBUG_CODE_BEGIN ();\r
  if (IoRead32 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIS) & B_QNC_GPE0BLK_SMIS_EOS) {\r
    DEBUG ((\r
      EFI_D_ERROR,\r
      "******************************************************************************\n"\r
      "BIG ERROR: SmmControl constructor couldn't properly initialize the ACPI table.\n"\r
      "           SmmControl->Clear will probably hang.                              \n"\r
      "              NOTE: SCI_EN = %d                                               \n"\r
      "******************************************************************************\n",\r
      SciEn\r
      ));\r
\r
    //\r
    // If we want the system to stop, then keep the ASSERT(FALSE).\r
    // Otherwise, comment it out.\r
    //\r
    ASSERT (FALSE);\r
  }\r
  DEBUG_CODE_END ();\r
\r
  Status = gBS->CreateEventEx (\r
                EVT_NOTIFY_SIGNAL,\r
                TPL_NOTIFY,\r
                SmmControlVirtualddressChangeEvent,\r
                NULL,\r
                &gEfiEventVirtualAddressChangeGuid,\r
                &Event\r
                );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	This module produces the SMM COntrol2 Protocol for QNC\r
	3	\r
	4	Copyright (c) 2013-2015 Intel Corporation.\r
	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#include <PiDxe.h>\r
	17	#include <Protocol/SmmControl2.h>\r
	18	#include <IndustryStandard/Pci.h>\r
	19	#include <Library/DebugLib.h>\r
	20	#include <Library/UefiBootServicesTableLib.h>\r
	21	#include <Library/UefiRuntimeServicesTableLib.h>\r
	22	#include <Library/PcdLib.h>\r
	23	#include <Library/IoLib.h>\r
	24	#include <Library/PciLib.h>\r
	25	#include <IntelQNCDxe.h>\r
	26	#include <Library/QNCAccessLib.h>\r
	27	#include <Uefi/UefiBaseType.h>\r
	28	\r
	29	#define EFI_INTERNAL_POINTER 0x00000004\r
	30	\r
	31	extern EFI_GUID gEfiEventVirtualAddressChangeGuid;\r
	32	\r
	33	/**\r
	34	Generates an SMI using the parameters passed in.\r
	35	\r
	36	@param This A pointer to an instance of\r
	37	EFI_SMM_CONTROL2_PROTOCOL\r
	38	@param ArgumentBuffer The argument buffer\r
	39	@param ArgumentBufferSize The size of the argument buffer\r
	40	@param Periodic TRUE to indicate a periodical SMI\r
	41	@param ActivationInterval Interval of the periodical SMI\r
	42	\r
	43	@retval EFI_INVALID_PARAMETER Periodic is TRUE or ArgumentBufferSize > 1\r
	44	@return Return value from SmmTrigger().\r
	45	\r
	46	**/\r
	47	EFI_STATUS\r
	48	EFIAPI\r
	49	Activate (\r
	50	IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,\r
	51	IN OUT UINT8 *CommandPort OPTIONAL,\r
	52	IN OUT UINT8 *DataPort OPTIONAL,\r
	53	IN BOOLEAN Periodic OPTIONAL,\r
	54	IN EFI_SMM_PERIOD ActivationInterval OPTIONAL\r
	55	);\r
	56	\r
	57	/**\r
	58	Clears an SMI.\r
	59	\r
	60	@param This Pointer to an instance of EFI_SMM_CONTROL2_PROTOCOL\r
	61	@param Periodic TRUE to indicate a periodical SMI\r
	62	\r
	63	@return Return value from SmmClear()\r
	64	\r
65	**/\r
66	EFI_STATUS\r
67	EFIAPI\r
68	Deactivate (\r
69	IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,\r
70	IN BOOLEAN Periodic OPTIONAL\r
71	);\r
72	\r
73	///\r
74	/// Handle for the SMM Control2 Protocol\r
75	///\r
76	EFI_HANDLE mSmmControl2Handle = NULL;\r
77	\r
78	///\r
79	/// SMM COntrol2 Protocol instance\r
80	///\r
81	EFI_SMM_CONTROL2_PROTOCOL mSmmControl2 = {\r
82	Activate,\r
83	Deactivate,\r
84	0\r
85	};\r
86	\r
87	VOID\r
88	EFIAPI\r
89	SmmControlVirtualddressChangeEvent (\r
90	IN EFI_EVENT Event,\r
91	IN VOID *Context\r
92	)\r
93	/*++\r
94	\r
95	Routine Description:\r
96	\r
97	Fixup internal data pointers so that the services can be called in virtual mode.\r
98	\r
99	Arguments:\r
100	\r
101	Event The event registered.\r
102	Context Event context.\r
103	\r
104	Returns:\r
105	\r
106	None.\r
107	\r
108	--*/\r
109	{\r
110	gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl2.Trigger));\r
111	gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl2.Clear));\r
112	}\r
113	\r
114	/**\r
115	Clear SMI related chipset status and re-enable SMI by setting the EOS bit.\r
116	\r
117	@retval EFI_SUCCESS The requested operation has been carried out successfully\r
118	@retval EFI_DEVICE_ERROR The EOS bit could not be set.\r
119	\r
120	**/\r
121	EFI_STATUS\r
122	SmmClear (\r
123	VOID\r
124	)\r
125	{\r
126	UINT16 PM1BLK_Base;\r
127	UINT16 GPE0BLK_Base;\r
128	\r
129	//\r
130	// Get PM1BLK_Base & GPE0BLK_Base\r
131	//\r
132	PM1BLK_Base = PcdGet16 (PcdPm1blkIoBaseAddress);\r
133	GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);\r
134	\r
135	//\r
136	// Clear the Power Button Override Status Bit, it gates EOS from being set.\r
137	// In QuarkNcSocId - Bit is read only. Handled by external SMC, do nothing.\r
138	//\r
139	\r
140	//\r
141	// Clear the APM SMI Status Bit\r
142	//\r
143	IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_APM);\r
144	\r
145	//\r
146	// Set the EOS Bit\r
147	//\r
148	IoOr32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_EOS);\r
149	\r
150	return EFI_SUCCESS;\r
151	}\r
152	\r
153	/**\r
154	Generates an SMI using the parameters passed in.\r
155	\r
156	@param This A pointer to an instance of\r
157	EFI_SMM_CONTROL_PROTOCOL\r
158	@param ArgumentBuffer The argument buffer\r
159	@param ArgumentBufferSize The size of the argument buffer\r
160	@param Periodic TRUE to indicate a periodical SMI\r
161	@param ActivationInterval Interval of the periodical SMI\r
162	\r
163	@retval EFI_INVALID_PARAMETER Periodic is TRUE or ArgumentBufferSize > 1\r
164	@retval EFI_SUCCESS SMI generated\r
165	\r
166	**/\r
167	EFI_STATUS\r
168	EFIAPI\r
169	Activate (\r
170	IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,\r
171	IN OUT UINT8 *CommandPort OPTIONAL,\r
172	IN OUT UINT8 *DataPort OPTIONAL,\r
173	IN BOOLEAN Periodic OPTIONAL,\r
174	IN EFI_SMM_PERIOD ActivationInterval OPTIONAL\r
175	)\r
176	{\r
177	UINT16 GPE0BLK_Base;\r
178	UINT32 NewValue;\r
179	\r
180	//\r
181	// Get GPE0BLK_Base\r
182	//\r
183	GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);\r
184	\r
185	if (Periodic) {\r
186	return EFI_INVALID_PARAMETER;\r
187	}\r
188	\r
189	//\r
190	// Clear any pending the APM SMI\r
191	//\r
192	if (EFI_ERROR (SmmClear())) {\r
193	return EFI_DEVICE_ERROR;\r
194	}\r
195	\r
196	//\r
197	// Enable the APMC SMI\r
198	//\r
199	IoOr32 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIE, B_QNC_GPE0BLK_SMIE_APM);\r
200	\r
201	//\r
202	// Enable SMI globally\r
203	//\r
204	NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);\r
205	NewValue \|= SMI_EN;\r
206	QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);\r
207	\r
208	\r
209	//\r
210	// Set APMC_STS\r
211	//\r
212	if (DataPort == NULL) {\r
213	IoWrite8 (PcdGet16 (PcdSmmDataPort), 0xFF);\r
214	} else {\r
215	IoWrite8 (PcdGet16 (PcdSmmDataPort), *DataPort);\r
216	}\r
217	\r
218	//\r
219	// Generate the APMC SMI\r
220	//\r
221	if (CommandPort == NULL) {\r
222	IoWrite8 (PcdGet16 (PcdSmmActivationPort), 0xFF);\r
223	} else {\r
224	IoWrite8 (PcdGet16 (PcdSmmActivationPort), *CommandPort);\r
225	}\r
226	\r
227	return EFI_SUCCESS;\r
228	}\r
229	\r
230	/**\r
231	Clears an SMI.\r
232	\r
233	@param This Pointer to an instance of EFI_SMM_CONTROL_PROTOCOL\r
234	@param Periodic TRUE to indicate a periodical SMI\r
235	\r
236	@return Return value from SmmClear()\r
237	\r
238	**/\r
239	EFI_STATUS\r
240	EFIAPI\r
241	Deactivate (\r
242	IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,\r
243	IN BOOLEAN Periodic\r
244	)\r
245	{\r
246	if (Periodic) {\r
247	return EFI_INVALID_PARAMETER;\r
248	}\r
249	\r
250	return SmmClear();\r
251	}\r
252	\r
253	/**\r
254	This is the constructor for the SMM Control protocol.\r
255	\r
256	This function installs EFI_SMM_CONTROL2_PROTOCOL.\r
257	\r
258	@param ImageHandle Handle for the image of this driver\r
259	@param SystemTable Pointer to the EFI System Table\r
260	\r
261	@retval EFI_UNSUPPORTED There's no Intel ICH on this platform\r
262	@return The status returned from InstallProtocolInterface().\r
263	\r
264	--*/\r
265	EFI_STATUS\r
266	SmmControl2Init (\r
267	IN EFI_HANDLE ImageHandle,\r
268	IN EFI_SYSTEM_TABLE *SystemTable\r
269	)\r
270	{\r
271	EFI_STATUS Status;\r
272	EFI_EVENT Event;\r
273	UINT16 PM1BLK_Base;\r
274	UINT16 GPE0BLK_Base;\r
275	BOOLEAN SciEn;\r
276	UINT32 NewValue;\r
277	\r
278	//\r
279	// Get PM1BLK_Base & GPE0BLK_Base\r
280	//\r
281	PM1BLK_Base = PcdGet16 (PcdPm1blkIoBaseAddress);\r
282	GPE0BLK_Base = PcdGet16 (PcdGpe0blkIoBaseAddress);\r
283	\r
284	//\r
285	// Install our protocol interfaces on the device's handle\r
286	//\r
287	Status = gBS->InstallMultipleProtocolInterfaces (\r
288	&mSmmControl2Handle,\r
289	&gEfiSmmControl2ProtocolGuid, &mSmmControl2,\r
290	NULL\r
291	);\r
292	ASSERT_EFI_ERROR (Status);\r
293	\r
294	//\r
295	// Determine whether an ACPI OS is present (via the SCI_EN bit)\r
296	//\r
297	SciEn = (BOOLEAN)((IoRead16 (PM1BLK_Base + R_QNC_PM1BLK_PM1C) & B_QNC_PM1BLK_PM1C_SCIEN) != 0);\r
298	if (!SciEn) {\r
299	//\r
300	// Clear any SMIs that double as SCIs (when SCI_EN==0)\r
301	//\r
302	IoWrite16 ((PM1BLK_Base + R_QNC_PM1BLK_PM1S), B_QNC_PM1BLK_PM1S_ALL);\r
303	IoWrite16 ((PM1BLK_Base + R_QNC_PM1BLK_PM1E), 0x00000000);\r
304	IoWrite32 ((PM1BLK_Base + R_QNC_PM1BLK_PM1C), 0x00000000);\r
305	IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_GPE0S), B_QNC_GPE0BLK_GPE0S_ALL);\r
306	IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_GPE0E), 0x00000000);\r
307	}\r
308	\r
309	//\r
310	// Clear and disable all SMIs that are unaffected by SCI_EN\r
311	// Set EOS\r
312	//\r
313	IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIE), 0x00000000);\r
314	IoWrite32 ((GPE0BLK_Base + R_QNC_GPE0BLK_SMIS), (B_QNC_GPE0BLK_SMIS_EOS + B_QNC_GPE0BLK_SMIS_ALL));\r
315	\r
316	//\r
317	// Enable SMI globally\r
318	//\r
319	NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);\r
320	NewValue \|= SMI_EN;\r
321	QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);\r
322	\r
323	//\r
324	// Make sure to write this register last -- EOS re-enables SMIs for the QNC\r
325	//\r
326	IoAndThenOr32 (\r
327	GPE0BLK_Base + R_QNC_GPE0BLK_SMIE,\r
328	(UINT32)(~B_QNC_GPE0BLK_SMIE_ALL),\r
329	B_QNC_GPE0BLK_SMIE_APM\r
330	);\r
331	\r
332	//\r
333	// Make sure EOS bit cleared\r
334	//\r
335	DEBUG_CODE_BEGIN ();\r
336	if (IoRead32 (GPE0BLK_Base + R_QNC_GPE0BLK_SMIS) & B_QNC_GPE0BLK_SMIS_EOS) {\r
337	DEBUG ((\r
338	EFI_D_ERROR,\r
339	"******************************************************************************\n"\r
340	"BIG ERROR: SmmControl constructor couldn't properly initialize the ACPI table.\n"\r
341	" SmmControl->Clear will probably hang. \n"\r
342	" NOTE: SCI_EN = %d \n"\r
343	"******************************************************************************\n",\r
344	SciEn\r
345	));\r
346	\r
347	//\r
348	// If we want the system to stop, then keep the ASSERT(FALSE).\r
349	// Otherwise, comment it out.\r
350	//\r
351	ASSERT (FALSE);\r
352	}\r
353	DEBUG_CODE_END ();\r
354	\r
355	Status = gBS->CreateEventEx (\r
356	EVT_NOTIFY_SIGNAL,\r
357	TPL_NOTIFY,\r
358	SmmControlVirtualddressChangeEvent,\r
359	NULL,\r
360	&gEfiEventVirtualAddressChangeGuid,\r
361	&Event\r
362	);\r
363	ASSERT_EFI_ERROR (Status);\r
364	\r
365	return Status;\r
366	}\r