[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Spi / Common / SpiCommon.h

/** @file\r
Header file for the PCH SPI Common Driver.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#ifndef _SPI_COMMON_H_\r
#define _SPI_COMMON_H_\r
\r
#include "Protocol/Spi.h"\r
#include <Library/PciLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/IntelQNCLib.h>\r
#include <Library/QNCAccessLib.h>\r
#include <Uefi/UefiBaseType.h>\r
\r
//\r
// Maximum time allowed while waiting the SPI cycle to complete\r
//  Wait Time = 6 seconds = 6000000 microseconds\r
//  Wait Period = 10 microseconds\r
//\r
#define WAIT_TIME   6000000\r
#define WAIT_PERIOD 10\r
//\r
// PCH Required SPI Commands -------- COMMAND SET I ------------\r
// SPI flash device must support in order to be compatible with PCH\r
//\r
#define PCH_SPI_COMMAND_PROGRAM_BYTE          0x02\r
#define PCH_SPI_COMMAND_READ_DATA             0x03\r
#define PCH_SPI_COMMAND_WRITE_DISABLE         0x04\r
#define PCH_SPI_COMMAND_READ_STATUS           0x05\r
#define PCH_SPI_COMMAND_WRITE_ENABLE          0x06\r
#define PCH_SPI_COMMAND_FAST_READ             0x0B\r
#define PCH_SPI_COMMAND_READ_ID               0x9F\r
#define PCH_SPI_COMMAND_DUAL_FAST_READ        0x3B  // Dual Output Fast Read\r
\r
//\r
// Need to support at least one of the following two kinds of size of sector for erasing\r
//\r
#define PCH_SPI_COMMAND_4KB_ERASE   0x20\r
#define PCH_SPI_COMMAND_64KB_ERASE  0xD8\r
//\r
// Recommended SPI Commands -------- COMMAND SET II ------------\r
// SPI flash device best to support\r
//\r
#define PCH_SPI_COMMAND_WRITE_STATUS    0x01\r
#define PCH_SPI_COMMAND_FULL_CHIP_ERASE 0xC7\r
\r
//\r
// Private data structure definitions for the driver\r
//\r
#define PCH_SPI_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('P', 'S', 'P', 'I')\r
\r
typedef struct {\r
  UINTN             Signature;\r
  EFI_HANDLE        Handle;\r
  EFI_SPI_PROTOCOL  SpiProtocol;\r
  SPI_INIT_TABLE    SpiInitTable;\r
  UINTN             PchRootComplexBar;\r
  BOOLEAN           InitDone; // Set to TRUE on SpiProtocolInit SUCCESS.\r
  SPI_INIT_INFO     InitInfo;\r
} SPI_INSTANCE;\r
\r
#define SPI_INSTANCE_FROM_SPIPROTOCOL(a)  CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)\r
\r
//\r
// Function prototypes used by the SPI protocol.\r
//\r
EFI_STATUS\r
SpiProtocolConstructor (\r
  SPI_INSTANCE          *SpiInstance\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Initialize an SPI protocol instance.\r
  The function will assert in debug if PCH RCBA has not been initialized\r
\r
Arguments:\r
\r
  SpiInstance   - Pointer to SpiInstance to initialize\r
\r
Returns:\r
\r
  EFI_SUCCESS     The protocol instance was properly initialized\r
  EFI_UNSUPPORTED The PCH is not supported by this module\r
\r
--*/\r
;\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolInit (\r
  IN EFI_SPI_PROTOCOL       *This,\r
  IN SPI_INIT_TABLE         *InitTable\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Initialize the host controller to execute SPI command.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitTable               Initialization data to be programmed into the SPI host controller.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Initialization completed.\r
  EFI_ACCESS_DENIED       The SPI static configuration interface has been locked-down.\r
  EFI_INVALID_PARAMETER   Bad input parameters.\r
--*/\r
;\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolLock (\r
  IN EFI_SPI_PROTOCOL       *This\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Lock the SPI Static Configuration Interface.\r
  Once locked, the interface can not be changed and can only be clear by system reset.\r
\r
Arguments:\r
\r
  This      Pointer to the EFI_SPI_PROTOCOL instance.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Lock operation succeed.\r
  EFI_DEVICE_ERROR        Device error, operation failed.\r
  EFI_ACCESS_DENIED       The interface has already been locked.\r
\r
--*/\r
;\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolExecute (\r
  IN     EFI_SPI_PROTOCOL   *This,\r
  IN     UINT8              OpcodeIndex,\r
  IN     UINT8              PrefixOpcodeIndex,\r
  IN     BOOLEAN            DataCycle,\r
  IN     BOOLEAN            Atomic,\r
  IN     BOOLEAN            ShiftOut,\r
  IN     UINTN              Address,\r
  IN     UINT32             DataByteCount,\r
  IN OUT UINT8              *Buffer,\r
  IN     SPI_REGION_TYPE    SpiRegionType\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Execute SPI commands from the host controller.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  OpcodeIndex             Index of the command in the OpCode Menu.\r
  PrefixOpcodeIndex       Index of the first command to run when in an atomic cycle sequence.\r
  DataCycle               TRUE if the SPI cycle contains data\r
  Atomic                  TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
  ShiftOut                If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
  Address                 In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                          Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                          this value specifies the offset from the start of the BIOS Image. In Non\r
                          Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                          Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                          Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                          supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                          the flash (in Non Descriptor Mode)\r
  DataByteCount           Number of bytes in the data portion of the SPI cycle.\r
  Buffer                  Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
  SpiRegionType           SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                          EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                          Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                          and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                          to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
\r
Returns:\r
\r
  EFI_SUCCESS             Command succeed.\r
  EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
  EFI_UNSUPPORTED         Command not supported.\r
  EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
\r
--*/\r
;\r
\r
EFI_STATUS\r
SendSpiCmd (\r
  IN     EFI_SPI_PROTOCOL   *This,\r
  IN     UINT8              OpcodeIndex,\r
  IN     UINT8              PrefixOpcodeIndex,\r
  IN     BOOLEAN            DataCycle,\r
  IN     BOOLEAN            Atomic,\r
  IN     BOOLEAN            ShiftOut,\r
  IN     UINTN              Address,\r
  IN     UINT32             DataByteCount,\r
  IN OUT UINT8              *Buffer,\r
  IN     SPI_REGION_TYPE    SpiRegionType\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  This function sends the programmed SPI command to the slave device.\r
\r
Arguments:\r
\r
  OpcodeIndex       Index of the command in the OpCode Menu.\r
  PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
  DataCycle         TRUE if the SPI cycle contains data\r
  Atomic            TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
  ShiftOut          If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
  Address           In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
                    Region, this value specifies the offset from the Region Base; for BIOS Region,\r
                    this value specifies the offset from the start of the BIOS Image. In Non\r
                    Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
                    Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
                    Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
                    supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
                    the flash (in Non Descriptor Mode)\r
  DataByteCount     Number of bytes in the data portion of the SPI cycle. This function may break the\r
                    data transfer into multiple operations. This function ensures each operation does\r
                    not cross 256 byte flash address boundary.\r
                    *NOTE: if there is some SPI chip that has a stricter address boundary requirement\r
                    (e.g., its write page size is < 256 byte), then the caller cannot rely on this\r
                    function to cut the data transfer at proper address boundaries, and it's the\r
                    caller's reponsibility to pass in a properly cut DataByteCount parameter.\r
  Buffer            Data received or sent during the SPI cycle.\r
  SpiRegionType     SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
                    EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
                    Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
                    and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
                    to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
\r
Returns:\r
\r
  EFI_SUCCESS             SPI command completes successfully.\r
  EFI_DEVICE_ERROR        Device error, the command aborts abnormally.\r
  EFI_ACCESS_DENIED       Some unrecognized command encountered in hardware sequencing mode\r
  EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
\r
--*/\r
;\r
\r
BOOLEAN\r
WaitForSpiCycleComplete (\r
  IN     EFI_SPI_PROTOCOL   *This,\r
  IN     BOOLEAN            ErrorCheck\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Wait execution cycle to complete on the SPI interface. Check both Hardware\r
  and Software Sequencing status registers\r
\r
Arguments:\r
\r
  This                - The SPI protocol instance\r
  UseSoftwareSequence - TRUE if this is a Hardware Sequencing operation\r
  ErrorCheck          - TRUE if the SpiCycle needs to do the error check\r
\r
Returns:\r
\r
  TRUE       SPI cycle completed on the interface.\r
  FALSE      Time out while waiting the SPI cycle to complete.\r
             It's not safe to program the next command on the SPI interface.\r
\r
--*/\r
;\r
\r
EFI_STATUS\r
EFIAPI\r
SpiProtocolInfo (\r
  IN EFI_SPI_PROTOCOL     *This,\r
  OUT SPI_INIT_INFO      **InitInfoPtr\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Return info about SPI host controller, to help callers usage of Execute\r
  service.\r
\r
  If 0xff is returned as an opcode index in init info struct\r
  then device does not support the operation.\r
\r
Arguments:\r
\r
  This                    Pointer to the EFI_SPI_PROTOCOL instance.\r
  InitInfoPtr             Pointer to init info written to this memory location.\r
\r
Returns:\r
\r
  EFI_SUCCESS             Information returned.\r
  EFI_INVALID_PARAMETER   Invalid parameter.\r
  EFI_NOT_READY           Required resources not setup.\r
  Others                  Unexpected error happened.\r
\r
--*/\r
;\r
\r
#endif\r
Commit	Line	Data
9b6bbcdb MK	1	/** @file\r
	2	Header file for the PCH SPI Common Driver.\r
	3	\r
	4	Copyright (c) 2013-2015 Intel Corporation.\r
	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	#ifndef _SPI_COMMON_H_\r
	16	#define _SPI_COMMON_H_\r
	17	\r
	18	#include "Protocol/Spi.h"\r
	19	#include <Library/PciLib.h>\r
	20	#include <Library/IoLib.h>\r
	21	#include <Library/DebugLib.h>\r
	22	#include <Library/PcdLib.h>\r
	23	#include <Library/BaseMemoryLib.h>\r
	24	#include <Library/IntelQNCLib.h>\r
	25	#include <Library/QNCAccessLib.h>\r
	26	#include <Uefi/UefiBaseType.h>\r
	27	\r
	28	//\r
	29	// Maximum time allowed while waiting the SPI cycle to complete\r
	30	// Wait Time = 6 seconds = 6000000 microseconds\r
	31	// Wait Period = 10 microseconds\r
	32	//\r
	33	#define WAIT_TIME 6000000\r
	34	#define WAIT_PERIOD 10\r
	35	//\r
	36	// PCH Required SPI Commands -------- COMMAND SET I ------------\r
	37	// SPI flash device must support in order to be compatible with PCH\r
	38	//\r
	39	#define PCH_SPI_COMMAND_PROGRAM_BYTE 0x02\r
	40	#define PCH_SPI_COMMAND_READ_DATA 0x03\r
	41	#define PCH_SPI_COMMAND_WRITE_DISABLE 0x04\r
	42	#define PCH_SPI_COMMAND_READ_STATUS 0x05\r
	43	#define PCH_SPI_COMMAND_WRITE_ENABLE 0x06\r
	44	#define PCH_SPI_COMMAND_FAST_READ 0x0B\r
	45	#define PCH_SPI_COMMAND_READ_ID 0x9F\r
	46	#define PCH_SPI_COMMAND_DUAL_FAST_READ 0x3B // Dual Output Fast Read\r
	47	\r
	48	//\r
	49	// Need to support at least one of the following two kinds of size of sector for erasing\r
	50	//\r
	51	#define PCH_SPI_COMMAND_4KB_ERASE 0x20\r
	52	#define PCH_SPI_COMMAND_64KB_ERASE 0xD8\r
	53	//\r
	54	// Recommended SPI Commands -------- COMMAND SET II ------------\r
	55	// SPI flash device best to support\r
	56	//\r
	57	#define PCH_SPI_COMMAND_WRITE_STATUS 0x01\r
	58	#define PCH_SPI_COMMAND_FULL_CHIP_ERASE 0xC7\r
	59	\r
	60	//\r
	61	// Private data structure definitions for the driver\r
	62	//\r
	63	#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')\r
	64	\r
65	typedef struct {\r
66	UINTN Signature;\r
67	EFI_HANDLE Handle;\r
68	EFI_SPI_PROTOCOL SpiProtocol;\r
69	SPI_INIT_TABLE SpiInitTable;\r
70	UINTN PchRootComplexBar;\r
71	BOOLEAN InitDone; // Set to TRUE on SpiProtocolInit SUCCESS.\r
72	SPI_INIT_INFO InitInfo;\r
73	} SPI_INSTANCE;\r
74	\r
75	#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)\r
76	\r
77	//\r
78	// Function prototypes used by the SPI protocol.\r
79	//\r
80	EFI_STATUS\r
81	SpiProtocolConstructor (\r
82	SPI_INSTANCE *SpiInstance\r
83	)\r
84	/*++\r
85	\r
86	Routine Description:\r
87	\r
88	Initialize an SPI protocol instance.\r
89	The function will assert in debug if PCH RCBA has not been initialized\r
90	\r
91	Arguments:\r
92	\r
93	SpiInstance - Pointer to SpiInstance to initialize\r
94	\r
95	Returns:\r
96	\r
97	EFI_SUCCESS The protocol instance was properly initialized\r
98	EFI_UNSUPPORTED The PCH is not supported by this module\r
99	\r
100	--*/\r
101	;\r
102	\r
103	EFI_STATUS\r
104	EFIAPI\r
105	SpiProtocolInit (\r
106	IN EFI_SPI_PROTOCOL *This,\r
107	IN SPI_INIT_TABLE *InitTable\r
108	)\r
109	/*++\r
110	\r
111	Routine Description:\r
112	\r
113	Initialize the host controller to execute SPI command.\r
114	\r
115	Arguments:\r
116	\r
117	This Pointer to the EFI_SPI_PROTOCOL instance.\r
118	InitTable Initialization data to be programmed into the SPI host controller.\r
119	\r
120	Returns:\r
121	\r
122	EFI_SUCCESS Initialization completed.\r
123	EFI_ACCESS_DENIED The SPI static configuration interface has been locked-down.\r
124	EFI_INVALID_PARAMETER Bad input parameters.\r
125	--*/\r
126	;\r
127	\r
128	EFI_STATUS\r
129	EFIAPI\r
130	SpiProtocolLock (\r
131	IN EFI_SPI_PROTOCOL *This\r
132	)\r
133	/*++\r
134	\r
135	Routine Description:\r
136	\r
137	Lock the SPI Static Configuration Interface.\r
138	Once locked, the interface can not be changed and can only be clear by system reset.\r
139	\r
140	Arguments:\r
141	\r
142	This Pointer to the EFI_SPI_PROTOCOL instance.\r
143	\r
144	Returns:\r
145	\r
146	EFI_SUCCESS Lock operation succeed.\r
147	EFI_DEVICE_ERROR Device error, operation failed.\r
148	EFI_ACCESS_DENIED The interface has already been locked.\r
149	\r
150	--*/\r
151	;\r
152	\r
153	EFI_STATUS\r
154	EFIAPI\r
155	SpiProtocolExecute (\r
156	IN EFI_SPI_PROTOCOL *This,\r
157	IN UINT8 OpcodeIndex,\r
158	IN UINT8 PrefixOpcodeIndex,\r
159	IN BOOLEAN DataCycle,\r
160	IN BOOLEAN Atomic,\r
161	IN BOOLEAN ShiftOut,\r
162	IN UINTN Address,\r
163	IN UINT32 DataByteCount,\r
164	IN OUT UINT8 *Buffer,\r
165	IN SPI_REGION_TYPE SpiRegionType\r
166	)\r
167	/*++\r
168	\r
169	Routine Description:\r
170	\r
171	Execute SPI commands from the host controller.\r
172	\r
173	Arguments:\r
174	\r
175	This Pointer to the EFI_SPI_PROTOCOL instance.\r
176	OpcodeIndex Index of the command in the OpCode Menu.\r
177	PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
178	DataCycle TRUE if the SPI cycle contains data\r
179	Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
180	ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
181	Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
182	Region, this value specifies the offset from the Region Base; for BIOS Region,\r
183	this value specifies the offset from the start of the BIOS Image. In Non\r
184	Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
185	Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
186	Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
187	supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
188	the flash (in Non Descriptor Mode)\r
189	DataByteCount Number of bytes in the data portion of the SPI cycle.\r
190	Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
191	SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
192	EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
193	Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
194	and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
195	to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
196	\r
197	Returns:\r
198	\r
199	EFI_SUCCESS Command succeed.\r
200	EFI_INVALID_PARAMETER The parameters specified are not valid.\r
201	EFI_UNSUPPORTED Command not supported.\r
202	EFI_DEVICE_ERROR Device error, command aborts abnormally.\r
203	\r
204	--*/\r
205	;\r
206	\r
207	EFI_STATUS\r
208	SendSpiCmd (\r
209	IN EFI_SPI_PROTOCOL *This,\r
210	IN UINT8 OpcodeIndex,\r
211	IN UINT8 PrefixOpcodeIndex,\r
212	IN BOOLEAN DataCycle,\r
213	IN BOOLEAN Atomic,\r
214	IN BOOLEAN ShiftOut,\r
215	IN UINTN Address,\r
216	IN UINT32 DataByteCount,\r
217	IN OUT UINT8 *Buffer,\r
218	IN SPI_REGION_TYPE SpiRegionType\r
219	)\r
220	/*++\r
221	\r
222	Routine Description:\r
223	\r
224	This function sends the programmed SPI command to the slave device.\r
225	\r
226	Arguments:\r
227	\r
228	OpcodeIndex Index of the command in the OpCode Menu.\r
229	PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
230	DataCycle TRUE if the SPI cycle contains data\r
231	Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
232	ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
233	Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
234	Region, this value specifies the offset from the Region Base; for BIOS Region,\r
235	this value specifies the offset from the start of the BIOS Image. In Non\r
236	Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
237	Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
238	Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
239	supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
240	the flash (in Non Descriptor Mode)\r
241	DataByteCount Number of bytes in the data portion of the SPI cycle. This function may break the\r
242	data transfer into multiple operations. This function ensures each operation does\r
243	not cross 256 byte flash address boundary.\r
244	*NOTE: if there is some SPI chip that has a stricter address boundary requirement\r
245	(e.g., its write page size is < 256 byte), then the caller cannot rely on this\r
246	function to cut the data transfer at proper address boundaries, and it's the\r
247	caller's reponsibility to pass in a properly cut DataByteCount parameter.\r
248	Buffer Data received or sent during the SPI cycle.\r
249	SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
250	EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
251	Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
252	and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
253	to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
254	\r
255	Returns:\r
256	\r
257	EFI_SUCCESS SPI command completes successfully.\r
258	EFI_DEVICE_ERROR Device error, the command aborts abnormally.\r
259	EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode\r
260	EFI_INVALID_PARAMETER The parameters specified are not valid.\r
261	\r
262	--*/\r
263	;\r
264	\r
265	BOOLEAN\r
266	WaitForSpiCycleComplete (\r
267	IN EFI_SPI_PROTOCOL *This,\r
268	IN BOOLEAN ErrorCheck\r
269	)\r
270	/*++\r
271	\r
272	Routine Description:\r
273	\r
274	Wait execution cycle to complete on the SPI interface. Check both Hardware\r
275	and Software Sequencing status registers\r
276	\r
277	Arguments:\r
278	\r
279	This - The SPI protocol instance\r
280	UseSoftwareSequence - TRUE if this is a Hardware Sequencing operation\r
281	ErrorCheck - TRUE if the SpiCycle needs to do the error check\r
282	\r
283	Returns:\r
284	\r
285	TRUE SPI cycle completed on the interface.\r
286	FALSE Time out while waiting the SPI cycle to complete.\r
287	It's not safe to program the next command on the SPI interface.\r
288	\r
289	--*/\r
290	;\r
291	\r
292	EFI_STATUS\r
293	EFIAPI\r
294	SpiProtocolInfo (\r
295	IN EFI_SPI_PROTOCOL *This,\r
296	OUT SPI_INIT_INFO **InitInfoPtr\r
297	)\r
298	/*++\r
299	\r
300	Routine Description:\r
301	\r
302	Return info about SPI host controller, to help callers usage of Execute\r
303	service.\r
304	\r
305	If 0xff is returned as an opcode index in init info struct\r
306	then device does not support the operation.\r
307	\r
308	Arguments:\r
309	\r
310	This Pointer to the EFI_SPI_PROTOCOL instance.\r
311	InitInfoPtr Pointer to init info written to this memory location.\r
312	\r
313	Returns:\r
314	\r
315	EFI_SUCCESS Information returned.\r
316	EFI_INVALID_PARAMETER Invalid parameter.\r
317	EFI_NOT_READY Required resources not setup.\r
318	Others Unexpected error happened.\r
319	\r
320	--*/\r
321	;\r
322	\r
323	#endif\r