QuarkSocPkg: Add new package for Quark SoC X1000

[mirror_edk2.git] / QuarkSocPkg / QuarkNorthCluster / Spi / RuntimeDxe / PchSpi.c

/** @file\r
PCH SPI Runtime Driver implements the SPI Host Controller Compatibility Interface.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#include "PchSpi.h"\r
\r
extern EFI_GUID gEfiEventVirtualAddressChangeGuid;\r
\r
//\r
// Global variables\r
//\r
SPI_INSTANCE  *mSpiInstance;\r
CONST UINT32 mSpiRegister[] = {\r
  R_QNC_RCRB_SPIS,\r
  R_QNC_RCRB_SPIPREOP,\r
  R_QNC_RCRB_SPIOPMENU,\r
  R_QNC_RCRB_SPIOPMENU + 4\r
  };\r
\r
//\r
// Function implementations\r
//\r
VOID\r
PchSpiVirtualddressChangeEvent (\r
  IN EFI_EVENT        Event,\r
  IN VOID             *Context\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Fixup internal data pointers so that the services can be called in virtual mode.\r
\r
Arguments:\r
\r
  Event     The event registered.\r
  Context   Event context. Not used in this event handler.\r
\r
Returns:\r
\r
  None.\r
\r
--*/\r
{\r
  gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSpiInstance->PchRootComplexBar));\r
  gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSpiInstance->SpiProtocol.Init));\r
  gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSpiInstance->SpiProtocol.Lock));\r
  gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSpiInstance->SpiProtocol.Execute));\r
  gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSpiInstance));\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
InstallPchSpi (\r
  IN EFI_HANDLE            ImageHandle,\r
  IN EFI_SYSTEM_TABLE      *SystemTable\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Entry point for the SPI host controller driver.\r
\r
Arguments:\r
\r
  ImageHandle       Image handle of this driver.\r
  SystemTable       Global system service table.\r
\r
Returns:\r
\r
  EFI_SUCCESS           Initialization complete.\r
  EFI_UNSUPPORTED       The chipset is unsupported by this driver.\r
  EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.\r
  EFI_DEVICE_ERROR      Device error, driver exits abnormally.\r
\r
--*/\r
{\r
  EFI_STATUS                      Status;\r
  UINT64                          BaseAddress;\r
  UINT64                          Length;\r
  EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdMemorySpaceDescriptor;\r
  UINT64                          Attributes;\r
  EFI_EVENT                       Event;\r
\r
  DEBUG ((DEBUG_INFO, "InstallPchSpi() Start\n"));\r
\r
  //\r
  // Allocate Runtime memory for the SPI protocol instance.\r
  //\r
  mSpiInstance = AllocateRuntimeZeroPool (sizeof (SPI_INSTANCE));\r
  if (mSpiInstance == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
  //\r
  // Initialize the SPI protocol instance\r
  //\r
  Status = SpiProtocolConstructor (mSpiInstance);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Install the EFI_SPI_PROTOCOL interface\r
  //\r
  Status = gBS->InstallMultipleProtocolInterfaces (\r
                  &(mSpiInstance->Handle),\r
                  &gEfiSpiProtocolGuid,\r
                  &(mSpiInstance->SpiProtocol),\r
                  NULL\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    FreePool (mSpiInstance);\r
    return EFI_DEVICE_ERROR;\r
  }\r
  //\r
  // Set RCBA space in GCD to be RUNTIME so that the range will be supported in\r
  // virtual address mode in EFI aware OS runtime.\r
  // It will assert if RCBA Memory Space is not allocated\r
  // The caller is responsible for the existence and allocation of the RCBA Memory Spaces\r
  //\r
  BaseAddress = (EFI_PHYSICAL_ADDRESS) (mSpiInstance->PchRootComplexBar);\r
  Length      = PcdGet64 (PcdRcbaMmioSize);\r
\r
  Status      = gDS->GetMemorySpaceDescriptor (BaseAddress, &GcdMemorySpaceDescriptor);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Attributes = GcdMemorySpaceDescriptor.Attributes | EFI_MEMORY_RUNTIME;\r
\r
  Status = gDS->AddMemorySpace (\r
                  EfiGcdMemoryTypeMemoryMappedIo,\r
                  BaseAddress,\r
                  Length,\r
                  EFI_MEMORY_RUNTIME | EFI_MEMORY_UC\r
                  );\r
  ASSERT_EFI_ERROR(Status);\r
\r
  Status = gDS->SetMemorySpaceAttributes (\r
                  BaseAddress,\r
                  Length,\r
                  Attributes\r
                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = gBS->CreateEventEx (\r
                  EVT_NOTIFY_SIGNAL,\r
                  TPL_NOTIFY,\r
                  PchSpiVirtualddressChangeEvent,\r
                  NULL,\r
                  &gEfiEventVirtualAddressChangeGuid,\r
                  &Event\r
                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  DEBUG ((DEBUG_INFO, "InstallPchSpi() End\n"));\r
\r
  return EFI_SUCCESS;\r
}\r
\r
VOID\r
EFIAPI\r
SpiPhaseInit (\r
  VOID\r
  )\r
/*++\r
Routine Description:\r
\r
  This function is a a hook for Spi Dxe phase specific initialization\r
\r
Arguments:\r
\r
  None\r
\r
Returns:\r
\r
  None\r
\r
--*/\r
{\r
  UINTN  Index;\r
\r
  //\r
  // Disable SMM BIOS write protect if it's not a SMM protocol\r
  //\r
  MmioAnd8 (\r
    PciDeviceMmBase (PCI_BUS_NUMBER_QNC,\r
    PCI_DEVICE_NUMBER_QNC_LPC,\r
    PCI_FUNCTION_NUMBER_QNC_LPC) + R_QNC_LPC_BIOS_CNTL,\r
    (UINT8) (~B_QNC_LPC_BIOS_CNTL_SMM_BWP)\r
    );\r
\r
    //\r
    // Save SPI Registers for S3 resume usage\r
    //\r
    for (Index = 0; Index < sizeof (mSpiRegister) / sizeof (UINT32); Index++) {\r
    S3BootScriptSaveMemWrite (\r
      S3BootScriptWidthUint32,\r
        (UINTN) (mSpiInstance->PchRootComplexBar + mSpiRegister[Index]),\r
        1,\r
        (VOID *) (UINTN) (mSpiInstance->PchRootComplexBar + mSpiRegister[Index])\r
        );\r
    }\r
}\r