projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 9b6bbcdb MK |
1 | /** @file\r |
| 2 | Include file for I2C DXE Driver register definitions (PCIe config. space and memory space).\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 5 | \r | |
| c9f231d0 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 9b6bbcdb MK |
7 | \r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | #ifndef _I2C_REGS_H_\r | |
| 11 | #define _I2C_REGS_H_\r | |
| 12 | \r | |
| 13 | \r | |
| 14 | //----------------------------------------------------------------------------\r | |
| 15 | /// I2C Device Address\r | |
| 16 | //----------------------------------------------------------------------------\r | |
| 17 | typedef struct {\r | |
| 18 | ///\r | |
| 19 | /// The I2C hardware address to which the I2C device is preassigned or allocated.\r | |
| 20 | ///\r | |
| 21 | UINTN I2CDeviceAddress : 10;\r | |
| 22 | } EFI_I2C_DEVICE_ADDRESS;\r | |
| 23 | \r | |
| 24 | //----------------------------------------------------------------------------\r | |
| 25 | /// I2C Addressing Mode (7-bit or 10 bit)\r | |
| 26 | //----------------------------------------------------------------------------\r | |
| 27 | typedef enum _EFI_I2C_ADDR_MODE {\r | |
| 28 | EfiI2CSevenBitAddrMode,\r | |
| 29 | EfiI2CTenBitAddrMode,\r | |
| 30 | } EFI_I2C_ADDR_MODE;\r | |
| 31 | \r | |
| 32 | \r | |
| 33 | //----------------------------------------------------------------------------\r | |
| 34 | // I2C Controller B:D:F\r | |
| 35 | //----------------------------------------------------------------------------\r | |
| 36 | #define I2C_Bus 0x00\r | |
| 37 | #define I2C_Device 0x15\r | |
| 38 | #define I2C_Func 0x02\r | |
| 39 | \r | |
| 40 | //----------------------------------------------------------------------------\r | |
| 41 | // Memory Mapped Registers\r | |
| 42 | //----------------------------------------------------------------------------\r | |
| 43 | #define I2C_REG_CON 0x00 // Control Register\r | |
| 44 | #define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10)\r | |
| 45 | #define B_I2C_REG_CON_10BITADD_MASTER (BIT4) // 7-bit addressing (0) or 10-bit addressing (1)\r | |
| 46 | #define I2C_REG_TAR 0x04 // Master Target Address Register\r | |
| 47 | #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits\r | |
| 48 | #define I2C_REG_DATA_CMD 0x10 // Data Buffer and Command Register\r | |
| 49 | #define B_I2C_REG_DATA_CMD_RW (BIT8) // Data Buffer and Command Register Read/Write bit\r | |
| 50 | #define B_I2C_REG_DATA_CMD_STOP (BIT9) // Data Buffer and Command Register STOP bit\r | |
| 51 | #define B_I2C_REG_DATA_CMD_RESTART (BIT10) // Data Buffer and Command Register RESTART bit\r | |
| 52 | #define I2C_REG_SS_SCL_HCNT 0x14 // Standard Speed Clock SCL High Count Register\r | |
| 53 | #define I2C_REG_SS_SCL_LCNT 0x18 // Standard Speed Clock SCL Low Count Register\r | |
| 54 | #define I2C_REG_FS_SCL_HCNT 0x1C // Fast Speed Clock SCL High Count Register\r | |
| 55 | #define I2C_REG_FS_SCL_LCNT 0x20 // Fast Speed Clock SCL Low Count Register\r | |
| 56 | #define I2C_REG_INTR_STAT 0x2C // Interrupt Status Register\r | |
| 57 | #define B_I2C_REG_INTR_STAT_STOP_DET (BIT9) // Interrupt Status Register STOP_DET signal status\r | |
| 58 | #define I2C_REG_INTR_MASK 0x30 // Interrupt Status Mask Register\r | |
| 59 | #define I2C_REG_RAW_INTR_STAT 0x34 // Raw Interrupt Status Register\r | |
| 60 | #define I2C_REG_RAW_INTR_STAT_STOP_DET (BIT9) // Raw Interrupt Status Register STOP_DET signal status.\r | |
| 61 | #define I2C_REG_RAW_INTR_STAT_TX_ABRT (BIT6) // Raw Interrupt Status Register TX Abort status.\r | |
| 62 | #define I2C_REG_RAW_INTR_STAT_TX_OVER (BIT3) // Raw Interrupt Status Register TX Overflow signal status.\r | |
| 63 | #define I2C_REG_RAW_INTR_STAT_RX_OVER (BIT1) // Raw Interrupt Status Register RX Overflow signal status.\r | |
| 64 | #define I2C_REG_RAW_INTR_STAT_RX_UNDER (BIT0) // Raw Interrupt Status Register RX Underflow signal status.\r | |
| 65 | #define I2C_REG_RX_TL 0x38 // Receive FIFO Threshold Level Register\r | |
| 66 | #define I2C_REG_TX_TL 0x3C // Transmit FIFO Threshold Level Register\r | |
| 67 | #define I2C_REG_CLR_INT 0x40 // Clear Combined and Individual Interrupt Register\r | |
| 68 | #define I2C_REG_CLR_RX_UNDER 0x44 // Clear RX Under Interrupt Register\r | |
| 69 | #define I2C_REG_CLR_RX_OVER 0x48 // Clear RX Over Interrupt Register\r | |
| 70 | #define I2C_REG_CLR_TX_OVER 0x4C // Clear TX Over Interrupt Register\r | |
| 71 | #define I2C_REG_CLR_RD_REQ 0x50 // Clear RD REQ Interrupt Register\r | |
| 72 | #define I2C_REG_CLR_TX_ABRT 0x54 // Clear TX ABRT Interrupt Register\r | |
| 73 | #define I2C_REG_CLR_ACTIVITY 0x5C // Clear Activity Interrupt Register\r | |
| 74 | #define I2C_REG_CLR_STOP_DET 0x60 // Clear STOP DET Interrupt Register\r | |
| 75 | #define B_I2C_REG_CLR_STOP_DET (BIT0) // Clear STOP DET Interrupt Register\r | |
| 76 | #define I2C_REG_CLR_START_DET 0x64 // Clear START DET Interrupt Register\r | |
| 77 | #define B_I2C_REG_CLR_START_DET (BIT0) // Clear START DET Interrupt Register\r | |
| 78 | #define I2C_REG_ENABLE 0x6C // Enable Register\r | |
| 79 | #define B_I2C_REG_ENABLE (BIT0) // Enable (1) or disable (0) I2C Controller\r | |
| 80 | #define I2C_REG_STATUS 0x70 // Status Register\r | |
| 81 | #define I2C_REG_TXFLR 0x74 // Transmit FIFO Level Register\r | |
| 82 | #define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register bits\r | |
| 83 | #define I2C_REG_RXFLR 0x78 // Receive FIFO Level Register\r | |
| 84 | #define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register bits\r | |
| 85 | #define I2C_REG_SDA_HOLD 0x7C // SDA HOLD Register\r | |
| 86 | #define I2C_REG_TX_ABRT_SOURCE 0x80 // Transmit Abort Source Register\r | |
| 87 | #define I2C_REG_ENABLE_STATUS 0x9C // Enable Status Register\r | |
| 88 | #define I2C_REG_FS_SPKLEN 0xA0 // SS and FS Spike Suppression Limit Register\r | |
| 89 | \r | |
| 90 | //\r | |
| 91 | // Features.\r | |
| 92 | //\r | |
| 93 | #define I2C_FIFO_SIZE 16\r | |
| 94 | \r | |
| 95 | #endif\r |