[mirror_edk2.git] / SecurityPkg / Include / Library / TpmCommLib.h

/** @file\r
  This library is only intended to be used by TPM modules.\r
  It provides basic TPM Interface Specification (TIS) and Command functions.\r
\r
Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution.  The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _TPM_COMM_LIB_H_\r
#define _TPM_COMM_LIB_H_\r
\r
#include <IndustryStandard/Tpm12.h>\r
\r
typedef EFI_HANDLE  TIS_TPM_HANDLE;\r
\r
///\r
/// TPM register base address.\r
///\r
#define TPM_BASE_ADDRESS            0xfed40000\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in TIS specification Chapter 10\r
//\r
typedef struct {\r
  ///\r
  /// Used to gain ownership for this particular port.\r
  ///\r
  UINT8                             Access;             // 0\r
  UINT8                             Reserved1[7];       // 1\r
  ///\r
  /// Controls interrupts.\r
  ///\r
  UINT32                            IntEnable;          // 8\r
  ///\r
  /// SIRQ vector to be used by the TPM.\r
  ///\r
  UINT8                             IntVector;          // 0ch\r
  UINT8                             Reserved2[3];       // 0dh\r
  ///\r
  /// What caused interrupt.\r
  ///\r
  UINT32                            IntSts;             // 10h\r
  ///\r
  /// Shows which interrupts are supported by that particular TPM.\r
  ///\r
  UINT32                            IntfCapability;     // 14h\r
  ///\r
  /// Status Register. Provides status of the TPM.\r
  ///\r
  UINT8                             Status;             // 18h\r
  ///\r
  /// Number of consecutive writes that can be done to the TPM.\r
  ///\r
  UINT16                            BurstCount;         // 19h\r
  UINT8                             Reserved3[9];\r
  ///\r
  /// Read or write FIFO, depending on transaction.\r
  ///\r
  UINT32                            DataFifo;           // 24\r
  UINT8                             Reserved4[0xed8];   // 28h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16                            Vid;                // 0f00h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16                            Did;                // 0f02h\r
  ///\r
  /// Revision ID\r
  ///\r
  UINT8                             Rid;                // 0f04h\r
  ///\r
  /// TCG defined configuration registers.\r
  ///\r
  UINT8                             TcgDefined[0x7b];   // 0f05h\r
  ///\r
  /// Alias to I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress1;     // 0f80h\r
  ///\r
  /// Additional 8 bits for I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress1Ex;   // 0f84h\r
  ///\r
  /// Alias to second I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress2;     // 0f88h\r
  ///\r
  /// Additional 8 bits for second I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress2Ex;   // 0f8ch\r
  ///\r
  /// Vendor-defined configuration registers.\r
  ///\r
  UINT8                             VendorDefined[0x70];// 0f90h\r
} TIS_PC_REGISTERS;\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;\r
\r
//\r
// TCG Platform Type based on TCG ACPI Specification Version 1.00\r
//\r
#define TCG_PLATFORM_TYPE_CLIENT   0\r
#define TCG_PLATFORM_TYPE_SERVER   1\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
#define TIS_PC_VALID                BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
#define TIS_PC_ACC_ACTIVE           BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
#define TIS_PC_ACC_SEIZED           BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
#define TIS_PC_ACC_SEIZE            BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
#define TIS_PC_ACC_PENDIND          BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
#define TIS_PC_ACC_RQUUSE           BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
#define TIS_PC_ACC_ESTABLISH        BIT0\r
\r
///\r
/// When this bit is 1, TPM is in the Ready state, \r
/// indicating it is ready to receive a new command.\r
///\r
#define TIS_PC_STS_READY            BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
#define TIS_PC_STS_GO               BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
#define TIS_PC_STS_DATA             BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
#define TIS_PC_STS_EXPECT           BIT3\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
#define TIS_PC_STS_RETRY            BIT1\r
\r
//\r
// Default TimeOut value\r
//\r
#define TIS_TIMEOUT_A               750 * 1000   // 750ms\r
#define TIS_TIMEOUT_B               2000 * 1000  // 2s\r
#define TIS_TIMEOUT_C               750 * 1000   // 750ms\r
#define TIS_TIMEOUT_D               750 * 1000   // 750ms\r
\r
//\r
// Max TPM command/reponse length\r
//\r
#define TPMCMDBUFLENGTH             1024\r
\r
/**\r
  Check whether the value of a TPM chip register satisfies the input BIT setting.\r
\r
  @param[in]  Register     Address port of register to be checked.\r
  @param[in]  BitSet       Check these data bits are set.\r
  @param[in]  BitClear     Check these data bits are clear.\r
  @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.\r
\r
  @retval     EFI_SUCCESS  The register satisfies the check bit.\r
  @retval     EFI_TIMEOUT  The register can't run into the expected status in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
TisPcWaitRegisterBits (\r
  IN UINT8   *Register,\r
  IN UINT8   BitSet,   \r
  IN UINT8   BitClear, \r
  IN UINT32  TimeOut   \r
  );\r
\r
/**\r
  Get BurstCount by reading the burstCount field of a TIS regiger \r
  in the time of default TIS_TIMEOUT_D.\r
\r
  @param[in]  TisReg                Pointer to TIS register.\r
  @param[out] BurstCount            Pointer to a buffer to store the got BurstConut.\r
\r
  @retval     EFI_SUCCESS           Get BurstCount.\r
  @retval     EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
  @retval     EFI_TIMEOUT           BurstCount can't be got in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
TisPcReadBurstCount (\r
  IN  TIS_PC_REGISTERS_PTR  TisReg,\r
  OUT UINT16                *BurstCount\r
  );\r
\r
/**\r
  Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r
  to Status Register in time.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           TPM chip enters into ready state.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_TIMEOUT           TPM chip can't be set to ready state in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
TisPcPrepareCommand (\r
  IN TIS_PC_REGISTERS_PTR  TisReg\r
  );\r
\r
/**\r
  Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r
  to ACCESS Register in the time of default TIS_TIMEOUT_D.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           Get the control of TPM chip.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_NOT_FOUND         TPM chip doesn't exit.\r
  @retval    EFI_TIMEOUT           Can't get the TPM control in time.\r
**/\r
EFI_STATUS\r
EFIAPI\r
TisPcRequestUseTpm (\r
  IN TIS_PC_REGISTERS_PTR  TisReg\r
  );\r
\r
/**\r
  Single function calculates SHA1 digest value for all raw data. It\r
  combines Sha1Init(), Sha1Update() and Sha1Final().\r
\r
  @param[in]  Data          Raw data to be digested.\r
  @param[in]  DataLen       Size of the raw data.\r
  @param[out] Digest        Pointer to a buffer that stores the final digest.\r
  \r
  @retval     EFI_SUCCESS   Always successfully calculate the final digest.\r
**/\r
EFI_STATUS\r
EFIAPI\r
TpmCommHashAll (\r
  IN  CONST UINT8       *Data,\r
  IN        UINTN       DataLen,\r
  OUT       TPM_DIGEST  *Digest\r
  );\r
\r
#endif\r
Commit	Line	Data
0c18794e	1	/** @file\r
07309c3d	2	This library is only intended to be used by TPM modules.\r
0c18794e	3	It provides basic TPM Interface Specification (TIS) and Command functions.\r
0c18794e	4	\r
07309c3d	5	Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>\r
0c18794e	6	This program and the accompanying materials \r
	7	are licensed and made available under the terms and conditions of the BSD License \r
	8	which accompanies this distribution. The full text of the license may be found at \r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _TPM_COMM_LIB_H_\r
	17	#define _TPM_COMM_LIB_H_\r
	18	\r
	19	#include <IndustryStandard/Tpm12.h>\r
	20	\r
	21	typedef EFI_HANDLE TIS_TPM_HANDLE;\r
	22	\r
	23	///\r
	24	/// TPM register base address.\r
	25	///\r
	26	#define TPM_BASE_ADDRESS 0xfed40000\r
	27	\r
	28	//\r
	29	// Set structure alignment to 1-byte\r
	30	//\r
	31	#pragma pack (1)\r
	32	\r
	33	//\r
	34	// Register set map as specified in TIS specification Chapter 10\r
	35	//\r
	36	typedef struct {\r
	37	///\r
	38	/// Used to gain ownership for this particular port.\r
	39	///\r
	40	UINT8 Access; // 0\r
	41	UINT8 Reserved1[7]; // 1\r
	42	///\r
	43	/// Controls interrupts.\r
	44	///\r
	45	UINT32 IntEnable; // 8\r
	46	///\r
	47	/// SIRQ vector to be used by the TPM.\r
	48	///\r
	49	UINT8 IntVector; // 0ch\r
	50	UINT8 Reserved2[3]; // 0dh\r
	51	///\r
	52	/// What caused interrupt.\r
	53	///\r
	54	UINT32 IntSts; // 10h\r
	55	///\r
	56	/// Shows which interrupts are supported by that particular TPM.\r
	57	///\r
	58	UINT32 IntfCapability; // 14h\r
	59	///\r
	60	/// Status Register. Provides status of the TPM.\r
	61	///\r
	62	UINT8 Status; // 18h\r
	63	///\r
	64	/// Number of consecutive writes that can be done to the TPM.\r
	65	///\r
	66	UINT16 BurstCount; // 19h\r
	67	UINT8 Reserved3[9];\r
	68	///\r
	69	/// Read or write FIFO, depending on transaction.\r
70	///\r
71	UINT32 DataFifo; // 24\r
72	UINT8 Reserved4[0xed8]; // 28h\r
73	///\r
74	/// Vendor ID\r
75	///\r
76	UINT16 Vid; // 0f00h\r
77	///\r
78	/// Device ID\r
79	///\r
80	UINT16 Did; // 0f02h\r
81	///\r
82	/// Revision ID\r
83	///\r
84	UINT8 Rid; // 0f04h\r
85	///\r
86	/// TCG defined configuration registers.\r
87	///\r
88	UINT8 TcgDefined[0x7b]; // 0f05h\r
89	///\r
90	/// Alias to I/O legacy space.\r
91	///\r
92	UINT32 LegacyAddress1; // 0f80h\r
93	///\r
94	/// Additional 8 bits for I/O legacy space extension.\r
95	///\r
96	UINT32 LegacyAddress1Ex; // 0f84h\r
97	///\r
98	/// Alias to second I/O legacy space.\r
99	///\r
100	UINT32 LegacyAddress2; // 0f88h\r
101	///\r
102	/// Additional 8 bits for second I/O legacy space extension.\r
103	///\r
104	UINT32 LegacyAddress2Ex; // 0f8ch\r
105	///\r
106	/// Vendor-defined configuration registers.\r
107	///\r
108	UINT8 VendorDefined[0x70];// 0f90h\r
109	} TIS_PC_REGISTERS;\r
110	\r
111	//\r
112	// Restore original structure alignment\r
113	//\r
114	#pragma pack ()\r
115	\r
116	//\r
117	// Define pointer types used to access TIS registers on PC\r
118	//\r
119	typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
120	\r
121	//\r
122	// TCG Platform Type based on TCG ACPI Specification Version 1.00\r
123	//\r
124	#define TCG_PLATFORM_TYPE_CLIENT 0\r
125	#define TCG_PLATFORM_TYPE_SERVER 1\r
126	\r
127	//\r
128	// Define bits of ACCESS and STATUS registers\r
129	//\r
130	\r
131	///\r
132	/// This bit is a 1 to indicate that the other bits in this register are valid.\r
133	///\r
134	#define TIS_PC_VALID BIT7\r
135	///\r
136	/// Indicate that this locality is active.\r
137	///\r
138	#define TIS_PC_ACC_ACTIVE BIT5\r
139	///\r
140	/// Set to 1 to indicate that this locality had the TPM taken away while\r
141	/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
142	///\r
143	#define TIS_PC_ACC_SEIZED BIT4\r
144	///\r
145	/// Set to 1 to indicate that TPM MUST reset the\r
146	/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
147	/// locality that is writing this bit.\r
148	///\r
149	#define TIS_PC_ACC_SEIZE BIT3\r
150	///\r
151	/// When this bit is 1, another locality is requesting usage of the TPM.\r
152	///\r
153	#define TIS_PC_ACC_PENDIND BIT2\r
154	///\r
155	/// Set to 1 to indicate that this locality is requesting to use TPM.\r
156	///\r
157	#define TIS_PC_ACC_RQUUSE BIT1\r
158	///\r
159	/// A value of 1 indicates that a T/OS has not been established on the platform\r
160	///\r
161	#define TIS_PC_ACC_ESTABLISH BIT0\r
162	\r
163	///\r
164	/// When this bit is 1, TPM is in the Ready state, \r
165	/// indicating it is ready to receive a new command.\r
166	///\r
167	#define TIS_PC_STS_READY BIT6\r
168	///\r
169	/// Write a 1 to this bit to cause the TPM to execute that command.\r
170	///\r
171	#define TIS_PC_STS_GO BIT5\r
172	///\r
173	/// This bit indicates that the TPM has data available as a response.\r
174	///\r
175	#define TIS_PC_STS_DATA BIT4\r
176	///\r
177	/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
178	///\r
179	#define TIS_PC_STS_EXPECT BIT3\r
180	///\r
181	/// Writes a 1 to this bit to force the TPM to re-send the response.\r
182	///\r
183	#define TIS_PC_STS_RETRY BIT1\r
184	\r
185	//\r
186	// Default TimeOut value\r
187	//\r
f941becd	188	#define TIS_TIMEOUT_A 750 * 1000 // 750ms\r
0c18794e	189	#define TIS_TIMEOUT_B 2000 * 1000 // 2s\r
	190	#define TIS_TIMEOUT_C 750 * 1000 // 750ms\r
	191	#define TIS_TIMEOUT_D 750 * 1000 // 750ms\r
	192	\r
	193	//\r
	194	// Max TPM command/reponse length\r
	195	//\r
	196	#define TPMCMDBUFLENGTH 1024\r
	197	\r
	198	/**\r
	199	Check whether the value of a TPM chip register satisfies the input BIT setting.\r
	200	\r
	201	@param[in] Register Address port of register to be checked.\r
	202	@param[in] BitSet Check these data bits are set.\r
	203	@param[in] BitClear Check these data bits are clear.\r
	204	@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r
	205	\r
	206	@retval EFI_SUCCESS The register satisfies the check bit.\r
	207	@retval EFI_TIMEOUT The register can't run into the expected status in time.\r
	208	**/\r
	209	EFI_STATUS\r
	210	EFIAPI\r
	211	TisPcWaitRegisterBits (\r
	212	IN UINT8 *Register,\r
	213	IN UINT8 BitSet, \r
	214	IN UINT8 BitClear, \r
	215	IN UINT32 TimeOut \r
	216	);\r
	217	\r
	218	/**\r
	219	Get BurstCount by reading the burstCount field of a TIS regiger \r
	220	in the time of default TIS_TIMEOUT_D.\r
	221	\r
	222	@param[in] TisReg Pointer to TIS register.\r
	223	@param[out] BurstCount Pointer to a buffer to store the got BurstConut.\r
	224	\r
	225	@retval EFI_SUCCESS Get BurstCount.\r
	226	@retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
	227	@retval EFI_TIMEOUT BurstCount can't be got in time.\r
	228	**/\r
	229	EFI_STATUS\r
	230	EFIAPI\r
	231	TisPcReadBurstCount (\r
	232	IN TIS_PC_REGISTERS_PTR TisReg,\r
	233	OUT UINT16 *BurstCount\r
	234	);\r
	235	\r
	236	/**\r
	237	Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r
	238	to Status Register in time.\r
	239	\r
	240	@param[in] TisReg Pointer to TIS register.\r
	241	\r
	242	@retval EFI_SUCCESS TPM chip enters into ready state.\r
	243	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
	244	@retval EFI_TIMEOUT TPM chip can't be set to ready state in time.\r
	245	**/\r
	246	EFI_STATUS\r
	247	EFIAPI\r
	248	TisPcPrepareCommand (\r
	249	IN TIS_PC_REGISTERS_PTR TisReg\r
	250	);\r
	251	\r
	252	/**\r
253	Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r
254	to ACCESS Register in the time of default TIS_TIMEOUT_D.\r
255	\r
256	@param[in] TisReg Pointer to TIS register.\r
257	\r
258	@retval EFI_SUCCESS Get the control of TPM chip.\r
259	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
260	@retval EFI_NOT_FOUND TPM chip doesn't exit.\r
261	@retval EFI_TIMEOUT Can't get the TPM control in time.\r
262	**/\r
263	EFI_STATUS\r
264	EFIAPI\r
265	TisPcRequestUseTpm (\r
266	IN TIS_PC_REGISTERS_PTR TisReg\r
267	);\r
268	\r
269	/**\r
270	Single function calculates SHA1 digest value for all raw data. It\r
271	combines Sha1Init(), Sha1Update() and Sha1Final().\r
272	\r
273	@param[in] Data Raw data to be digested.\r
274	@param[in] DataLen Size of the raw data.\r
275	@param[out] Digest Pointer to a buffer that stores the final digest.\r
276	\r
277	@retval EFI_SUCCESS Always successfully calculate the final digest.\r
278	**/\r
279	EFI_STATUS\r
280	EFIAPI\r
281	TpmCommHashAll (\r
282	IN CONST UINT8 *Data,\r
283	IN UINTN DataLen,\r
284	OUT TPM_DIGEST *Digest\r
285	);\r
286	\r
287	#endif\r