[mirror_edk2.git] / SecurityPkg / Library / Tpm12DeviceLibDTpm / Tpm12Tis.c

/** @file\r
  TIS (TPM Interface Specification) functions used by TPM1.2.\r
\r
Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Uefi.h>\r
#include <IndustryStandard/Tpm12.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/Tpm12CommandLib.h>\r
#include <Library/PcdLib.h>\r
\r
#include <IndustryStandard/TpmPtp.h>\r
#include <IndustryStandard/TpmTis.h>\r
\r
typedef enum {\r
  PtpInterfaceTis,\r
  PtpInterfaceFifo,\r
  PtpInterfaceCrb,\r
  PtpInterfaceMax,\r
} PTP_INTERFACE_TYPE;\r
\r
//\r
// Max TPM command/reponse length\r
//\r
#define TPMCMDBUFLENGTH             1024\r
\r
/**\r
  Check whether TPM chip exist.\r
\r
  @param[in] TisReg  Pointer to TIS register.\r
\r
  @retval    TRUE    TPM chip exists.\r
  @retval    FALSE   TPM chip is not found.\r
**/\r
BOOLEAN\r
Tpm12TisPcPresenceCheck (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  UINT8                             RegRead;\r
\r
  RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r
  return (BOOLEAN)(RegRead != (UINT8)-1);\r
}\r
\r
/**\r
  Return PTP interface type.\r
\r
  @param[in] Register                Pointer to PTP register.\r
\r
  @return PTP interface type.\r
**/\r
PTP_INTERFACE_TYPE\r
Tpm12GetPtpInterface (\r
  IN VOID *Register\r
  )\r
{\r
  PTP_CRB_INTERFACE_IDENTIFIER  InterfaceId;\r
  PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r
\r
  if (!Tpm12TisPcPresenceCheck (Register)) {\r
    return PtpInterfaceMax;\r
  }\r
  //\r
  // Check interface id\r
  //\r
  InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r
  InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r
\r
  if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&\r
      (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&\r
      (InterfaceId.Bits.CapCRB != 0)) {\r
    return PtpInterfaceCrb;\r
  }\r
  if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&\r
      (InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&\r
      (InterfaceId.Bits.CapFIFO != 0) &&\r
      (InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {\r
    return PtpInterfaceFifo;\r
  }\r
  return PtpInterfaceTis;\r
}\r
\r
/**\r
  Check whether the value of a TPM chip register satisfies the input BIT setting.\r
\r
  @param[in]  Register     Address port of register to be checked.\r
  @param[in]  BitSet       Check these data bits are set.\r
  @param[in]  BitClear     Check these data bits are clear.\r
  @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.\r
\r
  @retval     EFI_SUCCESS  The register satisfies the check bit.\r
  @retval     EFI_TIMEOUT  The register can't run into the expected status in time.\r
**/\r
EFI_STATUS\r
Tpm12TisPcWaitRegisterBits (\r
  IN      UINT8                     *Register,\r
  IN      UINT8                     BitSet,\r
  IN      UINT8                     BitClear,\r
  IN      UINT32                    TimeOut\r
  )\r
{\r
  UINT8                             RegRead;\r
  UINT32                            WaitTime;\r
\r
  for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
    RegRead = MmioRead8 ((UINTN)Register);\r
    if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
      return EFI_SUCCESS;\r
    MicroSecondDelay (30);\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Get BurstCount by reading the burstCount field of a TIS regiger\r
  in the time of default TIS_TIMEOUT_D.\r
\r
  @param[in]  TisReg                Pointer to TIS register.\r
  @param[out] BurstCount            Pointer to a buffer to store the got BurstConut.\r
\r
  @retval     EFI_SUCCESS           Get BurstCount.\r
  @retval     EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
  @retval     EFI_TIMEOUT           BurstCount can't be got in time.\r
**/\r
EFI_STATUS\r
Tpm12TisPcReadBurstCount (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg,\r
     OUT  UINT16                    *BurstCount\r
  )\r
{\r
  UINT32                            WaitTime;\r
  UINT8                             DataByte0;\r
  UINT8                             DataByte1;\r
\r
  if (BurstCount == NULL || TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  WaitTime = 0;\r
  do {\r
    //\r
    // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r
    // so it needs to use MmioRead8 to read two times\r
    //\r
    DataByte0   = MmioRead8 ((UINTN)&TisReg->BurstCount);\r
    DataByte1   = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r
    *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r
    if (*BurstCount != 0) {\r
      return EFI_SUCCESS;\r
    }\r
    MicroSecondDelay (30);\r
    WaitTime += 30;\r
  } while (WaitTime < TIS_TIMEOUT_D);\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Set TPM chip to ready state by sending ready command TIS_PC_STS_READY\r
  to Status Register in time.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           TPM chip enters into ready state.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_TIMEOUT           TPM chip can't be set to ready state in time.\r
**/\r
EFI_STATUS\r
Tpm12TisPcPrepareCommand (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  EFI_STATUS                        Status;\r
\r
  if (TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             TIS_PC_STS_READY,\r
             0,\r
             TIS_TIMEOUT_B\r
             );\r
  return Status;\r
}\r
\r
/**\r
  Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r
  to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           Get the control of TPM chip.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_NOT_FOUND         TPM chip doesn't exit.\r
  @retval    EFI_TIMEOUT           Can't get the TPM control in time.\r
**/\r
EFI_STATUS\r
Tpm12TisPcRequestUseTpm (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  EFI_STATUS                        Status;\r
\r
  if (TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (!Tpm12TisPcPresenceCheck (TisReg)) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Access,\r
             (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),\r
             0,\r
             TIS_TIMEOUT_A\r
             );\r
  return Status;\r
}\r
\r
/**\r
  Send a command to TPM for execution and return response data.\r
\r
  @param[in]      TisReg        TPM register space base address.\r
  @param[in]      BufferIn      Buffer for command data.\r
  @param[in]      SizeIn        Size of command data.\r
  @param[in, out] BufferOut     Buffer for response data.\r
  @param[in, out] SizeOut       Size of response data.\r
\r
  @retval EFI_SUCCESS           Operation completed successfully.\r
  @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.\r
  @retval EFI_DEVICE_ERROR      Unexpected device behavior.\r
  @retval EFI_UNSUPPORTED       Unsupported TPM version\r
\r
**/\r
EFI_STATUS\r
Tpm12TisTpmCommand (\r
  IN     TIS_PC_REGISTERS_PTR       TisReg,\r
  IN     UINT8                      *BufferIn,\r
  IN     UINT32                     SizeIn,\r
  IN OUT UINT8                      *BufferOut,\r
  IN OUT UINT32                     *SizeOut\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  UINT16                            BurstCount;\r
  UINT32                            Index;\r
  UINT32                            TpmOutSize;\r
  UINT16                            Data16;\r
  UINT32                            Data32;\r
  UINT16                            RspTag;\r
\r
  DEBUG_CODE (\r
    UINTN  DebugSize;\r
\r
    DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Send - "));\r
    if (SizeIn > 0x100) {\r
      DebugSize = 0x40;\r
    } else {\r
      DebugSize = SizeIn;\r
    }\r
    for (Index = 0; Index < DebugSize; Index++) {\r
      DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
    }\r
    if (DebugSize != SizeIn) {\r
      DEBUG ((EFI_D_VERBOSE, "...... "));\r
      for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
        DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
      }\r
    }\r
    DEBUG ((EFI_D_VERBOSE, "\n"));\r
  );\r
  TpmOutSize = 0;\r
\r
  Status = Tpm12TisPcPrepareCommand (TisReg);\r
  if (EFI_ERROR (Status)){\r
    DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));\r
    return EFI_DEVICE_ERROR;\r
  }\r
  //\r
  // Send the command data to Tpm\r
  //\r
  Index = 0;\r
  while (Index < SizeIn) {\r
    Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_DEVICE_ERROR;\r
      goto Exit;\r
    }\r
    for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
      MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
      Index++;\r
    }\r
  }\r
  //\r
  // Check the Tpm status STS_EXPECT change from 1 to 0\r
  //\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             (UINT8) TIS_PC_VALID,\r
             TIS_PC_STS_EXPECT,\r
             TIS_TIMEOUT_C\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));\r
    Status = EFI_BUFFER_TOO_SMALL;\r
    goto Exit;\r
  }\r
  //\r
  // Executed the TPM command and waiting for the response data ready\r
  //\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
  Status = Tpm12TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),\r
             0,\r
             TIS_TIMEOUT_B\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));\r
    Status = EFI_DEVICE_ERROR;\r
    goto Exit;\r
  }\r
  //\r
  // Get response data header\r
  //\r
  Index = 0;\r
  BurstCount = 0;\r
  while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {\r
    Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_DEVICE_ERROR;\r
      goto Exit;\r
    }\r
    for (; BurstCount > 0; BurstCount--) {\r
      *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
      Index++;\r
      if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;\r
    }\r
  }\r
  DEBUG_CODE (\r
    DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand ReceiveHeader - "));\r
    for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {\r
      DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
    }\r
    DEBUG ((EFI_D_VERBOSE, "\n"));\r
  );\r
  //\r
  // Check the response data header (tag, parasize and returncode)\r
  //\r
  CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
  RspTag = SwapBytes16 (Data16);\r
  if (RspTag != TPM_TAG_RSP_COMMAND && RspTag != TPM_TAG_RSP_AUTH1_COMMAND && RspTag != TPM_TAG_RSP_AUTH2_COMMAND) {\r
    DEBUG ((EFI_D_ERROR, "TPM12: Response tag error - current tag value is %x\n", RspTag));\r
    Status = EFI_UNSUPPORTED;\r
    goto Exit;\r
  }\r
\r
  CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
  TpmOutSize  = SwapBytes32 (Data32);\r
  if (*SizeOut < TpmOutSize) {\r
    Status = EFI_BUFFER_TOO_SMALL;\r
    goto Exit;\r
  }\r
  *SizeOut = TpmOutSize;\r
  //\r
  // Continue reading the remaining data\r
  //\r
  while ( Index < TpmOutSize ) {\r
    for (; BurstCount > 0; BurstCount--) {\r
      *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
      Index++;\r
      if (Index == TpmOutSize) {\r
        Status = EFI_SUCCESS;\r
        goto Exit;\r
      }\r
    }\r
    Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_DEVICE_ERROR;\r
      goto Exit;\r
    }\r
  }\r
Exit:\r
  DEBUG_CODE (\r
    DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Receive - "));\r
    for (Index = 0; Index < TpmOutSize; Index++) {\r
      DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
    }\r
    DEBUG ((EFI_D_VERBOSE, "\n"));\r
  );\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
  return Status;\r
}\r
\r
/**\r
  This service enables the sending of commands to the TPM12.\r
\r
  @param[in]      InputParameterBlockSize  Size of the TPM12 input parameter block.\r
  @param[in]      InputParameterBlock      Pointer to the TPM12 input parameter block.\r
  @param[in,out]  OutputParameterBlockSize Size of the TPM12 output parameter block.\r
  @param[in]      OutputParameterBlock     Pointer to the TPM12 output parameter block.\r
\r
  @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.\r
  @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.\r
  @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small.\r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12SubmitCommand (\r
  IN UINT32            InputParameterBlockSize,\r
  IN UINT8             *InputParameterBlock,\r
  IN OUT UINT32        *OutputParameterBlockSize,\r
  IN UINT8             *OutputParameterBlock\r
  )\r
{\r
  PTP_INTERFACE_TYPE  PtpInterface;\r
\r
  //\r
  // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.\r
  //\r
  PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
  switch (PtpInterface) {\r
  case PtpInterfaceFifo:\r
  case PtpInterfaceTis:\r
    return Tpm12TisTpmCommand (\r
             (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
             InputParameterBlock,\r
             InputParameterBlockSize,\r
             OutputParameterBlock,\r
             OutputParameterBlockSize\r
             );\r
  case PtpInterfaceCrb:\r
    //\r
    // No need to support CRB because it is only accept TPM2 command.\r
    //\r
  default:\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
}\r
\r
/**\r
  Check whether the value of a TPM chip register satisfies the input BIT setting.\r
\r
  @param[in]  Register     Address port of register to be checked.\r
  @param[in]  BitSet       Check these data bits are set.\r
  @param[in]  BitClear     Check these data bits are clear.\r
  @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.\r
\r
  @retval     EFI_SUCCESS  The register satisfies the check bit.\r
  @retval     EFI_TIMEOUT  The register can't run into the expected status in time.\r
**/\r
EFI_STATUS\r
Tpm12PtpCrbWaitRegisterBits (\r
  IN      UINT32                    *Register,\r
  IN      UINT32                    BitSet,\r
  IN      UINT32                    BitClear,\r
  IN      UINT32                    TimeOut\r
  )\r
{\r
  UINT32                            RegRead;\r
  UINT32                            WaitTime;\r
\r
  for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
    RegRead = MmioRead32 ((UINTN)Register);\r
    if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {\r
      return EFI_SUCCESS;\r
    }\r
    MicroSecondDelay (30);\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Get the control of TPM chip.\r
\r
  @param[in] CrbReg                Pointer to CRB register.\r
\r
  @retval    EFI_SUCCESS           Get the control of TPM chip.\r
  @retval    EFI_INVALID_PARAMETER CrbReg is NULL.\r
  @retval    EFI_NOT_FOUND         TPM chip doesn't exit.\r
  @retval    EFI_TIMEOUT           Can't get the TPM control in time.\r
**/\r
EFI_STATUS\r
Tpm12PtpCrbRequestUseTpm (\r
  IN      PTP_CRB_REGISTERS_PTR      CrbReg\r
  )\r
{\r
  EFI_STATUS                        Status;\r
\r
  MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);\r
  Status = Tpm12PtpCrbWaitRegisterBits (\r
             &CrbReg->LocalityStatus,\r
             PTP_CRB_LOCALITY_STATUS_GRANTED,\r
             0,\r
             PTP_TIMEOUT_A\r
             );\r
  return Status;\r
}\r
\r
/**\r
  This service requests use TPM12.\r
\r
  @retval EFI_SUCCESS      Get the control of TPM12 chip.\r
  @retval EFI_NOT_FOUND    TPM12 not found.\r
  @retval EFI_DEVICE_ERROR Unexpected device behavior.\r
**/\r
EFI_STATUS\r
EFIAPI\r
Tpm12RequestUseTpm (\r
  VOID\r
  )\r
{\r
  PTP_INTERFACE_TYPE  PtpInterface;\r
\r
  //\r
  // Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.\r
  // Some other program might leverage this function to check the existence of TPM chip.\r
  //\r
  PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
  switch (PtpInterface) {\r
  case PtpInterfaceCrb:\r
    return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
  case PtpInterfaceFifo:\r
  case PtpInterfaceTis:\r
    return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
  default:\r
    return EFI_NOT_FOUND;\r
  }\r
}\r
Commit	Line	Data
c1d93242 JY	1	/** @file\r
c1d93242 JY	2	TIS (TPM Interface Specification) functions used by TPM1.2.\r
b3548d32 LG	3	\r
b3548d32 LG	4	Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r
6aaac383	5	(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
b3548d32 LG	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
c1d93242 JY	9	http://opensource.org/licenses/bsd-license.php\r
c1d93242 JY	10	\r
b3548d32	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
c1d93242 JY	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#include <Uefi.h>\r
	17	#include <IndustryStandard/Tpm12.h>\r
	18	#include <Library/BaseLib.h>\r
	19	#include <Library/BaseMemoryLib.h>\r
	20	#include <Library/IoLib.h>\r
	21	#include <Library/TimerLib.h>\r
	22	#include <Library/DebugLib.h>\r
	23	#include <Library/Tpm12CommandLib.h>\r
	24	#include <Library/PcdLib.h>\r
	25	\r
8e997ab8 JY	26	#include <IndustryStandard/TpmPtp.h>\r
8e997ab8 JY	27	#include <IndustryStandard/TpmTis.h>\r
c1d93242	28	\r
8e997ab8 JY	29	typedef enum {\r
	30	PtpInterfaceTis,\r
	31	PtpInterfaceFifo,\r
	32	PtpInterfaceCrb,\r
	33	PtpInterfaceMax,\r
	34	} PTP_INTERFACE_TYPE;\r
c1d93242 JY	35	\r
	36	//\r
	37	// Max TPM command/reponse length\r
	38	//\r
	39	#define TPMCMDBUFLENGTH 1024\r
	40	\r
	41	/**\r
	42	Check whether TPM chip exist.\r
	43	\r
	44	@param[in] TisReg Pointer to TIS register.\r
	45	\r
	46	@retval TRUE TPM chip exists.\r
	47	@retval FALSE TPM chip is not found.\r
	48	**/\r
	49	BOOLEAN\r
	50	Tpm12TisPcPresenceCheck (\r
	51	IN TIS_PC_REGISTERS_PTR TisReg\r
	52	)\r
	53	{\r
	54	UINT8 RegRead;\r
b3548d32	55	\r
c1d93242 JY	56	RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r
	57	return (BOOLEAN)(RegRead != (UINT8)-1);\r
	58	}\r
	59	\r
e4780913 JY	60	/**\r
	61	Return PTP interface type.\r
	62	\r
	63	@param[in] Register Pointer to PTP register.\r
	64	\r
	65	@return PTP interface type.\r
	66	**/\r
	67	PTP_INTERFACE_TYPE\r
	68	Tpm12GetPtpInterface (\r
	69	IN VOID *Register\r
	70	)\r
	71	{\r
	72	PTP_CRB_INTERFACE_IDENTIFIER InterfaceId;\r
	73	PTP_FIFO_INTERFACE_CAPABILITY InterfaceCapability;\r
	74	\r
	75	if (!Tpm12TisPcPresenceCheck (Register)) {\r
	76	return PtpInterfaceMax;\r
	77	}\r
	78	//\r
	79	// Check interface id\r
	80	//\r
	81	InterfaceId.Uint32 = MmioRead32 ((UINTN)&((PTP_CRB_REGISTERS *)Register)->InterfaceId);\r
	82	InterfaceCapability.Uint32 = MmioRead32 ((UINTN)&((PTP_FIFO_REGISTERS *)Register)->InterfaceCapability);\r
	83	\r
	84	if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB) &&\r
	85	(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB) &&\r
	86	(InterfaceId.Bits.CapCRB != 0)) {\r
	87	return PtpInterfaceCrb;\r
	88	}\r
	89	if ((InterfaceId.Bits.InterfaceType == PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO) &&\r
	90	(InterfaceId.Bits.InterfaceVersion == PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO) &&\r
	91	(InterfaceId.Bits.CapFIFO != 0) &&\r
	92	(InterfaceCapability.Bits.InterfaceVersion == INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP)) {\r
	93	return PtpInterfaceFifo;\r
	94	}\r
	95	return PtpInterfaceTis;\r
	96	}\r
	97	\r
c1d93242 JY	98	/**\r
	99	Check whether the value of a TPM chip register satisfies the input BIT setting.\r
	100	\r
	101	@param[in] Register Address port of register to be checked.\r
	102	@param[in] BitSet Check these data bits are set.\r
	103	@param[in] BitClear Check these data bits are clear.\r
	104	@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r
	105	\r
	106	@retval EFI_SUCCESS The register satisfies the check bit.\r
	107	@retval EFI_TIMEOUT The register can't run into the expected status in time.\r
	108	**/\r
	109	EFI_STATUS\r
c1d93242 JY	110	Tpm12TisPcWaitRegisterBits (\r
	111	IN UINT8 *Register,\r
	112	IN UINT8 BitSet,\r
	113	IN UINT8 BitClear,\r
	114	IN UINT32 TimeOut\r
	115	)\r
	116	{\r
	117	UINT8 RegRead;\r
	118	UINT32 WaitTime;\r
	119	\r
	120	for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
	121	RegRead = MmioRead8 ((UINTN)Register);\r
	122	if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
	123	return EFI_SUCCESS;\r
	124	MicroSecondDelay (30);\r
	125	}\r
	126	return EFI_TIMEOUT;\r
	127	}\r
	128	\r
	129	/**\r
b3548d32	130	Get BurstCount by reading the burstCount field of a TIS regiger\r
c1d93242 JY	131	in the time of default TIS_TIMEOUT_D.\r
	132	\r
	133	@param[in] TisReg Pointer to TIS register.\r
	134	@param[out] BurstCount Pointer to a buffer to store the got BurstConut.\r
	135	\r
	136	@retval EFI_SUCCESS Get BurstCount.\r
	137	@retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
	138	@retval EFI_TIMEOUT BurstCount can't be got in time.\r
	139	**/\r
	140	EFI_STATUS\r
c1d93242 JY	141	Tpm12TisPcReadBurstCount (\r
	142	IN TIS_PC_REGISTERS_PTR TisReg,\r
	143	OUT UINT16 *BurstCount\r
	144	)\r
	145	{\r
	146	UINT32 WaitTime;\r
	147	UINT8 DataByte0;\r
	148	UINT8 DataByte1;\r
	149	\r
	150	if (BurstCount == NULL \|\| TisReg == NULL) {\r
	151	return EFI_INVALID_PARAMETER;\r
	152	}\r
	153	\r
	154	WaitTime = 0;\r
	155	do {\r
	156	//\r
	157	// TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r
	158	// so it needs to use MmioRead8 to read two times\r
	159	//\r
	160	DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);\r
	161	DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r
	162	*BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r
	163	if (*BurstCount != 0) {\r
	164	return EFI_SUCCESS;\r
	165	}\r
	166	MicroSecondDelay (30);\r
	167	WaitTime += 30;\r
	168	} while (WaitTime < TIS_TIMEOUT_D);\r
	169	\r
	170	return EFI_TIMEOUT;\r
	171	}\r
	172	\r
	173	/**\r
b3548d32	174	Set TPM chip to ready state by sending ready command TIS_PC_STS_READY\r
c1d93242 JY	175	to Status Register in time.\r
	176	\r
	177	@param[in] TisReg Pointer to TIS register.\r
	178	\r
	179	@retval EFI_SUCCESS TPM chip enters into ready state.\r
	180	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
	181	@retval EFI_TIMEOUT TPM chip can't be set to ready state in time.\r
	182	**/\r
	183	EFI_STATUS\r
c1d93242 JY	184	Tpm12TisPcPrepareCommand (\r
	185	IN TIS_PC_REGISTERS_PTR TisReg\r
	186	)\r
	187	{\r
	188	EFI_STATUS Status;\r
	189	\r
	190	if (TisReg == NULL) {\r
	191	return EFI_INVALID_PARAMETER;\r
	192	}\r
	193	\r
	194	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
	195	Status = Tpm12TisPcWaitRegisterBits (\r
	196	&TisReg->Status,\r
	197	TIS_PC_STS_READY,\r
	198	0,\r
	199	TIS_TIMEOUT_B\r
	200	);\r
	201	return Status;\r
	202	}\r
	203	\r
	204	/**\r
b3548d32	205	Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE\r
c1d93242 JY	206	to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
	207	\r
	208	@param[in] TisReg Pointer to TIS register.\r
	209	\r
	210	@retval EFI_SUCCESS Get the control of TPM chip.\r
	211	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
	212	@retval EFI_NOT_FOUND TPM chip doesn't exit.\r
	213	@retval EFI_TIMEOUT Can't get the TPM control in time.\r
	214	**/\r
	215	EFI_STATUS\r
c1d93242 JY	216	Tpm12TisPcRequestUseTpm (\r
	217	IN TIS_PC_REGISTERS_PTR TisReg\r
	218	)\r
	219	{\r
	220	EFI_STATUS Status;\r
b3548d32	221	\r
c1d93242 JY	222	if (TisReg == NULL) {\r
	223	return EFI_INVALID_PARAMETER;\r
	224	}\r
b3548d32	225	\r
c1d93242 JY	226	if (!Tpm12TisPcPresenceCheck (TisReg)) {\r
	227	return EFI_NOT_FOUND;\r
	228	}\r
	229	\r
	230	MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
	231	Status = Tpm12TisPcWaitRegisterBits (\r
	232	&TisReg->Access,\r
	233	(UINT8)(TIS_PC_ACC_ACTIVE \|TIS_PC_VALID),\r
	234	0,\r
	235	TIS_TIMEOUT_A\r
	236	);\r
	237	return Status;\r
	238	}\r
	239	\r
	240	/**\r
	241	Send a command to TPM for execution and return response data.\r
	242	\r
b3548d32 LG	243	@param[in] TisReg TPM register space base address.\r
	244	@param[in] BufferIn Buffer for command data.\r
	245	@param[in] SizeIn Size of command data.\r
	246	@param[in, out] BufferOut Buffer for response data.\r
	247	@param[in, out] SizeOut Size of response data.\r
	248	\r
c1d93242	249	@retval EFI_SUCCESS Operation completed successfully.\r
c1d93242 JY	250	@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r
	251	@retval EFI_DEVICE_ERROR Unexpected device behavior.\r
	252	@retval EFI_UNSUPPORTED Unsupported TPM version\r
	253	\r
	254	**/\r
	255	EFI_STATUS\r
	256	Tpm12TisTpmCommand (\r
	257	IN TIS_PC_REGISTERS_PTR TisReg,\r
	258	IN UINT8 *BufferIn,\r
	259	IN UINT32 SizeIn,\r
	260	IN OUT UINT8 *BufferOut,\r
	261	IN OUT UINT32 *SizeOut\r
	262	)\r
	263	{\r
	264	EFI_STATUS Status;\r
	265	UINT16 BurstCount;\r
	266	UINT32 Index;\r
	267	UINT32 TpmOutSize;\r
	268	UINT16 Data16;\r
	269	UINT32 Data32;\r
ee46ac08	270	UINT16 RspTag;\r
c1d93242 JY	271	\r
	272	DEBUG_CODE (\r
	273	UINTN DebugSize;\r
	274	\r
6aaac383	275	DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Send - "));\r
c1d93242 JY	276	if (SizeIn > 0x100) {\r
	277	DebugSize = 0x40;\r
	278	} else {\r
	279	DebugSize = SizeIn;\r
	280	}\r
	281	for (Index = 0; Index < DebugSize; Index++) {\r
6aaac383	282	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
c1d93242 JY	283	}\r
c1d93242 JY	284	if (DebugSize != SizeIn) {\r
6aaac383	285	DEBUG ((EFI_D_VERBOSE, "...... "));\r
c1d93242	286	for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
6aaac383	287	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
c1d93242 JY	288	}\r
c1d93242 JY	289	}\r
6aaac383	290	DEBUG ((EFI_D_VERBOSE, "\n"));\r
c1d93242 JY	291	);\r
	292	TpmOutSize = 0;\r
	293	\r
	294	Status = Tpm12TisPcPrepareCommand (TisReg);\r
	295	if (EFI_ERROR (Status)){\r
	296	DEBUG ((DEBUG_ERROR, "Tpm12 is not ready for command!\n"));\r
6f785cfc	297	return EFI_DEVICE_ERROR;\r
c1d93242 JY	298	}\r
	299	//\r
	300	// Send the command data to Tpm\r
	301	//\r
	302	Index = 0;\r
	303	while (Index < SizeIn) {\r
	304	Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
	305	if (EFI_ERROR (Status)) {\r
6f785cfc	306	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	307	goto Exit;\r
	308	}\r
	309	for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
	310	MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
	311	Index++;\r
	312	}\r
	313	}\r
	314	//\r
	315	// Check the Tpm status STS_EXPECT change from 1 to 0\r
	316	//\r
	317	Status = Tpm12TisPcWaitRegisterBits (\r
	318	&TisReg->Status,\r
	319	(UINT8) TIS_PC_VALID,\r
	320	TIS_PC_STS_EXPECT,\r
	321	TIS_TIMEOUT_C\r
	322	);\r
	323	if (EFI_ERROR (Status)) {\r
	324	DEBUG ((DEBUG_ERROR, "Tpm12 The send buffer too small!\n"));\r
	325	Status = EFI_BUFFER_TOO_SMALL;\r
	326	goto Exit;\r
	327	}\r
	328	//\r
	329	// Executed the TPM command and waiting for the response data ready\r
	330	//\r
	331	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
	332	Status = Tpm12TisPcWaitRegisterBits (\r
	333	&TisReg->Status,\r
	334	(UINT8) (TIS_PC_VALID \| TIS_PC_STS_DATA),\r
	335	0,\r
	336	TIS_TIMEOUT_B\r
	337	);\r
	338	if (EFI_ERROR (Status)) {\r
	339	DEBUG ((DEBUG_ERROR, "Wait for Tpm12 response data time out!!\n"));\r
6f785cfc	340	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	341	goto Exit;\r
	342	}\r
	343	//\r
	344	// Get response data header\r
	345	//\r
	346	Index = 0;\r
	347	BurstCount = 0;\r
	348	while (Index < sizeof (TPM_RSP_COMMAND_HDR)) {\r
	349	Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
	350	if (EFI_ERROR (Status)) {\r
6f785cfc	351	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	352	goto Exit;\r
	353	}\r
	354	for (; BurstCount > 0; BurstCount--) {\r
	355	*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
	356	Index++;\r
	357	if (Index == sizeof (TPM_RSP_COMMAND_HDR)) break;\r
	358	}\r
	359	}\r
	360	DEBUG_CODE (\r
6aaac383	361	DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand ReceiveHeader - "));\r
c1d93242	362	for (Index = 0; Index < sizeof (TPM_RSP_COMMAND_HDR); Index++) {\r
6aaac383	363	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
c1d93242	364	}\r
6aaac383	365	DEBUG ((EFI_D_VERBOSE, "\n"));\r
c1d93242 JY	366	);\r
c1d93242 JY	367	//\r
ee46ac08	368	// Check the response data header (tag, parasize and returncode)\r
c1d93242 JY	369	//\r
c1d93242 JY	370	CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
ee46ac08 ZC	371	RspTag = SwapBytes16 (Data16);\r
	372	if (RspTag != TPM_TAG_RSP_COMMAND && RspTag != TPM_TAG_RSP_AUTH1_COMMAND && RspTag != TPM_TAG_RSP_AUTH2_COMMAND) {\r
	373	DEBUG ((EFI_D_ERROR, "TPM12: Response tag error - current tag value is %x\n", RspTag));\r
c1d93242 JY	374	Status = EFI_UNSUPPORTED;\r
	375	goto Exit;\r
	376	}\r
	377	\r
	378	CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
	379	TpmOutSize = SwapBytes32 (Data32);\r
	380	if (*SizeOut < TpmOutSize) {\r
	381	Status = EFI_BUFFER_TOO_SMALL;\r
	382	goto Exit;\r
	383	}\r
	384	*SizeOut = TpmOutSize;\r
	385	//\r
	386	// Continue reading the remaining data\r
	387	//\r
	388	while ( Index < TpmOutSize ) {\r
	389	for (; BurstCount > 0; BurstCount--) {\r
	390	*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
	391	Index++;\r
	392	if (Index == TpmOutSize) {\r
	393	Status = EFI_SUCCESS;\r
	394	goto Exit;\r
	395	}\r
	396	}\r
	397	Status = Tpm12TisPcReadBurstCount (TisReg, &BurstCount);\r
	398	if (EFI_ERROR (Status)) {\r
6f785cfc	399	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	400	goto Exit;\r
	401	}\r
	402	}\r
	403	Exit:\r
	404	DEBUG_CODE (\r
6aaac383	405	DEBUG ((EFI_D_VERBOSE, "Tpm12TisTpmCommand Receive - "));\r
c1d93242	406	for (Index = 0; Index < TpmOutSize; Index++) {\r
6aaac383	407	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
c1d93242	408	}\r
6aaac383	409	DEBUG ((EFI_D_VERBOSE, "\n"));\r
c1d93242 JY	410	);\r
	411	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
	412	return Status;\r
	413	}\r
	414	\r
	415	/**\r
	416	This service enables the sending of commands to the TPM12.\r
	417	\r
	418	@param[in] InputParameterBlockSize Size of the TPM12 input parameter block.\r
	419	@param[in] InputParameterBlock Pointer to the TPM12 input parameter block.\r
	420	@param[in,out] OutputParameterBlockSize Size of the TPM12 output parameter block.\r
	421	@param[in] OutputParameterBlock Pointer to the TPM12 output parameter block.\r
	422	\r
	423	@retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r
	424	@retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r
b3548d32	425	@retval EFI_BUFFER_TOO_SMALL The output parameter block is too small.\r
c1d93242 JY	426	**/\r
	427	EFI_STATUS\r
	428	EFIAPI\r
	429	Tpm12SubmitCommand (\r
	430	IN UINT32 InputParameterBlockSize,\r
	431	IN UINT8 *InputParameterBlock,\r
	432	IN OUT UINT32 *OutputParameterBlockSize,\r
	433	IN UINT8 *OutputParameterBlock\r
	434	)\r
	435	{\r
e4780913	436	PTP_INTERFACE_TYPE PtpInterface;\r
c1d93242	437	\r
8e997ab8	438	//\r
e4780913	439	// Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.\r
8e997ab8	440	//\r
e4780913 JY	441	PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
	442	switch (PtpInterface) {\r
	443	case PtpInterfaceFifo:\r
	444	case PtpInterfaceTis:\r
	445	return Tpm12TisTpmCommand (\r
	446	(TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
	447	InputParameterBlock,\r
	448	InputParameterBlockSize,\r
	449	OutputParameterBlock,\r
	450	OutputParameterBlockSize\r
	451	);\r
	452	case PtpInterfaceCrb:\r
	453	//\r
	454	// No need to support CRB because it is only accept TPM2 command.\r
	455	//\r
	456	default:\r
	457	return EFI_DEVICE_ERROR;\r
8e997ab8	458	}\r
e4780913	459	\r
8e997ab8 JY	460	}\r
	461	\r
	462	/**\r
	463	Check whether the value of a TPM chip register satisfies the input BIT setting.\r
	464	\r
	465	@param[in] Register Address port of register to be checked.\r
	466	@param[in] BitSet Check these data bits are set.\r
	467	@param[in] BitClear Check these data bits are clear.\r
	468	@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r
	469	\r
	470	@retval EFI_SUCCESS The register satisfies the check bit.\r
	471	@retval EFI_TIMEOUT The register can't run into the expected status in time.\r
	472	**/\r
	473	EFI_STATUS\r
	474	Tpm12PtpCrbWaitRegisterBits (\r
	475	IN UINT32 *Register,\r
	476	IN UINT32 BitSet,\r
	477	IN UINT32 BitClear,\r
	478	IN UINT32 TimeOut\r
	479	)\r
	480	{\r
	481	UINT32 RegRead;\r
	482	UINT32 WaitTime;\r
	483	\r
	484	for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
	485	RegRead = MmioRead32 ((UINTN)Register);\r
	486	if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0) {\r
	487	return EFI_SUCCESS;\r
	488	}\r
	489	MicroSecondDelay (30);\r
	490	}\r
	491	return EFI_TIMEOUT;\r
	492	}\r
	493	\r
	494	/**\r
	495	Get the control of TPM chip.\r
	496	\r
	497	@param[in] CrbReg Pointer to CRB register.\r
	498	\r
	499	@retval EFI_SUCCESS Get the control of TPM chip.\r
	500	@retval EFI_INVALID_PARAMETER CrbReg is NULL.\r
	501	@retval EFI_NOT_FOUND TPM chip doesn't exit.\r
	502	@retval EFI_TIMEOUT Can't get the TPM control in time.\r
	503	**/\r
	504	EFI_STATUS\r
	505	Tpm12PtpCrbRequestUseTpm (\r
	506	IN PTP_CRB_REGISTERS_PTR CrbReg\r
	507	)\r
	508	{\r
	509	EFI_STATUS Status;\r
	510	\r
	511	MmioWrite32((UINTN)&CrbReg->LocalityControl, PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS);\r
	512	Status = Tpm12PtpCrbWaitRegisterBits (\r
	513	&CrbReg->LocalityStatus,\r
	514	PTP_CRB_LOCALITY_STATUS_GRANTED,\r
	515	0,\r
	516	PTP_TIMEOUT_A\r
	517	);\r
	518	return Status;\r
	519	}\r
	520	\r
c1d93242 JY	521	/**\r
	522	This service requests use TPM12.\r
	523	\r
	524	@retval EFI_SUCCESS Get the control of TPM12 chip.\r
	525	@retval EFI_NOT_FOUND TPM12 not found.\r
	526	@retval EFI_DEVICE_ERROR Unexpected device behavior.\r
	527	**/\r
	528	EFI_STATUS\r
	529	EFIAPI\r
	530	Tpm12RequestUseTpm (\r
	531	VOID\r
	532	)\r
	533	{\r
8e997ab8 JY	534	PTP_INTERFACE_TYPE PtpInterface;\r
	535	\r
	536	//\r
	537	// Special handle for TPM1.2 to check PTP too, because PTP/TIS share same register address.\r
	538	// Some other program might leverage this function to check the existence of TPM chip.\r
	539	//\r
	540	PtpInterface = Tpm12GetPtpInterface ((VOID *) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
	541	switch (PtpInterface) {\r
	542	case PtpInterfaceCrb:\r
	543	return Tpm12PtpCrbRequestUseTpm ((PTP_CRB_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
	544	case PtpInterfaceFifo:\r
	545	case PtpInterfaceTis:\r
	546	return Tpm12TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
	547	default:\r
	548	return EFI_NOT_FOUND;\r
	549	}\r
c1d93242	550	}\r