[mirror_edk2.git] / SecurityPkg / Library / Tpm2DeviceLibDTpm / Tpm2Tis.c

/** @file\r
  TIS (TPM Interface Specification) functions used by dTPM2.0 library.\r
  \r
Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution.  The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <IndustryStandard/Tpm20.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/Tpm2DeviceLib.h>\r
#include <Library/PcdLib.h>\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in TIS specification Chapter 10\r
//\r
typedef struct {\r
  ///\r
  /// Used to gain ownership for this particular port.\r
  ///\r
  UINT8                             Access;             // 0\r
  UINT8                             Reserved1[7];       // 1\r
  ///\r
  /// Controls interrupts.\r
  ///\r
  UINT32                            IntEnable;          // 8\r
  ///\r
  /// SIRQ vector to be used by the TPM.\r
  ///\r
  UINT8                             IntVector;          // 0ch\r
  UINT8                             Reserved2[3];       // 0dh\r
  ///\r
  /// What caused interrupt.\r
  ///\r
  UINT32                            IntSts;             // 10h\r
  ///\r
  /// Shows which interrupts are supported by that particular TPM.\r
  ///\r
  UINT32                            IntfCapability;     // 14h\r
  ///\r
  /// Status Register. Provides status of the TPM.\r
  ///\r
  UINT8                             Status;             // 18h\r
  ///\r
  /// Number of consecutive writes that can be done to the TPM.\r
  ///\r
  UINT16                            BurstCount;         // 19h\r
  ///\r
  /// TPM2 support CANCEL at BIT[24] of STATUS register (WO)\r
  ///\r
  UINT8                             StatusEx;           // 1Bh\r
  UINT8                             Reserved3[8];\r
  ///\r
  /// Read or write FIFO, depending on transaction.\r
  ///\r
  UINT32                            DataFifo;           // 24h\r
  UINT8                             Reserved4[0xed8];   // 28h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16                            Vid;                // 0f00h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16                            Did;                // 0f02h\r
  ///\r
  /// Revision ID\r
  ///\r
  UINT8                             Rid;                // 0f04h\r
  ///\r
  /// TCG defined configuration registers.\r
  ///\r
  UINT8                             TcgDefined[0x7b];   // 0f05h\r
  ///\r
  /// Alias to I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress1;     // 0f80h\r
  ///\r
  /// Additional 8 bits for I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress1Ex;   // 0f84h\r
  ///\r
  /// Alias to second I/O legacy space.\r
  ///\r
  UINT32                            LegacyAddress2;     // 0f88h\r
  ///\r
  /// Additional 8 bits for second I/O legacy space extension.\r
  ///\r
  UINT32                            LegacyAddress2Ex;   // 0f8ch\r
  ///\r
  /// Vendor-defined configuration registers.\r
  ///\r
  UINT8                             VendorDefined[0x70];// 0f90h\r
} TIS_PC_REGISTERS;\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
#define TIS_PC_VALID                BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
#define TIS_PC_ACC_ACTIVE           BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
#define TIS_PC_ACC_SEIZED           BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
#define TIS_PC_ACC_SEIZE            BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
#define TIS_PC_ACC_PENDIND          BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
#define TIS_PC_ACC_RQUUSE           BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
#define TIS_PC_ACC_ESTABLISH        BIT0\r
\r
///\r
/// When this bit is 1, TPM is in the Ready state, \r
/// indicating it is ready to receive a new command.\r
///\r
#define TIS_PC_STS_READY            BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
#define TIS_PC_STS_GO               BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
#define TIS_PC_STS_DATA             BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
#define TIS_PC_STS_EXPECT           BIT3\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
#define TIS_PC_STS_RETRY            BIT1\r
\r
//\r
// Default TimeOut value\r
//\r
#define TIS_TIMEOUT_A               (1000 * 1000)  // 1s\r
#define TIS_TIMEOUT_B               (2000 * 1000)  // 2s\r
#define TIS_TIMEOUT_C               (1000 * 1000)  // 1s\r
#define TIS_TIMEOUT_D               (1000 * 1000)  // 1s\r
\r
#define TIS_TIMEOUT_MAX             (90000 * 1000)  // 90s\r
\r
//\r
// Max TPM command/reponse length\r
//\r
#define TPMCMDBUFLENGTH             0x500\r
\r
/**\r
  Check whether TPM chip exist.\r
\r
  @param[in] TisReg  Pointer to TIS register.\r
\r
  @retval    TRUE    TPM chip exists.\r
  @retval    FALSE   TPM chip is not found.\r
**/\r
BOOLEAN\r
TisPcPresenceCheck (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  UINT8                             RegRead;\r
  \r
  RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r
  return (BOOLEAN)(RegRead != (UINT8)-1);\r
}\r
\r
/**\r
  Check whether the value of a TPM chip register satisfies the input BIT setting.\r
\r
  @param[in]  Register     Address port of register to be checked.\r
  @param[in]  BitSet       Check these data bits are set.\r
  @param[in]  BitClear     Check these data bits are clear.\r
  @param[in]  TimeOut      The max wait time (unit MicroSecond) when checking register.\r
\r
  @retval     EFI_SUCCESS  The register satisfies the check bit.\r
  @retval     EFI_TIMEOUT  The register can't run into the expected status in time.\r
**/\r
EFI_STATUS\r
TisPcWaitRegisterBits (\r
  IN      UINT8                     *Register,\r
  IN      UINT8                     BitSet,\r
  IN      UINT8                     BitClear,\r
  IN      UINT32                    TimeOut\r
  )\r
{\r
  UINT8                             RegRead;\r
  UINT32                            WaitTime;\r
\r
  for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
    RegRead = MmioRead8 ((UINTN)Register);\r
    if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
      return EFI_SUCCESS;\r
    MicroSecondDelay (30);\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Get BurstCount by reading the burstCount field of a TIS regiger \r
  in the time of default TIS_TIMEOUT_D.\r
\r
  @param[in]  TisReg                Pointer to TIS register.\r
  @param[out] BurstCount            Pointer to a buffer to store the got BurstConut.\r
\r
  @retval     EFI_SUCCESS           Get BurstCount.\r
  @retval     EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
  @retval     EFI_TIMEOUT           BurstCount can't be got in time.\r
**/\r
EFI_STATUS\r
TisPcReadBurstCount (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg,\r
     OUT  UINT16                    *BurstCount\r
  )\r
{\r
  UINT32                            WaitTime;\r
  UINT8                             DataByte0;\r
  UINT8                             DataByte1;\r
\r
  if (BurstCount == NULL || TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  WaitTime = 0;\r
  do {\r
    //\r
    // TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r
    // so it needs to use MmioRead8 to read two times\r
    //\r
    DataByte0   = MmioRead8 ((UINTN)&TisReg->BurstCount);\r
    DataByte1   = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r
    *BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r
    if (*BurstCount != 0) {\r
      return EFI_SUCCESS;\r
    }\r
    MicroSecondDelay (30);\r
    WaitTime += 30;\r
  } while (WaitTime < TIS_TIMEOUT_D);\r
\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
  Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r
  to Status Register in time.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           TPM chip enters into ready state.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_TIMEOUT           TPM chip can't be set to ready state in time.\r
**/\r
EFI_STATUS\r
TisPcPrepareCommand (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  EFI_STATUS                        Status;\r
\r
  if (TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
  Status = TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             TIS_PC_STS_READY,\r
             0,\r
             TIS_TIMEOUT_B\r
             );\r
  return Status;\r
}\r
\r
/**\r
  Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r
  to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
\r
  @param[in] TisReg                Pointer to TIS register.\r
\r
  @retval    EFI_SUCCESS           Get the control of TPM chip.\r
  @retval    EFI_INVALID_PARAMETER TisReg is NULL.\r
  @retval    EFI_NOT_FOUND         TPM chip doesn't exit.\r
  @retval    EFI_TIMEOUT           Can't get the TPM control in time.\r
**/\r
EFI_STATUS\r
TisPcRequestUseTpm (\r
  IN      TIS_PC_REGISTERS_PTR      TisReg\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  \r
  if (TisReg == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  \r
  if (!TisPcPresenceCheck (TisReg)) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
  Status = TisPcWaitRegisterBits (\r
             &TisReg->Access,\r
             (UINT8)(TIS_PC_ACC_ACTIVE |TIS_PC_VALID),\r
             0,\r
             TIS_TIMEOUT_A\r
             );\r
  return Status;\r
}\r
\r
/**\r
  Send a command to TPM for execution and return response data.\r
\r
  @param[in]      TisReg        TPM register space base address.  \r
  @param[in]      BufferIn      Buffer for command data.  \r
  @param[in]      SizeIn        Size of command data.  \r
  @param[in, out] BufferOut     Buffer for response data.  \r
  @param[in, out] SizeOut       Size of response data.  \r
 \r
  @retval EFI_SUCCESS           Operation completed successfully.\r
  @retval EFI_BUFFER_TOO_SMALL  Response data buffer is too small.\r
  @retval EFI_DEVICE_ERROR      Unexpected device behavior.\r
  @retval EFI_UNSUPPORTED       Unsupported TPM version\r
\r
**/\r
EFI_STATUS\r
Tpm2TisTpmCommand (\r
  IN     TIS_PC_REGISTERS_PTR       TisReg,\r
  IN     UINT8                      *BufferIn,\r
  IN     UINT32                     SizeIn,\r
  IN OUT UINT8                      *BufferOut,\r
  IN OUT UINT32                     *SizeOut\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  UINT16                            BurstCount;\r
  UINT32                            Index;\r
  UINT32                            TpmOutSize;\r
  UINT16                            Data16;\r
  UINT32                            Data32;\r
\r
  DEBUG_CODE (\r
    UINTN  DebugSize;\r
\r
    DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand Send - "));\r
    if (SizeIn > 0x100) {\r
      DebugSize = 0x40;\r
    } else {\r
      DebugSize = SizeIn;\r
    }\r
    for (Index = 0; Index < DebugSize; Index++) {\r
      DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
    }\r
    if (DebugSize != SizeIn) {\r
      DEBUG ((EFI_D_VERBOSE, "...... "));\r
      for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
        DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
      }\r
    }\r
    DEBUG ((EFI_D_VERBOSE, "\n"));\r
  );\r
  TpmOutSize = 0;\r
\r
  Status = TisPcPrepareCommand (TisReg);\r
  if (EFI_ERROR (Status)){\r
    DEBUG ((DEBUG_ERROR, "Tpm2 is not ready for command!\n"));\r
    return EFI_DEVICE_ERROR;\r
  }\r
  //\r
  // Send the command data to Tpm\r
  //\r
  Index = 0;\r
  while (Index < SizeIn) {\r
    Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_DEVICE_ERROR;\r
      goto Exit;\r
    }\r
    for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
      MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
      Index++;\r
    }\r
  }\r
  //\r
  // Check the Tpm status STS_EXPECT change from 1 to 0\r
  //\r
  Status = TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             (UINT8) TIS_PC_VALID,\r
             TIS_PC_STS_EXPECT,\r
             TIS_TIMEOUT_C\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "Tpm2 The send buffer too small!\n"));\r
    Status = EFI_BUFFER_TOO_SMALL;\r
    goto Exit;\r
  }\r
  //\r
  // Executed the TPM command and waiting for the response data ready\r
  //\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
\r
  //\r
  // NOTE: That may take many seconds to minutes for certain commands, such as key generation.\r
  //\r
  Status = TisPcWaitRegisterBits (\r
             &TisReg->Status,\r
             (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),\r
             0,\r
             TIS_TIMEOUT_MAX\r
             );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out!!\n"));\r
    Status = EFI_DEVICE_ERROR;\r
    goto Exit;\r
  }\r
  //\r
  // Get response data header\r
  //\r
  Index = 0;\r
  BurstCount = 0;\r
  while (Index < sizeof (TPM2_RESPONSE_HEADER)) {\r
    Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_DEVICE_ERROR;\r
      goto Exit;\r
    }\r
    for (; BurstCount > 0; BurstCount--) {\r
      *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
      Index++;\r
      if (Index == sizeof (TPM2_RESPONSE_HEADER)) break;\r
    }\r
  }\r
  DEBUG_CODE (\r
    DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand ReceiveHeader - "));\r
    for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r
      DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
    }\r
    DEBUG ((EFI_D_VERBOSE, "\n"));\r
  );\r
  //\r
  // Check the reponse data header (tag,parasize and returncode )\r
  //\r
  CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
  // TPM2 should not use this RSP_COMMAND\r
  if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {\r
    DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r
    Status = EFI_UNSUPPORTED;\r
    goto Exit;\r
  }\r
\r
  CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
  TpmOutSize  = SwapBytes32 (Data32);\r
  if (*SizeOut < TpmOutSize) {\r
    Status = EFI_BUFFER_TOO_SMALL;\r
    goto Exit;\r
  }\r
  *SizeOut = TpmOutSize;\r
  //\r
  // Continue reading the remaining data\r
  //\r
  while ( Index < TpmOutSize ) {\r
    for (; BurstCount > 0; BurstCount--) {\r
      *(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
      Index++;\r
      if (Index == TpmOutSize) {\r
        Status = EFI_SUCCESS;\r
        goto Exit;\r
      }\r
    }\r
    Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
    if (EFI_ERROR (Status)) {\r
      Status = EFI_DEVICE_ERROR;\r
      goto Exit;\r
    }\r
  }\r
Exit:\r
  DEBUG_CODE (\r
    DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand Receive - "));\r
    for (Index = 0; Index < TpmOutSize; Index++) {\r
      DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
    }\r
    DEBUG ((EFI_D_VERBOSE, "\n"));\r
  );\r
  MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
  return Status;\r
}\r
\r
/**\r
  This service enables the sending of commands to the TPM2.\r
\r
  @param[in]      InputParameterBlockSize  Size of the TPM2 input parameter block.\r
  @param[in]      InputParameterBlock      Pointer to the TPM2 input parameter block.\r
  @param[in,out]  OutputParameterBlockSize Size of the TPM2 output parameter block.\r
  @param[in]      OutputParameterBlock     Pointer to the TPM2 output parameter block.\r
\r
  @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.\r
  @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.\r
  @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small. \r
**/\r
EFI_STATUS\r
EFIAPI\r
DTpm2SubmitCommand (\r
  IN UINT32            InputParameterBlockSize,\r
  IN UINT8             *InputParameterBlock,\r
  IN OUT UINT32        *OutputParameterBlockSize,\r
  IN UINT8             *OutputParameterBlock\r
  )\r
{\r
  return Tpm2TisTpmCommand (\r
           (TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
           InputParameterBlock,\r
           InputParameterBlockSize,\r
           OutputParameterBlock,\r
           OutputParameterBlockSize\r
           );\r
}\r
\r
/**\r
  This service requests use TPM2.\r
\r
  @retval EFI_SUCCESS      Get the control of TPM2 chip.\r
  @retval EFI_NOT_FOUND    TPM2 not found.\r
  @retval EFI_DEVICE_ERROR Unexpected device behavior.\r
**/\r
EFI_STATUS\r
EFIAPI\r
DTpm2RequestUseTpm (\r
  VOID\r
  )\r
{\r
  return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
}\r
Commit	Line	Data
c1d93242 JY	1	/** @file\r
	2	TIS (TPM Interface Specification) functions used by dTPM2.0 library.\r
	3	\r
6f785cfc	4	Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r
6aaac383	5	(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
c1d93242 JY	6	This program and the accompanying materials \r
	7	are licensed and made available under the terms and conditions of the BSD License \r
	8	which accompanies this distribution. The full text of the license may be found at \r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#include <IndustryStandard/Tpm20.h>\r
	17	\r
	18	#include <Library/BaseLib.h>\r
	19	#include <Library/BaseMemoryLib.h>\r
	20	#include <Library/IoLib.h>\r
	21	#include <Library/TimerLib.h>\r
	22	#include <Library/DebugLib.h>\r
	23	#include <Library/Tpm2DeviceLib.h>\r
	24	#include <Library/PcdLib.h>\r
	25	\r
	26	//\r
	27	// Set structure alignment to 1-byte\r
	28	//\r
	29	#pragma pack (1)\r
	30	\r
	31	//\r
	32	// Register set map as specified in TIS specification Chapter 10\r
	33	//\r
	34	typedef struct {\r
	35	///\r
	36	/// Used to gain ownership for this particular port.\r
	37	///\r
	38	UINT8 Access; // 0\r
	39	UINT8 Reserved1[7]; // 1\r
	40	///\r
	41	/// Controls interrupts.\r
	42	///\r
	43	UINT32 IntEnable; // 8\r
	44	///\r
	45	/// SIRQ vector to be used by the TPM.\r
	46	///\r
	47	UINT8 IntVector; // 0ch\r
	48	UINT8 Reserved2[3]; // 0dh\r
	49	///\r
	50	/// What caused interrupt.\r
	51	///\r
	52	UINT32 IntSts; // 10h\r
	53	///\r
	54	/// Shows which interrupts are supported by that particular TPM.\r
	55	///\r
	56	UINT32 IntfCapability; // 14h\r
	57	///\r
	58	/// Status Register. Provides status of the TPM.\r
	59	///\r
	60	UINT8 Status; // 18h\r
	61	///\r
	62	/// Number of consecutive writes that can be done to the TPM.\r
	63	///\r
	64	UINT16 BurstCount; // 19h\r
	65	///\r
	66	/// TPM2 support CANCEL at BIT[24] of STATUS register (WO)\r
	67	///\r
	68	UINT8 StatusEx; // 1Bh\r
	69	UINT8 Reserved3[8];\r
70	///\r
71	/// Read or write FIFO, depending on transaction.\r
72	///\r
73	UINT32 DataFifo; // 24h\r
74	UINT8 Reserved4[0xed8]; // 28h\r
75	///\r
76	/// Vendor ID\r
77	///\r
78	UINT16 Vid; // 0f00h\r
79	///\r
80	/// Device ID\r
81	///\r
82	UINT16 Did; // 0f02h\r
83	///\r
84	/// Revision ID\r
85	///\r
86	UINT8 Rid; // 0f04h\r
87	///\r
88	/// TCG defined configuration registers.\r
89	///\r
90	UINT8 TcgDefined[0x7b]; // 0f05h\r
91	///\r
92	/// Alias to I/O legacy space.\r
93	///\r
94	UINT32 LegacyAddress1; // 0f80h\r
95	///\r
96	/// Additional 8 bits for I/O legacy space extension.\r
97	///\r
98	UINT32 LegacyAddress1Ex; // 0f84h\r
99	///\r
100	/// Alias to second I/O legacy space.\r
101	///\r
102	UINT32 LegacyAddress2; // 0f88h\r
103	///\r
104	/// Additional 8 bits for second I/O legacy space extension.\r
105	///\r
106	UINT32 LegacyAddress2Ex; // 0f8ch\r
107	///\r
108	/// Vendor-defined configuration registers.\r
109	///\r
110	UINT8 VendorDefined[0x70];// 0f90h\r
111	} TIS_PC_REGISTERS;\r
112	\r
113	//\r
114	// Restore original structure alignment\r
115	//\r
116	#pragma pack ()\r
117	\r
118	//\r
119	// Define pointer types used to access TIS registers on PC\r
120	//\r
121	typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
122	\r
123	//\r
124	// Define bits of ACCESS and STATUS registers\r
125	//\r
126	\r
127	///\r
128	/// This bit is a 1 to indicate that the other bits in this register are valid.\r
129	///\r
130	#define TIS_PC_VALID BIT7\r
131	///\r
132	/// Indicate that this locality is active.\r
133	///\r
134	#define TIS_PC_ACC_ACTIVE BIT5\r
135	///\r
136	/// Set to 1 to indicate that this locality had the TPM taken away while\r
137	/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
138	///\r
139	#define TIS_PC_ACC_SEIZED BIT4\r
140	///\r
141	/// Set to 1 to indicate that TPM MUST reset the\r
142	/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
143	/// locality that is writing this bit.\r
144	///\r
145	#define TIS_PC_ACC_SEIZE BIT3\r
146	///\r
147	/// When this bit is 1, another locality is requesting usage of the TPM.\r
148	///\r
149	#define TIS_PC_ACC_PENDIND BIT2\r
150	///\r
151	/// Set to 1 to indicate that this locality is requesting to use TPM.\r
152	///\r
153	#define TIS_PC_ACC_RQUUSE BIT1\r
154	///\r
155	/// A value of 1 indicates that a T/OS has not been established on the platform\r
156	///\r
157	#define TIS_PC_ACC_ESTABLISH BIT0\r
158	\r
159	///\r
160	/// When this bit is 1, TPM is in the Ready state, \r
161	/// indicating it is ready to receive a new command.\r
162	///\r
163	#define TIS_PC_STS_READY BIT6\r
164	///\r
165	/// Write a 1 to this bit to cause the TPM to execute that command.\r
166	///\r
167	#define TIS_PC_STS_GO BIT5\r
168	///\r
169	/// This bit indicates that the TPM has data available as a response.\r
170	///\r
171	#define TIS_PC_STS_DATA BIT4\r
172	///\r
173	/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
174	///\r
175	#define TIS_PC_STS_EXPECT BIT3\r
176	///\r
177	/// Writes a 1 to this bit to force the TPM to re-send the response.\r
178	///\r
179	#define TIS_PC_STS_RETRY BIT1\r
180	\r
181	//\r
182	// Default TimeOut value\r
183	//\r
184	#define TIS_TIMEOUT_A (1000 * 1000) // 1s\r
185	#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
186	#define TIS_TIMEOUT_C (1000 * 1000) // 1s\r
187	#define TIS_TIMEOUT_D (1000 * 1000) // 1s\r
188	\r
189	#define TIS_TIMEOUT_MAX (90000 * 1000) // 90s\r
190	\r
191	//\r
192	// Max TPM command/reponse length\r
193	//\r
194	#define TPMCMDBUFLENGTH 0x500\r
195	\r
196	/**\r
197	Check whether TPM chip exist.\r
198	\r
199	@param[in] TisReg Pointer to TIS register.\r
200	\r
201	@retval TRUE TPM chip exists.\r
202	@retval FALSE TPM chip is not found.\r
203	**/\r
204	BOOLEAN\r
205	TisPcPresenceCheck (\r
206	IN TIS_PC_REGISTERS_PTR TisReg\r
207	)\r
208	{\r
209	UINT8 RegRead;\r
210	\r
211	RegRead = MmioRead8 ((UINTN)&TisReg->Access);\r
212	return (BOOLEAN)(RegRead != (UINT8)-1);\r
213	}\r
214	\r
215	/**\r
216	Check whether the value of a TPM chip register satisfies the input BIT setting.\r
217	\r
218	@param[in] Register Address port of register to be checked.\r
219	@param[in] BitSet Check these data bits are set.\r
220	@param[in] BitClear Check these data bits are clear.\r
221	@param[in] TimeOut The max wait time (unit MicroSecond) when checking register.\r
222	\r
223	@retval EFI_SUCCESS The register satisfies the check bit.\r
224	@retval EFI_TIMEOUT The register can't run into the expected status in time.\r
225	**/\r
226	EFI_STATUS\r
c1d93242 JY	227	TisPcWaitRegisterBits (\r
	228	IN UINT8 *Register,\r
	229	IN UINT8 BitSet,\r
	230	IN UINT8 BitClear,\r
	231	IN UINT32 TimeOut\r
	232	)\r
	233	{\r
	234	UINT8 RegRead;\r
	235	UINT32 WaitTime;\r
	236	\r
	237	for (WaitTime = 0; WaitTime < TimeOut; WaitTime += 30){\r
	238	RegRead = MmioRead8 ((UINTN)Register);\r
	239	if ((RegRead & BitSet) == BitSet && (RegRead & BitClear) == 0)\r
	240	return EFI_SUCCESS;\r
	241	MicroSecondDelay (30);\r
	242	}\r
	243	return EFI_TIMEOUT;\r
	244	}\r
	245	\r
	246	/**\r
	247	Get BurstCount by reading the burstCount field of a TIS regiger \r
	248	in the time of default TIS_TIMEOUT_D.\r
	249	\r
	250	@param[in] TisReg Pointer to TIS register.\r
	251	@param[out] BurstCount Pointer to a buffer to store the got BurstConut.\r
	252	\r
	253	@retval EFI_SUCCESS Get BurstCount.\r
	254	@retval EFI_INVALID_PARAMETER TisReg is NULL or BurstCount is NULL.\r
	255	@retval EFI_TIMEOUT BurstCount can't be got in time.\r
	256	**/\r
	257	EFI_STATUS\r
c1d93242 JY	258	TisPcReadBurstCount (\r
	259	IN TIS_PC_REGISTERS_PTR TisReg,\r
	260	OUT UINT16 *BurstCount\r
	261	)\r
	262	{\r
	263	UINT32 WaitTime;\r
	264	UINT8 DataByte0;\r
	265	UINT8 DataByte1;\r
	266	\r
	267	if (BurstCount == NULL \|\| TisReg == NULL) {\r
	268	return EFI_INVALID_PARAMETER;\r
	269	}\r
	270	\r
	271	WaitTime = 0;\r
	272	do {\r
	273	//\r
	274	// TIS_PC_REGISTERS_PTR->burstCount is UINT16, but it is not 2bytes aligned,\r
	275	// so it needs to use MmioRead8 to read two times\r
	276	//\r
	277	DataByte0 = MmioRead8 ((UINTN)&TisReg->BurstCount);\r
	278	DataByte1 = MmioRead8 ((UINTN)&TisReg->BurstCount + 1);\r
	279	*BurstCount = (UINT16)((DataByte1 << 8) + DataByte0);\r
	280	if (*BurstCount != 0) {\r
	281	return EFI_SUCCESS;\r
	282	}\r
	283	MicroSecondDelay (30);\r
	284	WaitTime += 30;\r
	285	} while (WaitTime < TIS_TIMEOUT_D);\r
	286	\r
	287	return EFI_TIMEOUT;\r
	288	}\r
	289	\r
	290	/**\r
	291	Set TPM chip to ready state by sending ready command TIS_PC_STS_READY \r
	292	to Status Register in time.\r
	293	\r
	294	@param[in] TisReg Pointer to TIS register.\r
	295	\r
	296	@retval EFI_SUCCESS TPM chip enters into ready state.\r
	297	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
	298	@retval EFI_TIMEOUT TPM chip can't be set to ready state in time.\r
	299	**/\r
	300	EFI_STATUS\r
c1d93242 JY	301	TisPcPrepareCommand (\r
	302	IN TIS_PC_REGISTERS_PTR TisReg\r
	303	)\r
	304	{\r
	305	EFI_STATUS Status;\r
	306	\r
	307	if (TisReg == NULL) {\r
	308	return EFI_INVALID_PARAMETER;\r
	309	}\r
	310	\r
	311	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
	312	Status = TisPcWaitRegisterBits (\r
	313	&TisReg->Status,\r
	314	TIS_PC_STS_READY,\r
	315	0,\r
	316	TIS_TIMEOUT_B\r
	317	);\r
	318	return Status;\r
	319	}\r
	320	\r
	321	/**\r
	322	Get the control of TPM chip by sending requestUse command TIS_PC_ACC_RQUUSE \r
	323	to ACCESS Register in the time of default TIS_TIMEOUT_A.\r
	324	\r
	325	@param[in] TisReg Pointer to TIS register.\r
	326	\r
	327	@retval EFI_SUCCESS Get the control of TPM chip.\r
	328	@retval EFI_INVALID_PARAMETER TisReg is NULL.\r
	329	@retval EFI_NOT_FOUND TPM chip doesn't exit.\r
	330	@retval EFI_TIMEOUT Can't get the TPM control in time.\r
	331	**/\r
	332	EFI_STATUS\r
c1d93242 JY	333	TisPcRequestUseTpm (\r
	334	IN TIS_PC_REGISTERS_PTR TisReg\r
	335	)\r
	336	{\r
	337	EFI_STATUS Status;\r
	338	\r
	339	if (TisReg == NULL) {\r
	340	return EFI_INVALID_PARAMETER;\r
	341	}\r
	342	\r
	343	if (!TisPcPresenceCheck (TisReg)) {\r
	344	return EFI_NOT_FOUND;\r
	345	}\r
	346	\r
	347	MmioWrite8((UINTN)&TisReg->Access, TIS_PC_ACC_RQUUSE);\r
	348	Status = TisPcWaitRegisterBits (\r
	349	&TisReg->Access,\r
	350	(UINT8)(TIS_PC_ACC_ACTIVE \|TIS_PC_VALID),\r
	351	0,\r
	352	TIS_TIMEOUT_A\r
	353	);\r
	354	return Status;\r
	355	}\r
	356	\r
	357	/**\r
	358	Send a command to TPM for execution and return response data.\r
	359	\r
	360	@param[in] TisReg TPM register space base address. \r
	361	@param[in] BufferIn Buffer for command data. \r
	362	@param[in] SizeIn Size of command data. \r
	363	@param[in, out] BufferOut Buffer for response data. \r
	364	@param[in, out] SizeOut Size of response data. \r
	365	\r
	366	@retval EFI_SUCCESS Operation completed successfully.\r
c1d93242 JY	367	@retval EFI_BUFFER_TOO_SMALL Response data buffer is too small.\r
	368	@retval EFI_DEVICE_ERROR Unexpected device behavior.\r
	369	@retval EFI_UNSUPPORTED Unsupported TPM version\r
	370	\r
	371	**/\r
	372	EFI_STATUS\r
c2967d35	373	Tpm2TisTpmCommand (\r
c1d93242 JY	374	IN TIS_PC_REGISTERS_PTR TisReg,\r
	375	IN UINT8 *BufferIn,\r
	376	IN UINT32 SizeIn,\r
	377	IN OUT UINT8 *BufferOut,\r
	378	IN OUT UINT32 *SizeOut\r
	379	)\r
	380	{\r
	381	EFI_STATUS Status;\r
	382	UINT16 BurstCount;\r
	383	UINT32 Index;\r
	384	UINT32 TpmOutSize;\r
	385	UINT16 Data16;\r
	386	UINT32 Data32;\r
	387	\r
	388	DEBUG_CODE (\r
	389	UINTN DebugSize;\r
	390	\r
6aaac383	391	DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand Send - "));\r
c1d93242 JY	392	if (SizeIn > 0x100) {\r
	393	DebugSize = 0x40;\r
	394	} else {\r
	395	DebugSize = SizeIn;\r
	396	}\r
	397	for (Index = 0; Index < DebugSize; Index++) {\r
6aaac383	398	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
c1d93242 JY	399	}\r
c1d93242 JY	400	if (DebugSize != SizeIn) {\r
6aaac383	401	DEBUG ((EFI_D_VERBOSE, "...... "));\r
c1d93242	402	for (Index = SizeIn - 0x20; Index < SizeIn; Index++) {\r
6aaac383	403	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferIn[Index]));\r
c1d93242 JY	404	}\r
c1d93242 JY	405	}\r
6aaac383	406	DEBUG ((EFI_D_VERBOSE, "\n"));\r
c1d93242 JY	407	);\r
	408	TpmOutSize = 0;\r
	409	\r
	410	Status = TisPcPrepareCommand (TisReg);\r
	411	if (EFI_ERROR (Status)){\r
6f785cfc JY	412	DEBUG ((DEBUG_ERROR, "Tpm2 is not ready for command!\n"));\r
6f785cfc JY	413	return EFI_DEVICE_ERROR;\r
c1d93242 JY	414	}\r
	415	//\r
	416	// Send the command data to Tpm\r
	417	//\r
	418	Index = 0;\r
	419	while (Index < SizeIn) {\r
	420	Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
	421	if (EFI_ERROR (Status)) {\r
6f785cfc	422	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	423	goto Exit;\r
	424	}\r
	425	for (; BurstCount > 0 && Index < SizeIn; BurstCount--) {\r
	426	MmioWrite8((UINTN)&TisReg->DataFifo, *(BufferIn + Index));\r
	427	Index++;\r
	428	}\r
	429	}\r
	430	//\r
	431	// Check the Tpm status STS_EXPECT change from 1 to 0\r
	432	//\r
	433	Status = TisPcWaitRegisterBits (\r
	434	&TisReg->Status,\r
	435	(UINT8) TIS_PC_VALID,\r
	436	TIS_PC_STS_EXPECT,\r
	437	TIS_TIMEOUT_C\r
	438	);\r
	439	if (EFI_ERROR (Status)) {\r
6f785cfc	440	DEBUG ((DEBUG_ERROR, "Tpm2 The send buffer too small!\n"));\r
c1d93242 JY	441	Status = EFI_BUFFER_TOO_SMALL;\r
	442	goto Exit;\r
	443	}\r
	444	//\r
	445	// Executed the TPM command and waiting for the response data ready\r
	446	//\r
	447	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_GO);\r
	448	\r
	449	//\r
	450	// NOTE: That may take many seconds to minutes for certain commands, such as key generation.\r
	451	//\r
	452	Status = TisPcWaitRegisterBits (\r
	453	&TisReg->Status,\r
	454	(UINT8) (TIS_PC_VALID \| TIS_PC_STS_DATA),\r
	455	0,\r
	456	TIS_TIMEOUT_MAX\r
	457	);\r
	458	if (EFI_ERROR (Status)) {\r
6f785cfc JY	459	DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out!!\n"));\r
6f785cfc JY	460	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	461	goto Exit;\r
	462	}\r
	463	//\r
	464	// Get response data header\r
	465	//\r
	466	Index = 0;\r
	467	BurstCount = 0;\r
	468	while (Index < sizeof (TPM2_RESPONSE_HEADER)) {\r
	469	Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
	470	if (EFI_ERROR (Status)) {\r
6f785cfc	471	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	472	goto Exit;\r
	473	}\r
	474	for (; BurstCount > 0; BurstCount--) {\r
	475	*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
	476	Index++;\r
	477	if (Index == sizeof (TPM2_RESPONSE_HEADER)) break;\r
	478	}\r
	479	}\r
	480	DEBUG_CODE (\r
c2967d35	481	DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand ReceiveHeader - "));\r
c1d93242	482	for (Index = 0; Index < sizeof (TPM2_RESPONSE_HEADER); Index++) {\r
6aaac383	483	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
c1d93242	484	}\r
6aaac383	485	DEBUG ((EFI_D_VERBOSE, "\n"));\r
c1d93242 JY	486	);\r
	487	//\r
	488	// Check the reponse data header (tag,parasize and returncode )\r
	489	//\r
	490	CopyMem (&Data16, BufferOut, sizeof (UINT16));\r
	491	// TPM2 should not use this RSP_COMMAND\r
	492	if (SwapBytes16 (Data16) == TPM_ST_RSP_COMMAND) {\r
6f785cfc	493	DEBUG ((EFI_D_ERROR, "TPM2: TPM_ST_RSP error - %x\n", TPM_ST_RSP_COMMAND));\r
c1d93242 JY	494	Status = EFI_UNSUPPORTED;\r
	495	goto Exit;\r
	496	}\r
	497	\r
	498	CopyMem (&Data32, (BufferOut + 2), sizeof (UINT32));\r
	499	TpmOutSize = SwapBytes32 (Data32);\r
	500	if (*SizeOut < TpmOutSize) {\r
	501	Status = EFI_BUFFER_TOO_SMALL;\r
	502	goto Exit;\r
	503	}\r
	504	*SizeOut = TpmOutSize;\r
	505	//\r
	506	// Continue reading the remaining data\r
	507	//\r
	508	while ( Index < TpmOutSize ) {\r
	509	for (; BurstCount > 0; BurstCount--) {\r
	510	*(BufferOut + Index) = MmioRead8 ((UINTN)&TisReg->DataFifo);\r
	511	Index++;\r
	512	if (Index == TpmOutSize) {\r
	513	Status = EFI_SUCCESS;\r
	514	goto Exit;\r
	515	}\r
	516	}\r
	517	Status = TisPcReadBurstCount (TisReg, &BurstCount);\r
	518	if (EFI_ERROR (Status)) {\r
6f785cfc	519	Status = EFI_DEVICE_ERROR;\r
c1d93242 JY	520	goto Exit;\r
	521	}\r
	522	}\r
	523	Exit:\r
	524	DEBUG_CODE (\r
6aaac383	525	DEBUG ((EFI_D_VERBOSE, "Tpm2TisTpmCommand Receive - "));\r
c1d93242	526	for (Index = 0; Index < TpmOutSize; Index++) {\r
6aaac383	527	DEBUG ((EFI_D_VERBOSE, "%02x ", BufferOut[Index]));\r
c1d93242	528	}\r
6aaac383	529	DEBUG ((EFI_D_VERBOSE, "\n"));\r
c1d93242 JY	530	);\r
	531	MmioWrite8((UINTN)&TisReg->Status, TIS_PC_STS_READY);\r
	532	return Status;\r
	533	}\r
	534	\r
	535	/**\r
	536	This service enables the sending of commands to the TPM2.\r
	537	\r
	538	@param[in] InputParameterBlockSize Size of the TPM2 input parameter block.\r
	539	@param[in] InputParameterBlock Pointer to the TPM2 input parameter block.\r
	540	@param[in,out] OutputParameterBlockSize Size of the TPM2 output parameter block.\r
	541	@param[in] OutputParameterBlock Pointer to the TPM2 output parameter block.\r
	542	\r
	543	@retval EFI_SUCCESS The command byte stream was successfully sent to the device and a response was successfully received.\r
	544	@retval EFI_DEVICE_ERROR The command was not successfully sent to the device or a response was not successfully received from the device.\r
	545	@retval EFI_BUFFER_TOO_SMALL The output parameter block is too small. \r
	546	**/\r
	547	EFI_STATUS\r
	548	EFIAPI\r
	549	DTpm2SubmitCommand (\r
	550	IN UINT32 InputParameterBlockSize,\r
	551	IN UINT8 *InputParameterBlock,\r
	552	IN OUT UINT32 *OutputParameterBlockSize,\r
	553	IN UINT8 *OutputParameterBlock\r
	554	)\r
	555	{\r
c2967d35	556	return Tpm2TisTpmCommand (\r
c1d93242 JY	557	(TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress),\r
	558	InputParameterBlock,\r
	559	InputParameterBlockSize,\r
	560	OutputParameterBlock,\r
	561	OutputParameterBlockSize\r
	562	);\r
	563	}\r
	564	\r
	565	/**\r
	566	This service requests use TPM2.\r
	567	\r
	568	@retval EFI_SUCCESS Get the control of TPM2 chip.\r
	569	@retval EFI_NOT_FOUND TPM2 not found.\r
	570	@retval EFI_DEVICE_ERROR Unexpected device behavior.\r
	571	**/\r
	572	EFI_STATUS\r
	573	EFIAPI\r
	574	DTpm2RequestUseTpm (\r
	575	VOID\r
	576	)\r
	577	{\r
	578	return TisPcRequestUseTpm ((TIS_PC_REGISTERS_PTR) (UINTN) PcdGet64 (PcdTpmBaseAddress));\r
	579	}\r