SecurityPkg/Opal: Refine casting expression result to bigger size
[mirror_edk2.git] / SecurityPkg / Tcg / Opal / OpalPasswordSmm / OpalNvmeMode.c
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1/** @file\r
2 Provide functions to initialize NVME controller and perform NVME commands\r
3\r
5d7f27aa 4Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
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5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "OpalPasswordSmm.h"\r
16\r
17\r
18#define ALIGN(v, a) (UINTN)((((v) - 1) | ((a) - 1)) + 1)\r
19\r
20///\r
21/// NVME Host controller registers operation\r
22///\r
23#define NVME_GET_CAP(Nvme, Cap) NvmeMmioRead (Cap, Nvme->Nbar + NVME_CAP_OFFSET, sizeof (NVME_CAP))\r
24#define NVME_GET_CC(Nvme, Cc) NvmeMmioRead (Cc, Nvme->Nbar + NVME_CC_OFFSET, sizeof (NVME_CC))\r
25#define NVME_SET_CC(Nvme, Cc) NvmeMmioWrite (Nvme->Nbar + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))\r
26#define NVME_GET_CSTS(Nvme, Csts) NvmeMmioRead (Csts, Nvme->Nbar + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))\r
27#define NVME_GET_AQA(Nvme, Aqa) NvmeMmioRead (Aqa, Nvme->Nbar + NVME_AQA_OFFSET, sizeof (NVME_AQA))\r
28#define NVME_SET_AQA(Nvme, Aqa) NvmeMmioWrite (Nvme->Nbar + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))\r
29#define NVME_GET_ASQ(Nvme, Asq) NvmeMmioRead (Asq, Nvme->Nbar + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))\r
30#define NVME_SET_ASQ(Nvme, Asq) NvmeMmioWrite (Nvme->Nbar + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))\r
31#define NVME_GET_ACQ(Nvme, Acq) NvmeMmioRead (Acq, Nvme->Nbar + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))\r
32#define NVME_SET_ACQ(Nvme, Acq) NvmeMmioWrite (Nvme->Nbar + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))\r
33#define NVME_GET_VER(Nvme, Ver) NvmeMmioRead (Ver, Nvme->Nbar + NVME_VER_OFFSET, sizeof (NVME_VER))\r
34#define NVME_SET_SQTDBL(Nvme, Qid, Sqtdbl) NvmeMmioWrite (Nvme->Nbar + NVME_SQTDBL_OFFSET(Qid, Nvme->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))\r
35#define NVME_SET_CQHDBL(Nvme, Qid, Cqhdbl) NvmeMmioWrite (Nvme->Nbar + NVME_CQHDBL_OFFSET(Qid, Nvme->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))\r
36\r
37///\r
38/// Base memory address\r
39///\r
40enum {\r
41 BASEMEM_CONTROLLER_DATA,\r
42 BASEMEM_IDENTIFY_DATA,\r
43 BASEMEM_ASQ,\r
44 BASEMEM_ACQ,\r
45 BASEMEM_SQ,\r
46 BASEMEM_CQ,\r
47 BASEMEM_PRP,\r
48 BASEMEM_SECURITY,\r
49 MAX_BASEMEM_COUNT\r
50};\r
51\r
52///\r
53/// All of base memories are 4K(0x1000) alignment\r
54///\r
5d7f27aa 55#define NVME_MEM_BASE(Nvme) ((UINTN)(Nvme->BaseMem))\r
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56#define NVME_CONTROL_DATA_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_CONTROLLER_DATA)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
57#define NVME_NAMESPACE_DATA_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_IDENTIFY_DATA)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
58#define NVME_ASQ_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_ASQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
59#define NVME_ACQ_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_ACQ)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
60#define NVME_SQ_BASE(Nvme, index) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_SQ) + ((index)*(NVME_MAX_IO_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
61#define NVME_CQ_BASE(Nvme, index) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_CQ) + ((index)*(NVME_MAX_IO_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
62#define NVME_PRP_BASE(Nvme, index) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_PRP) + ((index)*NVME_PRP_SIZE)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
63#define NVME_SEC_BASE(Nvme) (ALIGN (NVME_MEM_BASE(Nvme) + ((NvmeGetBaseMemPages (BASEMEM_SECURITY)) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))\r
64\r
65/**\r
66 Transfer MMIO Data to memory.\r
67\r
68 @param[in,out] MemBuffer - Destination: Memory address\r
69 @param[in] MmioAddr - Source: MMIO address\r
70 @param[in] Size - Size for read\r
71\r
72 @retval EFI_SUCCESS - MMIO read sucessfully\r
73**/\r
74EFI_STATUS\r
75NvmeMmioRead (\r
76 IN OUT VOID *MemBuffer,\r
77 IN UINTN MmioAddr,\r
78 IN UINTN Size\r
79 )\r
80{\r
81 UINTN Offset;\r
82 UINT8 Data;\r
83 UINT8 *Ptr;\r
84\r
85 // priority has adjusted\r
86 switch (Size) {\r
87 case 4:\r
88 *((UINT32 *)MemBuffer) = MmioRead32 (MmioAddr);\r
89 break;\r
90\r
91 case 8:\r
92 *((UINT64 *)MemBuffer) = MmioRead64 (MmioAddr);\r
93 break;\r
94\r
95 case 2:\r
96 *((UINT16 *)MemBuffer) = MmioRead16 (MmioAddr);\r
97 break;\r
98\r
99 case 1:\r
100 *((UINT8 *)MemBuffer) = MmioRead8 (MmioAddr);\r
101 break;\r
102\r
103 default:\r
104 Ptr = (UINT8 *)MemBuffer;\r
105 for (Offset = 0; Offset < Size; Offset += 1) {\r
106 Data = MmioRead8 (MmioAddr + Offset);\r
107 Ptr[Offset] = Data;\r
108 }\r
109 break;\r
110 }\r
111\r
112 return EFI_SUCCESS;\r
113}\r
114\r
115/**\r
116 Transfer memory data to MMIO.\r
117\r
118 @param[in,out] MmioAddr - Destination: MMIO address\r
119 @param[in] MemBuffer - Source: Memory address\r
120 @param[in] Size - Size for write\r
121\r
122 @retval EFI_SUCCESS - MMIO write sucessfully\r
123**/\r
124EFI_STATUS\r
125NvmeMmioWrite (\r
126 IN OUT UINTN MmioAddr,\r
127 IN VOID *MemBuffer,\r
128 IN UINTN Size\r
129 )\r
130{\r
131 UINTN Offset;\r
132 UINT8 Data;\r
133 UINT8 *Ptr;\r
134\r
135 // priority has adjusted\r
136 switch (Size) {\r
137 case 4:\r
138 MmioWrite32 (MmioAddr, *((UINT32 *)MemBuffer));\r
139 break;\r
140\r
141 case 8:\r
142 MmioWrite64 (MmioAddr, *((UINT64 *)MemBuffer));\r
143 break;\r
144\r
145 case 2:\r
146 MmioWrite16 (MmioAddr, *((UINT16 *)MemBuffer));\r
147 break;\r
148\r
149 case 1:\r
150 MmioWrite8 (MmioAddr, *((UINT8 *)MemBuffer));\r
151 break;\r
152\r
153 default:\r
154 Ptr = (UINT8 *)MemBuffer;\r
155 for (Offset = 0; Offset < Size; Offset += 1) {\r
156 Data = Ptr[Offset];\r
157 MmioWrite8 (MmioAddr + Offset, Data);\r
158 }\r
159 break;\r
160 }\r
161\r
162 return EFI_SUCCESS;\r
163}\r
164\r
165/**\r
166 Transfer MMIO data to memory.\r
167\r
168 @param[in,out] MemBuffer - Destination: Memory address\r
169 @param[in] MmioAddr - Source: MMIO address\r
170 @param[in] Size - Size for read\r
171\r
172 @retval EFI_SUCCESS - MMIO read sucessfully\r
173**/\r
174EFI_STATUS\r
175OpalPciRead (\r
176 IN OUT VOID *MemBuffer,\r
177 IN UINTN MmioAddr,\r
178 IN UINTN Size\r
179 )\r
180{\r
181 UINTN Offset;\r
182 UINT8 Data;\r
183 UINT8 *Ptr;\r
184\r
185 // priority has adjusted\r
186 switch (Size) {\r
187 case 4:\r
188 *((UINT32 *)MemBuffer) = PciRead32 (MmioAddr);\r
189 break;\r
190\r
191 case 2:\r
192 *((UINT16 *)MemBuffer) = PciRead16 (MmioAddr);\r
193 break;\r
194\r
195 case 1:\r
196 *((UINT8 *)MemBuffer) = PciRead8 (MmioAddr);\r
197 break;\r
198\r
199 default:\r
200 Ptr = (UINT8 *)MemBuffer;\r
201 for (Offset = 0; Offset < Size; Offset += 1) {\r
202 Data = PciRead8 (MmioAddr + Offset);\r
203 Ptr[Offset] = Data;\r
204 }\r
205 break;\r
206 }\r
207\r
208 return EFI_SUCCESS;\r
209}\r
210\r
211/**\r
212 Transfer memory data to MMIO.\r
213\r
214 @param[in,out] MmioAddr - Destination: MMIO address\r
215 @param[in] MemBuffer - Source: Memory address\r
216 @param[in] Size - Size for write\r
217\r
218 @retval EFI_SUCCESS - MMIO write sucessfully\r
219**/\r
220EFI_STATUS\r
221OpalPciWrite (\r
222 IN OUT UINTN MmioAddr,\r
223 IN VOID *MemBuffer,\r
224 IN UINTN Size\r
225 )\r
226{\r
227 UINTN Offset;\r
228 UINT8 Data;\r
229 UINT8 *Ptr;\r
230\r
231 // priority has adjusted\r
232 switch (Size) {\r
233 case 4:\r
234 PciWrite32 (MmioAddr, *((UINT32 *)MemBuffer));\r
235 break;\r
236\r
237 case 2:\r
238 PciWrite16 (MmioAddr, *((UINT16 *)MemBuffer));\r
239 break;\r
240\r
241 case 1:\r
242 PciWrite8 (MmioAddr, *((UINT8 *)MemBuffer));\r
243 break;\r
244\r
245 default:\r
246 Ptr = (UINT8 *)MemBuffer;\r
247 for (Offset = 0; Offset < Size; Offset += 1) {\r
248 Data = Ptr[Offset];\r
249 PciWrite8 (MmioAddr + Offset, Data);\r
250 }\r
251 break;\r
252 }\r
253\r
254 return EFI_SUCCESS;\r
255}\r
256\r
257/**\r
258 Get total pages for specific NVME based memory.\r
259\r
260 @param[in] BaseMemIndex - The Index of BaseMem (0-based).\r
261\r
262 @retval - The page count for specific BaseMem Index\r
263\r
264**/\r
265UINT32\r
266NvmeGetBaseMemPages (\r
267 IN UINTN BaseMemIndex\r
268 )\r
269{\r
270 UINT32 Pages;\r
271 UINTN Index;\r
272 UINT32 PageSizeList[8];\r
273\r
274 PageSizeList[0] = 1; /* Controller Data */\r
275 PageSizeList[1] = 1; /* Identify Data */\r
276 PageSizeList[2] = 1; /* ASQ */\r
277 PageSizeList[3] = 1; /* ACQ */\r
278 PageSizeList[4] = 1; /* SQs */\r
279 PageSizeList[5] = 1; /* CQs */\r
280 PageSizeList[6] = NVME_PRP_SIZE * NVME_CSQ_DEPTH; /* PRPs */\r
281 PageSizeList[7] = 1; /* Security Commands */\r
282\r
283 if (BaseMemIndex > MAX_BASEMEM_COUNT) {\r
284 ASSERT (FALSE);\r
285 return 0;\r
286 }\r
287\r
288 Pages = 0;\r
289 for (Index = 0; Index < BaseMemIndex; Index++) {\r
290 Pages += PageSizeList[Index];\r
291 }\r
292\r
293 return Pages;\r
294}\r
295\r
296/**\r
297 Wait for NVME controller status to be ready or not.\r
298\r
299 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
300 @param[in] WaitReady - Flag for waitting status ready or not\r
301\r
302 @return EFI_SUCCESS - Successfully to wait specific status.\r
303 @return others - Fail to wait for specific controller status.\r
304\r
305**/\r
306STATIC\r
307EFI_STATUS\r
308NvmeWaitController (\r
309 IN NVME_CONTEXT *Nvme,\r
310 IN BOOLEAN WaitReady\r
311 )\r
312{\r
313 NVME_CSTS Csts;\r
314 EFI_STATUS Status;\r
315 UINT32 Index;\r
316 UINT8 Timeout;\r
317\r
318 //\r
319 // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after\r
320 // Cc.Enable. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.\r
321 //\r
322 if (Nvme->Cap.To == 0) {\r
323 Timeout = 1;\r
324 } else {\r
325 Timeout = Nvme->Cap.To;\r
326 }\r
327\r
328 Status = EFI_SUCCESS;\r
329 for(Index = (Timeout * 500); Index != 0; --Index) {\r
330 MicroSecondDelay (1000);\r
331\r
332 //\r
333 // Check if the controller is initialized\r
334 //\r
335 Status = NVME_GET_CSTS (Nvme, &Csts);\r
336 if (EFI_ERROR(Status)) {\r
337 DEBUG ((DEBUG_ERROR, "NVME_GET_CSTS fail, Status = %r\n", Status));\r
338 return Status;\r
339 }\r
340\r
341 if ((BOOLEAN) Csts.Rdy == WaitReady) {\r
342 break;\r
343 }\r
344 }\r
345\r
346 if (Index == 0) {\r
347 Status = EFI_TIMEOUT;\r
348 }\r
349\r
350 return Status;\r
351}\r
352\r
353/**\r
354 Disable the Nvm Express controller.\r
355\r
356 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
357\r
358 @return EFI_SUCCESS - Successfully disable the controller.\r
359 @return others - Fail to disable the controller.\r
360\r
361**/\r
362STATIC\r
363EFI_STATUS\r
364NvmeDisableController (\r
365 IN NVME_CONTEXT *Nvme\r
366 )\r
367{\r
368 NVME_CC Cc;\r
369 NVME_CSTS Csts;\r
370 EFI_STATUS Status;\r
371\r
372 Status = NVME_GET_CSTS (Nvme, &Csts);\r
373\r
374 ///\r
375 /// Read Controller Configuration Register.\r
376 ///\r
377 Status = NVME_GET_CC (Nvme, &Cc);\r
378 if (EFI_ERROR(Status)) {\r
379 DEBUG ((DEBUG_ERROR, "NVME_GET_CC fail, Status = %r\n", Status));\r
380 goto Done;\r
381 }\r
382\r
383 if (Cc.En == 1) {\r
384 Cc.En = 0;\r
385 ///\r
386 /// Disable the controller.\r
387 ///\r
388 Status = NVME_SET_CC (Nvme, &Cc);\r
389 if (EFI_ERROR(Status)) {\r
390 DEBUG ((DEBUG_ERROR, "NVME_SET_CC fail, Status = %r\n", Status));\r
391 goto Done;\r
392 }\r
393 }\r
394\r
395 Status = NvmeWaitController (Nvme, FALSE);\r
396 if (EFI_ERROR(Status)) {\r
397 DEBUG ((DEBUG_ERROR, "NvmeWaitController fail, Status = %r\n", Status));\r
398 goto Done;\r
399 }\r
400\r
401 return EFI_SUCCESS;\r
402\r
403Done:\r
404 DEBUG ((DEBUG_INFO, "NvmeDisableController fail, Status: %r\n", Status));\r
405 return Status;\r
406}\r
407\r
408/**\r
409 Enable the Nvm Express controller.\r
410\r
411 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
412\r
413 @return EFI_SUCCESS - Successfully enable the controller.\r
414 @return EFI_DEVICE_ERROR - Fail to enable the controller.\r
415 @return EFI_TIMEOUT - Fail to enable the controller in given time slot.\r
416\r
417**/\r
418STATIC\r
419EFI_STATUS\r
420NvmeEnableController (\r
421 IN NVME_CONTEXT *Nvme\r
422 )\r
423{\r
424 NVME_CC Cc;\r
425 EFI_STATUS Status;\r
426\r
427 //\r
428 // Enable the controller\r
429 //\r
430 ZeroMem (&Cc, sizeof (NVME_CC));\r
431 Cc.En = 1;\r
432 Cc.Iosqes = 6;\r
433 Cc.Iocqes = 4;\r
434 Status = NVME_SET_CC (Nvme, &Cc);\r
435 if (EFI_ERROR(Status)) {\r
436 DEBUG ((DEBUG_ERROR, "NVME_SET_CC fail, Status = %r\n", Status));\r
437 goto Done;\r
438 }\r
439\r
440 Status = NvmeWaitController (Nvme, TRUE);\r
441 if (EFI_ERROR(Status)) {\r
442 DEBUG ((DEBUG_ERROR, "NvmeWaitController fail, Status = %r\n", Status));\r
443 goto Done;\r
444 }\r
445\r
446 return EFI_SUCCESS;\r
447\r
448Done:\r
449 DEBUG ((DEBUG_INFO, "NvmeEnableController fail, Status: %r\n", Status));\r
450 return Status;\r
451}\r
452\r
453/**\r
454 Shutdown the Nvm Express controller.\r
455\r
456 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
457\r
458 @return EFI_SUCCESS - Successfully shutdown the controller.\r
459 @return EFI_DEVICE_ERROR - Fail to shutdown the controller.\r
460 @return EFI_TIMEOUT - Fail to shutdown the controller in given time slot.\r
461\r
462**/\r
463STATIC\r
464EFI_STATUS\r
465NvmeShutdownController (\r
466 IN NVME_CONTEXT *Nvme\r
467 )\r
468{\r
469 NVME_CC Cc;\r
470 NVME_CSTS Csts;\r
471 EFI_STATUS Status;\r
472 UINT32 Index;\r
473 UINTN Timeout;\r
474\r
475 Status = NVME_GET_CC (Nvme, &Cc);\r
476 if (EFI_ERROR(Status)) {\r
477 DEBUG ((DEBUG_ERROR, "NVME_GET_CC fail, Status = %r\n", Status));\r
478 return Status;\r
479 }\r
480\r
481 Cc.Shn = 1; // Normal shutdown\r
482\r
483 Status = NVME_SET_CC (Nvme, &Cc);\r
484 if (EFI_ERROR(Status)) {\r
485 DEBUG ((DEBUG_ERROR, "NVME_SET_CC fail, Status = %r\n", Status));\r
486 return Status;\r
487 }\r
488\r
489 Timeout = NVME_GENERIC_TIMEOUT/1000; // ms\r
490 for(Index = (UINT32)(Timeout); Index != 0; --Index) {\r
491 MicroSecondDelay (1000);\r
492\r
493 Status = NVME_GET_CSTS (Nvme, &Csts);\r
494 if (EFI_ERROR(Status)) {\r
495 DEBUG ((DEBUG_ERROR, "NVME_GET_CSTS fail, Status = %r\n", Status));\r
496 return Status;\r
497 }\r
498\r
499 if (Csts.Shst == 2) { // Shutdown processing complete\r
500 break;\r
501 }\r
502 }\r
503\r
504 if (Index == 0) {\r
505 Status = EFI_TIMEOUT;\r
506 }\r
507\r
508 return Status;\r
509}\r
510\r
511/**\r
512 Check the execution status from a given completion queue entry.\r
513\r
514 @param[in] Cq - A pointer to the NVME_CQ item.\r
515\r
516**/\r
517EFI_STATUS\r
518NvmeCheckCqStatus (\r
519 IN NVME_CQ *Cq\r
520 )\r
521{\r
522 if (Cq->Sct == 0x0 && Cq->Sc == 0x0) {\r
523 return EFI_SUCCESS;\r
524 }\r
525\r
526 DEBUG ((DEBUG_INFO, "Dump NVMe Completion Entry Status from [0x%x]:\n", (UINTN)Cq));\r
527 DEBUG ((DEBUG_INFO, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r
528 DEBUG ((DEBUG_INFO, " NVMe Cmd Execution Result - "));\r
529\r
530 switch (Cq->Sct) {\r
531 case 0x0:\r
532 switch (Cq->Sc) {\r
533 case 0x0:\r
534 DEBUG ((DEBUG_INFO, "Successful Completion\n"));\r
535 return EFI_SUCCESS;\r
536 case 0x1:\r
537 DEBUG ((DEBUG_INFO, "Invalid Command Opcode\n"));\r
538 break;\r
539 case 0x2:\r
540 DEBUG ((DEBUG_INFO, "Invalid Field in Command\n"));\r
541 break;\r
542 case 0x3:\r
543 DEBUG ((DEBUG_INFO, "Command ID Conflict\n"));\r
544 break;\r
545 case 0x4:\r
546 DEBUG ((DEBUG_INFO, "Data Transfer Error\n"));\r
547 break;\r
548 case 0x5:\r
549 DEBUG ((DEBUG_INFO, "Commands Aborted due to Power Loss Notification\n"));\r
550 break;\r
551 case 0x6:\r
552 DEBUG ((DEBUG_INFO, "Internal Device Error\n"));\r
553 break;\r
554 case 0x7:\r
555 DEBUG ((DEBUG_INFO, "Command Abort Requested\n"));\r
556 break;\r
557 case 0x8:\r
558 DEBUG ((DEBUG_INFO, "Command Aborted due to SQ Deletion\n"));\r
559 break;\r
560 case 0x9:\r
561 DEBUG ((DEBUG_INFO, "Command Aborted due to Failed Fused Command\n"));\r
562 break;\r
563 case 0xA:\r
564 DEBUG ((DEBUG_INFO, "Command Aborted due to Missing Fused Command\n"));\r
565 break;\r
566 case 0xB:\r
567 DEBUG ((DEBUG_INFO, "Invalid Namespace or Format\n"));\r
568 break;\r
569 case 0xC:\r
570 DEBUG ((DEBUG_INFO, "Command Sequence Error\n"));\r
571 break;\r
572 case 0xD:\r
573 DEBUG ((DEBUG_INFO, "Invalid SGL Last Segment Descriptor\n"));\r
574 break;\r
575 case 0xE:\r
576 DEBUG ((DEBUG_INFO, "Invalid Number of SGL Descriptors\n"));\r
577 break;\r
578 case 0xF:\r
579 DEBUG ((DEBUG_INFO, "Data SGL Length Invalid\n"));\r
580 break;\r
581 case 0x10:\r
582 DEBUG ((DEBUG_INFO, "Metadata SGL Length Invalid\n"));\r
583 break;\r
584 case 0x11:\r
585 DEBUG ((DEBUG_INFO, "SGL Descriptor Type Invalid\n"));\r
586 break;\r
587 case 0x80:\r
588 DEBUG ((DEBUG_INFO, "LBA Out of Range\n"));\r
589 break;\r
590 case 0x81:\r
591 DEBUG ((DEBUG_INFO, "Capacity Exceeded\n"));\r
592 break;\r
593 case 0x82:\r
594 DEBUG ((DEBUG_INFO, "Namespace Not Ready\n"));\r
595 break;\r
596 case 0x83:\r
597 DEBUG ((DEBUG_INFO, "Reservation Conflict\n"));\r
598 break;\r
599 }\r
600 break;\r
601\r
602 case 0x1:\r
603 switch (Cq->Sc) {\r
604 case 0x0:\r
605 DEBUG ((DEBUG_INFO, "Completion Queue Invalid\n"));\r
606 break;\r
607 case 0x1:\r
608 DEBUG ((DEBUG_INFO, "Invalid Queue Identifier\n"));\r
609 break;\r
610 case 0x2:\r
611 DEBUG ((DEBUG_INFO, "Maximum Queue Size Exceeded\n"));\r
612 break;\r
613 case 0x3:\r
614 DEBUG ((DEBUG_INFO, "Abort Command Limit Exceeded\n"));\r
615 break;\r
616 case 0x5:\r
617 DEBUG ((DEBUG_INFO, "Asynchronous Event Request Limit Exceeded\n"));\r
618 break;\r
619 case 0x6:\r
620 DEBUG ((DEBUG_INFO, "Invalid Firmware Slot\n"));\r
621 break;\r
622 case 0x7:\r
623 DEBUG ((DEBUG_INFO, "Invalid Firmware Image\n"));\r
624 break;\r
625 case 0x8:\r
626 DEBUG ((DEBUG_INFO, "Invalid Interrupt Vector\n"));\r
627 break;\r
628 case 0x9:\r
629 DEBUG ((DEBUG_INFO, "Invalid Log Page\n"));\r
630 break;\r
631 case 0xA:\r
632 DEBUG ((DEBUG_INFO, "Invalid Format\n"));\r
633 break;\r
634 case 0xB:\r
635 DEBUG ((DEBUG_INFO, "Firmware Application Requires Conventional Reset\n"));\r
636 break;\r
637 case 0xC:\r
638 DEBUG ((DEBUG_INFO, "Invalid Queue Deletion\n"));\r
639 break;\r
640 case 0xD:\r
641 DEBUG ((DEBUG_INFO, "Feature Identifier Not Saveable\n"));\r
642 break;\r
643 case 0xE:\r
644 DEBUG ((DEBUG_INFO, "Feature Not Changeable\n"));\r
645 break;\r
646 case 0xF:\r
647 DEBUG ((DEBUG_INFO, "Feature Not Namespace Specific\n"));\r
648 break;\r
649 case 0x10:\r
650 DEBUG ((DEBUG_INFO, "Firmware Application Requires NVM Subsystem Reset\n"));\r
651 break;\r
652 case 0x80:\r
653 DEBUG ((DEBUG_INFO, "Conflicting Attributes\n"));\r
654 break;\r
655 case 0x81:\r
656 DEBUG ((DEBUG_INFO, "Invalid Protection Information\n"));\r
657 break;\r
658 case 0x82:\r
659 DEBUG ((DEBUG_INFO, "Attempted Write to Read Only Range\n"));\r
660 break;\r
661 }\r
662 break;\r
663\r
664 case 0x2:\r
665 switch (Cq->Sc) {\r
666 case 0x80:\r
667 DEBUG ((DEBUG_INFO, "Write Fault\n"));\r
668 break;\r
669 case 0x81:\r
670 DEBUG ((DEBUG_INFO, "Unrecovered Read Error\n"));\r
671 break;\r
672 case 0x82:\r
673 DEBUG ((DEBUG_INFO, "End-to-end Guard Check Error\n"));\r
674 break;\r
675 case 0x83:\r
676 DEBUG ((DEBUG_INFO, "End-to-end Application Tag Check Error\n"));\r
677 break;\r
678 case 0x84:\r
679 DEBUG ((DEBUG_INFO, "End-to-end Reference Tag Check Error\n"));\r
680 break;\r
681 case 0x85:\r
682 DEBUG ((DEBUG_INFO, "Compare Failure\n"));\r
683 break;\r
684 case 0x86:\r
685 DEBUG ((DEBUG_INFO, "Access Denied\n"));\r
686 break;\r
687 }\r
688 break;\r
689\r
690 default:\r
691 DEBUG ((DEBUG_INFO, "Unknown error\n"));\r
692 break;\r
693 }\r
694\r
695 return EFI_DEVICE_ERROR;\r
696}\r
697\r
698/**\r
699 Create PRP lists for Data transfer which is larger than 2 memory pages.\r
700 Note here we calcuate the number of required PRP lists and allocate them at one time.\r
701\r
702 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
703 @param[in] SqId - The SQ index for this PRP\r
704 @param[in] PhysicalAddr - The physical base address of Data Buffer.\r
705 @param[in] Pages - The number of pages to be transfered.\r
706 @param[out] PrpListHost - The host base address of PRP lists.\r
707 @param[in,out] PrpListNo - The number of PRP List.\r
708\r
709 @retval The pointer Value to the first PRP List of the PRP lists.\r
710\r
711**/\r
712STATIC\r
713UINT64\r
714NvmeCreatePrpList (\r
715 IN NVME_CONTEXT *Nvme,\r
716 IN UINT16 SqId,\r
717 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r
718 IN UINTN Pages,\r
719 OUT VOID **PrpListHost,\r
720 IN OUT UINTN *PrpListNo\r
721 )\r
722{\r
723 UINTN PrpEntryNo;\r
724 UINT64 PrpListBase;\r
725 UINTN PrpListIndex;\r
726 UINTN PrpEntryIndex;\r
727 UINT64 Remainder;\r
728 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r
729 UINTN Bytes;\r
730 UINT8 *PrpEntry;\r
731 EFI_PHYSICAL_ADDRESS NewPhyAddr;\r
732\r
733 ///\r
734 /// The number of Prp Entry in a memory page.\r
735 ///\r
736 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r
737\r
738 ///\r
739 /// Calculate total PrpList number.\r
740 ///\r
741 *PrpListNo = (UINTN) DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);\r
742 if (Remainder != 0) {\r
743 *PrpListNo += 1;\r
744 }\r
745\r
746 if (*PrpListNo > NVME_PRP_SIZE) {\r
747 DEBUG ((DEBUG_INFO, "NvmeCreatePrpList (PhysicalAddr: %lx, Pages: %x) PrpEntryNo: %x\n",\r
748 PhysicalAddr, Pages, PrpEntryNo));\r
749 DEBUG ((DEBUG_INFO, "*PrpListNo: %x, Remainder: %lx", *PrpListNo, Remainder));\r
750 ASSERT (FALSE);\r
751 }\r
752 *PrpListHost = (VOID *)(UINTN) NVME_PRP_BASE (Nvme, SqId);\r
753\r
754 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r
755 PrpListPhyAddr = (UINT64)(UINTN)(*PrpListHost);\r
756\r
757 ///\r
758 /// Fill all PRP lists except of last one.\r
759 ///\r
760 ZeroMem (*PrpListHost, Bytes);\r
761 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r
762 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
763\r
764 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r
765 PrpEntry = (UINT8 *)(UINTN) (PrpListBase + PrpEntryIndex * sizeof(UINT64));\r
766 if (PrpEntryIndex != PrpEntryNo - 1) {\r
767 ///\r
768 /// Fill all PRP entries except of last one.\r
769 ///\r
770 CopyMem (PrpEntry, (VOID *)(UINTN) (&PhysicalAddr), sizeof (UINT64));\r
771 PhysicalAddr += EFI_PAGE_SIZE;\r
772 } else {\r
773 ///\r
774 /// Fill last PRP entries with next PRP List pointer.\r
775 ///\r
776 NewPhyAddr = (PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE);\r
777 CopyMem (PrpEntry, (VOID *)(UINTN) (&NewPhyAddr), sizeof (UINT64));\r
778 }\r
779 }\r
780 }\r
781\r
782 ///\r
783 /// Fill last PRP list.\r
784 ///\r
785 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
786 for (PrpEntryIndex = 0; PrpEntryIndex < ((Remainder != 0) ? Remainder : PrpEntryNo); ++PrpEntryIndex) {\r
787 PrpEntry = (UINT8 *)(UINTN) (PrpListBase + PrpEntryIndex * sizeof(UINT64));\r
788 CopyMem (PrpEntry, (VOID *)(UINTN) (&PhysicalAddr), sizeof (UINT64));\r
789\r
790 PhysicalAddr += EFI_PAGE_SIZE;\r
791 }\r
792\r
793 return PrpListPhyAddr;\r
794}\r
795\r
796/**\r
797 Check whether there are available command slots.\r
798\r
799 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
800 @param[in] Qid - Queue index\r
801\r
802 @retval EFI_SUCCESS - Available command slot is found\r
803 @retval EFI_NOT_READY - No available command slot is found\r
804 @retval EFI_DEVICE_ERROR - Error occurred on device side.\r
805\r
806**/\r
807EFI_STATUS\r
808NvmeHasFreeCmdSlot (\r
809 IN NVME_CONTEXT *Nvme,\r
810 IN UINT8 Qid\r
811 )\r
812{\r
813 return TRUE;\r
814}\r
815\r
816/**\r
817 Check whether all command slots are clean.\r
818\r
819 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
820 @param[in] Qid - Queue index\r
821\r
822 @retval EFI_SUCCESS - All command slots are clean\r
823 @retval EFI_NOT_READY - Not all command slots are clean\r
824 @retval EFI_DEVICE_ERROR - Error occurred on device side.\r
825\r
826**/\r
827EFI_STATUS\r
828NvmeIsAllCmdSlotClean (\r
829 IN NVME_CONTEXT *Nvme,\r
830 IN UINT8 Qid\r
831 )\r
832{\r
833 return EFI_SUCCESS;\r
834}\r
835\r
836/**\r
837 Waits until all NVME commands completed.\r
838\r
839 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
840 @param[in] Qid - Queue index\r
841\r
842 @retval EFI_SUCCESS - All NVME commands have completed\r
843 @retval EFI_TIMEOUT - Timeout occured\r
844 @retval EFI_NOT_READY - Not all NVME commands have completed\r
845 @retval others - Error occurred on device side.\r
846**/\r
847EFI_STATUS\r
848NvmeWaitAllComplete (\r
849 IN NVME_CONTEXT *Nvme,\r
850 IN UINT8 Qid\r
851 )\r
852{\r
853 return EFI_SUCCESS;\r
854}\r
855\r
856/**\r
857 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
858 both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
859 I/O functionality is optional.\r
860\r
861 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
862 @param[in] NamespaceId - Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
863 A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
864 ID specifies that the command packet should be sent to all valid namespaces.\r
865 @param[in] NamespaceUuid - Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
866 A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace\r
867 UUID specifies that the command packet should be sent to all valid namespaces.\r
868 @param[in,out] Packet - A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
869 by NamespaceId.\r
870\r
871 @retval EFI_SUCCESS - The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
872 to, or from DataBuffer.\r
873 @retval EFI_NOT_READY - The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
874 may retry again later.\r
875 @retval EFI_DEVICE_ERROR - A device error occurred while attempting to send the NVM Express Command Packet.\r
876 @retval EFI_INVALID_PARAMETER - Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
877 Express Command Packet was not sent, so no additional status information is available.\r
878 @retval EFI_UNSUPPORTED - The command described by the NVM Express Command Packet is not supported by the host adapter.\r
879 The NVM Express Command Packet was not sent, so no additional status information is available.\r
880 @retval EFI_TIMEOUT - A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
881\r
882**/\r
883EFI_STATUS\r
884NvmePassThru (\r
885 IN NVME_CONTEXT *Nvme,\r
886 IN UINT32 NamespaceId,\r
887 IN UINT64 NamespaceUuid,\r
888 IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet\r
889 )\r
890{\r
891 EFI_STATUS Status;\r
892 NVME_SQ *Sq;\r
893 NVME_CQ *Cq;\r
894 UINT8 Qid;\r
895 UINT32 Bytes;\r
896 UINT32 Offset;\r
897 EFI_PHYSICAL_ADDRESS PhyAddr;\r
898 VOID *PrpListHost;\r
899 UINTN PrpListNo;\r
900 UINT32 Timer;\r
901 UINTN SqSize;\r
902 UINTN CqSize;\r
903\r
904 ///\r
905 /// check the Data fields in Packet parameter.\r
906 ///\r
907 if ((Nvme == NULL) || (Packet == NULL)) {\r
908 DEBUG ((DEBUG_ERROR, "NvmePassThru, invalid parameter: Nvme(%x)/Packet(%x)\n",\r
909 (UINTN)Nvme, (UINTN)Packet));\r
910 return EFI_INVALID_PARAMETER;\r
911 }\r
912\r
913 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeResponse == NULL)) {\r
914 DEBUG ((DEBUG_ERROR, "NvmePassThru, invalid parameter: NvmeCmd(%x)/NvmeResponse(%x)\n",\r
915 (UINTN)Packet->NvmeCmd, (UINTN)Packet->NvmeResponse));\r
916 return EFI_INVALID_PARAMETER;\r
917 }\r
918\r
919 if (Packet->QueueId != NVME_ADMIN_QUEUE && Packet->QueueId != NVME_IO_QUEUE) {\r
920 DEBUG ((DEBUG_ERROR, "NvmePassThru, invalid parameter: QueueId(%x)\n",\r
921 Packet->QueueId));\r
922 return EFI_INVALID_PARAMETER;\r
923 }\r
924\r
925 PrpListHost = NULL;\r
926 PrpListNo = 0;\r
927 Status = EFI_SUCCESS;\r
928\r
929 Qid = Packet->QueueId;\r
930 Sq = Nvme->SqBuffer[Qid] + Nvme->SqTdbl[Qid].Sqt;\r
931 Cq = Nvme->CqBuffer[Qid] + Nvme->CqHdbl[Qid].Cqh;\r
932 if (Qid == NVME_ADMIN_QUEUE) {\r
933 SqSize = NVME_ASQ_SIZE + 1;\r
934 CqSize = NVME_ACQ_SIZE + 1;\r
935 } else {\r
936 SqSize = NVME_CSQ_DEPTH;\r
937 CqSize = NVME_CCQ_DEPTH;\r
938 }\r
939\r
940 if (Packet->NvmeCmd->Nsid != NamespaceId) {\r
941 DEBUG ((DEBUG_ERROR, "NvmePassThru: Nsid mismatch (%x, %x)\n",\r
942 Packet->NvmeCmd->Nsid, NamespaceId));\r
943 return EFI_INVALID_PARAMETER;\r
944 }\r
945\r
946 ZeroMem (Sq, sizeof (NVME_SQ));\r
947 Sq->Opc = Packet->NvmeCmd->Cdw0.Opcode;\r
948 Sq->Fuse = Packet->NvmeCmd->Cdw0.FusedOperation;\r
949 Sq->Cid = Packet->NvmeCmd->Cdw0.Cid;\r
950 Sq->Nsid = Packet->NvmeCmd->Nsid;\r
951\r
952 ///\r
953 /// Currently we only support PRP for Data transfer, SGL is NOT supported.\r
954 ///\r
955 ASSERT (Sq->Psdt == 0);\r
956 if (Sq->Psdt != 0) {\r
957 DEBUG ((DEBUG_ERROR, "NvmePassThru: doesn't support SGL mechanism\n"));\r
958 return EFI_UNSUPPORTED;\r
959 }\r
960\r
961 Sq->Prp[0] = Packet->TransferBuffer;\r
962 Sq->Prp[1] = 0;\r
963\r
964 if(Packet->MetadataBuffer != (UINT64)(UINTN)NULL) {\r
965 Sq->Mptr = Packet->MetadataBuffer;\r
966 }\r
967\r
968 ///\r
969 /// If the Buffer Size spans more than two memory pages (page Size as defined in CC.Mps),\r
970 /// then build a PRP list in the second PRP submission queue entry.\r
971 ///\r
972 Offset = ((UINT32)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r
973 Bytes = Packet->TransferLength;\r
974\r
975 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r
976 ///\r
977 /// Create PrpList for remaining Data Buffer.\r
978 ///\r
979 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
980 Sq->Prp[1] = NvmeCreatePrpList (Nvme, Nvme->SqTdbl[Qid].Sqt, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo);\r
981 if (Sq->Prp[1] == 0) {\r
982 Status = EFI_OUT_OF_RESOURCES;\r
983 DEBUG ((DEBUG_ERROR, "NvmeCreatePrpList fail, Status: %r\n", Status));\r
984 goto EXIT;\r
985 }\r
986\r
987 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r
988 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
989 }\r
990\r
991 if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r
992 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r
993 }\r
994 if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r
995 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r
996 }\r
997 if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r
998 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r
999 }\r
1000 if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r
1001 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r
1002 }\r
1003 if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r
1004 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r
1005 }\r
1006 if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r
1007 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r
1008 }\r
1009\r
cb274a27
ED
1010 ///\r
1011 /// Ring the submission queue doorbell.\r
1012 ///\r
1013 Nvme->SqTdbl[Qid].Sqt++;\r
1014 if(Nvme->SqTdbl[Qid].Sqt == SqSize) {\r
1015 Nvme->SqTdbl[Qid].Sqt = 0;\r
1016 }\r
1017 Status = NVME_SET_SQTDBL (Nvme, Qid, &Nvme->SqTdbl[Qid]);\r
1018 if (EFI_ERROR(Status)) {\r
1019 DEBUG ((DEBUG_ERROR, "NVME_SET_SQTDBL fail, Status: %r\n", Status));\r
1020 goto EXIT;\r
1021 }\r
1022\r
1023 ///\r
1024 /// Wait for completion queue to get filled in.\r
1025 ///\r
1026 Status = EFI_TIMEOUT;\r
1027 Timer = 0;\r
1028 while (Timer < NVME_CMD_TIMEOUT) {\r
1029 //DEBUG ((DEBUG_VERBOSE, "Timer: %x, Cq:\n", Timer));\r
1030 //DumpMem (Cq, sizeof (NVME_CQ));\r
1031 if (Cq->Pt != Nvme->Pt[Qid]) {\r
1032 Status = EFI_SUCCESS;\r
1033 break;\r
1034 }\r
1035\r
1036 MicroSecondDelay (NVME_CMD_WAIT);\r
1037 Timer += NVME_CMD_WAIT;\r
1038 }\r
1039\r
1040 Nvme->CqHdbl[Qid].Cqh++;\r
1041 if (Nvme->CqHdbl[Qid].Cqh == CqSize) {\r
1042 Nvme->CqHdbl[Qid].Cqh = 0;\r
1043 Nvme->Pt[Qid] ^= 1;\r
1044 }\r
1045\r
1046 ///\r
1047 /// Copy the Respose Queue entry for this command to the callers response Buffer\r
1048 ///\r
1049 CopyMem (Packet->NvmeResponse, Cq, sizeof(NVM_EXPRESS_RESPONSE));\r
1050\r
1051 if (!EFI_ERROR(Status)) { // We still need to check CQ status if no timeout error occured\r
1052 Status = NvmeCheckCqStatus (Cq);\r
1053 }\r
1054 NVME_SET_CQHDBL (Nvme, Qid, &Nvme->CqHdbl[Qid]);\r
1055\r
1056EXIT:\r
1057 return Status;\r
1058}\r
1059\r
1060/**\r
1061 Get identify controller Data.\r
1062\r
1063 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1064 @param[in] Buffer - The Buffer used to store the identify controller Data.\r
1065\r
1066 @return EFI_SUCCESS - Successfully get the identify controller Data.\r
1067 @return others - Fail to get the identify controller Data.\r
1068\r
1069**/\r
1070STATIC\r
1071EFI_STATUS\r
1072NvmeIdentifyController (\r
1073 IN NVME_CONTEXT *Nvme,\r
1074 IN VOID *Buffer\r
1075 )\r
1076{\r
1077 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1078 NVM_EXPRESS_COMMAND Command;\r
1079 NVM_EXPRESS_RESPONSE Response;\r
1080 EFI_STATUS Status;\r
1081\r
1082 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1083 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1084 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1085\r
1086 Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_OPC;\r
1087 Command.Cdw0.Cid = Nvme->Cid[NVME_ADMIN_QUEUE]++;\r
1088 //\r
1089 // According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.\r
1090 // For the Identify command, the Namespace Identifier is only used for the Namespace Data structure.\r
1091 //\r
1092 Command.Nsid = 0;\r
1093\r
1094 CommandPacket.NvmeCmd = &Command;\r
1095 CommandPacket.NvmeResponse = &Response;\r
1096 CommandPacket.TransferBuffer = (UINT64)(UINTN)Buffer;\r
1097 CommandPacket.TransferLength = sizeof (NVME_ADMIN_CONTROLLER_DATA);\r
1098 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1099 CommandPacket.QueueId = NVME_ADMIN_QUEUE;\r
1100 //\r
1101 // Set bit 0 (Cns bit) to 1 to identify a controller\r
1102 //\r
1103 Command.Cdw10 = 1;\r
1104 Command.Flags = CDW10_VALID;\r
1105\r
1106 Status = NvmePassThru (\r
1107 Nvme,\r
1108 NVME_CONTROLLER_ID,\r
1109 0,\r
1110 &CommandPacket\r
1111 );\r
1112 if (!EFI_ERROR (Status)) {\r
1113 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
1114 }\r
1115\r
1116 return Status;\r
1117}\r
1118\r
1119/**\r
1120 Get specified identify namespace Data.\r
1121\r
1122 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1123 @param[in] NamespaceId - The specified namespace identifier.\r
1124 @param[in] Buffer - The Buffer used to store the identify namespace Data.\r
1125\r
1126 @return EFI_SUCCESS - Successfully get the identify namespace Data.\r
1127 @return others - Fail to get the identify namespace Data.\r
1128\r
1129**/\r
1130STATIC\r
1131EFI_STATUS\r
1132NvmeIdentifyNamespace (\r
1133 IN NVME_CONTEXT *Nvme,\r
1134 IN UINT32 NamespaceId,\r
1135 IN VOID *Buffer\r
1136 )\r
1137{\r
1138 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1139 NVM_EXPRESS_COMMAND Command;\r
1140 NVM_EXPRESS_RESPONSE Response;\r
1141 EFI_STATUS Status;\r
1142\r
1143 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1144 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1145 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1146\r
1147 CommandPacket.NvmeCmd = &Command;\r
1148 CommandPacket.NvmeResponse = &Response;\r
1149\r
1150 Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_OPC;\r
1151 Command.Cdw0.Cid = Nvme->Cid[NVME_ADMIN_QUEUE]++;\r
1152 Command.Nsid = NamespaceId;\r
1153 CommandPacket.TransferBuffer = (UINT64)(UINTN)Buffer;\r
1154 CommandPacket.TransferLength = sizeof (NVME_ADMIN_NAMESPACE_DATA);\r
1155 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1156 CommandPacket.QueueId = NVME_ADMIN_QUEUE;\r
1157 //\r
1158 // Set bit 0 (Cns bit) to 1 to identify a namespace\r
1159 //\r
1160 CommandPacket.NvmeCmd->Cdw10 = 0;\r
1161 CommandPacket.NvmeCmd->Flags = CDW10_VALID;\r
1162\r
1163 Status = NvmePassThru (\r
1164 Nvme,\r
1165 NamespaceId,\r
1166 0,\r
1167 &CommandPacket\r
1168 );\r
1169 if (!EFI_ERROR (Status)) {\r
1170 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
1171 }\r
1172\r
1173 return Status;\r
1174}\r
1175\r
1176/**\r
1177 Get Block Size for specific namespace of NVME.\r
1178\r
1179 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1180\r
1181 @return - Block Size in bytes\r
1182\r
1183**/\r
1184STATIC\r
1185UINT32\r
1186NvmeGetBlockSize (\r
1187 IN NVME_CONTEXT *Nvme\r
1188 )\r
1189{\r
1190 UINT32 BlockSize;\r
1191 UINT32 Lbads;\r
1192 UINT32 Flbas;\r
1193 UINT32 LbaFmtIdx;\r
1194\r
1195 Flbas = Nvme->NamespaceData->Flbas;\r
1196 LbaFmtIdx = Flbas & 3;\r
1197 Lbads = Nvme->NamespaceData->LbaFormat[LbaFmtIdx].Lbads;\r
1198\r
1199 BlockSize = (UINT32)1 << Lbads;\r
1200 return BlockSize;\r
1201}\r
1202\r
1203/**\r
1204 Get last LBA for specific namespace of NVME.\r
1205\r
1206 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1207\r
1208 @return - Last LBA address\r
1209\r
1210**/\r
1211STATIC\r
1212EFI_LBA\r
1213NvmeGetLastLba (\r
1214 IN NVME_CONTEXT *Nvme\r
1215 )\r
1216{\r
1217 EFI_LBA LastBlock;\r
1218 LastBlock = Nvme->NamespaceData->Nsze - 1;\r
1219 return LastBlock;\r
1220}\r
1221\r
1222/**\r
1223 Create io completion queue.\r
1224\r
1225 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1226\r
1227 @return EFI_SUCCESS - Successfully create io completion queue.\r
1228 @return others - Fail to create io completion queue.\r
1229\r
1230**/\r
1231STATIC\r
1232EFI_STATUS\r
1233NvmeCreateIoCompletionQueue (\r
1234 IN NVME_CONTEXT *Nvme\r
1235 )\r
1236{\r
1237 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1238 NVM_EXPRESS_COMMAND Command;\r
1239 NVM_EXPRESS_RESPONSE Response;\r
1240 EFI_STATUS Status;\r
1241 NVME_ADMIN_CRIOCQ CrIoCq;\r
1242\r
1243 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1244 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1245 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1246 ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));\r
1247\r
1248 CommandPacket.NvmeCmd = &Command;\r
1249 CommandPacket.NvmeResponse = &Response;\r
1250\r
1251 Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_OPC;\r
1252 Command.Cdw0.Cid = Nvme->Cid[NVME_ADMIN_QUEUE]++;\r
1253 CommandPacket.TransferBuffer = (UINT64)(UINTN)Nvme->CqBuffer[NVME_IO_QUEUE];\r
1254 CommandPacket.TransferLength = EFI_PAGE_SIZE;\r
1255 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1256 CommandPacket.QueueId = NVME_ADMIN_QUEUE;\r
1257\r
1258 CrIoCq.Qid = NVME_IO_QUEUE;\r
1259 CrIoCq.Qsize = NVME_CCQ_SIZE;\r
1260 CrIoCq.Pc = 1;\r
1261 CopyMem (&CommandPacket.NvmeCmd->Cdw10, &CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));\r
1262 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;\r
1263\r
1264 Status = NvmePassThru (\r
1265 Nvme,\r
1266 NVME_CONTROLLER_ID,\r
1267 0,\r
1268 &CommandPacket\r
1269 );\r
1270 if (!EFI_ERROR (Status)) {\r
1271 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
1272 }\r
1273\r
1274 return Status;\r
1275}\r
1276\r
1277/**\r
1278 Create io submission queue.\r
1279\r
1280 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1281\r
1282 @return EFI_SUCCESS - Successfully create io submission queue.\r
1283 @return others - Fail to create io submission queue.\r
1284\r
1285**/\r
1286STATIC\r
1287EFI_STATUS\r
1288NvmeCreateIoSubmissionQueue (\r
1289 IN NVME_CONTEXT *Nvme\r
1290 )\r
1291{\r
1292 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1293 NVM_EXPRESS_COMMAND Command;\r
1294 NVM_EXPRESS_RESPONSE Response;\r
1295 EFI_STATUS Status;\r
1296 NVME_ADMIN_CRIOSQ CrIoSq;\r
1297\r
1298 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1299 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1300 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1301 ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));\r
1302\r
1303 CommandPacket.NvmeCmd = &Command;\r
1304 CommandPacket.NvmeResponse = &Response;\r
1305\r
1306 Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_OPC;\r
1307 Command.Cdw0.Cid = Nvme->Cid[NVME_ADMIN_QUEUE]++;\r
1308 CommandPacket.TransferBuffer = (UINT64)(UINTN)Nvme->SqBuffer[NVME_IO_QUEUE];\r
1309 CommandPacket.TransferLength = EFI_PAGE_SIZE;\r
1310 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1311 CommandPacket.QueueId = NVME_ADMIN_QUEUE;\r
1312\r
1313 CrIoSq.Qid = NVME_IO_QUEUE;\r
1314 CrIoSq.Qsize = NVME_CSQ_SIZE;\r
1315 CrIoSq.Pc = 1;\r
1316 CrIoSq.Cqid = NVME_IO_QUEUE;\r
1317 CrIoSq.Qprio = 0;\r
1318 CopyMem (&CommandPacket.NvmeCmd->Cdw10, &CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));\r
1319 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;\r
1320\r
1321 Status = NvmePassThru (\r
1322 Nvme,\r
1323 NVME_CONTROLLER_ID,\r
1324 0,\r
1325 &CommandPacket\r
1326 );\r
1327 if (!EFI_ERROR (Status)) {\r
1328 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
1329 }\r
1330\r
1331 return Status;\r
1332}\r
1333\r
1334/**\r
1335 Security send and receive commands.\r
1336\r
1337 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1338 @param[in] SendCommand - The flag to indicate the command type, TRUE for Send command and FALSE for receive command\r
1339 @param[in] SecurityProtocol - Security Protocol\r
1340 @param[in] SpSpecific - Security Protocol Specific\r
1341 @param[in] TransferLength - Transfer Length of Buffer (in bytes) - always a multiple of 512\r
1342 @param[in,out] TransferBuffer - Address of Data to transfer\r
1343\r
1344 @return EFI_SUCCESS - Successfully create io submission queue.\r
1345 @return others - Fail to send/receive commands.\r
1346\r
1347**/\r
1348EFI_STATUS\r
1349NvmeSecuritySendReceive (\r
1350 IN NVME_CONTEXT *Nvme,\r
1351 IN BOOLEAN SendCommand,\r
1352 IN UINT8 SecurityProtocol,\r
1353 IN UINT16 SpSpecific,\r
1354 IN UINTN TransferLength,\r
1355 IN OUT VOID *TransferBuffer\r
1356 )\r
1357{\r
1358 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1359 NVM_EXPRESS_COMMAND Command;\r
1360 NVM_EXPRESS_RESPONSE Response;\r
1361 EFI_STATUS Status;\r
1362 NVME_ADMIN_SECSEND SecSend;\r
1363 OACS *Oacs;\r
1364 UINT8 Opcode;\r
1365 VOID* *SecBuff;\r
1366\r
1367 Oacs = (OACS *)&Nvme->ControllerData->Oacs;\r
1368\r
1369 //\r
1370 // Verify security bit for Security Send/Receive commands\r
1371 //\r
1372 if (Oacs->Security == 0) {\r
1373 DEBUG ((DEBUG_ERROR, "Security command doesn't support.\n"));\r
1374 return EFI_NOT_READY;\r
1375 }\r
1376\r
1377 SecBuff = (VOID *)(UINTN) NVME_SEC_BASE (Nvme);\r
1378\r
1379 //\r
1380 // Actions for sending security command\r
1381 //\r
1382 if (SendCommand) {\r
cb274a27
ED
1383 CopyMem (SecBuff, TransferBuffer, TransferLength);\r
1384 }\r
1385\r
1386 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1387 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1388 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1389 ZeroMem (&SecSend, sizeof(NVME_ADMIN_SECSEND));\r
1390\r
1391 CommandPacket.NvmeCmd = &Command;\r
1392 CommandPacket.NvmeResponse = &Response;\r
1393\r
1394 Opcode = (UINT8)(SendCommand ? NVME_ADMIN_SECURITY_SEND_OPC : NVME_ADMIN_SECURITY_RECV_OPC);\r
1395 Command.Cdw0.Opcode = Opcode;\r
1396 Command.Cdw0.Cid = Nvme->Cid[NVME_ADMIN_QUEUE]++;\r
1397 CommandPacket.TransferBuffer = (UINT64)(UINTN)SecBuff;\r
1398 CommandPacket.TransferLength = (UINT32)TransferLength;\r
1399 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1400 CommandPacket.QueueId = NVME_ADMIN_QUEUE;\r
1401\r
1402 SecSend.Spsp = SpSpecific;\r
1403 SecSend.Secp = SecurityProtocol;\r
1404 SecSend.Tl = (UINT32)TransferLength;\r
1405\r
1406 CopyMem (&CommandPacket.NvmeCmd->Cdw10, &SecSend, sizeof (NVME_ADMIN_SECSEND));\r
1407 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;\r
1408\r
1409 Status = NvmePassThru (\r
1410 Nvme,\r
1411 NVME_CONTROLLER_ID,\r
1412 0,\r
1413 &CommandPacket\r
1414 );\r
1415 if (!EFI_ERROR (Status)) {\r
1416 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
1417 }\r
1418\r
1419 //\r
1420 // Actions for receiving security command\r
1421 //\r
1422 if (!SendCommand) {\r
1423 CopyMem (TransferBuffer, SecBuff, TransferLength);\r
cb274a27
ED
1424 }\r
1425\r
1426 return Status;\r
1427}\r
1428\r
1429/**\r
1430 Destroy io completion queue.\r
1431\r
1432 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1433\r
1434 @return EFI_SUCCESS - Successfully destroy io completion queue.\r
1435 @return others - Fail to destroy io completion queue.\r
1436\r
1437**/\r
1438STATIC\r
1439EFI_STATUS\r
1440NvmeDestroyIoCompletionQueue (\r
1441 IN NVME_CONTEXT *Nvme\r
1442 )\r
1443{\r
1444 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1445 NVM_EXPRESS_COMMAND Command;\r
1446 NVM_EXPRESS_RESPONSE Response;\r
1447 EFI_STATUS Status;\r
1448 NVME_ADMIN_DEIOCQ DelIoCq;\r
1449\r
1450 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1451 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1452 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1453 ZeroMem (&DelIoCq, sizeof(NVME_ADMIN_DEIOCQ));\r
1454\r
1455 CommandPacket.NvmeCmd = &Command;\r
1456 CommandPacket.NvmeResponse = &Response;\r
1457\r
1458 Command.Cdw0.Opcode = NVME_ADMIN_DELIOCQ_OPC;\r
1459 Command.Cdw0.Cid = Nvme->Cid[NVME_ADMIN_QUEUE]++;\r
1460 CommandPacket.TransferBuffer = (UINT64)(UINTN)Nvme->CqBuffer[NVME_IO_QUEUE];\r
1461 CommandPacket.TransferLength = EFI_PAGE_SIZE;\r
1462 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1463 CommandPacket.QueueId = NVME_ADMIN_QUEUE;\r
1464\r
1465 DelIoCq.Qid = NVME_IO_QUEUE;\r
1466 CopyMem (&CommandPacket.NvmeCmd->Cdw10, &DelIoCq, sizeof (NVME_ADMIN_DEIOCQ));\r
1467 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;\r
1468\r
1469 Status = NvmePassThru (\r
1470 Nvme,\r
1471 NVME_CONTROLLER_ID,\r
1472 0,\r
1473 &CommandPacket\r
1474 );\r
1475 if (!EFI_ERROR (Status)) {\r
1476 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
1477 }\r
1478\r
1479 return Status;\r
1480}\r
1481\r
1482/**\r
1483 Destroy io submission queue.\r
1484\r
1485 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1486\r
1487 @return EFI_SUCCESS - Successfully destroy io submission queue.\r
1488 @return others - Fail to destroy io submission queue.\r
1489\r
1490**/\r
1491STATIC\r
1492EFI_STATUS\r
1493NvmeDestroyIoSubmissionQueue (\r
1494 IN NVME_CONTEXT *Nvme\r
1495 )\r
1496{\r
1497 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1498 NVM_EXPRESS_COMMAND Command;\r
1499 NVM_EXPRESS_RESPONSE Response;\r
1500 EFI_STATUS Status;\r
1501 NVME_ADMIN_DEIOSQ DelIoSq;\r
1502\r
1503 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1504 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1505 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1506 ZeroMem (&DelIoSq, sizeof(NVME_ADMIN_DEIOSQ));\r
1507\r
1508 CommandPacket.NvmeCmd = &Command;\r
1509 CommandPacket.NvmeResponse = &Response;\r
1510\r
1511 Command.Cdw0.Opcode = NVME_ADMIN_DELIOSQ_OPC;\r
1512 Command.Cdw0.Cid = Nvme->Cid[NVME_ADMIN_QUEUE]++;\r
1513 CommandPacket.TransferBuffer = (UINT64)(UINTN)Nvme->SqBuffer[NVME_IO_QUEUE];\r
1514 CommandPacket.TransferLength = EFI_PAGE_SIZE;\r
1515 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1516 CommandPacket.QueueId = NVME_ADMIN_QUEUE;\r
1517\r
1518 DelIoSq.Qid = NVME_IO_QUEUE;\r
1519 CopyMem (&CommandPacket.NvmeCmd->Cdw10, &DelIoSq, sizeof (NVME_ADMIN_DEIOSQ));\r
1520 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;\r
1521\r
1522 Status = NvmePassThru (\r
1523 Nvme,\r
1524 NVME_CONTROLLER_ID,\r
1525 0,\r
1526 &CommandPacket\r
1527 );\r
1528 if (!EFI_ERROR (Status)) {\r
1529 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
1530 }\r
1531\r
1532 return Status;\r
1533}\r
1534\r
1535/**\r
1536 Allocate transfer-related Data struct which is used at Nvme.\r
1537\r
1538 @param[in] ImageHandle Image handle for this driver image\r
1539 @param[in] Nvme The pointer to the NVME_CONTEXT Data structure.\r
1540\r
1541 @retval EFI_OUT_OF_RESOURCE The allocation is failure.\r
1542 @retval EFI_SUCCESS Successful to allocate memory.\r
1543\r
1544**/\r
1545EFI_STATUS\r
1546EFIAPI\r
1547NvmeAllocateResource (\r
1548 IN EFI_HANDLE ImageHandle,\r
1549 IN NVME_CONTEXT *Nvme\r
1550 )\r
1551{\r
1552 EFI_STATUS Status;\r
1553 EFI_PHYSICAL_ADDRESS Addr;\r
1554 UINT32 Size;\r
1555\r
1556 //\r
1557 // Allocate resources required by NVMe host controller.\r
1558 //\r
1559 // NBAR\r
1560 Size = 0x10000;\r
1561 Addr = 0xFFFFFFFF;\r
1562 Status = gDS->AllocateMemorySpace (\r
1563 EfiGcdAllocateMaxAddressSearchBottomUp,\r
1564 EfiGcdMemoryTypeMemoryMappedIo,\r
1565 15, // 2^15: 32K Alignment\r
1566 Size,\r
1567 &Addr,\r
1568 ImageHandle,\r
1569 NULL\r
1570 );\r
1571 if (EFI_ERROR (Status)) {\r
1572 return EFI_OUT_OF_RESOURCES;\r
1573 }\r
1574 Nvme->Nbar = (UINT32) Addr;\r
1575\r
1576 // DMA Buffer\r
1577 Size = NVME_MEM_MAX_SIZE;\r
1578 Addr = 0xFFFFFFFF;\r
1579 Status = gBS->AllocatePages (\r
1580 AllocateMaxAddress,\r
1581 EfiACPIMemoryNVS,\r
1582 EFI_SIZE_TO_PAGES (Size),\r
1583 (EFI_PHYSICAL_ADDRESS *)&Addr\r
1584 );\r
1585 if (EFI_ERROR (Status)) {\r
1586 return EFI_OUT_OF_RESOURCES;\r
1587 }\r
1588 Nvme->BaseMem = (UINT32) Addr;\r
1589\r
1590 // Clean up DMA Buffer before using\r
1591 ZeroMem ((VOID *)(UINTN)Addr, NVME_MEM_MAX_SIZE);\r
1592\r
1593 return EFI_SUCCESS;\r
1594}\r
1595\r
1596/**\r
1597 Free allocated transfer-related Data struct which is used at NVMe.\r
1598\r
1599 @param[in] Nvme The pointer to the NVME_CONTEXT Data structure.\r
1600\r
1601**/\r
1602VOID\r
1603EFIAPI\r
1604NvmeFreeResource (\r
1605 IN NVME_CONTEXT *Nvme\r
1606 )\r
1607{\r
1608 UINT32 Size;\r
1609\r
1610 // NBAR\r
1611 if (Nvme->BaseMem != 0) {\r
1612 Size = 0x10000;\r
1613 gDS->FreeMemorySpace (Nvme->Nbar, Size);\r
1614 }\r
1615\r
1616 // DMA Buffer\r
1617 if (Nvme->Nbar != 0) {\r
1618 Size = NVME_MEM_MAX_SIZE;\r
1619 gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN) Nvme->Nbar, EFI_SIZE_TO_PAGES (Size));\r
1620 }\r
1621}\r
1622\r
1623\r
1624/**\r
1625 Initialize the Nvm Express controller.\r
1626\r
1627 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1628\r
1629 @retval EFI_SUCCESS - The NVM Express Controller is initialized successfully.\r
1630 @retval Others - A device error occurred while initializing the controller.\r
1631\r
1632**/\r
1633EFI_STATUS\r
1634NvmeControllerInit (\r
1635 IN NVME_CONTEXT *Nvme\r
1636 )\r
1637{\r
1638 EFI_STATUS Status;\r
1639 NVME_AQA Aqa;\r
1640 NVME_ASQ Asq;\r
1641 NVME_ACQ Acq;\r
1642 NVME_VER Ver;\r
1643\r
1644 UINT32 MlBAR;\r
1645 UINT32 MuBAR;\r
1646\r
1647 ///\r
1648 /// Update PCIE BAR0/1 for NVME device\r
1649 ///\r
1650 MlBAR = Nvme->Nbar;\r
1651 MuBAR = 0;\r
1652 PciWrite32 (Nvme->PciBase + 0x10, MlBAR); // MLBAR (BAR0)\r
1653 PciWrite32 (Nvme->PciBase + 0x14, MuBAR); // MUBAR (BAR1)\r
1654\r
1655 ///\r
1656 /// Enable PCIE decode\r
1657 ///\r
1658 PciWrite8 (Nvme->PciBase + NVME_PCIE_PCICMD, 0x6);\r
1659\r
1660 // Version\r
1661 NVME_GET_VER (Nvme, &Ver);\r
1662 if (!(Ver.Mjr == 0x0001) && (Ver.Mnr == 0x0000)) {\r
1663 DEBUG ((DEBUG_INFO, "\n!!!\n!!! NVME Version mismatch for the implementation !!!\n!!!\n"));\r
1664 }\r
1665\r
1666 ///\r
1667 /// Read the Controller Capabilities register and verify that the NVM command set is supported\r
1668 ///\r
1669 Status = NVME_GET_CAP (Nvme, &Nvme->Cap);\r
1670 if (EFI_ERROR (Status)) {\r
1671 DEBUG ((DEBUG_ERROR, "NVME_GET_CAP fail, Status: %r\n", Status));\r
1672 goto Done;\r
1673 }\r
1674\r
1675 if (Nvme->Cap.Css != 0x01) {\r
1676 DEBUG ((DEBUG_ERROR, "NvmeControllerInit fail: the controller doesn't support NVMe command set\n"));\r
1677 Status = EFI_UNSUPPORTED;\r
1678 goto Done;\r
1679 }\r
1680\r
1681 ///\r
1682 /// Currently the driver only supports 4k page Size.\r
1683 ///\r
1684 if ((Nvme->Cap.Mpsmin + 12) > EFI_PAGE_SHIFT) {\r
1685 DEBUG ((DEBUG_ERROR, "NvmeControllerInit fail: only supports 4k page Size\n"));\r
1686 ASSERT (FALSE);\r
1687 Status = EFI_UNSUPPORTED;\r
1688 goto Done;\r
1689 }\r
1690\r
1691 Nvme->Cid[0] = 0;\r
1692 Nvme->Cid[1] = 0;\r
1693\r
0acd8df4
ED
1694 Nvme->Pt[0] = 0;\r
1695 Nvme->Pt[1] = 0;\r
1696\r
1697 ZeroMem ((VOID *)(UINTN)(&(Nvme->SqTdbl[0])), sizeof (NVME_SQTDBL) * NVME_MAX_IO_QUEUES);\r
1698 ZeroMem ((VOID *)(UINTN)(&(Nvme->CqHdbl[0])), sizeof (NVME_CQHDBL) * NVME_MAX_IO_QUEUES);\r
1699\r
1700 ZeroMem ((VOID *)(UINTN)Nvme->BaseMem, NVME_MEM_MAX_SIZE);\r
1701\r
cb274a27
ED
1702 Status = NvmeDisableController (Nvme);\r
1703 if (EFI_ERROR(Status)) {\r
1704 DEBUG ((DEBUG_ERROR, "NvmeDisableController fail, Status: %r\n", Status));\r
1705 goto Done;\r
1706 }\r
1707\r
1708 ///\r
1709 /// set number of entries admin submission & completion queues.\r
1710 ///\r
1711 Aqa.Asqs = NVME_ASQ_SIZE;\r
1712 Aqa.Rsvd1 = 0;\r
1713 Aqa.Acqs = NVME_ACQ_SIZE;\r
1714 Aqa.Rsvd2 = 0;\r
1715\r
1716 ///\r
1717 /// Address of admin submission queue.\r
1718 ///\r
1719 Asq = (UINT64)(UINTN)(NVME_ASQ_BASE (Nvme) & ~0xFFF);\r
1720\r
1721 ///\r
1722 /// Address of admin completion queue.\r
1723 ///\r
1724 Acq = (UINT64)(UINTN)(NVME_ACQ_BASE (Nvme) & ~0xFFF);\r
1725\r
1726 ///\r
1727 /// Address of I/O submission & completion queue.\r
1728 ///\r
1729 Nvme->SqBuffer[0] = (NVME_SQ *)(UINTN)NVME_ASQ_BASE (Nvme); // NVME_ADMIN_QUEUE\r
1730 Nvme->CqBuffer[0] = (NVME_CQ *)(UINTN)NVME_ACQ_BASE (Nvme); // NVME_ADMIN_QUEUE\r
1731 Nvme->SqBuffer[1] = (NVME_SQ *)(UINTN)NVME_SQ_BASE (Nvme, 0); // NVME_IO_QUEUE\r
1732 Nvme->CqBuffer[1] = (NVME_CQ *)(UINTN)NVME_CQ_BASE (Nvme, 0); // NVME_IO_QUEUE\r
1733\r
1734 DEBUG ((DEBUG_INFO, "BaseMem = [%08X]\n", Nvme->BaseMem));\r
1735 DEBUG ((DEBUG_INFO, "Admin Submission Queue Size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));\r
1736 DEBUG ((DEBUG_INFO, "Admin Completion Queue Size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));\r
1737 DEBUG ((DEBUG_INFO, "Admin Submission Queue (SqBuffer[0]) = [%08X]\n", Nvme->SqBuffer[0]));\r
1738 DEBUG ((DEBUG_INFO, "Admin Completion Queue (CqBuffer[0]) = [%08X]\n", Nvme->CqBuffer[0]));\r
1739 DEBUG ((DEBUG_INFO, "I/O Submission Queue (SqBuffer[1]) = [%08X]\n", Nvme->SqBuffer[1]));\r
1740 DEBUG ((DEBUG_INFO, "I/O Completion Queue (CqBuffer[1]) = [%08X]\n", Nvme->CqBuffer[1]));\r
1741\r
1742 ///\r
1743 /// Program admin queue attributes.\r
1744 ///\r
1745 Status = NVME_SET_AQA (Nvme, &Aqa);\r
1746 if (EFI_ERROR(Status)) {\r
1747 goto Done;\r
1748 }\r
1749\r
1750 ///\r
1751 /// Program admin submission queue address.\r
1752 ///\r
1753 Status = NVME_SET_ASQ (Nvme, &Asq);\r
1754 if (EFI_ERROR(Status)) {\r
1755 goto Done;\r
1756 }\r
1757\r
1758 ///\r
1759 /// Program admin completion queue address.\r
1760 ///\r
1761 Status = NVME_SET_ACQ (Nvme, &Acq);\r
1762 if (EFI_ERROR(Status)) {\r
1763 goto Done;\r
1764 }\r
1765\r
1766 Status = NvmeEnableController (Nvme);\r
1767 if (EFI_ERROR(Status)) {\r
1768 goto Done;\r
1769 }\r
1770\r
1771 ///\r
1772 /// Create one I/O completion queue.\r
1773 ///\r
1774 Status = NvmeCreateIoCompletionQueue (Nvme);\r
1775 if (EFI_ERROR(Status)) {\r
1776 goto Done;\r
1777 }\r
1778\r
1779 ///\r
1780 /// Create one I/O Submission queue.\r
1781 ///\r
1782 Status = NvmeCreateIoSubmissionQueue (Nvme);\r
1783 if (EFI_ERROR(Status)) {\r
1784 goto Done;\r
1785 }\r
1786\r
1787 ///\r
1788 /// Get current Identify Controller Data\r
1789 ///\r
1790 Nvme->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)(UINTN) NVME_CONTROL_DATA_BASE (Nvme);\r
1791 Status = NvmeIdentifyController (Nvme, Nvme->ControllerData);\r
1792 if (EFI_ERROR(Status)) {\r
1793 goto Done;\r
1794 }\r
1795\r
1796 ///\r
1797 /// Dump NvmExpress Identify Controller Data\r
1798 ///\r
1799 Nvme->ControllerData->Sn[19] = 0;\r
1800 Nvme->ControllerData->Mn[39] = 0;\r
1801 //NvmeDumpIdentifyController (Nvme->ControllerData);\r
1802\r
1803 ///\r
1804 /// Get current Identify Namespace Data\r
1805 ///\r
1806 Nvme->NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)NVME_NAMESPACE_DATA_BASE (Nvme);\r
1807 Status = NvmeIdentifyNamespace (Nvme, Nvme->Nsid, Nvme->NamespaceData);\r
1808 if (EFI_ERROR(Status)) {\r
1809 DEBUG ((DEBUG_ERROR, "NvmeIdentifyNamespace fail, Status = %r\n", Status));\r
1810 goto Done;\r
1811 }\r
1812\r
1813 ///\r
1814 /// Dump NvmExpress Identify Namespace Data\r
1815 ///\r
1816 if (Nvme->NamespaceData->Ncap == 0) {\r
1817 DEBUG ((DEBUG_ERROR, "Invalid Namespace, Ncap: %lx\n", Nvme->NamespaceData->Ncap));\r
1818 Status = EFI_DEVICE_ERROR;\r
1819 goto Done;\r
1820 }\r
1821\r
1822 Nvme->BlockSize = NvmeGetBlockSize (Nvme);\r
1823 Nvme->LastBlock = NvmeGetLastLba (Nvme);\r
1824\r
1825 Nvme->State = NvmeStatusInit;\r
1826\r
1827 return EFI_SUCCESS;\r
1828\r
1829Done:\r
1830 return Status;\r
1831}\r
1832\r
1833/**\r
1834 Un-initialize the Nvm Express controller.\r
1835\r
1836 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1837\r
1838 @retval EFI_SUCCESS - The NVM Express Controller is un-initialized successfully.\r
1839 @retval Others - A device error occurred while un-initializing the controller.\r
1840\r
1841**/\r
1842EFI_STATUS\r
1843NvmeControllerExit (\r
1844 IN NVME_CONTEXT *Nvme\r
1845 )\r
1846{\r
1847 EFI_STATUS Status;\r
1848\r
1849 Status = EFI_SUCCESS;\r
1850 if (Nvme->State == NvmeStatusInit || Nvme->State == NvmeStatusMax) {\r
1851 ///\r
1852 /// Destroy I/O Submission queue.\r
1853 ///\r
1854 Status = NvmeDestroyIoSubmissionQueue (Nvme);\r
1855 if (EFI_ERROR(Status)) {\r
1856 DEBUG ((DEBUG_ERROR, "NvmeDestroyIoSubmissionQueue fail, Status = %r\n", Status));\r
1857 return Status;\r
1858 }\r
1859\r
1860 ///\r
1861 /// Destroy I/O completion queue.\r
1862 ///\r
1863 Status = NvmeDestroyIoCompletionQueue (Nvme);\r
1864 if (EFI_ERROR(Status)) {\r
1865 DEBUG ((DEBUG_ERROR, "NvmeDestroyIoCompletionQueue fail, Status = %r\n", Status));\r
1866 return Status;\r
1867 }\r
1868\r
1869 Status = NvmeShutdownController (Nvme);\r
1870 if (EFI_ERROR(Status)) {\r
1871 DEBUG ((DEBUG_ERROR, "NvmeShutdownController fail, Status: %r\n", Status));\r
1872 }\r
1873 }\r
1874\r
1875 ///\r
1876 /// Disable PCIE decode\r
1877 ///\r
1878 PciWrite8 (Nvme->PciBase + NVME_PCIE_PCICMD, 0x0);\r
1879 PciWrite32 (Nvme->PciBase + 0x10, 0); // MLBAR (BAR0)\r
1880 PciWrite32 (Nvme->PciBase + 0x14, 0); // MUBAR (BAR1)\r
1881\r
1882 Nvme->State = NvmeStatusUnknown;\r
1883 return Status;\r
1884}\r
1885\r
1886/**\r
1887 Read sector Data from the NVMe device.\r
1888\r
1889 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1890 @param[in,out] Buffer - The Buffer used to store the Data read from the device.\r
1891 @param[in] Lba - The start block number.\r
1892 @param[in] Blocks - Total block number to be read.\r
1893\r
1894 @retval EFI_SUCCESS - Datum are read from the device.\r
1895 @retval Others - Fail to read all the datum.\r
1896\r
1897**/\r
1898EFI_STATUS\r
1899NvmeReadSectors (\r
1900 IN NVME_CONTEXT *Nvme,\r
1901 IN OUT UINT64 Buffer,\r
1902 IN UINT64 Lba,\r
1903 IN UINT32 Blocks\r
1904 )\r
1905{\r
1906 UINT32 Bytes;\r
1907 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1908 NVM_EXPRESS_COMMAND Command;\r
1909 NVM_EXPRESS_RESPONSE Response;\r
1910 EFI_STATUS Status;\r
1911 UINT32 BlockSize;\r
1912\r
1913 BlockSize = Nvme->BlockSize;\r
1914 Bytes = Blocks * BlockSize;\r
1915\r
1916 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1917 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1918 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1919\r
1920 CommandPacket.NvmeCmd = &Command;\r
1921 CommandPacket.NvmeResponse = &Response;\r
1922\r
1923 CommandPacket.NvmeCmd->Cdw0.Opcode = NVME_IO_READ_OPC;\r
1924 CommandPacket.NvmeCmd->Cdw0.Cid = Nvme->Cid[NVME_IO_QUEUE]++;\r
1925 CommandPacket.NvmeCmd->Nsid = Nvme->Nsid;\r
1926 CommandPacket.TransferBuffer = Buffer;\r
1927\r
1928 CommandPacket.TransferLength = Bytes;\r
1929 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1930 CommandPacket.QueueId = NVME_IO_QUEUE;\r
1931\r
1932 CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;\r
1933 CommandPacket.NvmeCmd->Cdw11 = (UINT32)(RShiftU64 (Lba, 32));\r
1934 CommandPacket.NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;\r
1935\r
1936 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID | CDW12_VALID;\r
1937\r
1938 Status = NvmePassThru (\r
1939 Nvme,\r
1940 Nvme->Nsid,\r
1941 0,\r
1942 &CommandPacket\r
1943 );\r
1944\r
1945 return Status;\r
1946}\r
1947\r
1948/**\r
1949 Write sector Data to the NVMe device.\r
1950\r
1951 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
1952 @param[in] Buffer - The Buffer to be written into the device.\r
1953 @param[in] Lba - The start block number.\r
1954 @param[in] Blocks - Total block number to be written.\r
1955\r
1956 @retval EFI_SUCCESS - Datum are written into the Buffer.\r
1957 @retval Others - Fail to write all the datum.\r
1958\r
1959**/\r
1960EFI_STATUS\r
1961NvmeWriteSectors (\r
1962 IN NVME_CONTEXT *Nvme,\r
1963 IN UINT64 Buffer,\r
1964 IN UINT64 Lba,\r
1965 IN UINT32 Blocks\r
1966 )\r
1967{\r
1968 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
1969 NVM_EXPRESS_COMMAND Command;\r
1970 NVM_EXPRESS_RESPONSE Response;\r
1971 EFI_STATUS Status;\r
1972 UINT32 Bytes;\r
1973 UINT32 BlockSize;\r
1974\r
1975 BlockSize = Nvme->BlockSize;\r
1976 Bytes = Blocks * BlockSize;\r
1977\r
1978 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
1979 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
1980 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
1981\r
1982 CommandPacket.NvmeCmd = &Command;\r
1983 CommandPacket.NvmeResponse = &Response;\r
1984\r
1985 CommandPacket.NvmeCmd->Cdw0.Opcode = NVME_IO_WRITE_OPC;\r
1986 CommandPacket.NvmeCmd->Cdw0.Cid = Nvme->Cid[NVME_IO_QUEUE]++;\r
1987 CommandPacket.NvmeCmd->Nsid = Nvme->Nsid;\r
1988 CommandPacket.TransferBuffer = Buffer;\r
1989\r
1990 CommandPacket.TransferLength = Bytes;\r
1991 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
1992 CommandPacket.QueueId = NVME_IO_QUEUE;\r
1993\r
1994 CommandPacket.NvmeCmd->Cdw10 = (UINT32)Lba;\r
1995 CommandPacket.NvmeCmd->Cdw11 = (UINT32)(RShiftU64 (Lba, 32));\r
1996 CommandPacket.NvmeCmd->Cdw12 = (Blocks - 1) & 0xFFFF;\r
1997\r
1998 CommandPacket.MetadataBuffer = (UINT64)(UINTN)NULL;\r
1999 CommandPacket.MetadataLength = 0;\r
2000\r
2001 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID | CDW12_VALID;\r
2002\r
2003 Status = NvmePassThru (\r
2004 Nvme,\r
2005 Nvme->Nsid,\r
2006 0,\r
2007 &CommandPacket\r
2008 );\r
2009\r
2010 return Status;\r
2011}\r
2012\r
2013/**\r
2014 Flushes all modified Data to the device.\r
2015\r
2016 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
2017\r
2018 @retval EFI_SUCCESS - Datum are written into the Buffer.\r
2019 @retval Others - Fail to write all the datum.\r
2020\r
2021**/\r
2022EFI_STATUS\r
2023NvmeFlush (\r
2024 IN NVME_CONTEXT *Nvme\r
2025 )\r
2026{\r
2027 NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;\r
2028 NVM_EXPRESS_COMMAND Command;\r
2029 NVM_EXPRESS_RESPONSE Response;\r
2030 EFI_STATUS Status;\r
2031\r
2032 ZeroMem (&CommandPacket, sizeof(NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));\r
2033 ZeroMem (&Command, sizeof(NVM_EXPRESS_COMMAND));\r
2034 ZeroMem (&Response, sizeof(NVM_EXPRESS_RESPONSE));\r
2035\r
2036 CommandPacket.NvmeCmd = &Command;\r
2037 CommandPacket.NvmeResponse = &Response;\r
2038\r
2039 CommandPacket.NvmeCmd->Cdw0.Opcode = NVME_IO_FLUSH_OPC;\r
2040 CommandPacket.NvmeCmd->Cdw0.Cid = Nvme->Cid[NVME_IO_QUEUE]++;\r
2041 CommandPacket.NvmeCmd->Nsid = Nvme->Nsid;\r
2042 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;\r
2043 CommandPacket.QueueId = NVME_IO_QUEUE;\r
2044\r
2045 Status = NvmePassThru (\r
2046 Nvme,\r
2047 Nvme->Nsid,\r
2048 0,\r
2049 &CommandPacket\r
2050 );\r
2051 if (!EFI_ERROR (Status)) {\r
2052 Status = NvmeWaitAllComplete (Nvme, CommandPacket.QueueId);\r
2053 }\r
2054\r
2055 return Status;\r
2056}\r
2057\r
2058/**\r
2059 Read some blocks from the device.\r
2060\r
2061 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
2062 @param[out] Buffer - The Buffer used to store the Data read from the device.\r
2063 @param[in] Lba - The start block number.\r
2064 @param[in] Blocks - Total block number to be read.\r
2065\r
2066 @retval EFI_SUCCESS - Datum are read from the device.\r
2067 @retval Others - Fail to read all the datum.\r
2068\r
2069**/\r
2070EFI_STATUS\r
2071NvmeRead (\r
2072 IN NVME_CONTEXT *Nvme,\r
2073 OUT UINT64 Buffer,\r
2074 IN UINT64 Lba,\r
2075 IN UINTN Blocks\r
2076 )\r
2077{\r
2078 EFI_STATUS Status;\r
2079 UINT32 BlockSize;\r
2080 UINT32 MaxTransferBlocks;\r
2081\r
2082 ASSERT (Blocks <= NVME_MAX_SECTORS);\r
2083 Status = EFI_SUCCESS;\r
2084 BlockSize = Nvme->BlockSize;\r
2085 if (Nvme->ControllerData->Mdts != 0) {\r
2086 MaxTransferBlocks = (1 << (Nvme->ControllerData->Mdts)) * (1 << (Nvme->Cap.Mpsmin + 12)) / BlockSize;\r
2087 } else {\r
2088 MaxTransferBlocks = 1024;\r
2089 }\r
2090\r
2091 while (Blocks > 0) {\r
2092 if (Blocks > MaxTransferBlocks) {\r
2093 Status = NvmeReadSectors (Nvme, Buffer, Lba, MaxTransferBlocks);\r
2094\r
2095 Blocks -= MaxTransferBlocks;\r
2096 Buffer += (MaxTransferBlocks * BlockSize);\r
2097 Lba += MaxTransferBlocks;\r
2098 } else {\r
2099 Status = NvmeReadSectors (Nvme, Buffer, Lba, (UINT32) Blocks);\r
2100 Blocks = 0;\r
2101 }\r
2102\r
2103 if (EFI_ERROR(Status)) {\r
2104 DEBUG ((DEBUG_ERROR, "NvmeRead fail, Status = %r\n", Status));\r
2105 break;\r
2106 }\r
2107 }\r
2108\r
2109 return Status;\r
2110}\r
2111\r
2112/**\r
2113 Write some blocks to the device.\r
2114\r
2115 @param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.\r
2116 @param[in] Buffer - The Buffer to be written into the device.\r
2117 @param[in] Lba - The start block number.\r
2118 @param[in] Blocks - Total block number to be written.\r
2119\r
2120 @retval EFI_SUCCESS - Datum are written into the Buffer.\r
2121 @retval Others - Fail to write all the datum.\r
2122\r
2123**/\r
2124EFI_STATUS\r
2125NvmeWrite (\r
2126 IN NVME_CONTEXT *Nvme,\r
2127 IN UINT64 Buffer,\r
2128 IN UINT64 Lba,\r
2129 IN UINTN Blocks\r
2130 )\r
2131{\r
2132 EFI_STATUS Status;\r
2133 UINT32 BlockSize;\r
2134 UINT32 MaxTransferBlocks;\r
2135\r
2136 ASSERT (Blocks <= NVME_MAX_SECTORS);\r
2137 Status = EFI_SUCCESS;\r
2138 BlockSize = Nvme->BlockSize;\r
2139\r
2140 if (Nvme->ControllerData->Mdts != 0) {\r
2141 MaxTransferBlocks = (1 << (Nvme->ControllerData->Mdts)) * (1 << (Nvme->Cap.Mpsmin + 12)) / BlockSize;\r
2142 } else {\r
2143 MaxTransferBlocks = 1024;\r
2144 }\r
2145\r
2146 while (Blocks > 0) {\r
2147 if (Blocks > MaxTransferBlocks) {\r
2148 Status = NvmeWriteSectors (Nvme, Buffer, Lba, MaxTransferBlocks);\r
2149\r
2150 Blocks -= MaxTransferBlocks;\r
2151 Buffer += (MaxTransferBlocks * BlockSize);\r
2152 Lba += MaxTransferBlocks;\r
2153 } else {\r
2154 Status = NvmeWriteSectors (Nvme, Buffer, Lba, (UINT32) Blocks);\r
2155 Blocks = 0;\r
2156 }\r
2157\r
2158 if (EFI_ERROR(Status)) {\r
2159 DEBUG ((DEBUG_ERROR, "NvmeWrite fail, Status = %r\n", Status));\r
2160 break;\r
2161 }\r
2162 }\r
2163\r
2164 return Status;\r
2165}\r