projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1abfa4ce JY |
1 | /** @file\r |
| 2 | Header file for NV data structure definition.\r | |
| 3 | \r | |
| b3548d32 | 4 | Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 289b714b | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 1abfa4ce JY |
6 | \r |
| 7 | **/\r | |
| 8 | \r | |
| 9 | #ifndef __TCG2_CONFIG_NV_DATA_H__\r | |
| 10 | #define __TCG2_CONFIG_NV_DATA_H__\r | |
| 11 | \r | |
| 12 | #include <Guid/HiiPlatformSetupFormset.h>\r | |
| 13 | #include <Guid/Tcg2ConfigHii.h>\r | |
| 14 | #include <IndustryStandard/TcgPhysicalPresence.h>\r | |
| 15 | \r | |
| c411b485 MK |
16 | #define TCG2_CONFIGURATION_VARSTORE_ID 0x0001\r |
| 17 | #define TCG2_CONFIGURATION_INFO_VARSTORE_ID 0x0002\r | |
| 18 | #define TCG2_VERSION_VARSTORE_ID 0x0003\r | |
| 19 | #define TCG2_CONFIGURATION_FORM_ID 0x0001\r | |
| 20 | \r | |
| 21 | #define KEY_TPM_DEVICE 0x2000\r | |
| 22 | #define KEY_TPM2_OPERATION 0x2001\r | |
| 23 | #define KEY_TPM2_OPERATION_PARAMETER 0x2002\r | |
| 24 | #define KEY_TPM2_PCR_BANKS_REQUEST_0 0x2003\r | |
| 25 | #define KEY_TPM2_PCR_BANKS_REQUEST_1 0x2004\r | |
| 26 | #define KEY_TPM2_PCR_BANKS_REQUEST_2 0x2005\r | |
| 27 | #define KEY_TPM2_PCR_BANKS_REQUEST_3 0x2006\r | |
| 28 | #define KEY_TPM2_PCR_BANKS_REQUEST_4 0x2007\r | |
| 29 | #define KEY_TPM_DEVICE_INTERFACE 0x2008\r | |
| 30 | #define KEY_TCG2_PPI_VERSION 0x2009\r | |
| 31 | #define KEY_TPM2_ACPI_REVISION 0x200A\r | |
| 32 | \r | |
| 33 | #define TPM_DEVICE_NULL 0\r | |
| 34 | #define TPM_DEVICE_1_2 1\r | |
| 35 | #define TPM_DEVICE_2_0_DTPM 2\r | |
| 36 | #define TPM_DEVICE_MIN TPM_DEVICE_1_2\r | |
| 37 | #define TPM_DEVICE_MAX TPM_DEVICE_2_0_DTPM\r | |
| 38 | #define TPM_DEVICE_DEFAULT TPM_DEVICE_1_2\r | |
| 39 | \r | |
| 40 | #define TPM2_ACPI_REVISION_3 3\r | |
| 41 | #define TPM2_ACPI_REVISION_4 4\r | |
| fca42289 | 42 | \r |
| 518b6f65 JY |
43 | #define TPM_DEVICE_INTERFACE_TIS 0\r |
| 44 | #define TPM_DEVICE_INTERFACE_PTP_FIFO 1\r | |
| 45 | #define TPM_DEVICE_INTERFACE_PTP_CRB 2\r | |
| 46 | #define TPM_DEVICE_INTERFACE_MAX TPM_DEVICE_INTERFACE_PTP_FIFO\r | |
| 47 | #define TPM_DEVICE_INTERFACE_DEFAULT TPM_DEVICE_INTERFACE_PTP_CRB\r | |
| 48 | \r | |
| c411b485 MK |
49 | #define TCG2_PPI_VERSION_1_2 0x322E31 // "1.2"\r |
| 50 | #define TCG2_PPI_VERSION_1_3 0x332E31 // "1.3"\r | |
| dd6d0a52 | 51 | \r |
| 1abfa4ce JY |
52 | //\r |
| 53 | // Nv Data structure referenced by IFR, TPM device user desired\r | |
| 54 | //\r | |
| 55 | typedef struct {\r | |
| c411b485 | 56 | UINT8 TpmDevice;\r |
| 1abfa4ce JY |
57 | } TCG2_CONFIGURATION;\r |
| 58 | \r | |
| dd6d0a52 | 59 | typedef struct {\r |
| c411b485 MK |
60 | UINT64 PpiVersion;\r |
| 61 | UINT8 Tpm2AcpiTableRev;\r | |
| dd6d0a52 SZ |
62 | } TCG2_VERSION;\r |
| 63 | \r | |
| c41eeb44 | 64 | typedef struct {\r |
| c411b485 MK |
65 | BOOLEAN Sha1Supported;\r |
| 66 | BOOLEAN Sha256Supported;\r | |
| 67 | BOOLEAN Sha384Supported;\r | |
| 68 | BOOLEAN Sha512Supported;\r | |
| 69 | BOOLEAN Sm3Supported;\r | |
| 70 | UINT8 TpmDeviceInterfaceAttempt;\r | |
| 71 | BOOLEAN TpmDeviceInterfacePtpFifoSupported;\r | |
| 72 | BOOLEAN TpmDeviceInterfacePtpCrbSupported;\r | |
| 73 | BOOLEAN ChangeEPSSupported;\r | |
| c41eeb44 JY |
74 | } TCG2_CONFIGURATION_INFO;\r |
| 75 | \r | |
| 1abfa4ce JY |
76 | //\r |
| 77 | // Variable saved for S3, TPM detected, only valid in S3 path.\r | |
| 78 | // This variable is ReadOnly.\r | |
| 79 | //\r | |
| 80 | typedef struct {\r | |
| c411b485 | 81 | UINT8 TpmDeviceDetected;\r |
| 1abfa4ce JY |
82 | } TCG2_DEVICE_DETECTION;\r |
| 83 | \r | |
| c41eeb44 JY |
84 | #define TCG2_STORAGE_NAME L"TCG2_CONFIGURATION"\r |
| 85 | #define TCG2_STORAGE_INFO_NAME L"TCG2_CONFIGURATION_INFO"\r | |
| 1abfa4ce | 86 | #define TCG2_DEVICE_DETECTION_NAME L"TCG2_DEVICE_DETECTION"\r |
| dd6d0a52 | 87 | #define TCG2_VERSION_NAME L"TCG2_VERSION"\r |
| 1abfa4ce | 88 | \r |
| 1abfa4ce | 89 | #endif\r |