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SecurityPkg Tcg: Use SW SMI IO port PCD in Tpm.asl
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1abfa4ce 1/** @file\r
b3548d32 2 The TPM2 definition block in ACPI table for TCG2 physical presence\r
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3 and MemoryClear.\r
4\r
c4122dca 5Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
447f73db 6(c)Copyright 2016 HP Development Company, L.P.<BR>\r
6e3c834a 7Copyright (c) Microsoft Corporation.<BR>\r
289b714b 8SPDX-License-Identifier: BSD-2-Clause-Patent\r
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9\r
10**/\r
11\r
12DefinitionBlock (\r
13 "Tpm.aml",\r
14 "SSDT",\r
15 2,\r
16 "INTEL ",\r
17 "Tpm2Tabl",\r
18 0x1000\r
19 )\r
20{\r
21 Scope (\_SB)\r
22 {\r
23 Device (TPM)\r
24 {\r
25 //\r
26 // TCG2\r
27 //\r
9a9fa14e 28\r
73126ac2 29 //\r
9a9fa14e 30 // TAG for patching TPM2.0 _HID\r
73126ac2 31 //\r
9a9fa14e 32 Name (_HID, "NNNN0000")\r
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33\r
34 Name (_CID, "MSFT0101")\r
35\r
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36 //\r
37 // Readable name of this device, don't know if this way is correct yet\r
38 //\r
39 Name (_STR, Unicode ("TPM 2.0 Device"))\r
40\r
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41 //\r
42 // Operational region for Smi port access\r
43 //\r
6e3c834a 44 OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)\r
1abfa4ce 45 Field (SMIP, ByteAcc, NoLock, Preserve)\r
b3548d32 46 {\r
6e3c834a 47 IOPN, 8\r
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48 }\r
49\r
50 //\r
51 // Operational region for TPM access\r
52 //\r
53 OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
54 Field (TPMR, AnyAcc, NoLock, Preserve)\r
55 {\r
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56 ACC0, 8, // TPM_ACCESS_0\r
57 Offset(0x8),\r
58 INTE, 32, // TPM_INT_ENABLE_0\r
59 INTV, 8, // TPM_INT_VECTOR_0\r
60 Offset(0x10),\r
61 INTS, 32, // TPM_INT_STATUS_0\r
62 INTF, 32, // TPM_INTF_CAPABILITY_0\r
63 STS0, 32, // TPM_STS_0\r
64 Offset(0x24),\r
65 FIFO, 32, // TPM_DATA_FIFO_0\r
66 Offset(0x30),\r
67 TID0, 32, // TPM_INTERFACE_ID_0\r
68 // ignore the rest\r
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69 }\r
70\r
71 //\r
72 // Operational region for TPM support, TPM Physical Presence and TPM Memory Clear\r
73 // Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.\r
74 //\r
75 OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)\r
76 Field (TNVS, AnyAcc, NoLock, Preserve)\r
77 {\r
78 PPIN, 8, // Software SMI for Physical Presence Interface\r
d6b926e7 79 PPIP, 32, // Used for save physical presence parameter\r
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80 PPRP, 32, // Physical Presence request operation response\r
81 PPRQ, 32, // Physical Presence request operation\r
82 PPRM, 32, // Physical Presence request operation parameter\r
83 LPPR, 32, // Last Physical Presence request operation\r
84 FRET, 32, // Physical Presence function return code\r
85 MCIN, 8, // Software SMI for Memory Clear Interface\r
d6b926e7 86 MCIP, 32, // Used for save the Mor parameter\r
1abfa4ce 87 MORD, 32, // Memory Overwrite Request Data\r
053f31e3 88 MRET, 32, // Memory Overwrite function return code\r
d6b926e7 89 UCRQ, 32, // Physical Presence request operation to Get User Confirmation Status\r
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90 IRQN, 32, // IRQ Number for _CRS\r
91 SFRB, 8 // Is shortformed Pkglength for resource buffer\r
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92 }\r
93\r
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94 //\r
95 // Possible resource settings returned by _PRS method\r
96 // RESS : ResourceTemplate with PkgLength <=63\r
97 // RESL : ResourceTemplate with PkgLength > 63\r
98 //\r
99 // The format of the data has to follow the same format as\r
100 // _CRS (according to ACPI spec).\r
101 //\r
102 Name (RESS, ResourceTemplate() {\r
103 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
104 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10}\r
105 })\r
106\r
107 Name (RESL, ResourceTemplate() {\r
108 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
109 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
110 })\r
111\r
112 //\r
113 // Current resource settings for _CRS method\r
114 //\r
115 Name(RES0, ResourceTemplate () {\r
116 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG0)\r
73d77732 117 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , INTR) {12}\r
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118 })\r
119\r
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120 Name(RES1, ResourceTemplate () {\r
121 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG1)\r
122 })\r
123\r
124\r
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125 //\r
126 // Return the resource consumed by TPM device.\r
127 //\r
128 Method(_CRS,0,Serialized)\r
129 {\r
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130 //\r
131 // IRQNum = 0 means disable IRQ support\r
132 //\r
133 If (LEqual(IRQN, 0)) {\r
134 Return (RES1)\r
135 }\r
136 Else\r
137 {\r
138 CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
139 Store(IRQN, LIRQ)\r
140 Return (RES0)\r
141 }\r
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142 }\r
143\r
144 //\r
145 // Set resources consumed by the TPM device. This is used to\r
146 // assign an interrupt number to the device. The input byte stream\r
147 // has to be the same as returned by _CRS (according to ACPI spec).\r
148 //\r
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149 // Platform may choose to override this function with specific interrupt\r
150 // programing logic to replace FIFO/TIS SIRQ registers programing\r
151 //\r
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152 Method(_SRS,1,Serialized)\r
153 {\r
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154 //\r
155 // Do not configure Interrupt if IRQ Num is configured 0 by default\r
156 //\r
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157 If (LNotEqual(IRQN, 0)) {\r
158 //\r
159 // Update resource descriptor\r
160 // Use the field name to identify the offsets in the argument\r
161 // buffer and RES0 buffer.\r
162 //\r
163 CreateDWordField(Arg0, ^INTR._INT, IRQ0)\r
164 CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
165 Store(IRQ0, LIRQ)\r
166 Store(IRQ0, IRQN)\r
edf7647b 167\r
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168 CreateBitField(Arg0, ^INTR._HE, ITRG)\r
169 CreateBitField(RES0, ^INTR._HE, LTRG)\r
170 Store(ITRG, LTRG)\r
edf7647b 171\r
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172 CreateBitField(Arg0, ^INTR._LL, ILVL)\r
173 CreateBitField(RES0, ^INTR._LL, LLVL)\r
174 Store(ILVL, LLVL)\r
edf7647b 175\r
edf7647b 176 //\r
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177 // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
178 // nibble.\r
179 // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
180 // 1111 - FIFO interface as defined in TIS1.3 is active\r
edf7647b 181 //\r
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182 If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
183 //\r
184 // If FIFO interface, interrupt vector register is\r
185 // available. TCG PTP specification allows only\r
186 // values 1..15 in this field. For other interrupts\r
187 // the field should stay 0.\r
188 //\r
189 If (LLess (IRQ0, 16)) {\r
190 Store (And(IRQ0, 0xF), INTV)\r
191 }\r
192 //\r
193 // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
194 // contains settings for interrupt polarity.\r
195 // The other bits of the byte enable individual interrupts.\r
196 // They should be all be zero, but to avoid changing the\r
197 // configuration, the other bits are be preserved.\r
198 // 00 - high level\r
199 // 01 - low level\r
200 // 10 - rising edge\r
201 // 11 - falling edge\r
202 //\r
203 // ACPI spec definitions:\r
204 // _HE: '1' is Edge, '0' is Level\r
205 // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
206 //\r
207 If (LEqual (ITRG, 1)) {\r
208 Or(INTE, 0x00000010, INTE)\r
209 } Else {\r
210 And(INTE, 0xFFFFFFEF, INTE)\r
211 }\r
212 if (LEqual (ILVL, 0)) {\r
213 Or(INTE, 0x00000008, INTE)\r
214 } Else {\r
215 And(INTE, 0xFFFFFFF7, INTE)\r
216 }\r
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217 }\r
218 }\r
219 }\r
220\r
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221 Method(_PRS,0,Serialized)\r
222 {\r
223 //\r
224 // IRQNum = 0 means disable IRQ support\r
225 //\r
226 If (LEqual(IRQN, 0)) {\r
227 Return (RES1)\r
228 } ElseIf(LEqual(SFRB, 0)) {\r
229 //\r
230 // Long format. Possible resources PkgLength > 63\r
231 //\r
232 Return (RESL)\r
233 } Else {\r
234 //\r
235 // Short format. Possible resources PkgLength <=63\r
236 //\r
237 Return (RESS)\r
238 }\r
239 }\r
edf7647b 240\r
1abfa4ce 241 Method (PTS, 1, Serialized)\r
b3548d32 242 {\r
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243 //\r
244 // Detect Sx state for MOR, only S4, S5 need to handle\r
245 //\r
246 If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))\r
b3548d32 247 {\r
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248 //\r
249 // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.\r
250 //\r
251 If (LNot (And (MORD, 0x10)))\r
252 {\r
253 //\r
60ee3bd8 254 // Trigger the SMI through ACPI _PTS method.\r
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255 //\r
256 Store (0x02, MCIP)\r
b3548d32 257\r
1abfa4ce 258 //\r
60ee3bd8 259 // Trigger the SMI interrupt\r
1abfa4ce 260 //\r
6e3c834a 261 Store (MCIN, IOPN)\r
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262 }\r
263 }\r
264 Return (0)\r
b3548d32 265 }\r
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266\r
267 Method (_STA, 0)\r
268 {\r
269 if (LEqual (ACC0, 0xff))\r
270 {\r
271 Return (0)\r
272 }\r
273 Return (0x0f)\r
274 }\r
275\r
276 //\r
277 // TCG Hardware Information\r
278 //\r
39699d07 279 Method (HINF, 1, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj}) // IntObj\r
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280 {\r
281 //\r
282 // Switch by function index\r
283 //\r
39699d07 284 Switch (ToInteger(Arg0))\r
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285 {\r
286 Case (0)\r
287 {\r
288 //\r
289 // Standard query\r
290 //\r
291 Return (Buffer () {0x03})\r
292 }\r
293 Case (1)\r
294 {\r
295 //\r
296 // Return failure if no TPM present\r
297 //\r
298 Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})\r
299 if (LEqual (_STA (), 0x00))\r
300 {\r
301 Return (Package () {0x00})\r
302 }\r
303\r
304 //\r
305 // Return TPM version\r
306 //\r
307 Return (TPMV)\r
308 }\r
309 Default {BreakPoint}\r
310 }\r
311 Return (Buffer () {0})\r
312 }\r
313\r
314 Name(TPM2, Package (0x02){\r
b3548d32 315 Zero,\r
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316 Zero\r
317 })\r
318\r
319 Name(TPM3, Package (0x03){\r
b3548d32 320 Zero,\r
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321 Zero,\r
322 Zero\r
323 })\r
324\r
325 //\r
326 // TCG Physical Presence Interface\r
327 //\r
39699d07 328 Method (TPPI, 2, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj}) // IntObj, PkgObj\r
b3548d32 329 {\r
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330 //\r
331 // Switch by function index\r
332 //\r
39699d07 333 Switch (ToInteger(Arg0))\r
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334 {\r
335 Case (0)\r
336 {\r
337 //\r
338 // Standard query, supports function 1-8\r
339 //\r
340 Return (Buffer () {0xFF, 0x01})\r
341 }\r
342 Case (1)\r
343 {\r
344 //\r
345 // a) Get Physical Presence Interface Version\r
346 //\r
cd643013 347 Return ("$PV")\r
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348 }\r
349 Case (2)\r
350 {\r
351 //\r
352 // b) Submit TPM Operation Request to Pre-OS Environment\r
353 //\r
b3548d32 354\r
39699d07 355 Store (DerefOf (Index (Arg1, 0x00)), PPRQ)\r
edb0fda2 356 Store (0, PPRM)\r
1abfa4ce 357 Store (0x02, PPIP)\r
b3548d32 358\r
1abfa4ce 359 //\r
60ee3bd8 360 // Trigger the SMI interrupt\r
1abfa4ce 361 //\r
6e3c834a 362 Store (PPIN, IOPN)\r
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363 Return (FRET)\r
364\r
365\r
366 }\r
367 Case (3)\r
368 {\r
369 //\r
370 // c) Get Pending TPM Operation Requested By the OS\r
371 //\r
b3548d32 372\r
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373 Store (PPRQ, Index (TPM2, 0x01))\r
374 Return (TPM2)\r
375 }\r
376 Case (4)\r
377 {\r
378 //\r
379 // d) Get Platform-Specific Action to Transition to Pre-OS Environment\r
380 //\r
381 Return (2)\r
382 }\r
383 Case (5)\r
384 {\r
385 //\r
386 // e) Return TPM Operation Response to OS Environment\r
387 //\r
388 Store (0x05, PPIP)\r
b3548d32 389\r
1abfa4ce 390 //\r
60ee3bd8 391 // Trigger the SMI interrupt\r
1abfa4ce 392 //\r
6e3c834a 393 Store (PPIN, IOPN)\r
b3548d32 394\r
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395 Store (LPPR, Index (TPM3, 0x01))\r
396 Store (PPRP, Index (TPM3, 0x02))\r
397\r
398 Return (TPM3)\r
399 }\r
400 Case (6)\r
401 {\r
402\r
403 //\r
404 // f) Submit preferred user language (Not implemented)\r
405 //\r
406\r
407 Return (3)\r
408\r
409 }\r
410 Case (7)\r
411 {\r
412 //\r
413 // g) Submit TPM Operation Request to Pre-OS Environment 2\r
414 //\r
415 Store (7, PPIP)\r
39699d07 416 Store (DerefOf (Index (Arg1, 0x00)), PPRQ)\r
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417 Store (0, PPRM)\r
418 If (LEqual (PPRQ, 23)) {\r
39699d07 419 Store (DerefOf (Index (Arg1, 0x01)), PPRM)\r
1abfa4ce 420 }\r
b3548d32 421\r
1abfa4ce 422 //\r
60ee3bd8 423 // Trigger the SMI interrupt\r
1abfa4ce 424 //\r
6e3c834a 425 Store (PPIN, IOPN)\r
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426 Return (FRET)\r
427 }\r
428 Case (8)\r
429 {\r
430 //\r
431 // e) Get User Confirmation Status for Operation\r
432 //\r
433 Store (8, PPIP)\r
39699d07 434 Store (DerefOf (Index (Arg1, 0x00)), UCRQ)\r
b3548d32 435\r
1abfa4ce 436 //\r
60ee3bd8 437 // Trigger the SMI interrupt\r
1abfa4ce 438 //\r
6e3c834a 439 Store (PPIN, IOPN)\r
b3548d32 440\r
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441 Return (FRET)\r
442 }\r
443\r
444 Default {BreakPoint}\r
445 }\r
446 Return (1)\r
447 }\r
448\r
39699d07 449 Method (TMCI, 2, Serialized, 0, IntObj, {UnknownObj, UnknownObj}) // IntObj, PkgObj\r
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450 {\r
451 //\r
452 // Switch by function index\r
453 //\r
39699d07 454 Switch (ToInteger (Arg0))\r
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455 {\r
456 Case (0)\r
457 {\r
458 //\r
459 // Standard query, supports function 1-1\r
460 //\r
461 Return (Buffer () {0x03})\r
462 }\r
463 Case (1)\r
464 {\r
465 //\r
466 // Save the Operation Value of the Request to MORD (reserved memory)\r
467 //\r
39699d07 468 Store (DerefOf (Index (Arg1, 0x00)), MORD)\r
b3548d32 469\r
1abfa4ce 470 //\r
60ee3bd8 471 // Trigger the SMI through ACPI _DSM method.\r
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472 //\r
473 Store (0x01, MCIP)\r
b3548d32 474\r
1abfa4ce 475 //\r
60ee3bd8 476 // Trigger the SMI interrupt\r
1abfa4ce 477 //\r
6e3c834a 478 Store (MCIN, IOPN)\r
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479 Return (MRET)\r
480 }\r
481 Default {BreakPoint}\r
482 }\r
b3548d32 483 Return (1)\r
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484 }\r
485\r
486 Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
487 {\r
488\r
489 //\r
490 // TCG Hardware Information\r
491 //\r
492 If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))\r
493 {\r
39699d07 494 Return (HINF (Arg2))\r
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495 }\r
496\r
497 //\r
498 // TCG Physical Presence Interface\r
499 //\r
500 If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))\r
501 {\r
39699d07 502 Return (TPPI (Arg2, Arg3))\r
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503 }\r
504\r
505 //\r
506 // TCG Memory Clear Interface\r
507 //\r
508 If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))\r
509 {\r
39699d07 510 Return (TMCI (Arg2, Arg3))\r
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511 }\r
512\r
513 Return (Buffer () {0})\r
514 }\r
515 }\r
516 }\r
517}\r