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[mirror_edk2.git] / SecurityPkg / Tcg / Tcg2Smm / Tpm.asl
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1abfa4ce 1/** @file\r
b3548d32 2 The TPM2 definition block in ACPI table for TCG2 physical presence\r
1abfa4ce
JY		 3 and MemoryClear.\r
4\r
c4122dca 5Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
447f73db 6(c)Copyright 2016 HP Development Company, L.P.<BR>\r
af9743ef 7Copyright (c) 2017, Microsoft Corporation. All rights reserved. <BR>\r
b3548d32
LG		 8This program and the accompanying materials\r
9are licensed and made available under the terms and conditions of the BSD License\r
10which accompanies this distribution. The full text of the license may be found at\r
1abfa4ce
JY		 11http://opensource.org/licenses/bsd-license.php\r
12\r
b3548d32 13THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
1abfa4ce
JY		 14WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
15\r
16**/\r
17\r
18DefinitionBlock (\r
19 "Tpm.aml",\r
20 "SSDT",\r
21 2,\r
22 "INTEL ",\r
23 "Tpm2Tabl",\r
24 0x1000\r
25 )\r
26{\r
27 Scope (\_SB)\r
28 {\r
29 Device (TPM)\r
30 {\r
31 //\r
32 // TCG2\r
33 //\r
9a9fa14e 34\r
73126ac2 35 //\r
9a9fa14e 36 // TAG for patching TPM2.0 _HID\r
73126ac2 37 //\r
9a9fa14e 38 Name (_HID, "NNNN0000")\r
73126ac2
ZC		 39\r
40 Name (_CID, "MSFT0101")\r
41\r
1abfa4ce
JY		 42 //\r
43 // Readable name of this device, don't know if this way is correct yet\r
44 //\r
45 Name (_STR, Unicode ("TPM 2.0 Device"))\r
46\r
1abfa4ce
JY		 47 //\r
48 // Operational region for Smi port access\r
49 //\r
50 OperationRegion (SMIP, SystemIO, 0xB2, 1)\r
51 Field (SMIP, ByteAcc, NoLock, Preserve)\r
b3548d32 52 {\r
1abfa4ce
JY		 53 IOB2, 8\r
54 }\r
55\r
56 //\r
57 // Operational region for TPM access\r
58 //\r
59 OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
60 Field (TPMR, AnyAcc, NoLock, Preserve)\r
61 {\r
edf7647b
ZC		 62 ACC0, 8, // TPM_ACCESS_0\r
63 Offset(0x8),\r
64 INTE, 32, // TPM_INT_ENABLE_0\r
65 INTV, 8, // TPM_INT_VECTOR_0\r
66 Offset(0x10),\r
67 INTS, 32, // TPM_INT_STATUS_0\r
68 INTF, 32, // TPM_INTF_CAPABILITY_0\r
69 STS0, 32, // TPM_STS_0\r
70 Offset(0x24),\r
71 FIFO, 32, // TPM_DATA_FIFO_0\r
72 Offset(0x30),\r
73 TID0, 32, // TPM_INTERFACE_ID_0\r
74 // ignore the rest\r
1abfa4ce
JY		 75 }\r
76\r
77 //\r
78 // Operational region for TPM support, TPM Physical Presence and TPM Memory Clear\r
79 // Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.\r
80 //\r
81 OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)\r
82 Field (TNVS, AnyAcc, NoLock, Preserve)\r
83 {\r
84 PPIN, 8, // Software SMI for Physical Presence Interface\r
85 PPIP, 32, // Used for save physical presence paramter\r
86 PPRP, 32, // Physical Presence request operation response\r
87 PPRQ, 32, // Physical Presence request operation\r
88 PPRM, 32, // Physical Presence request operation parameter\r
89 LPPR, 32, // Last Physical Presence request operation\r
90 FRET, 32, // Physical Presence function return code\r
91 MCIN, 8, // Software SMI for Memory Clear Interface\r
92 MCIP, 32, // Used for save the Mor paramter\r
93 MORD, 32, // Memory Overwrite Request Data\r
053f31e3 94 MRET, 32, // Memory Overwrite function return code\r
c4122dca
ZC		 95 UCRQ, 32, // Phyical Presence request operation to Get User Confirmation Status\r
96 IRQN, 32, // IRQ Number for _CRS\r
97 SFRB, 8 // Is shortformed Pkglength for resource buffer\r
1abfa4ce
JY		 98 }\r
99\r
c4122dca
ZC		 100 //\r
101 // Possible resource settings returned by _PRS method\r
102 // RESS : ResourceTemplate with PkgLength <=63\r
103 // RESL : ResourceTemplate with PkgLength > 63\r
104 //\r
105 // The format of the data has to follow the same format as\r
106 // _CRS (according to ACPI spec).\r
107 //\r
108 Name (RESS, ResourceTemplate() {\r
109 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
110 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10}\r
111 })\r
112\r
113 Name (RESL, ResourceTemplate() {\r
114 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
115 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
116 })\r
117\r
118 //\r
119 // Current resource settings for _CRS method\r
120 //\r
121 Name(RES0, ResourceTemplate () {\r
122 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG0)\r
73d77732 123 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , INTR) {12}\r
edf7647b
ZC		 124 })\r
125\r
c4122dca
ZC		 126 Name(RES1, ResourceTemplate () {\r
127 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REG1)\r
128 })\r
129\r
130\r
edf7647b
ZC		 131 //\r
132 // Return the resource consumed by TPM device.\r
133 //\r
134 Method(_CRS,0,Serialized)\r
135 {\r
c4122dca
ZC		 136 //\r
137 // IRQNum = 0 means disable IRQ support\r
138 //\r
139 If (LEqual(IRQN, 0)) {\r
140 Return (RES1)\r
141 }\r
142 Else\r
143 {\r
144 CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
145 Store(IRQN, LIRQ)\r
146 Return (RES0)\r
147 }\r
edf7647b
ZC		 148 }\r
149\r
150 //\r
151 // Set resources consumed by the TPM device. This is used to\r
152 // assign an interrupt number to the device. The input byte stream\r
153 // has to be the same as returned by _CRS (according to ACPI spec).\r
154 //\r
c4122dca
ZC		 155 // Platform may choose to override this function with specific interrupt\r
156 // programing logic to replace FIFO/TIS SIRQ registers programing\r
157 //\r
edf7647b
ZC		 158 Method(_SRS,1,Serialized)\r
159 {\r
c4122dca
ZC		 160 //\r
161 // Do not configure Interrupt if IRQ Num is configured 0 by default\r
162 //\r
163 If (LEqual(IRQN, 0)) {\r
164 Return (0)\r
165 }\r
166\r
edf7647b
ZC		 167 //\r
168 // Update resource descriptor\r
169 // Use the field name to identify the offsets in the argument\r
c4122dca 170 // buffer and RES0 buffer.\r
edf7647b 171 //\r
73d77732 172 CreateDWordField(Arg0, ^INTR._INT, IRQ0)\r
c4122dca 173 CreateDWordField(RES0, ^INTR._INT, LIRQ)\r
edf7647b 174 Store(IRQ0, LIRQ)\r
c4122dca 175 Store(IRQ0, IRQN)\r
edf7647b 176\r
73d77732 177 CreateBitField(Arg0, ^INTR._HE, ITRG)\r
c4122dca 178 CreateBitField(RES0, ^INTR._HE, LTRG)\r
edf7647b
ZC		 179 Store(ITRG, LTRG)\r
180\r
73d77732 181 CreateBitField(Arg0, ^INTR._LL, ILVL)\r
c4122dca 182 CreateBitField(RES0, ^INTR._LL, LLVL)\r
edf7647b
ZC		 183 Store(ILVL, LLVL)\r
184\r
185 //\r
186 // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
187 // nibble.\r
188 // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
189 // 1111 - FIFO interface as defined in TIS1.3 is active\r
190 //\r
191 If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
192 //\r
193 // If FIFO interface, interrupt vector register is\r
194 // available. TCG PTP specification allows only\r
195 // values 1..15 in this field. For other interrupts\r
196 // the field should stay 0.\r
197 //\r
198 If (LLess (IRQ0, 16)) {\r
199 Store (And(IRQ0, 0xF), INTV)\r
200 }\r
201 //\r
202 // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
203 // contains settings for interrupt polarity.\r
204 // The other bits of the byte enable individual interrupts.\r
205 // They should be all be zero, but to avoid changing the\r
206 // configuration, the other bits are be preserved.\r
207 // 00 - high level\r
208 // 01 - low level\r
209 // 10 - rising edge\r
210 // 11 - falling edge\r
211 //\r
212 // ACPI spec definitions:\r
213 // _HE: '1' is Edge, '0' is Level\r
214 // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
215 //\r
216 If (LEqual (ITRG, 1)) {\r
217 Or(INTE, 0x00000010, INTE)\r
218 } Else {\r
219 And(INTE, 0xFFFFFFEF, INTE)\r
220 }\r
221 if (LEqual (ILVL, 0)) {\r
222 Or(INTE, 0x00000008, INTE)\r
223 } Else {\r
224 And(INTE, 0xFFFFFFF7, INTE)\r
225 }\r
226 }\r
227 }\r
228\r
c4122dca
ZC		 229 Method(_PRS,0,Serialized)\r
230 {\r
231 //\r
232 // IRQNum = 0 means disable IRQ support\r
233 //\r
234 If (LEqual(IRQN, 0)) {\r
235 Return (RES1)\r
236 } ElseIf(LEqual(SFRB, 0)) {\r
237 //\r
238 // Long format. Possible resources PkgLength > 63\r
239 //\r
240 Return (RESL)\r
241 } Else {\r
242 //\r
243 // Short format. Possible resources PkgLength <=63\r
244 //\r
245 Return (RESS)\r
246 }\r
247 }\r
edf7647b 248\r
1abfa4ce 249 Method (PTS, 1, Serialized)\r
b3548d32 250 {\r
1abfa4ce
JY		 251 //\r
252 // Detect Sx state for MOR, only S4, S5 need to handle\r
253 //\r
254 If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))\r
b3548d32 255 {\r
1abfa4ce
JY		 256 //\r
257 // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.\r
258 //\r
259 If (LNot (And (MORD, 0x10)))\r
260 {\r
261 //\r
262 // Triggle the SMI through ACPI _PTS method.\r
263 //\r
264 Store (0x02, MCIP)\r
b3548d32 265\r
1abfa4ce
JY		 266 //\r
267 // Triggle the SMI interrupt\r
268 //\r
269 Store (MCIN, IOB2)\r
270 }\r
271 }\r
272 Return (0)\r
b3548d32 273 }\r
1abfa4ce
JY		 274\r
275 Method (_STA, 0)\r
276 {\r
277 if (LEqual (ACC0, 0xff))\r
278 {\r
279 Return (0)\r
280 }\r
281 Return (0x0f)\r
282 }\r
283\r
284 //\r
285 // TCG Hardware Information\r
286 //\r
287 Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
288 {\r
289 //\r
290 // Switch by function index\r
291 //\r
292 Switch (ToInteger(Arg1))\r
293 {\r
294 Case (0)\r
295 {\r
296 //\r
297 // Standard query\r
298 //\r
299 Return (Buffer () {0x03})\r
300 }\r
301 Case (1)\r
302 {\r
303 //\r
304 // Return failure if no TPM present\r
305 //\r
306 Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})\r
307 if (LEqual (_STA (), 0x00))\r
308 {\r
309 Return (Package () {0x00})\r
310 }\r
311\r
312 //\r
313 // Return TPM version\r
314 //\r
315 Return (TPMV)\r
316 }\r
317 Default {BreakPoint}\r
318 }\r
319 Return (Buffer () {0})\r
320 }\r
321\r
322 Name(TPM2, Package (0x02){\r
b3548d32 323 Zero,\r
1abfa4ce
JY		 324 Zero\r
325 })\r
326\r
327 Name(TPM3, Package (0x03){\r
b3548d32 328 Zero,\r
1abfa4ce
JY		 329 Zero,\r
330 Zero\r
331 })\r
332\r
333 //\r
334 // TCG Physical Presence Interface\r
335 //\r
336 Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
b3548d32 337 {\r
1abfa4ce
JY		 338 //\r
339 // Switch by function index\r
340 //\r
341 Switch (ToInteger(Arg1))\r
342 {\r
343 Case (0)\r
344 {\r
345 //\r
346 // Standard query, supports function 1-8\r
347 //\r
348 Return (Buffer () {0xFF, 0x01})\r
349 }\r
350 Case (1)\r
351 {\r
352 //\r
353 // a) Get Physical Presence Interface Version\r
354 //\r
cd643013 355 Return ("$PV")\r
1abfa4ce
JY		 356 }\r
357 Case (2)\r
358 {\r
359 //\r
360 // b) Submit TPM Operation Request to Pre-OS Environment\r
361 //\r
b3548d32 362\r
1abfa4ce 363 Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
edb0fda2 364 Store (0, PPRM)\r
1abfa4ce 365 Store (0x02, PPIP)\r
b3548d32 366\r
1abfa4ce
JY		 367 //\r
368 // Triggle the SMI interrupt\r
369 //\r
370 Store (PPIN, IOB2)\r
371 Return (FRET)\r
372\r
373\r
374 }\r
375 Case (3)\r
376 {\r
377 //\r
378 // c) Get Pending TPM Operation Requested By the OS\r
379 //\r
b3548d32 380\r
1abfa4ce
JY		 381 Store (PPRQ, Index (TPM2, 0x01))\r
382 Return (TPM2)\r
383 }\r
384 Case (4)\r
385 {\r
386 //\r
387 // d) Get Platform-Specific Action to Transition to Pre-OS Environment\r
388 //\r
389 Return (2)\r
390 }\r
391 Case (5)\r
392 {\r
393 //\r
394 // e) Return TPM Operation Response to OS Environment\r
395 //\r
396 Store (0x05, PPIP)\r
b3548d32 397\r
1abfa4ce
JY		 398 //\r
399 // Triggle the SMI interrupt\r
400 //\r
401 Store (PPIN, IOB2)\r
b3548d32 402\r
1abfa4ce
JY		 403 Store (LPPR, Index (TPM3, 0x01))\r
404 Store (PPRP, Index (TPM3, 0x02))\r
405\r
406 Return (TPM3)\r
407 }\r
408 Case (6)\r
409 {\r
410\r
411 //\r
412 // f) Submit preferred user language (Not implemented)\r
413 //\r
414\r
415 Return (3)\r
416\r
417 }\r
418 Case (7)\r
419 {\r
420 //\r
421 // g) Submit TPM Operation Request to Pre-OS Environment 2\r
422 //\r
423 Store (7, PPIP)\r
424 Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
425 Store (0, PPRM)\r
426 If (LEqual (PPRQ, 23)) {\r
427 Store (DerefOf (Index (Arg2, 0x01)), PPRM)\r
428 }\r
b3548d32 429\r
1abfa4ce 430 //\r
b3548d32 431 // Triggle the SMI interrupt\r
1abfa4ce 432 //\r
b3548d32 433 Store (PPIN, IOB2)\r
1abfa4ce
JY		 434 Return (FRET)\r
435 }\r
436 Case (8)\r
437 {\r
438 //\r
439 // e) Get User Confirmation Status for Operation\r
440 //\r
441 Store (8, PPIP)\r
053f31e3 442 Store (DerefOf (Index (Arg2, 0x00)), UCRQ)\r
b3548d32 443\r
1abfa4ce
JY		 444 //\r
445 // Triggle the SMI interrupt\r
446 //\r
447 Store (PPIN, IOB2)\r
b3548d32 448\r
1abfa4ce
JY		 449 Return (FRET)\r
450 }\r
451\r
452 Default {BreakPoint}\r
453 }\r
454 Return (1)\r
455 }\r
456\r
457 Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
458 {\r
459 //\r
460 // Switch by function index\r
461 //\r
462 Switch (ToInteger (Arg1))\r
463 {\r
464 Case (0)\r
465 {\r
466 //\r
467 // Standard query, supports function 1-1\r
468 //\r
469 Return (Buffer () {0x03})\r
470 }\r
471 Case (1)\r
472 {\r
473 //\r
474 // Save the Operation Value of the Request to MORD (reserved memory)\r
475 //\r
476 Store (DerefOf (Index (Arg2, 0x00)), MORD)\r
b3548d32 477\r
1abfa4ce
JY		 478 //\r
479 // Triggle the SMI through ACPI _DSM method.\r
480 //\r
481 Store (0x01, MCIP)\r
b3548d32 482\r
1abfa4ce
JY		 483 //\r
484 // Triggle the SMI interrupt\r
485 //\r
486 Store (MCIN, IOB2)\r
487 Return (MRET)\r
488 }\r
489 Default {BreakPoint}\r
490 }\r
b3548d32 491 Return (1)\r
1abfa4ce
JY		 492 }\r
493\r
494 Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
495 {\r
496\r
497 //\r
498 // TCG Hardware Information\r
499 //\r
500 If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))\r
501 {\r
502 Return (HINF (Arg1, Arg2, Arg3))\r
503 }\r
504\r
505 //\r
506 // TCG Physical Presence Interface\r
507 //\r
508 If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))\r
509 {\r
510 Return (TPPI (Arg1, Arg2, Arg3))\r
511 }\r
512\r
513 //\r
514 // TCG Memory Clear Interface\r
515 //\r
516 If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))\r
517 {\r
518 Return (TMCI (Arg1, Arg2, Arg3))\r
519 }\r
520\r
521 Return (Buffer () {0})\r
522 }\r
523 }\r
524 }\r
525}\r
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