SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support
[mirror_edk2.git] / SecurityPkg / Tcg / Tcg2Smm / Tpm.asl
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1/** @file\r
2 The TPM2 definition block in ACPI table for TCG2 physical presence \r
3 and MemoryClear.\r
4\r
9a9fa14e 5Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>\r
447f73db 6(c)Copyright 2016 HP Development Company, L.P.<BR>\r
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7This program and the accompanying materials \r
8are licensed and made available under the terms and conditions of the BSD License \r
9which accompanies this distribution. The full text of the license may be found at \r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17DefinitionBlock (\r
18 "Tpm.aml",\r
19 "SSDT",\r
20 2,\r
21 "INTEL ",\r
22 "Tpm2Tabl",\r
23 0x1000\r
24 )\r
25{\r
26 Scope (\_SB)\r
27 {\r
28 Device (TPM)\r
29 {\r
30 //\r
31 // TCG2\r
32 //\r
9a9fa14e 33\r
73126ac2 34 //\r
9a9fa14e 35 // TAG for patching TPM2.0 _HID\r
73126ac2 36 //\r
9a9fa14e 37 Name (_HID, "NNNN0000")\r
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38\r
39 Name (_CID, "MSFT0101")\r
40\r
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41 //\r
42 // Readable name of this device, don't know if this way is correct yet\r
43 //\r
44 Name (_STR, Unicode ("TPM 2.0 Device"))\r
45\r
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46 //\r
47 // Operational region for Smi port access\r
48 //\r
49 OperationRegion (SMIP, SystemIO, 0xB2, 1)\r
50 Field (SMIP, ByteAcc, NoLock, Preserve)\r
51 { \r
52 IOB2, 8\r
53 }\r
54\r
55 //\r
56 // Operational region for TPM access\r
57 //\r
58 OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)\r
59 Field (TPMR, AnyAcc, NoLock, Preserve)\r
60 {\r
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61 ACC0, 8, // TPM_ACCESS_0\r
62 Offset(0x8),\r
63 INTE, 32, // TPM_INT_ENABLE_0\r
64 INTV, 8, // TPM_INT_VECTOR_0\r
65 Offset(0x10),\r
66 INTS, 32, // TPM_INT_STATUS_0\r
67 INTF, 32, // TPM_INTF_CAPABILITY_0\r
68 STS0, 32, // TPM_STS_0\r
69 Offset(0x24),\r
70 FIFO, 32, // TPM_DATA_FIFO_0\r
71 Offset(0x30),\r
72 TID0, 32, // TPM_INTERFACE_ID_0\r
73 // ignore the rest\r
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74 }\r
75\r
76 //\r
77 // Operational region for TPM support, TPM Physical Presence and TPM Memory Clear\r
78 // Region Offset 0xFFFF0000 and Length 0xF0 will be fixed in C code.\r
79 //\r
80 OperationRegion (TNVS, SystemMemory, 0xFFFF0000, 0xF0)\r
81 Field (TNVS, AnyAcc, NoLock, Preserve)\r
82 {\r
83 PPIN, 8, // Software SMI for Physical Presence Interface\r
84 PPIP, 32, // Used for save physical presence paramter\r
85 PPRP, 32, // Physical Presence request operation response\r
86 PPRQ, 32, // Physical Presence request operation\r
87 PPRM, 32, // Physical Presence request operation parameter\r
88 LPPR, 32, // Last Physical Presence request operation\r
89 FRET, 32, // Physical Presence function return code\r
90 MCIN, 8, // Software SMI for Memory Clear Interface\r
91 MCIP, 32, // Used for save the Mor paramter\r
92 MORD, 32, // Memory Overwrite Request Data\r
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93 MRET, 32, // Memory Overwrite function return code\r
94 UCRQ, 32 // Phyical Presence request operation to Get User Confirmation Status \r
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95 }\r
96\r
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97 Name(RESO, ResourceTemplate () {\r
98 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS)\r
99 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12}\r
100 })\r
101\r
102 //\r
103 // Return the resource consumed by TPM device.\r
104 //\r
105 Method(_CRS,0,Serialized)\r
106 {\r
107 Return(RESO)\r
108 }\r
109\r
110 //\r
111 // Set resources consumed by the TPM device. This is used to\r
112 // assign an interrupt number to the device. The input byte stream\r
113 // has to be the same as returned by _CRS (according to ACPI spec).\r
114 //\r
115 Method(_SRS,1,Serialized)\r
116 {\r
117 //\r
118 // Update resource descriptor\r
119 // Use the field name to identify the offsets in the argument\r
120 // buffer and RESO buffer.\r
121 //\r
122 CreateDWordField(Arg0, ^IRQ._INT, IRQ0)\r
123 CreateDWordField(RESO, ^IRQ._INT, LIRQ)\r
124 Store(IRQ0, LIRQ)\r
125\r
126 CreateBitField(Arg0, ^IRQ._HE, ITRG)\r
127 CreateBitField(RESO, ^IRQ._HE, LTRG)\r
128 Store(ITRG, LTRG)\r
129\r
130 CreateBitField(Arg0, ^IRQ._LL, ILVL)\r
131 CreateBitField(RESO, ^IRQ._LL, LLVL)\r
132 Store(ILVL, LLVL)\r
133\r
134 //\r
135 // Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest\r
136 // nibble.\r
137 // 0000 - FIFO interface as defined in PTP for TPM 2.0 is active\r
138 // 1111 - FIFO interface as defined in TIS1.3 is active\r
139 //\r
140 If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {\r
141 //\r
142 // If FIFO interface, interrupt vector register is\r
143 // available. TCG PTP specification allows only\r
144 // values 1..15 in this field. For other interrupts\r
145 // the field should stay 0.\r
146 //\r
147 If (LLess (IRQ0, 16)) {\r
148 Store (And(IRQ0, 0xF), INTV)\r
149 }\r
150 //\r
151 // Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4\r
152 // contains settings for interrupt polarity.\r
153 // The other bits of the byte enable individual interrupts.\r
154 // They should be all be zero, but to avoid changing the\r
155 // configuration, the other bits are be preserved.\r
156 // 00 - high level\r
157 // 01 - low level\r
158 // 10 - rising edge\r
159 // 11 - falling edge\r
160 //\r
161 // ACPI spec definitions:\r
162 // _HE: '1' is Edge, '0' is Level\r
163 // _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)\r
164 //\r
165 If (LEqual (ITRG, 1)) {\r
166 Or(INTE, 0x00000010, INTE)\r
167 } Else {\r
168 And(INTE, 0xFFFFFFEF, INTE)\r
169 }\r
170 if (LEqual (ILVL, 0)) {\r
171 Or(INTE, 0x00000008, INTE)\r
172 } Else {\r
173 And(INTE, 0xFFFFFFF7, INTE)\r
174 }\r
175 }\r
176 }\r
177\r
178 //\r
179 // Possible resource settings.\r
180 // The format of the data has to follow the same format as\r
181 // _CRS (according to ACPI spec).\r
182 //\r
183 Name (_PRS, ResourceTemplate() {\r
184 Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)\r
185 Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}\r
186 })\r
187\r
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188 Method (PTS, 1, Serialized)\r
189 { \r
190 //\r
191 // Detect Sx state for MOR, only S4, S5 need to handle\r
192 //\r
193 If (LAnd (LLess (Arg0, 6), LGreater (Arg0, 3)))\r
194 { \r
195 //\r
196 // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect.\r
197 //\r
198 If (LNot (And (MORD, 0x10)))\r
199 {\r
200 //\r
201 // Triggle the SMI through ACPI _PTS method.\r
202 //\r
203 Store (0x02, MCIP)\r
204 \r
205 //\r
206 // Triggle the SMI interrupt\r
207 //\r
208 Store (MCIN, IOB2)\r
209 }\r
210 }\r
211 Return (0)\r
212 } \r
213\r
214 Method (_STA, 0)\r
215 {\r
216 if (LEqual (ACC0, 0xff))\r
217 {\r
218 Return (0)\r
219 }\r
220 Return (0x0f)\r
221 }\r
222\r
223 //\r
224 // TCG Hardware Information\r
225 //\r
226 Method (HINF, 3, Serialized, 0, {BuffObj, PkgObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
227 {\r
228 //\r
229 // Switch by function index\r
230 //\r
231 Switch (ToInteger(Arg1))\r
232 {\r
233 Case (0)\r
234 {\r
235 //\r
236 // Standard query\r
237 //\r
238 Return (Buffer () {0x03})\r
239 }\r
240 Case (1)\r
241 {\r
242 //\r
243 // Return failure if no TPM present\r
244 //\r
245 Name(TPMV, Package () {0x01, Package () {0x2, 0x0}})\r
246 if (LEqual (_STA (), 0x00))\r
247 {\r
248 Return (Package () {0x00})\r
249 }\r
250\r
251 //\r
252 // Return TPM version\r
253 //\r
254 Return (TPMV)\r
255 }\r
256 Default {BreakPoint}\r
257 }\r
258 Return (Buffer () {0})\r
259 }\r
260\r
261 Name(TPM2, Package (0x02){\r
262 Zero, \r
263 Zero\r
264 })\r
265\r
266 Name(TPM3, Package (0x03){\r
267 Zero, \r
268 Zero,\r
269 Zero\r
270 })\r
271\r
272 //\r
273 // TCG Physical Presence Interface\r
274 //\r
275 Method (TPPI, 3, Serialized, 0, {BuffObj, PkgObj, IntObj, StrObj}, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
276 { \r
277 //\r
278 // Switch by function index\r
279 //\r
280 Switch (ToInteger(Arg1))\r
281 {\r
282 Case (0)\r
283 {\r
284 //\r
285 // Standard query, supports function 1-8\r
286 //\r
287 Return (Buffer () {0xFF, 0x01})\r
288 }\r
289 Case (1)\r
290 {\r
291 //\r
292 // a) Get Physical Presence Interface Version\r
293 //\r
cd643013 294 Return ("$PV")\r
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295 }\r
296 Case (2)\r
297 {\r
298 //\r
299 // b) Submit TPM Operation Request to Pre-OS Environment\r
300 //\r
301 \r
302 Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
edb0fda2 303 Store (0, PPRM)\r
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304 Store (0x02, PPIP)\r
305 \r
306 //\r
307 // Triggle the SMI interrupt\r
308 //\r
309 Store (PPIN, IOB2)\r
310 Return (FRET)\r
311\r
312\r
313 }\r
314 Case (3)\r
315 {\r
316 //\r
317 // c) Get Pending TPM Operation Requested By the OS\r
318 //\r
319 \r
320 Store (PPRQ, Index (TPM2, 0x01))\r
321 Return (TPM2)\r
322 }\r
323 Case (4)\r
324 {\r
325 //\r
326 // d) Get Platform-Specific Action to Transition to Pre-OS Environment\r
327 //\r
328 Return (2)\r
329 }\r
330 Case (5)\r
331 {\r
332 //\r
333 // e) Return TPM Operation Response to OS Environment\r
334 //\r
335 Store (0x05, PPIP)\r
336 \r
337 //\r
338 // Triggle the SMI interrupt\r
339 //\r
340 Store (PPIN, IOB2)\r
341 \r
342 Store (LPPR, Index (TPM3, 0x01))\r
343 Store (PPRP, Index (TPM3, 0x02))\r
344\r
345 Return (TPM3)\r
346 }\r
347 Case (6)\r
348 {\r
349\r
350 //\r
351 // f) Submit preferred user language (Not implemented)\r
352 //\r
353\r
354 Return (3)\r
355\r
356 }\r
357 Case (7)\r
358 {\r
359 //\r
360 // g) Submit TPM Operation Request to Pre-OS Environment 2\r
361 //\r
362 Store (7, PPIP)\r
363 Store (DerefOf (Index (Arg2, 0x00)), PPRQ)\r
364 Store (0, PPRM)\r
365 If (LEqual (PPRQ, 23)) {\r
366 Store (DerefOf (Index (Arg2, 0x01)), PPRM)\r
367 }\r
368 \r
369 //\r
370 // Triggle the SMI interrupt \r
371 //\r
372 Store (PPIN, IOB2) \r
373 Return (FRET)\r
374 }\r
375 Case (8)\r
376 {\r
377 //\r
378 // e) Get User Confirmation Status for Operation\r
379 //\r
380 Store (8, PPIP)\r
053f31e3 381 Store (DerefOf (Index (Arg2, 0x00)), UCRQ)\r
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382 \r
383 //\r
384 // Triggle the SMI interrupt\r
385 //\r
386 Store (PPIN, IOB2)\r
387 \r
388 Return (FRET)\r
389 }\r
390\r
391 Default {BreakPoint}\r
392 }\r
393 Return (1)\r
394 }\r
395\r
396 Method (TMCI, 3, Serialized, 0, IntObj, {UnknownObj, UnknownObj, UnknownObj}) // IntObj, IntObj, PkgObj\r
397 {\r
398 //\r
399 // Switch by function index\r
400 //\r
401 Switch (ToInteger (Arg1))\r
402 {\r
403 Case (0)\r
404 {\r
405 //\r
406 // Standard query, supports function 1-1\r
407 //\r
408 Return (Buffer () {0x03})\r
409 }\r
410 Case (1)\r
411 {\r
412 //\r
413 // Save the Operation Value of the Request to MORD (reserved memory)\r
414 //\r
415 Store (DerefOf (Index (Arg2, 0x00)), MORD)\r
416 \r
417 //\r
418 // Triggle the SMI through ACPI _DSM method.\r
419 //\r
420 Store (0x01, MCIP)\r
421 \r
422 //\r
423 // Triggle the SMI interrupt\r
424 //\r
425 Store (MCIN, IOB2)\r
426 Return (MRET)\r
427 }\r
428 Default {BreakPoint}\r
429 }\r
430 Return (1) \r
431 }\r
432\r
433 Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
434 {\r
435\r
436 //\r
437 // TCG Hardware Information\r
438 //\r
439 If(LEqual(Arg0, ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8")))\r
440 {\r
441 Return (HINF (Arg1, Arg2, Arg3))\r
442 }\r
443\r
444 //\r
445 // TCG Physical Presence Interface\r
446 //\r
447 If(LEqual(Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653")))\r
448 {\r
449 Return (TPPI (Arg1, Arg2, Arg3))\r
450 }\r
451\r
452 //\r
453 // TCG Memory Clear Interface\r
454 //\r
455 If(LEqual(Arg0, ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))\r
456 {\r
457 Return (TMCI (Arg1, Arg2, Arg3))\r
458 }\r
459\r
460 Return (Buffer () {0})\r
461 }\r
462 }\r
463 }\r
464}\r