]>
Commit | Line | Data |
---|---|---|
5d73d92f | 1 | /** @file\r |
2 | Main file for Pci shell Debug1 function.\r | |
3 | \r | |
42fe8ca4 | 4 | Copyright (c) 2005 - 2021, Intel Corporation. All rights reserved.<BR>\r |
231ad7d8 | 5 | (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r |
ba0014b9 | 6 | (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r |
56ba3746 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
5d73d92f | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | #include "UefiShellDebug1CommandsLib.h"\r | |
12 | #include <Protocol/PciRootBridgeIo.h>\r | |
13 | #include <Library/ShellLib.h>\r | |
14 | #include <IndustryStandard/Pci.h>\r | |
15 | #include <IndustryStandard/Acpi.h>\r | |
16 | #include "Pci.h"\r | |
17 | \r | |
5d73d92f | 18 | //\r |
19 | // Printable strings for Pci class code\r | |
20 | //\r | |
21 | typedef struct {\r | |
47d20b54 MK |
22 | CHAR16 *BaseClass; // Pointer to the PCI base class string\r |
23 | CHAR16 *SubClass; // Pointer to the PCI sub class string\r | |
24 | CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r | |
5d73d92f | 25 | } PCI_CLASS_STRINGS;\r |
26 | \r | |
27 | //\r | |
28 | // a structure holding a single entry, which also points to its lower level\r | |
29 | // class\r | |
30 | //\r | |
31 | typedef struct PCI_CLASS_ENTRY_TAG {\r | |
47d20b54 MK |
32 | UINT8 Code; // Class, subclass or I/F code\r |
33 | CHAR16 *DescText; // Description string\r | |
34 | struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r | |
5d73d92f | 35 | } PCI_CLASS_ENTRY;\r |
36 | \r | |
37 | //\r | |
38 | // Declarations of entries which contain printable strings for class codes\r | |
39 | // in PCI configuration space\r | |
40 | //\r | |
47d20b54 MK |
41 | PCI_CLASS_ENTRY PCIBlankEntry[];\r |
42 | PCI_CLASS_ENTRY PCISubClass_00[];\r | |
43 | PCI_CLASS_ENTRY PCISubClass_01[];\r | |
44 | PCI_CLASS_ENTRY PCISubClass_02[];\r | |
45 | PCI_CLASS_ENTRY PCISubClass_03[];\r | |
46 | PCI_CLASS_ENTRY PCISubClass_04[];\r | |
47 | PCI_CLASS_ENTRY PCISubClass_05[];\r | |
48 | PCI_CLASS_ENTRY PCISubClass_06[];\r | |
49 | PCI_CLASS_ENTRY PCISubClass_07[];\r | |
50 | PCI_CLASS_ENTRY PCISubClass_08[];\r | |
51 | PCI_CLASS_ENTRY PCISubClass_09[];\r | |
52 | PCI_CLASS_ENTRY PCISubClass_0a[];\r | |
53 | PCI_CLASS_ENTRY PCISubClass_0b[];\r | |
54 | PCI_CLASS_ENTRY PCISubClass_0c[];\r | |
55 | PCI_CLASS_ENTRY PCISubClass_0d[];\r | |
56 | PCI_CLASS_ENTRY PCISubClass_0e[];\r | |
57 | PCI_CLASS_ENTRY PCISubClass_0f[];\r | |
58 | PCI_CLASS_ENTRY PCISubClass_10[];\r | |
59 | PCI_CLASS_ENTRY PCISubClass_11[];\r | |
60 | PCI_CLASS_ENTRY PCISubClass_12[];\r | |
61 | PCI_CLASS_ENTRY PCISubClass_13[];\r | |
62 | PCI_CLASS_ENTRY PCIPIFClass_0100[];\r | |
63 | PCI_CLASS_ENTRY PCIPIFClass_0101[];\r | |
64 | PCI_CLASS_ENTRY PCIPIFClass_0105[];\r | |
65 | PCI_CLASS_ENTRY PCIPIFClass_0106[];\r | |
66 | PCI_CLASS_ENTRY PCIPIFClass_0107[];\r | |
67 | PCI_CLASS_ENTRY PCIPIFClass_0108[];\r | |
68 | PCI_CLASS_ENTRY PCIPIFClass_0109[];\r | |
69 | PCI_CLASS_ENTRY PCIPIFClass_0300[];\r | |
70 | PCI_CLASS_ENTRY PCIPIFClass_0604[];\r | |
71 | PCI_CLASS_ENTRY PCIPIFClass_0609[];\r | |
72 | PCI_CLASS_ENTRY PCIPIFClass_060b[];\r | |
73 | PCI_CLASS_ENTRY PCIPIFClass_0700[];\r | |
74 | PCI_CLASS_ENTRY PCIPIFClass_0701[];\r | |
75 | PCI_CLASS_ENTRY PCIPIFClass_0703[];\r | |
76 | PCI_CLASS_ENTRY PCIPIFClass_0800[];\r | |
77 | PCI_CLASS_ENTRY PCIPIFClass_0801[];\r | |
78 | PCI_CLASS_ENTRY PCIPIFClass_0802[];\r | |
79 | PCI_CLASS_ENTRY PCIPIFClass_0803[];\r | |
80 | PCI_CLASS_ENTRY PCIPIFClass_0904[];\r | |
81 | PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r | |
82 | PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r | |
83 | PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r | |
84 | PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r | |
85 | PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r | |
5d73d92f | 86 | \r |
87 | //\r | |
88 | // Base class strings entries\r | |
89 | //\r | |
47d20b54 | 90 | PCI_CLASS_ENTRY gClassStringList[] = {\r |
5d73d92f | 91 | {\r |
92 | 0x00,\r | |
93 | L"Pre 2.0 device",\r | |
94 | PCISubClass_00\r | |
95 | },\r | |
96 | {\r | |
97 | 0x01,\r | |
98 | L"Mass Storage Controller",\r | |
99 | PCISubClass_01\r | |
100 | },\r | |
101 | {\r | |
102 | 0x02,\r | |
103 | L"Network Controller",\r | |
104 | PCISubClass_02\r | |
105 | },\r | |
106 | {\r | |
107 | 0x03,\r | |
108 | L"Display Controller",\r | |
109 | PCISubClass_03\r | |
110 | },\r | |
111 | {\r | |
112 | 0x04,\r | |
113 | L"Multimedia Device",\r | |
114 | PCISubClass_04\r | |
115 | },\r | |
116 | {\r | |
117 | 0x05,\r | |
118 | L"Memory Controller",\r | |
119 | PCISubClass_05\r | |
120 | },\r | |
121 | {\r | |
122 | 0x06,\r | |
123 | L"Bridge Device",\r | |
124 | PCISubClass_06\r | |
125 | },\r | |
126 | {\r | |
127 | 0x07,\r | |
128 | L"Simple Communications Controllers",\r | |
129 | PCISubClass_07\r | |
130 | },\r | |
131 | {\r | |
132 | 0x08,\r | |
133 | L"Base System Peripherals",\r | |
134 | PCISubClass_08\r | |
135 | },\r | |
136 | {\r | |
137 | 0x09,\r | |
138 | L"Input Devices",\r | |
139 | PCISubClass_09\r | |
140 | },\r | |
141 | {\r | |
142 | 0x0a,\r | |
143 | L"Docking Stations",\r | |
144 | PCISubClass_0a\r | |
145 | },\r | |
146 | {\r | |
147 | 0x0b,\r | |
148 | L"Processors",\r | |
149 | PCISubClass_0b\r | |
150 | },\r | |
151 | {\r | |
152 | 0x0c,\r | |
153 | L"Serial Bus Controllers",\r | |
154 | PCISubClass_0c\r | |
155 | },\r | |
156 | {\r | |
157 | 0x0d,\r | |
158 | L"Wireless Controllers",\r | |
159 | PCISubClass_0d\r | |
160 | },\r | |
161 | {\r | |
162 | 0x0e,\r | |
163 | L"Intelligent IO Controllers",\r | |
164 | PCISubClass_0e\r | |
165 | },\r | |
166 | {\r | |
167 | 0x0f,\r | |
168 | L"Satellite Communications Controllers",\r | |
169 | PCISubClass_0f\r | |
170 | },\r | |
171 | {\r | |
172 | 0x10,\r | |
173 | L"Encryption/Decryption Controllers",\r | |
174 | PCISubClass_10\r | |
175 | },\r | |
176 | {\r | |
177 | 0x11,\r | |
178 | L"Data Acquisition & Signal Processing Controllers",\r | |
179 | PCISubClass_11\r | |
180 | },\r | |
f056e4c1 JC |
181 | {\r |
182 | 0x12,\r | |
183 | L"Processing Accelerators",\r | |
184 | PCISubClass_12\r | |
185 | },\r | |
186 | {\r | |
187 | 0x13,\r | |
188 | L"Non-Essential Instrumentation",\r | |
189 | PCISubClass_13\r | |
190 | },\r | |
5d73d92f | 191 | {\r |
192 | 0xff,\r | |
193 | L"Device does not fit in any defined classes",\r | |
194 | PCIBlankEntry\r | |
195 | },\r | |
196 | {\r | |
197 | 0x00,\r | |
198 | NULL,\r | |
47d20b54 | 199 | /* null string ends the list */ NULL\r |
5d73d92f | 200 | }\r |
201 | };\r | |
202 | \r | |
203 | //\r | |
204 | // Subclass strings entries\r | |
205 | //\r | |
47d20b54 | 206 | PCI_CLASS_ENTRY PCIBlankEntry[] = {\r |
5d73d92f | 207 | {\r |
208 | 0x00,\r | |
209 | L"",\r | |
210 | PCIBlankEntry\r | |
211 | },\r | |
212 | {\r | |
213 | 0x00,\r | |
214 | NULL,\r | |
47d20b54 | 215 | /* null string ends the list */ NULL\r |
5d73d92f | 216 | }\r |
217 | };\r | |
218 | \r | |
47d20b54 | 219 | PCI_CLASS_ENTRY PCISubClass_00[] = {\r |
5d73d92f | 220 | {\r |
221 | 0x00,\r | |
222 | L"All devices other than VGA",\r | |
223 | PCIBlankEntry\r | |
224 | },\r | |
225 | {\r | |
226 | 0x01,\r | |
227 | L"VGA-compatible devices",\r | |
228 | PCIBlankEntry\r | |
229 | },\r | |
230 | {\r | |
231 | 0x00,\r | |
232 | NULL,\r | |
47d20b54 | 233 | /* null string ends the list */ NULL\r |
5d73d92f | 234 | }\r |
235 | };\r | |
236 | \r | |
47d20b54 | 237 | PCI_CLASS_ENTRY PCISubClass_01[] = {\r |
5d73d92f | 238 | {\r |
239 | 0x00,\r | |
f056e4c1 JC |
240 | L"SCSI",\r |
241 | PCIPIFClass_0100\r | |
5d73d92f | 242 | },\r |
243 | {\r | |
244 | 0x01,\r | |
245 | L"IDE controller",\r | |
246 | PCIPIFClass_0101\r | |
247 | },\r | |
248 | {\r | |
249 | 0x02,\r | |
250 | L"Floppy disk controller",\r | |
251 | PCIBlankEntry\r | |
252 | },\r | |
253 | {\r | |
254 | 0x03,\r | |
255 | L"IPI controller",\r | |
256 | PCIBlankEntry\r | |
257 | },\r | |
258 | {\r | |
259 | 0x04,\r | |
260 | L"RAID controller",\r | |
261 | PCIBlankEntry\r | |
262 | },\r | |
f056e4c1 JC |
263 | {\r |
264 | 0x05,\r | |
265 | L"ATA controller with ADMA interface",\r | |
266 | PCIPIFClass_0105\r | |
267 | },\r | |
268 | {\r | |
269 | 0x06,\r | |
270 | L"Serial ATA controller",\r | |
271 | PCIPIFClass_0106\r | |
272 | },\r | |
273 | {\r | |
274 | 0x07,\r | |
275 | L"Serial Attached SCSI (SAS) controller ",\r | |
276 | PCIPIFClass_0107\r | |
277 | },\r | |
278 | {\r | |
279 | 0x08,\r | |
280 | L"Non-volatile memory subsystem",\r | |
281 | PCIPIFClass_0108\r | |
282 | },\r | |
283 | {\r | |
284 | 0x09,\r | |
285 | L"Universal Flash Storage (UFS) controller ",\r | |
286 | PCIPIFClass_0109\r | |
287 | },\r | |
5d73d92f | 288 | {\r |
289 | 0x80,\r | |
290 | L"Other mass storage controller",\r | |
291 | PCIBlankEntry\r | |
292 | },\r | |
293 | {\r | |
294 | 0x00,\r | |
295 | NULL,\r | |
47d20b54 | 296 | /* null string ends the list */ NULL\r |
5d73d92f | 297 | }\r |
298 | };\r | |
299 | \r | |
47d20b54 | 300 | PCI_CLASS_ENTRY PCISubClass_02[] = {\r |
5d73d92f | 301 | {\r |
302 | 0x00,\r | |
303 | L"Ethernet controller",\r | |
304 | PCIBlankEntry\r | |
305 | },\r | |
306 | {\r | |
307 | 0x01,\r | |
308 | L"Token ring controller",\r | |
309 | PCIBlankEntry\r | |
310 | },\r | |
311 | {\r | |
312 | 0x02,\r | |
313 | L"FDDI controller",\r | |
314 | PCIBlankEntry\r | |
315 | },\r | |
316 | {\r | |
317 | 0x03,\r | |
318 | L"ATM controller",\r | |
319 | PCIBlankEntry\r | |
320 | },\r | |
321 | {\r | |
322 | 0x04,\r | |
323 | L"ISDN controller",\r | |
324 | PCIBlankEntry\r | |
325 | },\r | |
f056e4c1 JC |
326 | {\r |
327 | 0x05,\r | |
328 | L"WorldFip controller",\r | |
329 | PCIBlankEntry\r | |
330 | },\r | |
331 | {\r | |
332 | 0x06,\r | |
333 | L"PICMG 2.14 Multi Computing",\r | |
334 | PCIBlankEntry\r | |
335 | },\r | |
336 | {\r | |
337 | 0x07,\r | |
338 | L"InfiniBand controller",\r | |
339 | PCIBlankEntry\r | |
340 | },\r | |
5d73d92f | 341 | {\r |
342 | 0x80,\r | |
343 | L"Other network controller",\r | |
344 | PCIBlankEntry\r | |
345 | },\r | |
346 | {\r | |
347 | 0x00,\r | |
348 | NULL,\r | |
47d20b54 | 349 | /* null string ends the list */ NULL\r |
5d73d92f | 350 | }\r |
351 | };\r | |
352 | \r | |
47d20b54 | 353 | PCI_CLASS_ENTRY PCISubClass_03[] = {\r |
5d73d92f | 354 | {\r |
355 | 0x00,\r | |
356 | L"VGA/8514 controller",\r | |
357 | PCIPIFClass_0300\r | |
358 | },\r | |
359 | {\r | |
360 | 0x01,\r | |
361 | L"XGA controller",\r | |
362 | PCIBlankEntry\r | |
363 | },\r | |
364 | {\r | |
365 | 0x02,\r | |
366 | L"3D controller",\r | |
367 | PCIBlankEntry\r | |
368 | },\r | |
369 | {\r | |
370 | 0x80,\r | |
371 | L"Other display controller",\r | |
372 | PCIBlankEntry\r | |
373 | },\r | |
374 | {\r | |
375 | 0x00,\r | |
376 | NULL,\r | |
47d20b54 | 377 | /* null string ends the list */ PCIBlankEntry\r |
5d73d92f | 378 | }\r |
379 | };\r | |
380 | \r | |
47d20b54 | 381 | PCI_CLASS_ENTRY PCISubClass_04[] = {\r |
5d73d92f | 382 | {\r |
383 | 0x00,\r | |
384 | L"Video device",\r | |
385 | PCIBlankEntry\r | |
386 | },\r | |
387 | {\r | |
388 | 0x01,\r | |
389 | L"Audio device",\r | |
390 | PCIBlankEntry\r | |
391 | },\r | |
392 | {\r | |
393 | 0x02,\r | |
394 | L"Computer Telephony device",\r | |
395 | PCIBlankEntry\r | |
396 | },\r | |
f056e4c1 JC |
397 | {\r |
398 | 0x03,\r | |
399 | L"Mixed mode device",\r | |
400 | PCIBlankEntry\r | |
401 | },\r | |
5d73d92f | 402 | {\r |
403 | 0x80,\r | |
404 | L"Other multimedia device",\r | |
405 | PCIBlankEntry\r | |
406 | },\r | |
407 | {\r | |
408 | 0x00,\r | |
409 | NULL,\r | |
47d20b54 | 410 | /* null string ends the list */ NULL\r |
5d73d92f | 411 | }\r |
412 | };\r | |
413 | \r | |
47d20b54 | 414 | PCI_CLASS_ENTRY PCISubClass_05[] = {\r |
5d73d92f | 415 | {\r |
416 | 0x00,\r | |
417 | L"RAM memory controller",\r | |
418 | PCIBlankEntry\r | |
419 | },\r | |
420 | {\r | |
421 | 0x01,\r | |
422 | L"Flash memory controller",\r | |
423 | PCIBlankEntry\r | |
424 | },\r | |
425 | {\r | |
426 | 0x80,\r | |
427 | L"Other memory controller",\r | |
428 | PCIBlankEntry\r | |
429 | },\r | |
430 | {\r | |
431 | 0x00,\r | |
432 | NULL,\r | |
47d20b54 | 433 | /* null string ends the list */ NULL\r |
5d73d92f | 434 | }\r |
435 | };\r | |
436 | \r | |
47d20b54 | 437 | PCI_CLASS_ENTRY PCISubClass_06[] = {\r |
5d73d92f | 438 | {\r |
439 | 0x00,\r | |
440 | L"Host/PCI bridge",\r | |
441 | PCIBlankEntry\r | |
442 | },\r | |
443 | {\r | |
444 | 0x01,\r | |
445 | L"PCI/ISA bridge",\r | |
446 | PCIBlankEntry\r | |
447 | },\r | |
448 | {\r | |
449 | 0x02,\r | |
450 | L"PCI/EISA bridge",\r | |
451 | PCIBlankEntry\r | |
452 | },\r | |
453 | {\r | |
454 | 0x03,\r | |
455 | L"PCI/Micro Channel bridge",\r | |
456 | PCIBlankEntry\r | |
457 | },\r | |
458 | {\r | |
459 | 0x04,\r | |
460 | L"PCI/PCI bridge",\r | |
461 | PCIPIFClass_0604\r | |
462 | },\r | |
463 | {\r | |
464 | 0x05,\r | |
465 | L"PCI/PCMCIA bridge",\r | |
466 | PCIBlankEntry\r | |
467 | },\r | |
468 | {\r | |
469 | 0x06,\r | |
470 | L"NuBus bridge",\r | |
471 | PCIBlankEntry\r | |
472 | },\r | |
473 | {\r | |
474 | 0x07,\r | |
475 | L"CardBus bridge",\r | |
476 | PCIBlankEntry\r | |
477 | },\r | |
478 | {\r | |
479 | 0x08,\r | |
480 | L"RACEway bridge",\r | |
481 | PCIBlankEntry\r | |
482 | },\r | |
f056e4c1 JC |
483 | {\r |
484 | 0x09,\r | |
485 | L"Semi-transparent PCI-to-PCI bridge",\r | |
486 | PCIPIFClass_0609\r | |
487 | },\r | |
488 | {\r | |
489 | 0x0A,\r | |
490 | L"InfiniBand-to-PCI host bridge",\r | |
491 | PCIBlankEntry\r | |
492 | },\r | |
493 | {\r | |
494 | 0x0B,\r | |
495 | L"Advanced Switching to PCI host bridge",\r | |
496 | PCIPIFClass_060b\r | |
497 | },\r | |
5d73d92f | 498 | {\r |
499 | 0x80,\r | |
500 | L"Other bridge type",\r | |
501 | PCIBlankEntry\r | |
502 | },\r | |
503 | {\r | |
504 | 0x00,\r | |
505 | NULL,\r | |
47d20b54 | 506 | /* null string ends the list */ NULL\r |
5d73d92f | 507 | }\r |
508 | };\r | |
509 | \r | |
47d20b54 | 510 | PCI_CLASS_ENTRY PCISubClass_07[] = {\r |
5d73d92f | 511 | {\r |
512 | 0x00,\r | |
513 | L"Serial controller",\r | |
514 | PCIPIFClass_0700\r | |
515 | },\r | |
516 | {\r | |
517 | 0x01,\r | |
518 | L"Parallel port",\r | |
519 | PCIPIFClass_0701\r | |
520 | },\r | |
521 | {\r | |
522 | 0x02,\r | |
523 | L"Multiport serial controller",\r | |
524 | PCIBlankEntry\r | |
525 | },\r | |
526 | {\r | |
527 | 0x03,\r | |
528 | L"Modem",\r | |
529 | PCIPIFClass_0703\r | |
530 | },\r | |
f056e4c1 JC |
531 | {\r |
532 | 0x04,\r | |
533 | L"GPIB (IEEE 488.1/2) controller",\r | |
534 | PCIBlankEntry\r | |
535 | },\r | |
536 | {\r | |
537 | 0x05,\r | |
538 | L"Smart Card",\r | |
539 | PCIBlankEntry\r | |
540 | },\r | |
5d73d92f | 541 | {\r |
542 | 0x80,\r | |
543 | L"Other communication device",\r | |
544 | PCIBlankEntry\r | |
545 | },\r | |
546 | {\r | |
547 | 0x00,\r | |
548 | NULL,\r | |
47d20b54 | 549 | /* null string ends the list */ NULL\r |
5d73d92f | 550 | }\r |
551 | };\r | |
552 | \r | |
47d20b54 | 553 | PCI_CLASS_ENTRY PCISubClass_08[] = {\r |
5d73d92f | 554 | {\r |
555 | 0x00,\r | |
556 | L"PIC",\r | |
557 | PCIPIFClass_0800\r | |
558 | },\r | |
559 | {\r | |
560 | 0x01,\r | |
561 | L"DMA controller",\r | |
562 | PCIPIFClass_0801\r | |
563 | },\r | |
564 | {\r | |
565 | 0x02,\r | |
566 | L"System timer",\r | |
567 | PCIPIFClass_0802\r | |
568 | },\r | |
569 | {\r | |
570 | 0x03,\r | |
571 | L"RTC controller",\r | |
572 | PCIPIFClass_0803\r | |
573 | },\r | |
574 | {\r | |
575 | 0x04,\r | |
576 | L"Generic PCI Hot-Plug controller",\r | |
577 | PCIBlankEntry\r | |
578 | },\r | |
f056e4c1 JC |
579 | {\r |
580 | 0x05,\r | |
581 | L"SD Host controller",\r | |
582 | PCIBlankEntry\r | |
583 | },\r | |
584 | {\r | |
585 | 0x06,\r | |
586 | L"IOMMU",\r | |
587 | PCIBlankEntry\r | |
588 | },\r | |
589 | {\r | |
590 | 0x07,\r | |
591 | L"Root Complex Event Collector",\r | |
592 | PCIBlankEntry\r | |
593 | },\r | |
5d73d92f | 594 | {\r |
595 | 0x80,\r | |
596 | L"Other system peripheral",\r | |
597 | PCIBlankEntry\r | |
598 | },\r | |
599 | {\r | |
600 | 0x00,\r | |
601 | NULL,\r | |
47d20b54 | 602 | /* null string ends the list */ NULL\r |
5d73d92f | 603 | }\r |
604 | };\r | |
605 | \r | |
47d20b54 | 606 | PCI_CLASS_ENTRY PCISubClass_09[] = {\r |
5d73d92f | 607 | {\r |
608 | 0x00,\r | |
609 | L"Keyboard controller",\r | |
610 | PCIBlankEntry\r | |
611 | },\r | |
612 | {\r | |
613 | 0x01,\r | |
614 | L"Digitizer (pen)",\r | |
615 | PCIBlankEntry\r | |
616 | },\r | |
617 | {\r | |
618 | 0x02,\r | |
619 | L"Mouse controller",\r | |
620 | PCIBlankEntry\r | |
621 | },\r | |
622 | {\r | |
623 | 0x03,\r | |
624 | L"Scanner controller",\r | |
625 | PCIBlankEntry\r | |
626 | },\r | |
627 | {\r | |
628 | 0x04,\r | |
629 | L"Gameport controller",\r | |
630 | PCIPIFClass_0904\r | |
631 | },\r | |
632 | {\r | |
633 | 0x80,\r | |
634 | L"Other input controller",\r | |
635 | PCIBlankEntry\r | |
636 | },\r | |
637 | {\r | |
638 | 0x00,\r | |
639 | NULL,\r | |
47d20b54 | 640 | /* null string ends the list */ NULL\r |
5d73d92f | 641 | }\r |
642 | };\r | |
643 | \r | |
47d20b54 | 644 | PCI_CLASS_ENTRY PCISubClass_0a[] = {\r |
5d73d92f | 645 | {\r |
646 | 0x00,\r | |
647 | L"Generic docking station",\r | |
648 | PCIBlankEntry\r | |
649 | },\r | |
650 | {\r | |
651 | 0x80,\r | |
652 | L"Other type of docking station",\r | |
653 | PCIBlankEntry\r | |
654 | },\r | |
655 | {\r | |
656 | 0x00,\r | |
657 | NULL,\r | |
47d20b54 | 658 | /* null string ends the list */ NULL\r |
5d73d92f | 659 | }\r |
660 | };\r | |
661 | \r | |
47d20b54 | 662 | PCI_CLASS_ENTRY PCISubClass_0b[] = {\r |
5d73d92f | 663 | {\r |
664 | 0x00,\r | |
665 | L"386",\r | |
666 | PCIBlankEntry\r | |
667 | },\r | |
668 | {\r | |
669 | 0x01,\r | |
670 | L"486",\r | |
671 | PCIBlankEntry\r | |
672 | },\r | |
673 | {\r | |
674 | 0x02,\r | |
675 | L"Pentium",\r | |
676 | PCIBlankEntry\r | |
677 | },\r | |
678 | {\r | |
679 | 0x10,\r | |
680 | L"Alpha",\r | |
681 | PCIBlankEntry\r | |
682 | },\r | |
683 | {\r | |
684 | 0x20,\r | |
685 | L"PowerPC",\r | |
686 | PCIBlankEntry\r | |
687 | },\r | |
688 | {\r | |
689 | 0x30,\r | |
690 | L"MIPS",\r | |
691 | PCIBlankEntry\r | |
692 | },\r | |
693 | {\r | |
694 | 0x40,\r | |
695 | L"Co-processor",\r | |
696 | PCIBlankEntry\r | |
697 | },\r | |
698 | {\r | |
699 | 0x80,\r | |
700 | L"Other processor",\r | |
701 | PCIBlankEntry\r | |
702 | },\r | |
703 | {\r | |
704 | 0x00,\r | |
705 | NULL,\r | |
47d20b54 | 706 | /* null string ends the list */ NULL\r |
5d73d92f | 707 | }\r |
708 | };\r | |
709 | \r | |
47d20b54 | 710 | PCI_CLASS_ENTRY PCISubClass_0c[] = {\r |
5d73d92f | 711 | {\r |
712 | 0x00,\r | |
f056e4c1 JC |
713 | L"IEEE 1394",\r |
714 | PCIPIFClass_0c00\r | |
5d73d92f | 715 | },\r |
716 | {\r | |
717 | 0x01,\r | |
718 | L"ACCESS.bus",\r | |
719 | PCIBlankEntry\r | |
720 | },\r | |
721 | {\r | |
722 | 0x02,\r | |
723 | L"SSA",\r | |
724 | PCIBlankEntry\r | |
725 | },\r | |
726 | {\r | |
727 | 0x03,\r | |
728 | L"USB",\r | |
f056e4c1 | 729 | PCIPIFClass_0c03\r |
5d73d92f | 730 | },\r |
731 | {\r | |
732 | 0x04,\r | |
733 | L"Fibre Channel",\r | |
734 | PCIBlankEntry\r | |
735 | },\r | |
736 | {\r | |
737 | 0x05,\r | |
738 | L"System Management Bus",\r | |
739 | PCIBlankEntry\r | |
740 | },\r | |
f056e4c1 JC |
741 | {\r |
742 | 0x06,\r | |
743 | L"InfiniBand",\r | |
744 | PCIBlankEntry\r | |
745 | },\r | |
746 | {\r | |
747 | 0x07,\r | |
748 | L"IPMI",\r | |
749 | PCIPIFClass_0c07\r | |
750 | },\r | |
751 | {\r | |
752 | 0x08,\r | |
753 | L"SERCOS Interface Standard (IEC 61491)",\r | |
754 | PCIBlankEntry\r | |
755 | },\r | |
756 | {\r | |
757 | 0x09,\r | |
758 | L"CANbus",\r | |
759 | PCIBlankEntry\r | |
760 | },\r | |
5d73d92f | 761 | {\r |
762 | 0x80,\r | |
763 | L"Other bus type",\r | |
764 | PCIBlankEntry\r | |
765 | },\r | |
766 | {\r | |
767 | 0x00,\r | |
768 | NULL,\r | |
47d20b54 | 769 | /* null string ends the list */ NULL\r |
5d73d92f | 770 | }\r |
771 | };\r | |
772 | \r | |
47d20b54 | 773 | PCI_CLASS_ENTRY PCISubClass_0d[] = {\r |
5d73d92f | 774 | {\r |
775 | 0x00,\r | |
776 | L"iRDA compatible controller",\r | |
777 | PCIBlankEntry\r | |
778 | },\r | |
779 | {\r | |
780 | 0x01,\r | |
f056e4c1 JC |
781 | L"",\r |
782 | PCIPIFClass_0d01\r | |
5d73d92f | 783 | },\r |
784 | {\r | |
785 | 0x10,\r | |
786 | L"RF controller",\r | |
787 | PCIBlankEntry\r | |
788 | },\r | |
f056e4c1 JC |
789 | {\r |
790 | 0x11,\r | |
791 | L"Bluetooth",\r | |
792 | PCIBlankEntry\r | |
793 | },\r | |
794 | {\r | |
795 | 0x12,\r | |
796 | L"Broadband",\r | |
797 | PCIBlankEntry\r | |
798 | },\r | |
799 | {\r | |
800 | 0x20,\r | |
59577231 | 801 | L"Ethernet (802.11a - 5 GHz)",\r |
f056e4c1 JC |
802 | PCIBlankEntry\r |
803 | },\r | |
804 | {\r | |
805 | 0x21,\r | |
59577231 | 806 | L"Ethernet (802.11b - 2.4 GHz)",\r |
f056e4c1 JC |
807 | PCIBlankEntry\r |
808 | },\r | |
5d73d92f | 809 | {\r |
810 | 0x80,\r | |
811 | L"Other type of wireless controller",\r | |
812 | PCIBlankEntry\r | |
813 | },\r | |
814 | {\r | |
815 | 0x00,\r | |
816 | NULL,\r | |
47d20b54 | 817 | /* null string ends the list */ NULL\r |
5d73d92f | 818 | }\r |
819 | };\r | |
820 | \r | |
47d20b54 | 821 | PCI_CLASS_ENTRY PCISubClass_0e[] = {\r |
5d73d92f | 822 | {\r |
823 | 0x00,\r | |
824 | L"I2O Architecture",\r | |
825 | PCIPIFClass_0e00\r | |
826 | },\r | |
827 | {\r | |
828 | 0x00,\r | |
829 | NULL,\r | |
47d20b54 | 830 | /* null string ends the list */ NULL\r |
5d73d92f | 831 | }\r |
832 | };\r | |
833 | \r | |
47d20b54 | 834 | PCI_CLASS_ENTRY PCISubClass_0f[] = {\r |
5d73d92f | 835 | {\r |
f056e4c1 | 836 | 0x01,\r |
5d73d92f | 837 | L"TV",\r |
838 | PCIBlankEntry\r | |
839 | },\r | |
840 | {\r | |
f056e4c1 | 841 | 0x02,\r |
5d73d92f | 842 | L"Audio",\r |
843 | PCIBlankEntry\r | |
844 | },\r | |
845 | {\r | |
f056e4c1 | 846 | 0x03,\r |
5d73d92f | 847 | L"Voice",\r |
848 | PCIBlankEntry\r | |
849 | },\r | |
850 | {\r | |
f056e4c1 | 851 | 0x04,\r |
5d73d92f | 852 | L"Data",\r |
853 | PCIBlankEntry\r | |
854 | },\r | |
f056e4c1 JC |
855 | {\r |
856 | 0x80,\r | |
857 | L"Other satellite communication controller",\r | |
858 | PCIBlankEntry\r | |
859 | },\r | |
5d73d92f | 860 | {\r |
861 | 0x00,\r | |
862 | NULL,\r | |
47d20b54 | 863 | /* null string ends the list */ NULL\r |
5d73d92f | 864 | }\r |
865 | };\r | |
866 | \r | |
47d20b54 | 867 | PCI_CLASS_ENTRY PCISubClass_10[] = {\r |
5d73d92f | 868 | {\r |
869 | 0x00,\r | |
870 | L"Network & computing Encrypt/Decrypt",\r | |
871 | PCIBlankEntry\r | |
872 | },\r | |
873 | {\r | |
874 | 0x01,\r | |
875 | L"Entertainment Encrypt/Decrypt",\r | |
876 | PCIBlankEntry\r | |
877 | },\r | |
878 | {\r | |
879 | 0x80,\r | |
880 | L"Other Encrypt/Decrypt",\r | |
881 | PCIBlankEntry\r | |
882 | },\r | |
883 | {\r | |
884 | 0x00,\r | |
885 | NULL,\r | |
47d20b54 | 886 | /* null string ends the list */ NULL\r |
5d73d92f | 887 | }\r |
888 | };\r | |
889 | \r | |
47d20b54 | 890 | PCI_CLASS_ENTRY PCISubClass_11[] = {\r |
5d73d92f | 891 | {\r |
892 | 0x00,\r | |
893 | L"DPIO modules",\r | |
894 | PCIBlankEntry\r | |
895 | },\r | |
f056e4c1 JC |
896 | {\r |
897 | 0x01,\r | |
898 | L"Performance Counters",\r | |
899 | PCIBlankEntry\r | |
900 | },\r | |
901 | {\r | |
902 | 0x10,\r | |
903 | L"Communications synchronization plus time and frequency test/measurement ",\r | |
904 | PCIBlankEntry\r | |
905 | },\r | |
906 | {\r | |
907 | 0x20,\r | |
908 | L"Management card",\r | |
909 | PCIBlankEntry\r | |
910 | },\r | |
5d73d92f | 911 | {\r |
912 | 0x80,\r | |
913 | L"Other DAQ & SP controllers",\r | |
914 | PCIBlankEntry\r | |
915 | },\r | |
916 | {\r | |
917 | 0x00,\r | |
918 | NULL,\r | |
47d20b54 | 919 | /* null string ends the list */ NULL\r |
5d73d92f | 920 | }\r |
921 | };\r | |
922 | \r | |
47d20b54 | 923 | PCI_CLASS_ENTRY PCISubClass_12[] = {\r |
f056e4c1 JC |
924 | {\r |
925 | 0x00,\r | |
926 | L"Processing Accelerator",\r | |
927 | PCIBlankEntry\r | |
928 | },\r | |
929 | {\r | |
930 | 0x00,\r | |
931 | NULL,\r | |
47d20b54 | 932 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
933 | }\r |
934 | };\r | |
935 | \r | |
47d20b54 | 936 | PCI_CLASS_ENTRY PCISubClass_13[] = {\r |
f056e4c1 JC |
937 | {\r |
938 | 0x00,\r | |
939 | L"Non-Essential Instrumentation Function",\r | |
940 | PCIBlankEntry\r | |
941 | },\r | |
942 | {\r | |
943 | 0x00,\r | |
944 | NULL,\r | |
47d20b54 | 945 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
946 | }\r |
947 | };\r | |
948 | \r | |
5d73d92f | 949 | //\r |
950 | // Programming Interface entries\r | |
951 | //\r | |
47d20b54 | 952 | PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r |
f056e4c1 JC |
953 | {\r |
954 | 0x00,\r | |
955 | L"SCSI controller",\r | |
956 | PCIBlankEntry\r | |
957 | },\r | |
958 | {\r | |
959 | 0x11,\r | |
960 | L"SCSI storage device SOP using PQI",\r | |
961 | PCIBlankEntry\r | |
962 | },\r | |
963 | {\r | |
964 | 0x12,\r | |
965 | L"SCSI controller SOP using PQI",\r | |
966 | PCIBlankEntry\r | |
967 | },\r | |
968 | {\r | |
969 | 0x13,\r | |
970 | L"SCSI storage device and controller SOP using PQI",\r | |
971 | PCIBlankEntry\r | |
972 | },\r | |
973 | {\r | |
974 | 0x21,\r | |
975 | L"SCSI storage device SOP using NVMe",\r | |
976 | PCIBlankEntry\r | |
977 | },\r | |
978 | {\r | |
979 | 0x00,\r | |
980 | NULL,\r | |
47d20b54 | 981 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
982 | }\r |
983 | };\r | |
984 | \r | |
47d20b54 | 985 | PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r |
5d73d92f | 986 | {\r |
987 | 0x00,\r | |
988 | L"",\r | |
989 | PCIBlankEntry\r | |
990 | },\r | |
991 | {\r | |
992 | 0x01,\r | |
993 | L"OM-primary",\r | |
994 | PCIBlankEntry\r | |
995 | },\r | |
996 | {\r | |
997 | 0x02,\r | |
998 | L"PI-primary",\r | |
999 | PCIBlankEntry\r | |
1000 | },\r | |
1001 | {\r | |
1002 | 0x03,\r | |
1003 | L"OM/PI-primary",\r | |
1004 | PCIBlankEntry\r | |
1005 | },\r | |
1006 | {\r | |
1007 | 0x04,\r | |
1008 | L"OM-secondary",\r | |
1009 | PCIBlankEntry\r | |
1010 | },\r | |
1011 | {\r | |
1012 | 0x05,\r | |
1013 | L"OM-primary, OM-secondary",\r | |
1014 | PCIBlankEntry\r | |
1015 | },\r | |
1016 | {\r | |
1017 | 0x06,\r | |
1018 | L"PI-primary, OM-secondary",\r | |
1019 | PCIBlankEntry\r | |
1020 | },\r | |
1021 | {\r | |
1022 | 0x07,\r | |
1023 | L"OM/PI-primary, OM-secondary",\r | |
1024 | PCIBlankEntry\r | |
1025 | },\r | |
1026 | {\r | |
1027 | 0x08,\r | |
1028 | L"OM-secondary",\r | |
1029 | PCIBlankEntry\r | |
1030 | },\r | |
1031 | {\r | |
1032 | 0x09,\r | |
1033 | L"OM-primary, PI-secondary",\r | |
1034 | PCIBlankEntry\r | |
1035 | },\r | |
1036 | {\r | |
1037 | 0x0a,\r | |
1038 | L"PI-primary, PI-secondary",\r | |
1039 | PCIBlankEntry\r | |
1040 | },\r | |
1041 | {\r | |
1042 | 0x0b,\r | |
1043 | L"OM/PI-primary, PI-secondary",\r | |
1044 | PCIBlankEntry\r | |
1045 | },\r | |
1046 | {\r | |
1047 | 0x0c,\r | |
1048 | L"OM-secondary",\r | |
1049 | PCIBlankEntry\r | |
1050 | },\r | |
1051 | {\r | |
1052 | 0x0d,\r | |
1053 | L"OM-primary, OM/PI-secondary",\r | |
1054 | PCIBlankEntry\r | |
1055 | },\r | |
1056 | {\r | |
1057 | 0x0e,\r | |
1058 | L"PI-primary, OM/PI-secondary",\r | |
1059 | PCIBlankEntry\r | |
1060 | },\r | |
1061 | {\r | |
1062 | 0x0f,\r | |
1063 | L"OM/PI-primary, OM/PI-secondary",\r | |
1064 | PCIBlankEntry\r | |
1065 | },\r | |
1066 | {\r | |
1067 | 0x80,\r | |
1068 | L"Master",\r | |
1069 | PCIBlankEntry\r | |
1070 | },\r | |
1071 | {\r | |
1072 | 0x81,\r | |
1073 | L"Master, OM-primary",\r | |
1074 | PCIBlankEntry\r | |
1075 | },\r | |
1076 | {\r | |
1077 | 0x82,\r | |
1078 | L"Master, PI-primary",\r | |
1079 | PCIBlankEntry\r | |
1080 | },\r | |
1081 | {\r | |
1082 | 0x83,\r | |
1083 | L"Master, OM/PI-primary",\r | |
1084 | PCIBlankEntry\r | |
1085 | },\r | |
1086 | {\r | |
1087 | 0x84,\r | |
1088 | L"Master, OM-secondary",\r | |
1089 | PCIBlankEntry\r | |
1090 | },\r | |
1091 | {\r | |
1092 | 0x85,\r | |
1093 | L"Master, OM-primary, OM-secondary",\r | |
1094 | PCIBlankEntry\r | |
1095 | },\r | |
1096 | {\r | |
1097 | 0x86,\r | |
1098 | L"Master, PI-primary, OM-secondary",\r | |
1099 | PCIBlankEntry\r | |
1100 | },\r | |
1101 | {\r | |
1102 | 0x87,\r | |
1103 | L"Master, OM/PI-primary, OM-secondary",\r | |
1104 | PCIBlankEntry\r | |
1105 | },\r | |
1106 | {\r | |
1107 | 0x88,\r | |
1108 | L"Master, OM-secondary",\r | |
1109 | PCIBlankEntry\r | |
1110 | },\r | |
1111 | {\r | |
1112 | 0x89,\r | |
1113 | L"Master, OM-primary, PI-secondary",\r | |
1114 | PCIBlankEntry\r | |
1115 | },\r | |
1116 | {\r | |
1117 | 0x8a,\r | |
1118 | L"Master, PI-primary, PI-secondary",\r | |
1119 | PCIBlankEntry\r | |
1120 | },\r | |
1121 | {\r | |
1122 | 0x8b,\r | |
1123 | L"Master, OM/PI-primary, PI-secondary",\r | |
1124 | PCIBlankEntry\r | |
1125 | },\r | |
1126 | {\r | |
1127 | 0x8c,\r | |
1128 | L"Master, OM-secondary",\r | |
1129 | PCIBlankEntry\r | |
1130 | },\r | |
1131 | {\r | |
1132 | 0x8d,\r | |
1133 | L"Master, OM-primary, OM/PI-secondary",\r | |
1134 | PCIBlankEntry\r | |
1135 | },\r | |
1136 | {\r | |
1137 | 0x8e,\r | |
1138 | L"Master, PI-primary, OM/PI-secondary",\r | |
1139 | PCIBlankEntry\r | |
1140 | },\r | |
1141 | {\r | |
1142 | 0x8f,\r | |
1143 | L"Master, OM/PI-primary, OM/PI-secondary",\r | |
1144 | PCIBlankEntry\r | |
1145 | },\r | |
1146 | {\r | |
1147 | 0x00,\r | |
1148 | NULL,\r | |
47d20b54 | 1149 | /* null string ends the list */ NULL\r |
5d73d92f | 1150 | }\r |
1151 | };\r | |
1152 | \r | |
47d20b54 | 1153 | PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r |
f056e4c1 JC |
1154 | {\r |
1155 | 0x20,\r | |
1156 | L"Single stepping",\r | |
1157 | PCIBlankEntry\r | |
1158 | },\r | |
1159 | {\r | |
1160 | 0x30,\r | |
1161 | L"Continuous operation",\r | |
1162 | PCIBlankEntry\r | |
1163 | },\r | |
1164 | {\r | |
1165 | 0x00,\r | |
1166 | NULL,\r | |
47d20b54 | 1167 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1168 | }\r |
1169 | };\r | |
1170 | \r | |
47d20b54 | 1171 | PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r |
f056e4c1 JC |
1172 | {\r |
1173 | 0x00,\r | |
1174 | L"",\r | |
1175 | PCIBlankEntry\r | |
1176 | },\r | |
1177 | {\r | |
1178 | 0x01,\r | |
1179 | L"AHCI",\r | |
1180 | PCIBlankEntry\r | |
1181 | },\r | |
1182 | {\r | |
1183 | 0x02,\r | |
1184 | L"Serial Storage Bus",\r | |
1185 | PCIBlankEntry\r | |
1186 | },\r | |
1187 | {\r | |
1188 | 0x00,\r | |
1189 | NULL,\r | |
47d20b54 | 1190 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1191 | }\r |
1192 | };\r | |
1193 | \r | |
47d20b54 | 1194 | PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r |
f056e4c1 JC |
1195 | {\r |
1196 | 0x00,\r | |
1197 | L"",\r | |
1198 | PCIBlankEntry\r | |
1199 | },\r | |
1200 | {\r | |
1201 | 0x01,\r | |
1202 | L"Obsolete",\r | |
1203 | PCIBlankEntry\r | |
1204 | },\r | |
1205 | {\r | |
1206 | 0x00,\r | |
1207 | NULL,\r | |
47d20b54 | 1208 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1209 | }\r |
1210 | };\r | |
1211 | \r | |
47d20b54 | 1212 | PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r |
f056e4c1 JC |
1213 | {\r |
1214 | 0x00,\r | |
1215 | L"",\r | |
1216 | PCIBlankEntry\r | |
1217 | },\r | |
1218 | {\r | |
1219 | 0x01,\r | |
1220 | L"NVMHCI",\r | |
1221 | PCIBlankEntry\r | |
1222 | },\r | |
1223 | {\r | |
1224 | 0x02,\r | |
1225 | L"NVM Express",\r | |
1226 | PCIBlankEntry\r | |
1227 | },\r | |
1228 | {\r | |
1229 | 0x00,\r | |
1230 | NULL,\r | |
47d20b54 | 1231 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1232 | }\r |
1233 | };\r | |
1234 | \r | |
47d20b54 | 1235 | PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r |
f056e4c1 JC |
1236 | {\r |
1237 | 0x00,\r | |
1238 | L"",\r | |
1239 | PCIBlankEntry\r | |
1240 | },\r | |
1241 | {\r | |
1242 | 0x01,\r | |
1243 | L"UFSHCI",\r | |
1244 | PCIBlankEntry\r | |
1245 | },\r | |
1246 | {\r | |
1247 | 0x00,\r | |
1248 | NULL,\r | |
47d20b54 | 1249 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1250 | }\r |
1251 | };\r | |
1252 | \r | |
47d20b54 | 1253 | PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r |
5d73d92f | 1254 | {\r |
1255 | 0x00,\r | |
1256 | L"VGA compatible",\r | |
1257 | PCIBlankEntry\r | |
1258 | },\r | |
1259 | {\r | |
1260 | 0x01,\r | |
1261 | L"8514 compatible",\r | |
1262 | PCIBlankEntry\r | |
1263 | },\r | |
1264 | {\r | |
1265 | 0x00,\r | |
1266 | NULL,\r | |
47d20b54 | 1267 | /* null string ends the list */ NULL\r |
5d73d92f | 1268 | }\r |
1269 | };\r | |
1270 | \r | |
47d20b54 | 1271 | PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r |
5d73d92f | 1272 | {\r |
1273 | 0x00,\r | |
1274 | L"",\r | |
1275 | PCIBlankEntry\r | |
1276 | },\r | |
1277 | {\r | |
1278 | 0x01,\r | |
1279 | L"Subtractive decode",\r | |
1280 | PCIBlankEntry\r | |
1281 | },\r | |
1282 | {\r | |
1283 | 0x00,\r | |
1284 | NULL,\r | |
47d20b54 | 1285 | /* null string ends the list */ NULL\r |
5d73d92f | 1286 | }\r |
1287 | };\r | |
1288 | \r | |
47d20b54 | 1289 | PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r |
f056e4c1 JC |
1290 | {\r |
1291 | 0x40,\r | |
1292 | L"Primary PCI bus side facing the system host processor",\r | |
1293 | PCIBlankEntry\r | |
1294 | },\r | |
1295 | {\r | |
1296 | 0x80,\r | |
1297 | L"Secondary PCI bus side facing the system host processor",\r | |
1298 | PCIBlankEntry\r | |
1299 | },\r | |
1300 | {\r | |
1301 | 0x00,\r | |
1302 | NULL,\r | |
47d20b54 | 1303 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1304 | }\r |
1305 | };\r | |
1306 | \r | |
47d20b54 | 1307 | PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r |
f056e4c1 JC |
1308 | {\r |
1309 | 0x00,\r | |
1310 | L"Custom",\r | |
1311 | PCIBlankEntry\r | |
1312 | },\r | |
1313 | {\r | |
1314 | 0x01,\r | |
1315 | L"ASI-SIG Defined Portal",\r | |
1316 | PCIBlankEntry\r | |
1317 | },\r | |
1318 | {\r | |
1319 | 0x00,\r | |
1320 | NULL,\r | |
47d20b54 | 1321 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1322 | }\r |
1323 | };\r | |
1324 | \r | |
47d20b54 | 1325 | PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r |
5d73d92f | 1326 | {\r |
1327 | 0x00,\r | |
1328 | L"Generic XT-compatible",\r | |
1329 | PCIBlankEntry\r | |
1330 | },\r | |
1331 | {\r | |
1332 | 0x01,\r | |
1333 | L"16450-compatible",\r | |
1334 | PCIBlankEntry\r | |
1335 | },\r | |
1336 | {\r | |
1337 | 0x02,\r | |
1338 | L"16550-compatible",\r | |
1339 | PCIBlankEntry\r | |
1340 | },\r | |
1341 | {\r | |
1342 | 0x03,\r | |
1343 | L"16650-compatible",\r | |
1344 | PCIBlankEntry\r | |
1345 | },\r | |
1346 | {\r | |
1347 | 0x04,\r | |
1348 | L"16750-compatible",\r | |
1349 | PCIBlankEntry\r | |
1350 | },\r | |
1351 | {\r | |
1352 | 0x05,\r | |
1353 | L"16850-compatible",\r | |
1354 | PCIBlankEntry\r | |
1355 | },\r | |
1356 | {\r | |
1357 | 0x06,\r | |
1358 | L"16950-compatible",\r | |
1359 | PCIBlankEntry\r | |
1360 | },\r | |
1361 | {\r | |
1362 | 0x00,\r | |
1363 | NULL,\r | |
47d20b54 | 1364 | /* null string ends the list */ NULL\r |
5d73d92f | 1365 | }\r |
1366 | };\r | |
1367 | \r | |
47d20b54 | 1368 | PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r |
5d73d92f | 1369 | {\r |
1370 | 0x00,\r | |
1371 | L"",\r | |
1372 | PCIBlankEntry\r | |
1373 | },\r | |
1374 | {\r | |
1375 | 0x01,\r | |
1376 | L"Bi-directional",\r | |
1377 | PCIBlankEntry\r | |
1378 | },\r | |
1379 | {\r | |
1380 | 0x02,\r | |
1381 | L"ECP 1.X-compliant",\r | |
1382 | PCIBlankEntry\r | |
1383 | },\r | |
1384 | {\r | |
1385 | 0x03,\r | |
1386 | L"IEEE 1284",\r | |
1387 | PCIBlankEntry\r | |
1388 | },\r | |
1389 | {\r | |
1390 | 0xfe,\r | |
1391 | L"IEEE 1284 target (not a controller)",\r | |
1392 | PCIBlankEntry\r | |
1393 | },\r | |
1394 | {\r | |
1395 | 0x00,\r | |
1396 | NULL,\r | |
47d20b54 | 1397 | /* null string ends the list */ NULL\r |
5d73d92f | 1398 | }\r |
1399 | };\r | |
1400 | \r | |
47d20b54 | 1401 | PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r |
5d73d92f | 1402 | {\r |
1403 | 0x00,\r | |
1404 | L"Generic",\r | |
1405 | PCIBlankEntry\r | |
1406 | },\r | |
1407 | {\r | |
1408 | 0x01,\r | |
1409 | L"Hayes-compatible 16450",\r | |
1410 | PCIBlankEntry\r | |
1411 | },\r | |
1412 | {\r | |
1413 | 0x02,\r | |
1414 | L"Hayes-compatible 16550",\r | |
1415 | PCIBlankEntry\r | |
1416 | },\r | |
1417 | {\r | |
1418 | 0x03,\r | |
1419 | L"Hayes-compatible 16650",\r | |
1420 | PCIBlankEntry\r | |
1421 | },\r | |
1422 | {\r | |
1423 | 0x04,\r | |
1424 | L"Hayes-compatible 16750",\r | |
1425 | PCIBlankEntry\r | |
1426 | },\r | |
1427 | {\r | |
1428 | 0x00,\r | |
1429 | NULL,\r | |
47d20b54 | 1430 | /* null string ends the list */ NULL\r |
5d73d92f | 1431 | }\r |
1432 | };\r | |
1433 | \r | |
47d20b54 | 1434 | PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r |
5d73d92f | 1435 | {\r |
1436 | 0x00,\r | |
1437 | L"Generic 8259",\r | |
1438 | PCIBlankEntry\r | |
1439 | },\r | |
1440 | {\r | |
1441 | 0x01,\r | |
1442 | L"ISA",\r | |
1443 | PCIBlankEntry\r | |
1444 | },\r | |
1445 | {\r | |
1446 | 0x02,\r | |
1447 | L"EISA",\r | |
1448 | PCIBlankEntry\r | |
1449 | },\r | |
1450 | {\r | |
1451 | 0x10,\r | |
1452 | L"IO APIC",\r | |
1453 | PCIBlankEntry\r | |
1454 | },\r | |
1455 | {\r | |
1456 | 0x20,\r | |
1457 | L"IO(x) APIC interrupt controller",\r | |
1458 | PCIBlankEntry\r | |
1459 | },\r | |
1460 | {\r | |
1461 | 0x00,\r | |
1462 | NULL,\r | |
47d20b54 | 1463 | /* null string ends the list */ NULL\r |
5d73d92f | 1464 | }\r |
1465 | };\r | |
1466 | \r | |
47d20b54 | 1467 | PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r |
5d73d92f | 1468 | {\r |
1469 | 0x00,\r | |
1470 | L"Generic 8237",\r | |
1471 | PCIBlankEntry\r | |
1472 | },\r | |
1473 | {\r | |
1474 | 0x01,\r | |
1475 | L"ISA",\r | |
1476 | PCIBlankEntry\r | |
1477 | },\r | |
1478 | {\r | |
1479 | 0x02,\r | |
1480 | L"EISA",\r | |
1481 | PCIBlankEntry\r | |
1482 | },\r | |
1483 | {\r | |
1484 | 0x00,\r | |
1485 | NULL,\r | |
47d20b54 | 1486 | /* null string ends the list */ NULL\r |
5d73d92f | 1487 | }\r |
1488 | };\r | |
1489 | \r | |
47d20b54 | 1490 | PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r |
5d73d92f | 1491 | {\r |
1492 | 0x00,\r | |
1493 | L"Generic 8254",\r | |
1494 | PCIBlankEntry\r | |
1495 | },\r | |
1496 | {\r | |
1497 | 0x01,\r | |
1498 | L"ISA",\r | |
1499 | PCIBlankEntry\r | |
1500 | },\r | |
1501 | {\r | |
1502 | 0x02,\r | |
1503 | L"EISA",\r | |
1504 | PCIBlankEntry\r | |
1505 | },\r | |
1506 | {\r | |
1507 | 0x00,\r | |
1508 | NULL,\r | |
47d20b54 | 1509 | /* null string ends the list */ NULL\r |
5d73d92f | 1510 | }\r |
1511 | };\r | |
1512 | \r | |
47d20b54 | 1513 | PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r |
5d73d92f | 1514 | {\r |
1515 | 0x00,\r | |
1516 | L"Generic",\r | |
1517 | PCIBlankEntry\r | |
1518 | },\r | |
1519 | {\r | |
1520 | 0x01,\r | |
1521 | L"ISA",\r | |
1522 | PCIBlankEntry\r | |
1523 | },\r | |
1524 | {\r | |
1525 | 0x02,\r | |
1526 | L"EISA",\r | |
1527 | PCIBlankEntry\r | |
1528 | },\r | |
1529 | {\r | |
1530 | 0x00,\r | |
1531 | NULL,\r | |
47d20b54 | 1532 | /* null string ends the list */ NULL\r |
5d73d92f | 1533 | }\r |
1534 | };\r | |
1535 | \r | |
47d20b54 | 1536 | PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r |
5d73d92f | 1537 | {\r |
1538 | 0x00,\r | |
1539 | L"Generic",\r | |
1540 | PCIBlankEntry\r | |
1541 | },\r | |
1542 | {\r | |
1543 | 0x10,\r | |
1544 | L"",\r | |
1545 | PCIBlankEntry\r | |
1546 | },\r | |
1547 | {\r | |
1548 | 0x00,\r | |
1549 | NULL,\r | |
47d20b54 | 1550 | /* null string ends the list */ NULL\r |
5d73d92f | 1551 | }\r |
1552 | };\r | |
1553 | \r | |
47d20b54 | 1554 | PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r |
5d73d92f | 1555 | {\r |
1556 | 0x00,\r | |
f056e4c1 JC |
1557 | L"",\r |
1558 | PCIBlankEntry\r | |
1559 | },\r | |
1560 | {\r | |
1561 | 0x10,\r | |
1562 | L"Using 1394 OpenHCI spec",\r | |
1563 | PCIBlankEntry\r | |
1564 | },\r | |
1565 | {\r | |
1566 | 0x00,\r | |
1567 | NULL,\r | |
47d20b54 | 1568 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1569 | }\r |
1570 | };\r | |
1571 | \r | |
47d20b54 | 1572 | PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r |
f056e4c1 JC |
1573 | {\r |
1574 | 0x00,\r | |
1575 | L"UHCI",\r | |
5d73d92f | 1576 | PCIBlankEntry\r |
1577 | },\r | |
1578 | {\r | |
1579 | 0x10,\r | |
f056e4c1 JC |
1580 | L"OHCI",\r |
1581 | PCIBlankEntry\r | |
1582 | },\r | |
1583 | {\r | |
1584 | 0x20,\r | |
1585 | L"EHCI",\r | |
1586 | PCIBlankEntry\r | |
1587 | },\r | |
1588 | {\r | |
1589 | 0x30,\r | |
1590 | L"xHCI",\r | |
5d73d92f | 1591 | PCIBlankEntry\r |
1592 | },\r | |
1593 | {\r | |
1594 | 0x80,\r | |
1595 | L"No specific programming interface",\r | |
1596 | PCIBlankEntry\r | |
1597 | },\r | |
1598 | {\r | |
1599 | 0xfe,\r | |
1600 | L"(Not Host Controller)",\r | |
1601 | PCIBlankEntry\r | |
1602 | },\r | |
1603 | {\r | |
1604 | 0x00,\r | |
1605 | NULL,\r | |
47d20b54 | 1606 | /* null string ends the list */ NULL\r |
5d73d92f | 1607 | }\r |
1608 | };\r | |
1609 | \r | |
47d20b54 | 1610 | PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r |
5d73d92f | 1611 | {\r |
1612 | 0x00,\r | |
f056e4c1 JC |
1613 | L"SMIC",\r |
1614 | PCIBlankEntry\r | |
1615 | },\r | |
1616 | {\r | |
1617 | 0x01,\r | |
1618 | L"Keyboard Controller Style",\r | |
1619 | PCIBlankEntry\r | |
1620 | },\r | |
1621 | {\r | |
1622 | 0x02,\r | |
1623 | L"Block Transfer",\r | |
1624 | PCIBlankEntry\r | |
1625 | },\r | |
1626 | {\r | |
1627 | 0x00,\r | |
1628 | NULL,\r | |
47d20b54 | 1629 | /* null string ends the list */ NULL\r |
f056e4c1 JC |
1630 | }\r |
1631 | };\r | |
1632 | \r | |
47d20b54 | 1633 | PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r |
f056e4c1 JC |
1634 | {\r |
1635 | 0x00,\r | |
1636 | L"Consumer IR controller",\r | |
5d73d92f | 1637 | PCIBlankEntry\r |
1638 | },\r | |
1639 | {\r | |
1640 | 0x10,\r | |
f056e4c1 | 1641 | L"UWB Radio controller",\r |
5d73d92f | 1642 | PCIBlankEntry\r |
1643 | },\r | |
1644 | {\r | |
1645 | 0x00,\r | |
1646 | NULL,\r | |
47d20b54 | 1647 | /* null string ends the list */ NULL\r |
5d73d92f | 1648 | }\r |
1649 | };\r | |
1650 | \r | |
47d20b54 | 1651 | PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r |
5d73d92f | 1652 | {\r |
1653 | 0x00,\r | |
1654 | L"Message FIFO at offset 40h",\r | |
1655 | PCIBlankEntry\r | |
1656 | },\r | |
1657 | {\r | |
1658 | 0x01,\r | |
1659 | L"",\r | |
1660 | PCIBlankEntry\r | |
1661 | },\r | |
1662 | {\r | |
1663 | 0x00,\r | |
1664 | NULL,\r | |
47d20b54 | 1665 | /* null string ends the list */ NULL\r |
5d73d92f | 1666 | }\r |
1667 | };\r | |
1668 | \r | |
a1d4bfcc | 1669 | /**\r |
5d73d92f | 1670 | Generates printable Unicode strings that represent PCI device class,\r |
1671 | subclass and programmed I/F based on a value passed to the function.\r | |
1672 | \r | |
a1d4bfcc | 1673 | @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r |
5d73d92f | 1674 | PCI device. The encodings are:\r |
1675 | bits 23:16 - Base Class Code\r | |
1676 | bits 15:8 - Sub-Class Code\r | |
1677 | bits 7:0 - Programming Interface\r | |
4ff7e37b | 1678 | @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r |
5d73d92f | 1679 | printable class strings corresponding to ClassCode. The\r |
1680 | caller must not modify the strings that are pointed by\r | |
1681 | the fields in ClassStrings.\r | |
5d73d92f | 1682 | **/\r |
a1d4bfcc | 1683 | VOID\r |
1684 | PciGetClassStrings (\r | |
47d20b54 MK |
1685 | IN UINT32 ClassCode,\r |
1686 | IN OUT PCI_CLASS_STRINGS *ClassStrings\r | |
a1d4bfcc | 1687 | )\r |
5d73d92f | 1688 | {\r |
47d20b54 MK |
1689 | INTN Index;\r |
1690 | UINT8 Code;\r | |
1691 | PCI_CLASS_ENTRY *CurrentClass;\r | |
5d73d92f | 1692 | \r |
1693 | //\r | |
1694 | // Assume no strings found\r | |
1695 | //\r | |
1696 | ClassStrings->BaseClass = L"UNDEFINED";\r | |
1697 | ClassStrings->SubClass = L"UNDEFINED";\r | |
1698 | ClassStrings->PIFClass = L"UNDEFINED";\r | |
1699 | \r | |
1700 | CurrentClass = gClassStringList;\r | |
47d20b54 MK |
1701 | Code = (UINT8)(ClassCode >> 16);\r |
1702 | Index = 0;\r | |
5d73d92f | 1703 | \r |
1704 | //\r | |
1705 | // Go through all entries of the base class, until the entry with a matching\r | |
1706 | // base class code is found. If reaches an entry with a null description\r | |
1707 | // text, the last entry is met, which means no text for the base class was\r | |
1708 | // found, so no more action is needed.\r | |
1709 | //\r | |
1710 | while (Code != CurrentClass[Index].Code) {\r | |
1711 | if (NULL == CurrentClass[Index].DescText) {\r | |
47d20b54 | 1712 | return;\r |
5d73d92f | 1713 | }\r |
1714 | \r | |
1715 | Index++;\r | |
1716 | }\r | |
47d20b54 | 1717 | \r |
5d73d92f | 1718 | //\r |
1719 | // A base class was found. Assign description, and check if this class has\r | |
1720 | // sub-class defined. If sub-class defined, no more action is needed,\r | |
1721 | // otherwise, continue to find description for the sub-class code.\r | |
1722 | //\r | |
1723 | ClassStrings->BaseClass = CurrentClass[Index].DescText;\r | |
1724 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
47d20b54 | 1725 | return;\r |
5d73d92f | 1726 | }\r |
47d20b54 | 1727 | \r |
5d73d92f | 1728 | //\r |
1729 | // find Subclass entry\r | |
1730 | //\r | |
47d20b54 MK |
1731 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r |
1732 | Code = (UINT8)(ClassCode >> 8);\r | |
1733 | Index = 0;\r | |
5d73d92f | 1734 | \r |
1735 | //\r | |
1736 | // Go through all entries of the sub-class, until the entry with a matching\r | |
1737 | // sub-class code is found. If reaches an entry with a null description\r | |
1738 | // text, the last entry is met, which means no text for the sub-class was\r | |
1739 | // found, so no more action is needed.\r | |
1740 | //\r | |
1741 | while (Code != CurrentClass[Index].Code) {\r | |
1742 | if (NULL == CurrentClass[Index].DescText) {\r | |
47d20b54 | 1743 | return;\r |
5d73d92f | 1744 | }\r |
1745 | \r | |
1746 | Index++;\r | |
1747 | }\r | |
47d20b54 | 1748 | \r |
5d73d92f | 1749 | //\r |
1750 | // A class was found for the sub-class code. Assign description, and check if\r | |
1751 | // this sub-class has programming interface defined. If no, no more action is\r | |
1752 | // needed, otherwise, continue to find description for the programming\r | |
1753 | // interface.\r | |
1754 | //\r | |
1755 | ClassStrings->SubClass = CurrentClass[Index].DescText;\r | |
1756 | if (NULL == CurrentClass[Index].LowerLevelClass) {\r | |
47d20b54 | 1757 | return;\r |
5d73d92f | 1758 | }\r |
47d20b54 | 1759 | \r |
5d73d92f | 1760 | //\r |
1761 | // Find programming interface entry\r | |
1762 | //\r | |
47d20b54 MK |
1763 | CurrentClass = CurrentClass[Index].LowerLevelClass;\r |
1764 | Code = (UINT8)ClassCode;\r | |
1765 | Index = 0;\r | |
5d73d92f | 1766 | \r |
1767 | //\r | |
1768 | // Go through all entries of the I/F entries, until the entry with a\r | |
1769 | // matching I/F code is found. If reaches an entry with a null description\r | |
1770 | // text, the last entry is met, which means no text was found, so no more\r | |
1771 | // action is needed.\r | |
1772 | //\r | |
1773 | while (Code != CurrentClass[Index].Code) {\r | |
1774 | if (NULL == CurrentClass[Index].DescText) {\r | |
47d20b54 | 1775 | return;\r |
5d73d92f | 1776 | }\r |
1777 | \r | |
1778 | Index++;\r | |
1779 | }\r | |
47d20b54 | 1780 | \r |
5d73d92f | 1781 | //\r |
1782 | // A class was found for the I/F code. Assign description, done!\r | |
1783 | //\r | |
1784 | ClassStrings->PIFClass = CurrentClass[Index].DescText;\r | |
47d20b54 | 1785 | return;\r |
5d73d92f | 1786 | }\r |
1787 | \r | |
a1d4bfcc | 1788 | /**\r |
1789 | Print strings that represent PCI device class, subclass and programmed I/F.\r | |
1790 | \r | |
1791 | @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r | |
e8a57ade | 1792 | configuration space.\r |
a1d4bfcc | 1793 | @param[in] IncludePIF If the printed string should include the programming I/F part\r |
1794 | **/\r | |
5d73d92f | 1795 | VOID\r |
1796 | PciPrintClassCode (\r | |
47d20b54 MK |
1797 | IN UINT8 *ClassCodePtr,\r |
1798 | IN BOOLEAN IncludePIF\r | |
5d73d92f | 1799 | )\r |
5d73d92f | 1800 | {\r |
47d20b54 MK |
1801 | UINT32 ClassCode;\r |
1802 | PCI_CLASS_STRINGS ClassStrings;\r | |
5d73d92f | 1803 | \r |
47d20b54 | 1804 | ClassCode = 0;\r |
e8a57ade JC |
1805 | ClassCode |= (UINT32)ClassCodePtr[0];\r |
1806 | ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r | |
1807 | ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r | |
5d73d92f | 1808 | \r |
1809 | //\r | |
1810 | // Get name from class code\r | |
1811 | //\r | |
1812 | PciGetClassStrings (ClassCode, &ClassStrings);\r | |
1813 | \r | |
1814 | if (IncludePIF) {\r | |
1815 | //\r | |
c37e0f16 | 1816 | // Print base class, sub class, and programming inferface name\r |
5d73d92f | 1817 | //\r |
47d20b54 MK |
1818 | ShellPrintEx (\r |
1819 | -1,\r | |
1820 | -1,\r | |
1821 | L"%s - %s - %s",\r | |
5d73d92f | 1822 | ClassStrings.BaseClass,\r |
1823 | ClassStrings.SubClass,\r | |
1824 | ClassStrings.PIFClass\r | |
47d20b54 | 1825 | );\r |
5d73d92f | 1826 | } else {\r |
1827 | //\r | |
c37e0f16 | 1828 | // Only print base class and sub class name\r |
5d73d92f | 1829 | //\r |
47d20b54 MK |
1830 | ShellPrintEx (\r |
1831 | -1,\r | |
1832 | -1,\r | |
1833 | L"%s - %s",\r | |
5d73d92f | 1834 | ClassStrings.BaseClass,\r |
1835 | ClassStrings.SubClass\r | |
47d20b54 | 1836 | );\r |
5d73d92f | 1837 | }\r |
1838 | }\r | |
1839 | \r | |
a1d4bfcc | 1840 | /**\r |
1841 | This function finds out the protocol which is in charge of the given\r | |
1842 | segment, and its bus range covers the current bus number. It lookes\r | |
1843 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
1844 | criteria is found.\r | |
1845 | \r | |
1846 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1847 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
1848 | @param[in] Segment Segment number of device we are dealing with.\r | |
1849 | @param[in] Bus Bus number of device we are dealing with.\r | |
1850 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1851 | \r | |
1852 | @retval EFI_SUCCESS The command completed successfully.\r | |
1853 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 1854 | \r |
a1d4bfcc | 1855 | **/\r |
5d73d92f | 1856 | EFI_STATUS\r |
1857 | PciFindProtocolInterface (\r | |
47d20b54 MK |
1858 | IN EFI_HANDLE *HandleBuf,\r |
1859 | IN UINTN HandleCount,\r | |
1860 | IN UINT16 Segment,\r | |
1861 | IN UINT16 Bus,\r | |
1862 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
5d73d92f | 1863 | );\r |
1864 | \r | |
a1d4bfcc | 1865 | /**\r |
1866 | This function gets the protocol interface from the given handle, and\r | |
1867 | obtains its address space descriptors.\r | |
1868 | \r | |
1869 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
1870 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
1871 | @param[out] Descriptors Points to the address space descriptors.\r | |
1872 | \r | |
1873 | @retval EFI_SUCCESS The command completed successfully\r | |
1874 | **/\r | |
5d73d92f | 1875 | EFI_STATUS\r |
1876 | PciGetProtocolAndResource (\r | |
47d20b54 MK |
1877 | IN EFI_HANDLE Handle,\r |
1878 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
1879 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
5d73d92f | 1880 | );\r |
1881 | \r | |
a1d4bfcc | 1882 | /**\r |
1883 | This function get the next bus range of given address space descriptors.\r | |
1884 | It also moves the pointer backward a node, to get prepared to be called\r | |
1885 | again.\r | |
1886 | \r | |
4ff7e37b ED |
1887 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
1888 | descriptors.\r | |
1889 | @param[out] MinBus The lower range of bus number.\r | |
1890 | @param[out] MaxBus The upper range of bus number.\r | |
1891 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 1892 | \r |
1893 | @retval EFI_SUCCESS The command completed successfully.\r | |
1894 | **/\r | |
5d73d92f | 1895 | EFI_STATUS\r |
1896 | PciGetNextBusRange (\r | |
1897 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
1898 | OUT UINT16 *MinBus,\r | |
1899 | OUT UINT16 *MaxBus,\r | |
1900 | OUT BOOLEAN *IsEnd\r | |
1901 | );\r | |
1902 | \r | |
a1d4bfcc | 1903 | /**\r |
1904 | Explain the data in PCI configuration space. The part which is common for\r | |
1905 | PCI device and bridge is interpreted in this function. It calls other\r | |
1906 | functions to interpret data unique for device or bridge.\r | |
1907 | \r | |
1908 | @param[in] ConfigSpace Data in PCI configuration space.\r | |
1909 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1910 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
a1d4bfcc | 1911 | **/\r |
33cc487c RN |
1912 | VOID\r |
1913 | PciExplainPci (\r | |
47d20b54 MK |
1914 | IN PCI_CONFIG_SPACE *ConfigSpace,\r |
1915 | IN UINT64 Address,\r | |
1916 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 1917 | );\r |
1918 | \r | |
a1d4bfcc | 1919 | /**\r |
1920 | Explain the device specific part of data in PCI configuration space.\r | |
1921 | \r | |
1922 | @param[in] Device Data in PCI configuration space.\r | |
1923 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1924 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1925 | \r | |
1926 | @retval EFI_SUCCESS The command completed successfully.\r | |
1927 | **/\r | |
5d73d92f | 1928 | EFI_STATUS\r |
1929 | PciExplainDeviceData (\r | |
47d20b54 MK |
1930 | IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r |
1931 | IN UINT64 Address,\r | |
1932 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 1933 | );\r |
1934 | \r | |
a1d4bfcc | 1935 | /**\r |
1936 | Explain the bridge specific part of data in PCI configuration space.\r | |
1937 | \r | |
1938 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
1939 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1940 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1941 | \r | |
1942 | @retval EFI_SUCCESS The command completed successfully.\r | |
1943 | **/\r | |
5d73d92f | 1944 | EFI_STATUS\r |
1945 | PciExplainBridgeData (\r | |
47d20b54 MK |
1946 | IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r |
1947 | IN UINT64 Address,\r | |
1948 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 1949 | );\r |
1950 | \r | |
a1d4bfcc | 1951 | /**\r |
1952 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
1953 | \r | |
4ff7e37b ED |
1954 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
1955 | @param[in] Command Points to the register Command.\r | |
1956 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1957 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1958 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 1959 | \r |
1960 | @retval EFI_SUCCESS The command completed successfully.\r | |
1961 | **/\r | |
5d73d92f | 1962 | EFI_STATUS\r |
1963 | PciExplainBar (\r | |
47d20b54 MK |
1964 | IN UINT32 *Bar,\r |
1965 | IN UINT16 *Command,\r | |
1966 | IN UINT64 Address,\r | |
1967 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
1968 | IN OUT UINTN *Index\r | |
5d73d92f | 1969 | );\r |
1970 | \r | |
a1d4bfcc | 1971 | /**\r |
1972 | Explain the cardbus specific part of data in PCI configuration space.\r | |
1973 | \r | |
1974 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
1975 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
1976 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
1977 | \r | |
1978 | @retval EFI_SUCCESS The command completed successfully.\r | |
1979 | **/\r | |
5d73d92f | 1980 | EFI_STATUS\r |
1981 | PciExplainCardBusData (\r | |
47d20b54 MK |
1982 | IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r |
1983 | IN UINT64 Address,\r | |
1984 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 1985 | );\r |
1986 | \r | |
a1d4bfcc | 1987 | /**\r |
1988 | Explain each meaningful bit of register Status. The definition of Status is\r | |
1989 | slightly different depending on the PCI header type.\r | |
1990 | \r | |
1991 | @param[in] Status Points to the content of register Status.\r | |
1992 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
1993 | status).\r | |
1994 | @param[in] HeaderType Header type of this PCI device.\r | |
1995 | \r | |
1996 | @retval EFI_SUCCESS The command completed successfully.\r | |
1997 | **/\r | |
5d73d92f | 1998 | EFI_STATUS\r |
1999 | PciExplainStatus (\r | |
47d20b54 MK |
2000 | IN UINT16 *Status,\r |
2001 | IN BOOLEAN MainStatus,\r | |
2002 | IN PCI_HEADER_TYPE HeaderType\r | |
5d73d92f | 2003 | );\r |
2004 | \r | |
a1d4bfcc | 2005 | /**\r |
2006 | Explain each meaningful bit of register Command.\r | |
2007 | \r | |
2008 | @param[in] Command Points to the content of register Command.\r | |
2009 | \r | |
2010 | @retval EFI_SUCCESS The command completed successfully.\r | |
2011 | **/\r | |
5d73d92f | 2012 | EFI_STATUS\r |
2013 | PciExplainCommand (\r | |
47d20b54 | 2014 | IN UINT16 *Command\r |
5d73d92f | 2015 | );\r |
2016 | \r | |
a1d4bfcc | 2017 | /**\r |
2018 | Explain each meaningful bit of register Bridge Control.\r | |
2019 | \r | |
2020 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
2021 | @param[in] HeaderType The headertype.\r | |
2022 | \r | |
2023 | @retval EFI_SUCCESS The command completed successfully.\r | |
2024 | **/\r | |
5d73d92f | 2025 | EFI_STATUS\r |
2026 | PciExplainBridgeControl (\r | |
47d20b54 MK |
2027 | IN UINT16 *BridgeControl,\r |
2028 | IN PCI_HEADER_TYPE HeaderType\r | |
5d73d92f | 2029 | );\r |
2030 | \r | |
a1d4bfcc | 2031 | /**\r |
33cc487c | 2032 | Locate capability register block per capability ID.\r |
a1d4bfcc | 2033 | \r |
33cc487c RN |
2034 | @param[in] ConfigSpace Data in PCI configuration space.\r |
2035 | @param[in] CapabilityId The capability ID.\r | |
a1d4bfcc | 2036 | \r |
33cc487c | 2037 | @return The offset of the register block per capability ID.\r |
a1d4bfcc | 2038 | **/\r |
33cc487c RN |
2039 | UINT8\r |
2040 | LocatePciCapability (\r | |
47d20b54 MK |
2041 | IN PCI_CONFIG_SPACE *ConfigSpace,\r |
2042 | IN UINT8 CapabilityId\r | |
5d73d92f | 2043 | );\r |
2044 | \r | |
a1d4bfcc | 2045 | /**\r |
2046 | Display Pcie device structure.\r | |
2047 | \r | |
33cc487c RN |
2048 | @param[in] PciExpressCap PCI Express capability buffer.\r |
2049 | @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r | |
3d0df0f0 | 2050 | @param[in] ExtendedConfigSize PCI Express extended configuration size.\r |
33cc487c | 2051 | @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r |
a1d4bfcc | 2052 | **/\r |
33cc487c | 2053 | VOID\r |
5d73d92f | 2054 | PciExplainPciExpress (\r |
47d20b54 MK |
2055 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r |
2056 | IN UINT8 *ExtendedConfigSpace,\r | |
2057 | IN UINTN ExtendedConfigSize,\r | |
2058 | IN CONST UINT16 ExtendedCapability\r | |
5d73d92f | 2059 | );\r |
2060 | \r | |
a1d4bfcc | 2061 | /**\r |
2062 | Print out information of the capability information.\r | |
2063 | \r | |
2064 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2065 | \r | |
2066 | @retval EFI_SUCCESS The operation was successful.\r | |
2067 | **/\r | |
5d73d92f | 2068 | EFI_STATUS\r |
2069 | ExplainPcieCapReg (\r | |
47d20b54 | 2070 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2071 | );\r |
2072 | \r | |
2073 | /**\r | |
2074 | Print out information of the device capability information.\r | |
2075 | \r | |
2076 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2077 | \r |
a1d4bfcc | 2078 | @retval EFI_SUCCESS The operation was successful.\r |
2079 | **/\r | |
5d73d92f | 2080 | EFI_STATUS\r |
2081 | ExplainPcieDeviceCap (\r | |
47d20b54 | 2082 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2083 | );\r |
2084 | \r | |
2085 | /**\r | |
2086 | Print out information of the device control information.\r | |
5d73d92f | 2087 | \r |
a1d4bfcc | 2088 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2089 | \r | |
2090 | @retval EFI_SUCCESS The operation was successful.\r | |
2091 | **/\r | |
5d73d92f | 2092 | EFI_STATUS\r |
2093 | ExplainPcieDeviceControl (\r | |
47d20b54 | 2094 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2095 | );\r |
5d73d92f | 2096 | \r |
a1d4bfcc | 2097 | /**\r |
2098 | Print out information of the device status information.\r | |
2099 | \r | |
2100 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2101 | \r | |
2102 | @retval EFI_SUCCESS The operation was successful.\r | |
2103 | **/\r | |
5d73d92f | 2104 | EFI_STATUS\r |
2105 | ExplainPcieDeviceStatus (\r | |
47d20b54 | 2106 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2107 | );\r |
2108 | \r | |
2109 | /**\r | |
2110 | Print out information of the device link information.\r | |
2111 | \r | |
2112 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2113 | \r |
a1d4bfcc | 2114 | @retval EFI_SUCCESS The operation was successful.\r |
2115 | **/\r | |
5d73d92f | 2116 | EFI_STATUS\r |
2117 | ExplainPcieLinkCap (\r | |
47d20b54 | 2118 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2119 | );\r |
2120 | \r | |
2121 | /**\r | |
2122 | Print out information of the device link control information.\r | |
5d73d92f | 2123 | \r |
a1d4bfcc | 2124 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2125 | \r | |
2126 | @retval EFI_SUCCESS The operation was successful.\r | |
2127 | **/\r | |
5d73d92f | 2128 | EFI_STATUS\r |
2129 | ExplainPcieLinkControl (\r | |
47d20b54 | 2130 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2131 | );\r |
5d73d92f | 2132 | \r |
a1d4bfcc | 2133 | /**\r |
2134 | Print out information of the device link status information.\r | |
2135 | \r | |
2136 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2137 | \r | |
2138 | @retval EFI_SUCCESS The operation was successful.\r | |
2139 | **/\r | |
5d73d92f | 2140 | EFI_STATUS\r |
2141 | ExplainPcieLinkStatus (\r | |
47d20b54 | 2142 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2143 | );\r |
2144 | \r | |
2145 | /**\r | |
2146 | Print out information of the device slot information.\r | |
2147 | \r | |
2148 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2149 | \r |
a1d4bfcc | 2150 | @retval EFI_SUCCESS The operation was successful.\r |
2151 | **/\r | |
5d73d92f | 2152 | EFI_STATUS\r |
2153 | ExplainPcieSlotCap (\r | |
47d20b54 | 2154 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2155 | );\r |
2156 | \r | |
2157 | /**\r | |
2158 | Print out information of the device slot control information.\r | |
5d73d92f | 2159 | \r |
a1d4bfcc | 2160 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2161 | \r | |
2162 | @retval EFI_SUCCESS The operation was successful.\r | |
2163 | **/\r | |
5d73d92f | 2164 | EFI_STATUS\r |
2165 | ExplainPcieSlotControl (\r | |
47d20b54 | 2166 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2167 | );\r |
5d73d92f | 2168 | \r |
a1d4bfcc | 2169 | /**\r |
2170 | Print out information of the device slot status information.\r | |
2171 | \r | |
2172 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2173 | \r | |
2174 | @retval EFI_SUCCESS The operation was successful.\r | |
2175 | **/\r | |
5d73d92f | 2176 | EFI_STATUS\r |
2177 | ExplainPcieSlotStatus (\r | |
47d20b54 | 2178 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2179 | );\r |
2180 | \r | |
2181 | /**\r | |
2182 | Print out information of the device root information.\r | |
2183 | \r | |
2184 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5d73d92f | 2185 | \r |
a1d4bfcc | 2186 | @retval EFI_SUCCESS The operation was successful.\r |
2187 | **/\r | |
5d73d92f | 2188 | EFI_STATUS\r |
2189 | ExplainPcieRootControl (\r | |
47d20b54 | 2190 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2191 | );\r |
2192 | \r | |
2193 | /**\r | |
2194 | Print out information of the device root capability information.\r | |
5d73d92f | 2195 | \r |
a1d4bfcc | 2196 | @param[in] PciExpressCap The pointer to the structure about the device.\r |
2197 | \r | |
2198 | @retval EFI_SUCCESS The operation was successful.\r | |
2199 | **/\r | |
5d73d92f | 2200 | EFI_STATUS\r |
2201 | ExplainPcieRootCap (\r | |
47d20b54 | 2202 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2203 | );\r |
5d73d92f | 2204 | \r |
a1d4bfcc | 2205 | /**\r |
2206 | Print out information of the device root status information.\r | |
2207 | \r | |
2208 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
2209 | \r | |
2210 | @retval EFI_SUCCESS The operation was successful.\r | |
2211 | **/\r | |
5d73d92f | 2212 | EFI_STATUS\r |
2213 | ExplainPcieRootStatus (\r | |
47d20b54 | 2214 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 2215 | );\r |
5d73d92f | 2216 | \r |
47d20b54 MK |
2217 | typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (\r |
2218 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r | |
2219 | );\r | |
5d73d92f | 2220 | \r |
2221 | typedef enum {\r | |
2222 | FieldWidthUINT8,\r | |
2223 | FieldWidthUINT16,\r | |
2224 | FieldWidthUINT32\r | |
2225 | } PCIE_CAPREG_FIELD_WIDTH;\r | |
2226 | \r | |
2227 | typedef enum {\r | |
2228 | PcieExplainTypeCommon,\r | |
2229 | PcieExplainTypeDevice,\r | |
2230 | PcieExplainTypeLink,\r | |
2231 | PcieExplainTypeSlot,\r | |
2232 | PcieExplainTypeRoot,\r | |
2233 | PcieExplainTypeMax\r | |
2234 | } PCIE_EXPLAIN_TYPE;\r | |
2235 | \r | |
47d20b54 MK |
2236 | typedef struct {\r |
2237 | UINT16 Token;\r | |
2238 | UINTN Offset;\r | |
2239 | PCIE_CAPREG_FIELD_WIDTH Width;\r | |
2240 | PCIE_EXPLAIN_FUNCTION Func;\r | |
2241 | PCIE_EXPLAIN_TYPE Type;\r | |
5d73d92f | 2242 | } PCIE_EXPLAIN_STRUCT;\r |
2243 | \r | |
47d20b54 | 2244 | PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r |
5d73d92f | 2245 | {\r |
2246 | STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r | |
2247 | 0x00,\r | |
2248 | FieldWidthUINT8,\r | |
2249 | NULL,\r | |
2250 | PcieExplainTypeCommon\r | |
2251 | },\r | |
2252 | {\r | |
2253 | STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r | |
2254 | 0x01,\r | |
2255 | FieldWidthUINT8,\r | |
2256 | NULL,\r | |
2257 | PcieExplainTypeCommon\r | |
2258 | },\r | |
2259 | {\r | |
2260 | STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r | |
2261 | 0x02,\r | |
2262 | FieldWidthUINT16,\r | |
2263 | ExplainPcieCapReg,\r | |
2264 | PcieExplainTypeCommon\r | |
2265 | },\r | |
2266 | {\r | |
2267 | STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r | |
2268 | 0x04,\r | |
2269 | FieldWidthUINT32,\r | |
2270 | ExplainPcieDeviceCap,\r | |
2271 | PcieExplainTypeDevice\r | |
2272 | },\r | |
2273 | {\r | |
2274 | STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r | |
2275 | 0x08,\r | |
2276 | FieldWidthUINT16,\r | |
2277 | ExplainPcieDeviceControl,\r | |
2278 | PcieExplainTypeDevice\r | |
2279 | },\r | |
2280 | {\r | |
2281 | STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r | |
2282 | 0x0a,\r | |
2283 | FieldWidthUINT16,\r | |
2284 | ExplainPcieDeviceStatus,\r | |
2285 | PcieExplainTypeDevice\r | |
2286 | },\r | |
2287 | {\r | |
2288 | STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r | |
2289 | 0x0c,\r | |
2290 | FieldWidthUINT32,\r | |
2291 | ExplainPcieLinkCap,\r | |
2292 | PcieExplainTypeLink\r | |
2293 | },\r | |
2294 | {\r | |
2295 | STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r | |
2296 | 0x10,\r | |
2297 | FieldWidthUINT16,\r | |
2298 | ExplainPcieLinkControl,\r | |
2299 | PcieExplainTypeLink\r | |
2300 | },\r | |
2301 | {\r | |
2302 | STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r | |
2303 | 0x12,\r | |
2304 | FieldWidthUINT16,\r | |
2305 | ExplainPcieLinkStatus,\r | |
2306 | PcieExplainTypeLink\r | |
2307 | },\r | |
2308 | {\r | |
2309 | STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r | |
2310 | 0x14,\r | |
2311 | FieldWidthUINT32,\r | |
2312 | ExplainPcieSlotCap,\r | |
2313 | PcieExplainTypeSlot\r | |
2314 | },\r | |
2315 | {\r | |
2316 | STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r | |
2317 | 0x18,\r | |
2318 | FieldWidthUINT16,\r | |
2319 | ExplainPcieSlotControl,\r | |
2320 | PcieExplainTypeSlot\r | |
2321 | },\r | |
2322 | {\r | |
2323 | STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r | |
2324 | 0x1a,\r | |
2325 | FieldWidthUINT16,\r | |
2326 | ExplainPcieSlotStatus,\r | |
2327 | PcieExplainTypeSlot\r | |
2328 | },\r | |
2329 | {\r | |
2330 | STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r | |
2331 | 0x1c,\r | |
2332 | FieldWidthUINT16,\r | |
2333 | ExplainPcieRootControl,\r | |
2334 | PcieExplainTypeRoot\r | |
2335 | },\r | |
2336 | {\r | |
2337 | STRING_TOKEN (STR_PCIEX_RSVDP),\r | |
2338 | 0x1e,\r | |
2339 | FieldWidthUINT16,\r | |
2340 | ExplainPcieRootCap,\r | |
2341 | PcieExplainTypeRoot\r | |
2342 | },\r | |
2343 | {\r | |
2344 | STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r | |
2345 | 0x20,\r | |
2346 | FieldWidthUINT32,\r | |
2347 | ExplainPcieRootStatus,\r | |
2348 | PcieExplainTypeRoot\r | |
2349 | },\r | |
2350 | {\r | |
2351 | 0,\r | |
2352 | 0,\r | |
2353 | (PCIE_CAPREG_FIELD_WIDTH)0,\r | |
2354 | NULL,\r | |
2355 | PcieExplainTypeMax\r | |
2356 | }\r | |
2357 | };\r | |
2358 | \r | |
2359 | //\r | |
2360 | // Global Variables\r | |
2361 | //\r | |
47d20b54 MK |
2362 | PCI_CONFIG_SPACE *mConfigSpace = NULL;\r |
2363 | STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r | |
2364 | { L"-s", TypeValue },\r | |
2365 | { L"-i", TypeFlag },\r | |
2366 | { L"-ec", TypeValue },\r | |
2367 | { NULL, TypeMax }\r | |
2368 | };\r | |
2369 | \r | |
2370 | CHAR16 *DevicePortTypeTable[] = {\r | |
5d73d92f | 2371 | L"PCI Express Endpoint",\r |
2372 | L"Legacy PCI Express Endpoint",\r | |
2373 | L"Unknown Type",\r | |
2374 | L"Unknonw Type",\r | |
2375 | L"Root Port of PCI Express Root Complex",\r | |
2376 | L"Upstream Port of PCI Express Switch",\r | |
2377 | L"Downstream Port of PCI Express Switch",\r | |
2378 | L"PCI Express to PCI/PCI-X Bridge",\r | |
2379 | L"PCI/PCI-X to PCI Express Bridge",\r | |
2380 | L"Root Complex Integrated Endpoint",\r | |
2381 | L"Root Complex Event Collector"\r | |
2382 | };\r | |
2383 | \r | |
47d20b54 | 2384 | CHAR16 *L0sLatencyStrTable[] = {\r |
5d73d92f | 2385 | L"Less than 64ns",\r |
2386 | L"64ns to less than 128ns",\r | |
2387 | L"128ns to less than 256ns",\r | |
2388 | L"256ns to less than 512ns",\r | |
2389 | L"512ns to less than 1us",\r | |
2390 | L"1us to less than 2us",\r | |
2391 | L"2us-4us",\r | |
2392 | L"More than 4us"\r | |
2393 | };\r | |
2394 | \r | |
47d20b54 | 2395 | CHAR16 *L1LatencyStrTable[] = {\r |
5d73d92f | 2396 | L"Less than 1us",\r |
2397 | L"1us to less than 2us",\r | |
2398 | L"2us to less than 4us",\r | |
2399 | L"4us to less than 8us",\r | |
2400 | L"8us to less than 16us",\r | |
2401 | L"16us to less than 32us",\r | |
2402 | L"32us-64us",\r | |
2403 | L"More than 64us"\r | |
2404 | };\r | |
2405 | \r | |
47d20b54 | 2406 | CHAR16 *ASPMCtrlStrTable[] = {\r |
5d73d92f | 2407 | L"Disabled",\r |
2408 | L"L0s Entry Enabled",\r | |
2409 | L"L1 Entry Enabled",\r | |
2410 | L"L0s and L1 Entry Enabled"\r | |
2411 | };\r | |
2412 | \r | |
47d20b54 | 2413 | CHAR16 *SlotPwrLmtScaleTable[] = {\r |
5d73d92f | 2414 | L"1.0x",\r |
2415 | L"0.1x",\r | |
2416 | L"0.01x",\r | |
2417 | L"0.001x"\r | |
2418 | };\r | |
2419 | \r | |
47d20b54 | 2420 | CHAR16 *IndicatorTable[] = {\r |
5d73d92f | 2421 | L"Reserved",\r |
2422 | L"On",\r | |
2423 | L"Blink",\r | |
2424 | L"Off"\r | |
2425 | };\r | |
2426 | \r | |
a1d4bfcc | 2427 | /**\r |
2428 | Function for 'pci' command.\r | |
2429 | \r | |
2430 | @param[in] ImageHandle Handle to the Image (NULL if Internal).\r | |
2431 | @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r | |
2432 | **/\r | |
5d73d92f | 2433 | SHELL_STATUS\r |
2434 | EFIAPI\r | |
2435 | ShellCommandRunPci (\r | |
2436 | IN EFI_HANDLE ImageHandle,\r | |
2437 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
2438 | )\r | |
2439 | {\r | |
47d20b54 MK |
2440 | UINT16 Segment;\r |
2441 | UINT16 Bus;\r | |
2442 | UINT16 Device;\r | |
2443 | UINT16 Func;\r | |
2444 | UINT64 Address;\r | |
2445 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r | |
2446 | EFI_STATUS Status;\r | |
2447 | PCI_DEVICE_INDEPENDENT_REGION PciHeader;\r | |
2448 | PCI_CONFIG_SPACE ConfigSpace;\r | |
2449 | UINTN ScreenCount;\r | |
2450 | UINTN TempColumn;\r | |
2451 | UINTN ScreenSize;\r | |
2452 | BOOLEAN ExplainData;\r | |
2453 | UINTN Index;\r | |
2454 | UINTN SizeOfHeader;\r | |
2455 | BOOLEAN PrintTitle;\r | |
2456 | UINTN HandleBufSize;\r | |
2457 | EFI_HANDLE *HandleBuf;\r | |
2458 | UINTN HandleCount;\r | |
2459 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r | |
2460 | UINT16 MinBus;\r | |
2461 | UINT16 MaxBus;\r | |
2462 | BOOLEAN IsEnd;\r | |
2463 | LIST_ENTRY *Package;\r | |
2464 | CHAR16 *ProblemParam;\r | |
2465 | SHELL_STATUS ShellStatus;\r | |
2466 | CONST CHAR16 *Temp;\r | |
2467 | UINT64 RetVal;\r | |
2468 | UINT16 ExtendedCapability;\r | |
2469 | UINT8 PcieCapabilityPtr;\r | |
2470 | UINT8 *ExtendedConfigSpace;\r | |
2471 | UINTN ExtendedConfigSize;\r | |
2472 | \r | |
2473 | ShellStatus = SHELL_SUCCESS;\r | |
2474 | Status = EFI_SUCCESS;\r | |
2475 | Address = 0;\r | |
2476 | IoDev = NULL;\r | |
2477 | HandleBuf = NULL;\r | |
2478 | Package = NULL;\r | |
5d73d92f | 2479 | \r |
2480 | //\r | |
2481 | // initialize the shell lib (we must be in non-auto-init...)\r | |
2482 | //\r | |
47d20b54 MK |
2483 | Status = ShellInitialize ();\r |
2484 | ASSERT_EFI_ERROR (Status);\r | |
5d73d92f | 2485 | \r |
47d20b54 MK |
2486 | Status = CommandInit ();\r |
2487 | ASSERT_EFI_ERROR (Status);\r | |
5d73d92f | 2488 | \r |
2489 | //\r | |
2490 | // parse the command line\r | |
2491 | //\r | |
2492 | Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r | |
47d20b54 MK |
2493 | if (EFI_ERROR (Status)) {\r |
2494 | if ((Status == EFI_VOLUME_CORRUPTED) && (ProblemParam != NULL)) {\r | |
2495 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);\r | |
2496 | FreePool (ProblemParam);\r | |
5d73d92f | 2497 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2498 | } else {\r | |
47d20b54 | 2499 | ASSERT (FALSE);\r |
5d73d92f | 2500 | }\r |
2501 | } else {\r | |
47d20b54 MK |
2502 | if (ShellCommandLineGetCount (Package) == 2) {\r |
2503 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");\r | |
3737ac2b | 2504 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2505 | goto Done;\r | |
2506 | }\r | |
5d73d92f | 2507 | \r |
47d20b54 MK |
2508 | if (ShellCommandLineGetCount (Package) > 4) {\r |
2509 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");\r | |
3737ac2b | 2510 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2511 | goto Done;\r | |
2512 | }\r | |
47d20b54 MK |
2513 | \r |
2514 | if (ShellCommandLineGetFlag (Package, L"-ec") && (ShellCommandLineGetValue (Package, L"-ec") == NULL)) {\r | |
2515 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec");\r | |
c831a2c3 RN |
2516 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2517 | goto Done;\r | |
2518 | }\r | |
47d20b54 MK |
2519 | \r |
2520 | if (ShellCommandLineGetFlag (Package, L"-s") && (ShellCommandLineGetValue (Package, L"-s") == NULL)) {\r | |
2521 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s");\r | |
3737ac2b | 2522 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2523 | goto Done;\r | |
2524 | }\r | |
47d20b54 | 2525 | \r |
5d73d92f | 2526 | //\r |
2527 | // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r | |
2528 | // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r | |
2529 | // space for handles and call it again.\r | |
2530 | //\r | |
2531 | HandleBufSize = sizeof (EFI_HANDLE);\r | |
47d20b54 | 2532 | HandleBuf = (EFI_HANDLE *)AllocateZeroPool (HandleBufSize);\r |
5d73d92f | 2533 | if (HandleBuf == NULL) {\r |
47d20b54 | 2534 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2535 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r |
2536 | goto Done;\r | |
2537 | }\r | |
2538 | \r | |
2539 | Status = gBS->LocateHandle (\r | |
47d20b54 MK |
2540 | ByProtocol,\r |
2541 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2542 | NULL,\r | |
2543 | &HandleBufSize,\r | |
2544 | HandleBuf\r | |
2545 | );\r | |
5d73d92f | 2546 | \r |
2547 | if (Status == EFI_BUFFER_TOO_SMALL) {\r | |
2548 | HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r | |
2549 | if (HandleBuf == NULL) {\r | |
47d20b54 | 2550 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2551 | ShellStatus = SHELL_OUT_OF_RESOURCES;\r |
2552 | goto Done;\r | |
2553 | }\r | |
2554 | \r | |
2555 | Status = gBS->LocateHandle (\r | |
47d20b54 MK |
2556 | ByProtocol,\r |
2557 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
2558 | NULL,\r | |
2559 | &HandleBufSize,\r | |
2560 | HandleBuf\r | |
2561 | );\r | |
5d73d92f | 2562 | }\r |
2563 | \r | |
2564 | if (EFI_ERROR (Status)) {\r | |
47d20b54 | 2565 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2566 | ShellStatus = SHELL_NOT_FOUND;\r |
2567 | goto Done;\r | |
2568 | }\r | |
2569 | \r | |
2570 | HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r | |
2571 | //\r | |
2572 | // Argument Count == 1(no other argument): enumerate all pci functions\r | |
2573 | //\r | |
47d20b54 | 2574 | if (ShellCommandLineGetCount (Package) == 1) {\r |
5d73d92f | 2575 | gST->ConOut->QueryMode (\r |
47d20b54 MK |
2576 | gST->ConOut,\r |
2577 | gST->ConOut->Mode->Mode,\r | |
2578 | &TempColumn,\r | |
2579 | &ScreenSize\r | |
2580 | );\r | |
5d73d92f | 2581 | \r |
2582 | ScreenCount = 0;\r | |
2583 | ScreenSize -= 4;\r | |
2584 | if ((ScreenSize & 1) == 1) {\r | |
2585 | ScreenSize -= 1;\r | |
2586 | }\r | |
2587 | \r | |
2588 | PrintTitle = TRUE;\r | |
2589 | \r | |
2590 | //\r | |
2591 | // For each handle, which decides a segment and a bus number range,\r | |
2592 | // enumerate all devices on it.\r | |
2593 | //\r | |
2594 | for (Index = 0; Index < HandleCount; Index++) {\r | |
2595 | Status = PciGetProtocolAndResource (\r | |
47d20b54 MK |
2596 | HandleBuf[Index],\r |
2597 | &IoDev,\r | |
2598 | &Descriptors\r | |
2599 | );\r | |
5d73d92f | 2600 | if (EFI_ERROR (Status)) {\r |
47d20b54 | 2601 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2602 | ShellStatus = SHELL_NOT_FOUND;\r |
2603 | goto Done;\r | |
2604 | }\r | |
47d20b54 | 2605 | \r |
5d73d92f | 2606 | //\r |
2607 | // No document say it's impossible for a RootBridgeIo protocol handle\r | |
2608 | // to have more than one address space descriptors, so find out every\r | |
2609 | // bus range and for each of them do device enumeration.\r | |
2610 | //\r | |
2611 | while (TRUE) {\r | |
2612 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
2613 | \r | |
2614 | if (EFI_ERROR (Status)) {\r | |
47d20b54 | 2615 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2616 | ShellStatus = SHELL_NOT_FOUND;\r |
2617 | goto Done;\r | |
2618 | }\r | |
2619 | \r | |
2620 | if (IsEnd) {\r | |
2621 | break;\r | |
2622 | }\r | |
2623 | \r | |
2624 | for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r | |
2625 | //\r | |
2626 | // For each devices, enumerate all functions it contains\r | |
2627 | //\r | |
2628 | for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r | |
2629 | //\r | |
2630 | // For each function, read its configuration space and print summary\r | |
2631 | //\r | |
2632 | for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r | |
2633 | if (ShellGetExecutionBreakFlag ()) {\r | |
2634 | ShellStatus = SHELL_ABORTED;\r | |
2635 | goto Done;\r | |
2636 | }\r | |
47d20b54 | 2637 | \r |
0c84a69f | 2638 | Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r |
5d73d92f | 2639 | IoDev->Pci.Read (\r |
47d20b54 MK |
2640 | IoDev,\r |
2641 | EfiPciWidthUint16,\r | |
2642 | Address,\r | |
2643 | 1,\r | |
2644 | &PciHeader.VendorId\r | |
2645 | );\r | |
5d73d92f | 2646 | \r |
2647 | //\r | |
2648 | // If VendorId = 0xffff, there does not exist a device at this\r | |
2649 | // location. For each device, if there is any function on it,\r | |
2650 | // there must be 1 function at Function 0. So if Func = 0, there\r | |
2651 | // will be no more functions in the same device, so we can break\r | |
2652 | // loop to deal with the next device.\r | |
2653 | //\r | |
47d20b54 | 2654 | if ((PciHeader.VendorId == 0xffff) && (Func == 0)) {\r |
5d73d92f | 2655 | break;\r |
2656 | }\r | |
2657 | \r | |
2658 | if (PciHeader.VendorId != 0xffff) {\r | |
5d73d92f | 2659 | if (PrintTitle) {\r |
47d20b54 | 2660 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r |
5d73d92f | 2661 | PrintTitle = FALSE;\r |
2662 | }\r | |
2663 | \r | |
2664 | IoDev->Pci.Read (\r | |
47d20b54 MK |
2665 | IoDev,\r |
2666 | EfiPciWidthUint32,\r | |
2667 | Address,\r | |
2668 | sizeof (PciHeader) / sizeof (UINT32),\r | |
2669 | &PciHeader\r | |
2670 | );\r | |
2671 | \r | |
2672 | ShellPrintHiiEx (\r | |
2673 | -1,\r | |
2674 | -1,\r | |
2675 | NULL,\r | |
2676 | STRING_TOKEN (STR_PCI_LINE_P1),\r | |
2677 | gShellDebug1HiiHandle,\r | |
5d73d92f | 2678 | IoDev->SegmentNumber,\r |
2679 | Bus,\r | |
2680 | Device,\r | |
2681 | Func\r | |
47d20b54 | 2682 | );\r |
5d73d92f | 2683 | \r |
2684 | PciPrintClassCode (PciHeader.ClassCode, FALSE);\r | |
47d20b54 MK |
2685 | ShellPrintHiiEx (\r |
2686 | -1,\r | |
2687 | -1,\r | |
2688 | NULL,\r | |
2689 | STRING_TOKEN (STR_PCI_LINE_P2),\r | |
2690 | gShellDebug1HiiHandle,\r | |
5d73d92f | 2691 | PciHeader.VendorId,\r |
2692 | PciHeader.DeviceId,\r | |
2693 | PciHeader.ClassCode[0]\r | |
47d20b54 | 2694 | );\r |
5d73d92f | 2695 | \r |
2696 | ScreenCount += 2;\r | |
47d20b54 | 2697 | if ((ScreenCount >= ScreenSize) && (ScreenSize != 0)) {\r |
5d73d92f | 2698 | //\r |
2699 | // If ScreenSize == 0 we have the console redirected so don't\r | |
2700 | // block updates\r | |
2701 | //\r | |
2702 | ScreenCount = 0;\r | |
2703 | }\r | |
47d20b54 | 2704 | \r |
5d73d92f | 2705 | //\r |
2706 | // If this is not a multi-function device, we can leave the loop\r | |
2707 | // to deal with the next device.\r | |
2708 | //\r | |
47d20b54 | 2709 | if ((Func == 0) && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r |
5d73d92f | 2710 | break;\r |
2711 | }\r | |
2712 | }\r | |
2713 | }\r | |
2714 | }\r | |
2715 | }\r | |
47d20b54 | 2716 | \r |
5d73d92f | 2717 | //\r |
2718 | // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r | |
2719 | // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r | |
2720 | // devices on all bus, we can leave loop.\r | |
2721 | //\r | |
2722 | if (Descriptors == NULL) {\r | |
2723 | break;\r | |
2724 | }\r | |
2725 | }\r | |
2726 | }\r | |
2727 | \r | |
2728 | Status = EFI_SUCCESS;\r | |
2729 | goto Done;\r | |
2730 | }\r | |
2731 | \r | |
47d20b54 MK |
2732 | ExplainData = FALSE;\r |
2733 | Segment = 0;\r | |
2734 | Bus = 0;\r | |
2735 | Device = 0;\r | |
2736 | Func = 0;\r | |
2737 | ExtendedCapability = 0xFFFF;\r | |
2738 | if (ShellCommandLineGetFlag (Package, L"-i")) {\r | |
5d73d92f | 2739 | ExplainData = TRUE;\r |
2740 | }\r | |
2741 | \r | |
47d20b54 | 2742 | Temp = ShellCommandLineGetValue (Package, L"-s");\r |
5d73d92f | 2743 | if (Temp != NULL) {\r |
6855763e CP |
2744 | //\r |
2745 | // Input converted to hexadecimal number.\r | |
2746 | //\r | |
2747 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
47d20b54 | 2748 | Segment = (UINT16)RetVal;\r |
6855763e | 2749 | } else {\r |
ba0014b9 | 2750 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2751 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2752 | goto Done;\r | |
2753 | }\r | |
5d73d92f | 2754 | }\r |
2755 | \r | |
2756 | //\r | |
2757 | // The first Argument(except "-i") is assumed to be Bus number, second\r | |
2758 | // to be Device number, and third to be Func number.\r | |
2759 | //\r | |
47d20b54 | 2760 | Temp = ShellCommandLineGetRawValue (Package, 1);\r |
5d73d92f | 2761 | if (Temp != NULL) {\r |
6855763e CP |
2762 | //\r |
2763 | // Input converted to hexadecimal number.\r | |
2764 | //\r | |
2765 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
47d20b54 | 2766 | Bus = (UINT16)RetVal;\r |
6855763e | 2767 | } else {\r |
ba0014b9 | 2768 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2769 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2770 | goto Done;\r | |
2771 | }\r | |
2772 | \r | |
0c84a69f | 2773 | if (Bus > PCI_MAX_BUS) {\r |
47d20b54 | 2774 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r |
5d73d92f | 2775 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2776 | goto Done;\r | |
2777 | }\r | |
2778 | }\r | |
47d20b54 MK |
2779 | \r |
2780 | Temp = ShellCommandLineGetRawValue (Package, 2);\r | |
5d73d92f | 2781 | if (Temp != NULL) {\r |
6855763e CP |
2782 | //\r |
2783 | // Input converted to hexadecimal number.\r | |
2784 | //\r | |
2785 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
47d20b54 | 2786 | Device = (UINT16)RetVal;\r |
6855763e | 2787 | } else {\r |
ba0014b9 | 2788 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2789 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2790 | goto Done;\r | |
2791 | }\r | |
2792 | \r | |
47d20b54 MK |
2793 | if (Device > PCI_MAX_DEVICE) {\r |
2794 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r | |
5d73d92f | 2795 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2796 | goto Done;\r | |
2797 | }\r | |
2798 | }\r | |
2799 | \r | |
47d20b54 | 2800 | Temp = ShellCommandLineGetRawValue (Package, 3);\r |
5d73d92f | 2801 | if (Temp != NULL) {\r |
6855763e CP |
2802 | //\r |
2803 | // Input converted to hexadecimal number.\r | |
2804 | //\r | |
2805 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
47d20b54 | 2806 | Func = (UINT16)RetVal;\r |
6855763e | 2807 | } else {\r |
ba0014b9 | 2808 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
6855763e CP |
2809 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2810 | goto Done;\r | |
2811 | }\r | |
2812 | \r | |
47d20b54 MK |
2813 | if (Func > PCI_MAX_FUNC) {\r |
2814 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);\r | |
5d73d92f | 2815 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2816 | goto Done;\r | |
2817 | }\r | |
2818 | }\r | |
2819 | \r | |
31d7be01 RN |
2820 | Temp = ShellCommandLineGetValue (Package, L"-ec");\r |
2821 | if (Temp != NULL) {\r | |
2822 | //\r | |
2823 | // Input converted to hexadecimal number.\r | |
2824 | //\r | |
2825 | if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r | |
47d20b54 | 2826 | ExtendedCapability = (UINT16)RetVal;\r |
31d7be01 | 2827 | } else {\r |
ba0014b9 | 2828 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);\r |
31d7be01 RN |
2829 | ShellStatus = SHELL_INVALID_PARAMETER;\r |
2830 | goto Done;\r | |
2831 | }\r | |
2832 | }\r | |
2833 | \r | |
5d73d92f | 2834 | //\r |
2835 | // Find the protocol interface who's in charge of current segment, and its\r | |
2836 | // bus range covers the current bus\r | |
2837 | //\r | |
2838 | Status = PciFindProtocolInterface (\r | |
47d20b54 MK |
2839 | HandleBuf,\r |
2840 | HandleCount,\r | |
2841 | Segment,\r | |
2842 | Bus,\r | |
2843 | &IoDev\r | |
2844 | );\r | |
5d73d92f | 2845 | \r |
2846 | if (EFI_ERROR (Status)) {\r | |
47d20b54 MK |
2847 | ShellPrintHiiEx (\r |
2848 | -1,\r | |
2849 | -1,\r | |
2850 | NULL,\r | |
2851 | STRING_TOKEN (STR_PCI_NO_FIND),\r | |
2852 | gShellDebug1HiiHandle,\r | |
2853 | L"pci",\r | |
5d73d92f | 2854 | Segment,\r |
2855 | Bus\r | |
47d20b54 | 2856 | );\r |
5d73d92f | 2857 | ShellStatus = SHELL_NOT_FOUND;\r |
2858 | goto Done;\r | |
2859 | }\r | |
2860 | \r | |
0c84a69f | 2861 | Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r |
47d20b54 MK |
2862 | Status = IoDev->Pci.Read (\r |
2863 | IoDev,\r | |
2864 | EfiPciWidthUint8,\r | |
2865 | Address,\r | |
2866 | sizeof (ConfigSpace),\r | |
2867 | &ConfigSpace\r | |
2868 | );\r | |
5d73d92f | 2869 | \r |
2870 | if (EFI_ERROR (Status)) {\r | |
47d20b54 | 2871 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");\r |
5d73d92f | 2872 | ShellStatus = SHELL_ACCESS_DENIED;\r |
2873 | goto Done;\r | |
2874 | }\r | |
2875 | \r | |
2876 | mConfigSpace = &ConfigSpace;\r | |
47d20b54 | 2877 | ShellPrintHiiEx (\r |
5d73d92f | 2878 | -1,\r |
2879 | -1,\r | |
2880 | NULL,\r | |
2881 | STRING_TOKEN (STR_PCI_INFO),\r | |
2882 | gShellDebug1HiiHandle,\r | |
2883 | Segment,\r | |
2884 | Bus,\r | |
2885 | Device,\r | |
2886 | Func,\r | |
2887 | Segment,\r | |
2888 | Bus,\r | |
2889 | Device,\r | |
2890 | Func\r | |
47d20b54 | 2891 | );\r |
5d73d92f | 2892 | \r |
2893 | //\r | |
2894 | // Dump standard header of configuration space\r | |
2895 | //\r | |
2896 | SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r | |
2897 | \r | |
a1d4bfcc | 2898 | DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r |
47d20b54 | 2899 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 2900 | \r |
2901 | //\r | |
2902 | // Dump device dependent Part of configuration space\r | |
2903 | //\r | |
a1d4bfcc | 2904 | DumpHex (\r |
5d73d92f | 2905 | 2,\r |
2906 | SizeOfHeader,\r | |
2907 | sizeof (ConfigSpace) - SizeOfHeader,\r | |
2908 | ConfigSpace.Data\r | |
47d20b54 | 2909 | );\r |
5d73d92f | 2910 | \r |
33cc487c | 2911 | ExtendedConfigSpace = NULL;\r |
f1894fa2 | 2912 | ExtendedConfigSize = 0;\r |
47d20b54 | 2913 | PcieCapabilityPtr = LocatePciCapability (&ConfigSpace, EFI_PCI_CAPABILITY_ID_PCIEXP);\r |
33cc487c RN |
2914 | if (PcieCapabilityPtr != 0) {\r |
2915 | ExtendedConfigSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r | |
2916 | ExtendedConfigSpace = AllocatePool (ExtendedConfigSize);\r | |
2917 | if (ExtendedConfigSpace != NULL) {\r | |
2918 | Status = IoDev->Pci.Read (\r | |
2919 | IoDev,\r | |
2920 | EfiPciWidthUint32,\r | |
2921 | EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET),\r | |
2922 | ExtendedConfigSize / sizeof (UINT32),\r | |
2923 | ExtendedConfigSpace\r | |
2924 | );\r | |
2925 | if (EFI_ERROR (Status)) {\r | |
2926 | SHELL_FREE_NON_NULL (ExtendedConfigSpace);\r | |
2927 | }\r | |
2928 | }\r | |
2929 | }\r | |
2930 | \r | |
2931 | if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r | |
2932 | //\r | |
2933 | // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r | |
2934 | //\r | |
2935 | ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r | |
2936 | \r | |
2937 | DumpHex (\r | |
2938 | 2,\r | |
2939 | EFI_PCIE_CAPABILITY_BASE_OFFSET,\r | |
2940 | ExtendedConfigSize,\r | |
2941 | ExtendedConfigSpace\r | |
2942 | );\r | |
2943 | }\r | |
2944 | \r | |
5d73d92f | 2945 | //\r |
2946 | // If "-i" appears in command line, interpret data in configuration space\r | |
2947 | //\r | |
2948 | if (ExplainData) {\r | |
33cc487c | 2949 | PciExplainPci (&ConfigSpace, Address, IoDev);\r |
f1894fa2 | 2950 | if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r |
33cc487c | 2951 | PciExplainPciExpress (\r |
47d20b54 | 2952 | (PCI_CAPABILITY_PCIEXP *)((UINT8 *)&ConfigSpace + PcieCapabilityPtr),\r |
33cc487c | 2953 | ExtendedConfigSpace,\r |
3d0df0f0 | 2954 | ExtendedConfigSize,\r |
33cc487c RN |
2955 | ExtendedCapability\r |
2956 | );\r | |
2957 | }\r | |
5d73d92f | 2958 | }\r |
2959 | }\r | |
47d20b54 | 2960 | \r |
5d73d92f | 2961 | Done:\r |
2962 | if (HandleBuf != NULL) {\r | |
2963 | FreePool (HandleBuf);\r | |
2964 | }\r | |
47d20b54 | 2965 | \r |
5d73d92f | 2966 | if (Package != NULL) {\r |
2967 | ShellCommandLineFreeVarList (Package);\r | |
2968 | }\r | |
47d20b54 | 2969 | \r |
5d73d92f | 2970 | mConfigSpace = NULL;\r |
2971 | return ShellStatus;\r | |
2972 | }\r | |
2973 | \r | |
a1d4bfcc | 2974 | /**\r |
5d73d92f | 2975 | This function finds out the protocol which is in charge of the given\r |
2976 | segment, and its bus range covers the current bus number. It lookes\r | |
2977 | each instances of RootBridgeIoProtocol handle, until the one meets the\r | |
2978 | criteria is found.\r | |
2979 | \r | |
a1d4bfcc | 2980 | @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r |
2981 | @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r | |
2982 | @param[in] Segment Segment number of device we are dealing with.\r | |
2983 | @param[in] Bus Bus number of device we are dealing with.\r | |
2984 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
5d73d92f | 2985 | \r |
a1d4bfcc | 2986 | @retval EFI_SUCCESS The command completed successfully.\r |
2987 | @retval EFI_INVALID_PARAMETER Invalid parameter.\r | |
5d73d92f | 2988 | \r |
2989 | **/\r | |
a1d4bfcc | 2990 | EFI_STATUS\r |
2991 | PciFindProtocolInterface (\r | |
47d20b54 MK |
2992 | IN EFI_HANDLE *HandleBuf,\r |
2993 | IN UINTN HandleCount,\r | |
2994 | IN UINT16 Segment,\r | |
2995 | IN UINT16 Bus,\r | |
2996 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r | |
a1d4bfcc | 2997 | )\r |
5d73d92f | 2998 | {\r |
47d20b54 MK |
2999 | UINTN Index;\r |
3000 | EFI_STATUS Status;\r | |
3001 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r | |
3002 | UINT16 MinBus;\r | |
3003 | UINT16 MaxBus;\r | |
3004 | BOOLEAN IsEnd;\r | |
5d73d92f | 3005 | \r |
5d73d92f | 3006 | //\r |
3007 | // Go through all handles, until the one meets the criteria is found\r | |
3008 | //\r | |
3009 | for (Index = 0; Index < HandleCount; Index++) {\r | |
3010 | Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r | |
3011 | if (EFI_ERROR (Status)) {\r | |
3012 | return Status;\r | |
3013 | }\r | |
47d20b54 | 3014 | \r |
5d73d92f | 3015 | //\r |
3016 | // When Descriptors == NULL, the Configuration() is not implemented,\r | |
3017 | // so we only check the Segment number\r | |
3018 | //\r | |
47d20b54 | 3019 | if ((Descriptors == NULL) && (Segment == (*IoDev)->SegmentNumber)) {\r |
5d73d92f | 3020 | return EFI_SUCCESS;\r |
3021 | }\r | |
3022 | \r | |
3023 | if ((*IoDev)->SegmentNumber != Segment) {\r | |
3024 | continue;\r | |
3025 | }\r | |
3026 | \r | |
3027 | while (TRUE) {\r | |
3028 | Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r | |
3029 | if (EFI_ERROR (Status)) {\r | |
3030 | return Status;\r | |
3031 | }\r | |
3032 | \r | |
3033 | if (IsEnd) {\r | |
3034 | break;\r | |
3035 | }\r | |
3036 | \r | |
47d20b54 | 3037 | if ((MinBus <= Bus) && (MaxBus >= Bus)) {\r |
2c46dd23 | 3038 | return EFI_SUCCESS;\r |
5d73d92f | 3039 | }\r |
3040 | }\r | |
3041 | }\r | |
3042 | \r | |
2c46dd23 | 3043 | return EFI_NOT_FOUND;\r |
5d73d92f | 3044 | }\r |
3045 | \r | |
a1d4bfcc | 3046 | /**\r |
3047 | This function gets the protocol interface from the given handle, and\r | |
3048 | obtains its address space descriptors.\r | |
3049 | \r | |
3050 | @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r | |
3051 | @param[out] IoDev Handle used to access configuration space of PCI device.\r | |
3052 | @param[out] Descriptors Points to the address space descriptors.\r | |
3053 | \r | |
3054 | @retval EFI_SUCCESS The command completed successfully\r | |
3055 | **/\r | |
5d73d92f | 3056 | EFI_STATUS\r |
3057 | PciGetProtocolAndResource (\r | |
47d20b54 MK |
3058 | IN EFI_HANDLE Handle,\r |
3059 | OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r | |
3060 | OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r | |
5d73d92f | 3061 | )\r |
5d73d92f | 3062 | {\r |
3063 | EFI_STATUS Status;\r | |
3064 | \r | |
3065 | //\r | |
3066 | // Get inferface from protocol\r | |
3067 | //\r | |
3068 | Status = gBS->HandleProtocol (\r | |
47d20b54 MK |
3069 | Handle,\r |
3070 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
3071 | (VOID **)IoDev\r | |
3072 | );\r | |
5d73d92f | 3073 | \r |
3074 | if (EFI_ERROR (Status)) {\r | |
3075 | return Status;\r | |
3076 | }\r | |
47d20b54 | 3077 | \r |
5d73d92f | 3078 | //\r |
3079 | // Call Configuration() to get address space descriptors\r | |
3080 | //\r | |
47d20b54 | 3081 | Status = (*IoDev)->Configuration (*IoDev, (VOID **)Descriptors);\r |
5d73d92f | 3082 | if (Status == EFI_UNSUPPORTED) {\r |
3083 | *Descriptors = NULL;\r | |
3084 | return EFI_SUCCESS;\r | |
5d73d92f | 3085 | } else {\r |
3086 | return Status;\r | |
3087 | }\r | |
3088 | }\r | |
3089 | \r | |
a1d4bfcc | 3090 | /**\r |
3091 | This function get the next bus range of given address space descriptors.\r | |
3092 | It also moves the pointer backward a node, to get prepared to be called\r | |
3093 | again.\r | |
3094 | \r | |
4ff7e37b ED |
3095 | @param[in, out] Descriptors Points to current position of a serial of address space\r |
3096 | descriptors.\r | |
3097 | @param[out] MinBus The lower range of bus number.\r | |
3098 | @param[out] MaxBus The upper range of bus number.\r | |
3099 | @param[out] IsEnd Meet end of the serial of descriptors.\r | |
a1d4bfcc | 3100 | \r |
3101 | @retval EFI_SUCCESS The command completed successfully.\r | |
3102 | **/\r | |
5d73d92f | 3103 | EFI_STATUS\r |
3104 | PciGetNextBusRange (\r | |
3105 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r | |
3106 | OUT UINT16 *MinBus,\r | |
3107 | OUT UINT16 *MaxBus,\r | |
3108 | OUT BOOLEAN *IsEnd\r | |
3109 | )\r | |
5d73d92f | 3110 | {\r |
3111 | *IsEnd = FALSE;\r | |
3112 | \r | |
3113 | //\r | |
3114 | // When *Descriptors is NULL, Configuration() is not implemented, so assume\r | |
3115 | // range is 0~PCI_MAX_BUS\r | |
3116 | //\r | |
3117 | if ((*Descriptors) == NULL) {\r | |
3118 | *MinBus = 0;\r | |
3119 | *MaxBus = PCI_MAX_BUS;\r | |
3120 | return EFI_SUCCESS;\r | |
3121 | }\r | |
47d20b54 | 3122 | \r |
5d73d92f | 3123 | //\r |
3124 | // *Descriptors points to one or more address space descriptors, which\r | |
3125 | // ends with a end tagged descriptor. Examine each of the descriptors,\r | |
3126 | // if a bus typed one is found and its bus range covers bus, this handle\r | |
3127 | // is the handle we are looking for.\r | |
3128 | //\r | |
5d73d92f | 3129 | \r |
3130 | while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r | |
3131 | if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r | |
47d20b54 MK |
3132 | *MinBus = (UINT16)(*Descriptors)->AddrRangeMin;\r |
3133 | *MaxBus = (UINT16)(*Descriptors)->AddrRangeMax;\r | |
5d73d92f | 3134 | (*Descriptors)++;\r |
3737ac2b | 3135 | return (EFI_SUCCESS);\r |
5d73d92f | 3136 | }\r |
3137 | \r | |
3138 | (*Descriptors)++;\r | |
3139 | }\r | |
3140 | \r | |
3737ac2b | 3141 | if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r |
3142 | *IsEnd = TRUE;\r | |
3143 | }\r | |
3144 | \r | |
5d73d92f | 3145 | return EFI_SUCCESS;\r |
3146 | }\r | |
3147 | \r | |
a1d4bfcc | 3148 | /**\r |
5d73d92f | 3149 | Explain the data in PCI configuration space. The part which is common for\r |
3150 | PCI device and bridge is interpreted in this function. It calls other\r | |
3151 | functions to interpret data unique for device or bridge.\r | |
3152 | \r | |
a1d4bfcc | 3153 | @param[in] ConfigSpace Data in PCI configuration space.\r |
3154 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3155 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
5d73d92f | 3156 | **/\r |
33cc487c RN |
3157 | VOID\r |
3158 | PciExplainPci (\r | |
47d20b54 MK |
3159 | IN PCI_CONFIG_SPACE *ConfigSpace,\r |
3160 | IN UINT64 Address,\r | |
3161 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
a1d4bfcc | 3162 | )\r |
5d73d92f | 3163 | {\r |
47d20b54 MK |
3164 | PCI_DEVICE_INDEPENDENT_REGION *Common;\r |
3165 | PCI_HEADER_TYPE HeaderType;\r | |
5d73d92f | 3166 | \r |
3167 | Common = &(ConfigSpace->Common);\r | |
3168 | \r | |
c37e0f16 | 3169 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3170 | \r |
3171 | //\r | |
3172 | // Print Vendor Id and Device Id\r | |
3173 | //\r | |
47d20b54 MK |
3174 | ShellPrintHiiEx (\r |
3175 | -1,\r | |
3176 | -1,\r | |
3177 | NULL,\r | |
3178 | STRING_TOKEN (STR_PCI_LINE_VID_DID),\r | |
3179 | gShellDebug1HiiHandle,\r | |
5d73d92f | 3180 | INDEX_OF (&(Common->VendorId)),\r |
3181 | Common->VendorId,\r | |
3182 | INDEX_OF (&(Common->DeviceId)),\r | |
3183 | Common->DeviceId\r | |
47d20b54 | 3184 | );\r |
5d73d92f | 3185 | \r |
3186 | //\r | |
3187 | // Print register Command\r | |
3188 | //\r | |
3189 | PciExplainCommand (&(Common->Command));\r | |
3190 | \r | |
3191 | //\r | |
3192 | // Print register Status\r | |
3193 | //\r | |
3194 | PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r | |
3195 | \r | |
3196 | //\r | |
3197 | // Print register Revision ID\r | |
3198 | //\r | |
47d20b54 MK |
3199 | ShellPrintEx (-1, -1, L"\r\n");\r |
3200 | ShellPrintHiiEx (\r | |
3201 | -1,\r | |
3202 | -1,\r | |
3203 | NULL,\r | |
3204 | STRING_TOKEN (STR_PCI_LINE_RID),\r | |
3205 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3206 | INDEX_OF (&(Common->RevisionID)),\r |
3207 | Common->RevisionID\r | |
47d20b54 | 3208 | );\r |
5d73d92f | 3209 | \r |
3210 | //\r | |
3211 | // Print register BIST\r | |
3212 | //\r | |
47d20b54 | 3213 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r |
0c84a69f | 3214 | if ((Common->BIST & BIT7) != 0) {\r |
47d20b54 | 3215 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r |
5d73d92f | 3216 | } else {\r |
47d20b54 | 3217 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r |
5d73d92f | 3218 | }\r |
47d20b54 | 3219 | \r |
5d73d92f | 3220 | //\r |
3221 | // Print register Cache Line Size\r | |
3222 | //\r | |
47d20b54 MK |
3223 | ShellPrintHiiEx (\r |
3224 | -1,\r | |
3225 | -1,\r | |
3226 | NULL,\r | |
5d73d92f | 3227 | STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r |
3228 | gShellDebug1HiiHandle,\r | |
3229 | INDEX_OF (&(Common->CacheLineSize)),\r | |
3230 | Common->CacheLineSize\r | |
47d20b54 | 3231 | );\r |
5d73d92f | 3232 | \r |
3233 | //\r | |
3234 | // Print register Latency Timer\r | |
3235 | //\r | |
47d20b54 MK |
3236 | ShellPrintHiiEx (\r |
3237 | -1,\r | |
3238 | -1,\r | |
3239 | NULL,\r | |
5d73d92f | 3240 | STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r |
3241 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3242 | INDEX_OF (&(Common->LatencyTimer)),\r |
3243 | Common->LatencyTimer\r | |
47d20b54 | 3244 | );\r |
5d73d92f | 3245 | \r |
3246 | //\r | |
3247 | // Print register Header Type\r | |
3248 | //\r | |
47d20b54 MK |
3249 | ShellPrintHiiEx (\r |
3250 | -1,\r | |
3251 | -1,\r | |
3252 | NULL,\r | |
5d73d92f | 3253 | STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r |
3254 | gShellDebug1HiiHandle,\r | |
3255 | INDEX_OF (&(Common->HeaderType)),\r | |
3256 | Common->HeaderType\r | |
47d20b54 | 3257 | );\r |
5d73d92f | 3258 | \r |
0c84a69f | 3259 | if ((Common->HeaderType & BIT7) != 0) {\r |
47d20b54 | 3260 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r |
5d73d92f | 3261 | } else {\r |
47d20b54 | 3262 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r |
5d73d92f | 3263 | }\r |
3264 | \r | |
47d20b54 | 3265 | HeaderType = (PCI_HEADER_TYPE)(UINT8)(Common->HeaderType & 0x7f);\r |
5d73d92f | 3266 | switch (HeaderType) {\r |
47d20b54 MK |
3267 | case PciDevice:\r |
3268 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r | |
3269 | break;\r | |
5d73d92f | 3270 | \r |
47d20b54 MK |
3271 | case PciP2pBridge:\r |
3272 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r | |
3273 | break;\r | |
5d73d92f | 3274 | \r |
47d20b54 MK |
3275 | case PciCardBusBridge:\r |
3276 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r | |
3277 | break;\r | |
5d73d92f | 3278 | \r |
47d20b54 MK |
3279 | default:\r |
3280 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r | |
3281 | HeaderType = PciUndefined;\r | |
5d73d92f | 3282 | }\r |
3283 | \r | |
3284 | //\r | |
3285 | // Print register Class Code\r | |
3286 | //\r | |
47d20b54 MK |
3287 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r |
3288 | PciPrintClassCode ((UINT8 *)Common->ClassCode, TRUE);\r | |
c37e0f16 | 3289 | ShellPrintEx (-1, -1, L"\r\n");\r |
5d73d92f | 3290 | }\r |
3291 | \r | |
a1d4bfcc | 3292 | /**\r |
3293 | Explain the device specific part of data in PCI configuration space.\r | |
3294 | \r | |
3295 | @param[in] Device Data in PCI configuration space.\r | |
3296 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3297 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3298 | \r | |
3299 | @retval EFI_SUCCESS The command completed successfully.\r | |
3300 | **/\r | |
5d73d92f | 3301 | EFI_STATUS\r |
3302 | PciExplainDeviceData (\r | |
47d20b54 MK |
3303 | IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r |
3304 | IN UINT64 Address,\r | |
3305 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 3306 | )\r |
5d73d92f | 3307 | {\r |
3308 | UINTN Index;\r | |
3309 | BOOLEAN BarExist;\r | |
3310 | EFI_STATUS Status;\r | |
3311 | UINTN BarCount;\r | |
3312 | \r | |
3313 | //\r | |
3314 | // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r | |
3315 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3316 | // list detail information about this Bar.\r | |
3317 | //\r | |
47d20b54 | 3318 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r |
5d73d92f | 3319 | \r |
47d20b54 MK |
3320 | BarExist = FALSE;\r |
3321 | BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r | |
5d73d92f | 3322 | for (Index = 0; Index < BarCount; Index++) {\r |
3323 | if (Device->Bar[Index] == 0) {\r | |
3324 | continue;\r | |
3325 | }\r | |
3326 | \r | |
3327 | if (!BarExist) {\r | |
3328 | BarExist = TRUE;\r | |
47d20b54 | 3329 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r |
c37e0f16 | 3330 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3331 | }\r |
3332 | \r | |
3333 | Status = PciExplainBar (\r | |
47d20b54 MK |
3334 | &(Device->Bar[Index]),\r |
3335 | &(mConfigSpace->Common.Command),\r | |
3336 | Address,\r | |
3337 | IoDev,\r | |
3338 | &Index\r | |
3339 | );\r | |
5d73d92f | 3340 | \r |
3341 | if (EFI_ERROR (Status)) {\r | |
3342 | break;\r | |
3343 | }\r | |
3344 | }\r | |
3345 | \r | |
3346 | if (!BarExist) {\r | |
47d20b54 | 3347 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r |
5d73d92f | 3348 | } else {\r |
c37e0f16 | 3349 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3350 | }\r |
3351 | \r | |
3352 | //\r | |
3353 | // Print register Expansion ROM Base Address\r | |
3354 | //\r | |
0c84a69f | 3355 | if ((Device->ExpansionRomBar & BIT0) == 0) {\r |
47d20b54 | 3356 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ExpansionRomBar)));\r |
5d73d92f | 3357 | } else {\r |
47d20b54 MK |
3358 | ShellPrintHiiEx (\r |
3359 | -1,\r | |
3360 | -1,\r | |
3361 | NULL,\r | |
5d73d92f | 3362 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r |
3363 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3364 | INDEX_OF (&(Device->ExpansionRomBar)),\r |
3365 | Device->ExpansionRomBar\r | |
47d20b54 | 3366 | );\r |
5d73d92f | 3367 | }\r |
47d20b54 | 3368 | \r |
5d73d92f | 3369 | //\r |
3370 | // Print register Cardbus CIS ptr\r | |
3371 | //\r | |
47d20b54 MK |
3372 | ShellPrintHiiEx (\r |
3373 | -1,\r | |
3374 | -1,\r | |
3375 | NULL,\r | |
5d73d92f | 3376 | STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r |
3377 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3378 | INDEX_OF (&(Device->CISPtr)),\r |
3379 | Device->CISPtr\r | |
47d20b54 | 3380 | );\r |
5d73d92f | 3381 | \r |
3382 | //\r | |
3383 | // Print register Sub-vendor ID and subsystem ID\r | |
3384 | //\r | |
47d20b54 MK |
3385 | ShellPrintHiiEx (\r |
3386 | -1,\r | |
3387 | -1,\r | |
3388 | NULL,\r | |
5d73d92f | 3389 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r |
3390 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3391 | INDEX_OF (&(Device->SubsystemVendorID)),\r |
3392 | Device->SubsystemVendorID\r | |
47d20b54 | 3393 | );\r |
5d73d92f | 3394 | \r |
47d20b54 MK |
3395 | ShellPrintHiiEx (\r |
3396 | -1,\r | |
3397 | -1,\r | |
3398 | NULL,\r | |
5d73d92f | 3399 | STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r |
3400 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3401 | INDEX_OF (&(Device->SubsystemID)),\r |
3402 | Device->SubsystemID\r | |
47d20b54 | 3403 | );\r |
5d73d92f | 3404 | \r |
3405 | //\r | |
3406 | // Print register Capabilities Ptr\r | |
3407 | //\r | |
47d20b54 MK |
3408 | ShellPrintHiiEx (\r |
3409 | -1,\r | |
3410 | -1,\r | |
3411 | NULL,\r | |
5d73d92f | 3412 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r |
3413 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3414 | INDEX_OF (&(Device->CapabilityPtr)),\r |
3415 | Device->CapabilityPtr\r | |
47d20b54 | 3416 | );\r |
5d73d92f | 3417 | \r |
3418 | //\r | |
3419 | // Print register Interrupt Line and interrupt pin\r | |
3420 | //\r | |
47d20b54 MK |
3421 | ShellPrintHiiEx (\r |
3422 | -1,\r | |
3423 | -1,\r | |
3424 | NULL,\r | |
5d73d92f | 3425 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r |
3426 | gShellDebug1HiiHandle,\r | |
3427 | INDEX_OF (&(Device->InterruptLine)),\r | |
3428 | Device->InterruptLine\r | |
47d20b54 | 3429 | );\r |
5d73d92f | 3430 | \r |
47d20b54 MK |
3431 | ShellPrintHiiEx (\r |
3432 | -1,\r | |
3433 | -1,\r | |
3434 | NULL,\r | |
5d73d92f | 3435 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r |
3436 | gShellDebug1HiiHandle,\r | |
3437 | INDEX_OF (&(Device->InterruptPin)),\r | |
3438 | Device->InterruptPin\r | |
47d20b54 | 3439 | );\r |
5d73d92f | 3440 | \r |
3441 | //\r | |
3442 | // Print register Min_Gnt and Max_Lat\r | |
3443 | //\r | |
47d20b54 MK |
3444 | ShellPrintHiiEx (\r |
3445 | -1,\r | |
3446 | -1,\r | |
3447 | NULL,\r | |
5d73d92f | 3448 | STRING_TOKEN (STR_PCI2_MIN_GNT),\r |
3449 | gShellDebug1HiiHandle,\r | |
3450 | INDEX_OF (&(Device->MinGnt)),\r | |
3451 | Device->MinGnt\r | |
47d20b54 | 3452 | );\r |
5d73d92f | 3453 | \r |
47d20b54 MK |
3454 | ShellPrintHiiEx (\r |
3455 | -1,\r | |
3456 | -1,\r | |
3457 | NULL,\r | |
5d73d92f | 3458 | STRING_TOKEN (STR_PCI2_MAX_LAT),\r |
3459 | gShellDebug1HiiHandle,\r | |
3460 | INDEX_OF (&(Device->MaxLat)),\r | |
3461 | Device->MaxLat\r | |
47d20b54 | 3462 | );\r |
5d73d92f | 3463 | \r |
3464 | return EFI_SUCCESS;\r | |
3465 | }\r | |
3466 | \r | |
a1d4bfcc | 3467 | /**\r |
3468 | Explain the bridge specific part of data in PCI configuration space.\r | |
3469 | \r | |
3470 | @param[in] Bridge Bridge specific data region in PCI configuration space.\r | |
3471 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3472 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3473 | \r | |
3474 | @retval EFI_SUCCESS The command completed successfully.\r | |
3475 | **/\r | |
5d73d92f | 3476 | EFI_STATUS\r |
3477 | PciExplainBridgeData (\r | |
47d20b54 MK |
3478 | IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r |
3479 | IN UINT64 Address,\r | |
3480 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 3481 | )\r |
5d73d92f | 3482 | {\r |
3483 | UINTN Index;\r | |
3484 | BOOLEAN BarExist;\r | |
3485 | UINTN BarCount;\r | |
3486 | UINT32 IoAddress32;\r | |
3487 | EFI_STATUS Status;\r | |
3488 | \r | |
3489 | //\r | |
3490 | // Print Base Address Registers. When Bar = 0, this Bar does not\r | |
3491 | // exist. If these no Bar for this function, print "none", otherwise\r | |
3492 | // list detail information about this Bar.\r | |
3493 | //\r | |
47d20b54 | 3494 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r |
5d73d92f | 3495 | \r |
47d20b54 MK |
3496 | BarExist = FALSE;\r |
3497 | BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r | |
5d73d92f | 3498 | \r |
3499 | for (Index = 0; Index < BarCount; Index++) {\r | |
3500 | if (Bridge->Bar[Index] == 0) {\r | |
3501 | continue;\r | |
3502 | }\r | |
3503 | \r | |
3504 | if (!BarExist) {\r | |
3505 | BarExist = TRUE;\r | |
47d20b54 | 3506 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r |
c37e0f16 | 3507 | ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r |
5d73d92f | 3508 | }\r |
3509 | \r | |
3510 | Status = PciExplainBar (\r | |
47d20b54 MK |
3511 | &(Bridge->Bar[Index]),\r |
3512 | &(mConfigSpace->Common.Command),\r | |
3513 | Address,\r | |
3514 | IoDev,\r | |
3515 | &Index\r | |
3516 | );\r | |
5d73d92f | 3517 | \r |
3518 | if (EFI_ERROR (Status)) {\r | |
3519 | break;\r | |
3520 | }\r | |
3521 | }\r | |
3522 | \r | |
3523 | if (!BarExist) {\r | |
47d20b54 | 3524 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r |
5d73d92f | 3525 | } else {\r |
c37e0f16 | 3526 | ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r |
5d73d92f | 3527 | }\r |
3528 | \r | |
3529 | //\r | |
3530 | // Expansion register ROM Base Address\r | |
3531 | //\r | |
0c84a69f | 3532 | if ((Bridge->ExpansionRomBAR & BIT0) == 0) {\r |
47d20b54 | 3533 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ExpansionRomBAR)));\r |
5d73d92f | 3534 | } else {\r |
47d20b54 MK |
3535 | ShellPrintHiiEx (\r |
3536 | -1,\r | |
3537 | -1,\r | |
3538 | NULL,\r | |
5d73d92f | 3539 | STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r |
3540 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3541 | INDEX_OF (&(Bridge->ExpansionRomBAR)),\r |
3542 | Bridge->ExpansionRomBAR\r | |
47d20b54 | 3543 | );\r |
5d73d92f | 3544 | }\r |
47d20b54 | 3545 | \r |
5d73d92f | 3546 | //\r |
3547 | // Print Bus Numbers(Primary, Secondary, and Subordinate\r | |
3548 | //\r | |
47d20b54 MK |
3549 | ShellPrintHiiEx (\r |
3550 | -1,\r | |
3551 | -1,\r | |
3552 | NULL,\r | |
5d73d92f | 3553 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r |
3554 | gShellDebug1HiiHandle,\r | |
3555 | INDEX_OF (&(Bridge->PrimaryBus)),\r | |
3556 | INDEX_OF (&(Bridge->SecondaryBus)),\r | |
3557 | INDEX_OF (&(Bridge->SubordinateBus))\r | |
47d20b54 | 3558 | );\r |
5d73d92f | 3559 | \r |
c37e0f16 | 3560 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3561 | \r |
47d20b54 MK |
3562 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r |
3563 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r | |
3564 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r | |
5d73d92f | 3565 | \r |
3566 | //\r | |
3567 | // Print register Secondary Latency Timer\r | |
3568 | //\r | |
47d20b54 MK |
3569 | ShellPrintHiiEx (\r |
3570 | -1,\r | |
3571 | -1,\r | |
3572 | NULL,\r | |
5d73d92f | 3573 | STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r |
3574 | gShellDebug1HiiHandle,\r | |
3575 | INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r | |
3576 | Bridge->SecondaryLatencyTimer\r | |
47d20b54 | 3577 | );\r |
5d73d92f | 3578 | \r |
3579 | //\r | |
3580 | // Print register Secondary Status\r | |
3581 | //\r | |
3582 | PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r | |
3583 | \r | |
3584 | //\r | |
3585 | // Print I/O and memory ranges this bridge forwards. There are 3 resource\r | |
3586 | // types: I/O, memory, and pre-fetchable memory. For each resource type,\r | |
3587 | // base and limit address are listed.\r | |
3588 | //\r | |
47d20b54 | 3589 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r |
c37e0f16 | 3590 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3591 | \r |
3592 | //\r | |
3593 | // IO Base & Limit\r | |
3594 | //\r | |
47d20b54 | 3595 | IoAddress32 = (Bridge->IoBaseUpper16 << 16 | Bridge->IoBase << 8);\r |
5d73d92f | 3596 | IoAddress32 &= 0xfffff000;\r |
47d20b54 MK |
3597 | ShellPrintHiiEx (\r |
3598 | -1,\r | |
3599 | -1,\r | |
3600 | NULL,\r | |
5d73d92f | 3601 | STRING_TOKEN (STR_PCI2_TWO_VARS),\r |
3602 | gShellDebug1HiiHandle,\r | |
3603 | INDEX_OF (&(Bridge->IoBase)),\r | |
3604 | IoAddress32\r | |
47d20b54 | 3605 | );\r |
5d73d92f | 3606 | \r |
47d20b54 | 3607 | IoAddress32 = (Bridge->IoLimitUpper16 << 16 | Bridge->IoLimit << 8);\r |
5d73d92f | 3608 | IoAddress32 |= 0x00000fff;\r |
47d20b54 | 3609 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r |
5d73d92f | 3610 | \r |
3611 | //\r | |
3612 | // Memory Base & Limit\r | |
3613 | //\r | |
47d20b54 MK |
3614 | ShellPrintHiiEx (\r |
3615 | -1,\r | |
3616 | -1,\r | |
3617 | NULL,\r | |
5d73d92f | 3618 | STRING_TOKEN (STR_PCI2_MEMORY),\r |
3619 | gShellDebug1HiiHandle,\r | |
3620 | INDEX_OF (&(Bridge->MemoryBase)),\r | |
3621 | (Bridge->MemoryBase << 16) & 0xfff00000\r | |
47d20b54 | 3622 | );\r |
5d73d92f | 3623 | \r |
47d20b54 MK |
3624 | ShellPrintHiiEx (\r |
3625 | -1,\r | |
3626 | -1,\r | |
3627 | NULL,\r | |
5d73d92f | 3628 | STRING_TOKEN (STR_PCI2_ONE_VAR),\r |
3629 | gShellDebug1HiiHandle,\r | |
3630 | (Bridge->MemoryLimit << 16) | 0x000fffff\r | |
47d20b54 | 3631 | );\r |
5d73d92f | 3632 | \r |
3633 | //\r | |
3634 | // Pre-fetch-able Memory Base & Limit\r | |
3635 | //\r | |
47d20b54 MK |
3636 | ShellPrintHiiEx (\r |
3637 | -1,\r | |
3638 | -1,\r | |
3639 | NULL,\r | |
5d73d92f | 3640 | STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r |
3641 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3642 | INDEX_OF (&(Bridge->PrefetchableMemoryBase)),\r |
3643 | Bridge->PrefetchableBaseUpper32,\r | |
3644 | (Bridge->PrefetchableMemoryBase << 16) & 0xfff00000\r | |
47d20b54 | 3645 | );\r |
5d73d92f | 3646 | \r |
47d20b54 MK |
3647 | ShellPrintHiiEx (\r |
3648 | -1,\r | |
3649 | -1,\r | |
3650 | NULL,\r | |
5d73d92f | 3651 | STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r |
3652 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3653 | Bridge->PrefetchableLimitUpper32,\r |
3654 | (Bridge->PrefetchableMemoryLimit << 16) | 0x000fffff\r | |
47d20b54 | 3655 | );\r |
5d73d92f | 3656 | \r |
3657 | //\r | |
3658 | // Print register Capabilities Pointer\r | |
3659 | //\r | |
47d20b54 MK |
3660 | ShellPrintHiiEx (\r |
3661 | -1,\r | |
3662 | -1,\r | |
3663 | NULL,\r | |
5d73d92f | 3664 | STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r |
3665 | gShellDebug1HiiHandle,\r | |
0c84a69f RN |
3666 | INDEX_OF (&(Bridge->CapabilityPtr)),\r |
3667 | Bridge->CapabilityPtr\r | |
47d20b54 | 3668 | );\r |
5d73d92f | 3669 | \r |
3670 | //\r | |
3671 | // Print register Bridge Control\r | |
3672 | //\r | |
3673 | PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r | |
3674 | \r | |
3675 | //\r | |
3676 | // Print register Interrupt Line & PIN\r | |
3677 | //\r | |
47d20b54 MK |
3678 | ShellPrintHiiEx (\r |
3679 | -1,\r | |
3680 | -1,\r | |
3681 | NULL,\r | |
5d73d92f | 3682 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r |
3683 | gShellDebug1HiiHandle,\r | |
3684 | INDEX_OF (&(Bridge->InterruptLine)),\r | |
3685 | Bridge->InterruptLine\r | |
47d20b54 | 3686 | );\r |
5d73d92f | 3687 | \r |
47d20b54 MK |
3688 | ShellPrintHiiEx (\r |
3689 | -1,\r | |
3690 | -1,\r | |
3691 | NULL,\r | |
5d73d92f | 3692 | STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r |
3693 | gShellDebug1HiiHandle,\r | |
3694 | INDEX_OF (&(Bridge->InterruptPin)),\r | |
3695 | Bridge->InterruptPin\r | |
47d20b54 | 3696 | );\r |
5d73d92f | 3697 | \r |
3698 | return EFI_SUCCESS;\r | |
3699 | }\r | |
3700 | \r | |
a1d4bfcc | 3701 | /**\r |
3702 | Explain the Base Address Register(Bar) in PCI configuration space.\r | |
3703 | \r | |
4ff7e37b ED |
3704 | @param[in] Bar Points to the Base Address Register intended to interpret.\r |
3705 | @param[in] Command Points to the register Command.\r | |
3706 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3707 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3708 | @param[in, out] Index The Index.\r | |
a1d4bfcc | 3709 | \r |
3710 | @retval EFI_SUCCESS The command completed successfully.\r | |
3711 | **/\r | |
5d73d92f | 3712 | EFI_STATUS\r |
3713 | PciExplainBar (\r | |
47d20b54 MK |
3714 | IN UINT32 *Bar,\r |
3715 | IN UINT16 *Command,\r | |
3716 | IN UINT64 Address,\r | |
3717 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r | |
3718 | IN OUT UINTN *Index\r | |
5d73d92f | 3719 | )\r |
5d73d92f | 3720 | {\r |
47d20b54 MK |
3721 | UINT16 OldCommand;\r |
3722 | UINT16 NewCommand;\r | |
3723 | UINT64 Bar64;\r | |
3724 | UINT32 OldBar32;\r | |
3725 | UINT32 NewBar32;\r | |
3726 | UINT64 OldBar64;\r | |
3727 | UINT64 NewBar64;\r | |
3728 | BOOLEAN IsMem;\r | |
3729 | BOOLEAN IsBar32;\r | |
3730 | UINT64 RegAddress;\r | |
3731 | \r | |
3732 | IsBar32 = TRUE;\r | |
3733 | Bar64 = 0;\r | |
3734 | NewBar32 = 0;\r | |
3735 | NewBar64 = 0;\r | |
5d73d92f | 3736 | \r |
3737 | //\r | |
3738 | // According the bar type, list detail about this bar, for example: 32 or\r | |
3739 | // 64 bits; pre-fetchable or not.\r | |
3740 | //\r | |
0c84a69f | 3741 | if ((*Bar & BIT0) == 0) {\r |
5d73d92f | 3742 | //\r |
3743 | // This bar is of memory type\r | |
3744 | //\r | |
3745 | IsMem = TRUE;\r | |
3746 | \r | |
47d20b54 MK |
3747 | if (((*Bar & BIT1) == 0) && ((*Bar & BIT2) == 0)) {\r |
3748 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r | |
3749 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r | |
3750 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r | |
3751 | } else if (((*Bar & BIT1) == 0) && ((*Bar & BIT2) != 0)) {\r | |
5d73d92f | 3752 | Bar64 = 0x0;\r |
3753 | CopyMem (&Bar64, Bar, sizeof (UINT64));\r | |
47d20b54 MK |
3754 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32)RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r |
3755 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32)(Bar64 & 0xfffffffffffffff0ULL));\r | |
3756 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r | |
3757 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r | |
5d73d92f | 3758 | IsBar32 = FALSE;\r |
3759 | *Index += 1;\r | |
5d73d92f | 3760 | } else {\r |
3761 | //\r | |
3762 | // Reserved\r | |
3763 | //\r | |
47d20b54 MK |
3764 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r |
3765 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r | |
5d73d92f | 3766 | }\r |
3767 | \r | |
0c84a69f | 3768 | if ((*Bar & BIT3) == 0) {\r |
47d20b54 | 3769 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r |
5d73d92f | 3770 | } else {\r |
47d20b54 | 3771 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r |
5d73d92f | 3772 | }\r |
5d73d92f | 3773 | } else {\r |
3774 | //\r | |
3775 | // This bar is of io type\r | |
3776 | //\r | |
3777 | IsMem = FALSE;\r | |
47d20b54 | 3778 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r |
c37e0f16 | 3779 | ShellPrintEx (-1, -1, L"I/O ");\r |
5d73d92f | 3780 | }\r |
3781 | \r | |
3782 | //\r | |
3783 | // Get BAR length(or the amount of resource this bar demands for). To get\r | |
3784 | // Bar length, first we should temporarily disable I/O and memory access\r | |
3785 | // of this function(by set bits in the register Command), then write all\r | |
3786 | // "1"s to this bar. The bar value read back is the amount of resource\r | |
3787 | // this bar demands for.\r | |
3788 | //\r | |
3789 | //\r | |
3790 | // Disable io & mem access\r | |
3791 | //\r | |
47d20b54 MK |
3792 | OldCommand = *Command;\r |
3793 | NewCommand = (UINT16)(OldCommand & 0xfffc);\r | |
3794 | RegAddress = Address | INDEX_OF (Command);\r | |
5d73d92f | 3795 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r |
3796 | \r | |
3797 | RegAddress = Address | INDEX_OF (Bar);\r | |
3798 | \r | |
3799 | //\r | |
3800 | // Read after write the BAR to get the size\r | |
3801 | //\r | |
3802 | if (IsBar32) {\r | |
47d20b54 MK |
3803 | OldBar32 = *Bar;\r |
3804 | NewBar32 = 0xffffffff;\r | |
5d73d92f | 3805 | \r |
3806 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3807 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r | |
3808 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r | |
3809 | \r | |
3810 | if (IsMem) {\r | |
47d20b54 MK |
3811 | NewBar32 = NewBar32 & 0xfffffff0;\r |
3812 | NewBar32 = (~NewBar32) + 1;\r | |
5d73d92f | 3813 | } else {\r |
47d20b54 MK |
3814 | NewBar32 = NewBar32 & 0xfffffffc;\r |
3815 | NewBar32 = (~NewBar32) + 1;\r | |
3816 | NewBar32 = NewBar32 & 0x0000ffff;\r | |
5d73d92f | 3817 | }\r |
3818 | } else {\r | |
5d73d92f | 3819 | OldBar64 = 0x0;\r |
3820 | CopyMem (&OldBar64, Bar, sizeof (UINT64));\r | |
2b578de0 | 3821 | NewBar64 = 0xffffffffffffffffULL;\r |
5d73d92f | 3822 | \r |
3823 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3824 | IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r | |
3825 | IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r | |
3826 | \r | |
3827 | if (IsMem) {\r | |
47d20b54 MK |
3828 | NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r |
3829 | NewBar64 = (~NewBar64) + 1;\r | |
5d73d92f | 3830 | } else {\r |
47d20b54 MK |
3831 | NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r |
3832 | NewBar64 = (~NewBar64) + 1;\r | |
3833 | NewBar64 = NewBar64 & 0x000000000000ffff;\r | |
5d73d92f | 3834 | }\r |
3835 | }\r | |
47d20b54 | 3836 | \r |
5d73d92f | 3837 | //\r |
3838 | // Enable io & mem access\r | |
3839 | //\r | |
3840 | RegAddress = Address | INDEX_OF (Command);\r | |
3841 | IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r | |
3842 | \r | |
3843 | if (IsMem) {\r | |
3844 | if (IsBar32) {\r | |
47d20b54 MK |
3845 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r |
3846 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r | |
5d73d92f | 3847 | } else {\r |
47d20b54 MK |
3848 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)RShiftU64 (NewBar64, 32));\r |
3849 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)NewBar64);\r | |
c37e0f16 | 3850 | ShellPrintEx (-1, -1, L" ");\r |
47d20b54 MK |
3851 | ShellPrintHiiEx (\r |
3852 | -1,\r | |
3853 | -1,\r | |
3854 | NULL,\r | |
5d73d92f | 3855 | STRING_TOKEN (STR_PCI2_RSHIFT),\r |
3856 | gShellDebug1HiiHandle,\r | |
47d20b54 MK |
3857 | (UINT32)RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r |
3858 | );\r | |
3859 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32)(NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r | |
5d73d92f | 3860 | }\r |
3861 | } else {\r | |
47d20b54 MK |
3862 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r |
3863 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r | |
5d73d92f | 3864 | }\r |
3865 | \r | |
3866 | return EFI_SUCCESS;\r | |
3867 | }\r | |
3868 | \r | |
a1d4bfcc | 3869 | /**\r |
3870 | Explain the cardbus specific part of data in PCI configuration space.\r | |
3871 | \r | |
3872 | @param[in] CardBus CardBus specific region of PCI configuration space.\r | |
3873 | @param[in] Address Address used to access configuration space of this PCI device.\r | |
3874 | @param[in] IoDev Handle used to access configuration space of PCI device.\r | |
3875 | \r | |
3876 | @retval EFI_SUCCESS The command completed successfully.\r | |
3877 | **/\r | |
5d73d92f | 3878 | EFI_STATUS\r |
3879 | PciExplainCardBusData (\r | |
47d20b54 MK |
3880 | IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r |
3881 | IN UINT64 Address,\r | |
3882 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r | |
5d73d92f | 3883 | )\r |
5d73d92f | 3884 | {\r |
3885 | BOOLEAN Io32Bit;\r | |
3886 | PCI_CARDBUS_DATA *CardBusData;\r | |
3887 | \r | |
47d20b54 MK |
3888 | ShellPrintHiiEx (\r |
3889 | -1,\r | |
3890 | -1,\r | |
3891 | NULL,\r | |
5d73d92f | 3892 | STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r |
3893 | gShellDebug1HiiHandle,\r | |
3894 | INDEX_OF (&(CardBus->CardBusSocketReg)),\r | |
3895 | CardBus->CardBusSocketReg\r | |
47d20b54 | 3896 | );\r |
5d73d92f | 3897 | \r |
3898 | //\r | |
3899 | // Print Secondary Status\r | |
3900 | //\r | |
3901 | PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r | |
3902 | \r | |
3903 | //\r | |
3904 | // Print Bus Numbers(Primary bus number, CardBus bus number, and\r | |
3905 | // Subordinate bus number\r | |
3906 | //\r | |
47d20b54 MK |
3907 | ShellPrintHiiEx (\r |
3908 | -1,\r | |
3909 | -1,\r | |
3910 | NULL,\r | |
5d73d92f | 3911 | STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r |
3912 | gShellDebug1HiiHandle,\r | |
3913 | INDEX_OF (&(CardBus->PciBusNumber)),\r | |
3914 | INDEX_OF (&(CardBus->CardBusBusNumber)),\r | |
3915 | INDEX_OF (&(CardBus->SubordinateBusNumber))\r | |
47d20b54 | 3916 | );\r |
5d73d92f | 3917 | \r |
c37e0f16 | 3918 | ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r |
5d73d92f | 3919 | \r |
47d20b54 MK |
3920 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r |
3921 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r | |
3922 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r | |
5d73d92f | 3923 | \r |
3924 | //\r | |
3925 | // Print CardBus Latency Timer\r | |
3926 | //\r | |
47d20b54 MK |
3927 | ShellPrintHiiEx (\r |
3928 | -1,\r | |
3929 | -1,\r | |
3930 | NULL,\r | |
5d73d92f | 3931 | STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r |
3932 | gShellDebug1HiiHandle,\r | |
3933 | INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r | |
3934 | CardBus->CardBusLatencyTimer\r | |
47d20b54 | 3935 | );\r |
5d73d92f | 3936 | \r |
3937 | //\r | |
3938 | // Print Memory/Io ranges this cardbus bridge forwards\r | |
3939 | //\r | |
47d20b54 | 3940 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r |
c37e0f16 | 3941 | ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r |
5d73d92f | 3942 | \r |
47d20b54 MK |
3943 | ShellPrintHiiEx (\r |
3944 | -1,\r | |
3945 | -1,\r | |
3946 | NULL,\r | |
5d73d92f | 3947 | STRING_TOKEN (STR_PCI2_MEM_3),\r |
3948 | gShellDebug1HiiHandle,\r | |
3949 | INDEX_OF (&(CardBus->MemoryBase0)),\r | |
0c84a69f | 3950 | CardBus->BridgeControl & BIT8 ? L" Prefetchable" : L"Non-Prefetchable",\r |
5d73d92f | 3951 | CardBus->MemoryBase0 & 0xfffff000,\r |
3952 | CardBus->MemoryLimit0 | 0x00000fff\r | |
47d20b54 | 3953 | );\r |
5d73d92f | 3954 | \r |
47d20b54 MK |
3955 | ShellPrintHiiEx (\r |
3956 | -1,\r | |
3957 | -1,\r | |
3958 | NULL,\r | |
5d73d92f | 3959 | STRING_TOKEN (STR_PCI2_MEM_3),\r |
3960 | gShellDebug1HiiHandle,\r | |
3961 | INDEX_OF (&(CardBus->MemoryBase1)),\r | |
0c84a69f | 3962 | CardBus->BridgeControl & BIT9 ? L" Prefetchable" : L"Non-Prefetchable",\r |
5d73d92f | 3963 | CardBus->MemoryBase1 & 0xfffff000,\r |
3964 | CardBus->MemoryLimit1 | 0x00000fff\r | |
47d20b54 | 3965 | );\r |
5d73d92f | 3966 | \r |
47d20b54 MK |
3967 | Io32Bit = (BOOLEAN)(CardBus->IoBase0 & BIT0);\r |
3968 | ShellPrintHiiEx (\r | |
3969 | -1,\r | |
3970 | -1,\r | |
3971 | NULL,\r | |
5d73d92f | 3972 | STRING_TOKEN (STR_PCI2_IO_2),\r |
3973 | gShellDebug1HiiHandle,\r | |
3974 | INDEX_OF (&(CardBus->IoBase0)),\r | |
3975 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3976 | CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3977 | (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
47d20b54 | 3978 | );\r |
5d73d92f | 3979 | \r |
47d20b54 MK |
3980 | Io32Bit = (BOOLEAN)(CardBus->IoBase1 & BIT0);\r |
3981 | ShellPrintHiiEx (\r | |
3982 | -1,\r | |
3983 | -1,\r | |
3984 | NULL,\r | |
5d73d92f | 3985 | STRING_TOKEN (STR_PCI2_IO_2),\r |
3986 | gShellDebug1HiiHandle,\r | |
3987 | INDEX_OF (&(CardBus->IoBase1)),\r | |
3988 | Io32Bit ? L" 32 bit" : L" 16 bit",\r | |
3989 | CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r | |
d8f8021c | 3990 | (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r |
47d20b54 | 3991 | );\r |
5d73d92f | 3992 | \r |
3993 | //\r | |
3994 | // Print register Interrupt Line & PIN\r | |
3995 | //\r | |
47d20b54 MK |
3996 | ShellPrintHiiEx (\r |
3997 | -1,\r | |
3998 | -1,\r | |
3999 | NULL,\r | |
5d73d92f | 4000 | STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r |
4001 | gShellDebug1HiiHandle,\r | |
4002 | INDEX_OF (&(CardBus->InterruptLine)),\r | |
4003 | CardBus->InterruptLine,\r | |
4004 | INDEX_OF (&(CardBus->InterruptPin)),\r | |
4005 | CardBus->InterruptPin\r | |
47d20b54 | 4006 | );\r |
5d73d92f | 4007 | \r |
4008 | //\r | |
4009 | // Print register Bridge Control\r | |
4010 | //\r | |
4011 | PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r | |
4012 | \r | |
4013 | //\r | |
4014 | // Print some registers in data region of PCI configuration space for cardbus\r | |
4015 | // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r | |
4016 | // Address.\r | |
4017 | //\r | |
47d20b54 | 4018 | CardBusData = (PCI_CARDBUS_DATA *)((UINT8 *)CardBus + sizeof (PCI_CARDBUS_CONTROL_REGISTER));\r |
5d73d92f | 4019 | \r |
47d20b54 MK |
4020 | ShellPrintHiiEx (\r |
4021 | -1,\r | |
4022 | -1,\r | |
4023 | NULL,\r | |
5d73d92f | 4024 | STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r |
4025 | gShellDebug1HiiHandle,\r | |
4026 | INDEX_OF (&(CardBusData->SubVendorId)),\r | |
4027 | CardBusData->SubVendorId,\r | |
4028 | INDEX_OF (&(CardBusData->SubSystemId)),\r | |
4029 | CardBusData->SubSystemId\r | |
47d20b54 | 4030 | );\r |
5d73d92f | 4031 | \r |
47d20b54 MK |
4032 | ShellPrintHiiEx (\r |
4033 | -1,\r | |
4034 | -1,\r | |
4035 | NULL,\r | |
5d73d92f | 4036 | STRING_TOKEN (STR_PCI2_OPTIONAL),\r |
4037 | gShellDebug1HiiHandle,\r | |
4038 | INDEX_OF (&(CardBusData->LegacyBase)),\r | |
4039 | CardBusData->LegacyBase\r | |
47d20b54 | 4040 | );\r |
5d73d92f | 4041 | \r |
4042 | return EFI_SUCCESS;\r | |
4043 | }\r | |
4044 | \r | |
a1d4bfcc | 4045 | /**\r |
4046 | Explain each meaningful bit of register Status. The definition of Status is\r | |
4047 | slightly different depending on the PCI header type.\r | |
4048 | \r | |
4049 | @param[in] Status Points to the content of register Status.\r | |
4050 | @param[in] MainStatus Indicates if this register is main status(not secondary\r | |
4051 | status).\r | |
4052 | @param[in] HeaderType Header type of this PCI device.\r | |
4053 | \r | |
4054 | @retval EFI_SUCCESS The command completed successfully.\r | |
4055 | **/\r | |
5d73d92f | 4056 | EFI_STATUS\r |
4057 | PciExplainStatus (\r | |
47d20b54 MK |
4058 | IN UINT16 *Status,\r |
4059 | IN BOOLEAN MainStatus,\r | |
4060 | IN PCI_HEADER_TYPE HeaderType\r | |
5d73d92f | 4061 | )\r |
5d73d92f | 4062 | {\r |
4063 | if (MainStatus) {\r | |
47d20b54 | 4064 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r |
5d73d92f | 4065 | } else {\r |
47d20b54 | 4066 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r |
5d73d92f | 4067 | }\r |
4068 | \r | |
47d20b54 | 4069 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & BIT4) != 0);\r |
5d73d92f | 4070 | \r |
4071 | //\r | |
4072 | // Bit 5 is meaningless for CardBus Bridge\r | |
4073 | //\r | |
4074 | if (HeaderType == PciCardBusBridge) {\r | |
47d20b54 | 4075 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r |
5d73d92f | 4076 | } else {\r |
47d20b54 | 4077 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r |
5d73d92f | 4078 | }\r |
4079 | \r | |
47d20b54 | 4080 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & BIT7) != 0);\r |
5d73d92f | 4081 | \r |
47d20b54 | 4082 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & BIT8) != 0);\r |
5d73d92f | 4083 | //\r |
4084 | // Bit 9 and bit 10 together decides the DEVSEL timing\r | |
4085 | //\r | |
47d20b54 MK |
4086 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r |
4087 | if (((*Status & BIT9) == 0) && ((*Status & BIT10) == 0)) {\r | |
4088 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r | |
4089 | } else if (((*Status & BIT9) != 0) && ((*Status & BIT10) == 0)) {\r | |
4090 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r | |
4091 | } else if (((*Status & BIT9) == 0) && ((*Status & BIT10) != 0)) {\r | |
4092 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r | |
5d73d92f | 4093 | } else {\r |
47d20b54 | 4094 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r |
5d73d92f | 4095 | }\r |
4096 | \r | |
47d20b54 MK |
4097 | ShellPrintHiiEx (\r |
4098 | -1,\r | |
4099 | -1,\r | |
4100 | NULL,\r | |
5d73d92f | 4101 | STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r |
4102 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4103 | (*Status & BIT11) != 0\r |
47d20b54 | 4104 | );\r |
5d73d92f | 4105 | \r |
47d20b54 MK |
4106 | ShellPrintHiiEx (\r |
4107 | -1,\r | |
4108 | -1,\r | |
4109 | NULL,\r | |
5d73d92f | 4110 | STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r |
4111 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4112 | (*Status & BIT12) != 0\r |
47d20b54 | 4113 | );\r |
5d73d92f | 4114 | \r |
47d20b54 MK |
4115 | ShellPrintHiiEx (\r |
4116 | -1,\r | |
4117 | -1,\r | |
4118 | NULL,\r | |
5d73d92f | 4119 | STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r |
4120 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4121 | (*Status & BIT13) != 0\r |
47d20b54 | 4122 | );\r |
5d73d92f | 4123 | \r |
4124 | if (MainStatus) {\r | |
47d20b54 MK |
4125 | ShellPrintHiiEx (\r |
4126 | -1,\r | |
4127 | -1,\r | |
4128 | NULL,\r | |
5d73d92f | 4129 | STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r |
4130 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4131 | (*Status & BIT14) != 0\r |
47d20b54 | 4132 | );\r |
5d73d92f | 4133 | } else {\r |
47d20b54 MK |
4134 | ShellPrintHiiEx (\r |
4135 | -1,\r | |
4136 | -1,\r | |
4137 | NULL,\r | |
5d73d92f | 4138 | STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r |
4139 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4140 | (*Status & BIT14) != 0\r |
47d20b54 | 4141 | );\r |
5d73d92f | 4142 | }\r |
4143 | \r | |
47d20b54 MK |
4144 | ShellPrintHiiEx (\r |
4145 | -1,\r | |
4146 | -1,\r | |
4147 | NULL,\r | |
5d73d92f | 4148 | STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r |
4149 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4150 | (*Status & BIT15) != 0\r |
47d20b54 | 4151 | );\r |
5d73d92f | 4152 | \r |
4153 | return EFI_SUCCESS;\r | |
4154 | }\r | |
4155 | \r | |
a1d4bfcc | 4156 | /**\r |
5d73d92f | 4157 | Explain each meaningful bit of register Command.\r |
4158 | \r | |
a1d4bfcc | 4159 | @param[in] Command Points to the content of register Command.\r |
5d73d92f | 4160 | \r |
a1d4bfcc | 4161 | @retval EFI_SUCCESS The command completed successfully.\r |
5d73d92f | 4162 | **/\r |
a1d4bfcc | 4163 | EFI_STATUS\r |
4164 | PciExplainCommand (\r | |
47d20b54 | 4165 | IN UINT16 *Command\r |
a1d4bfcc | 4166 | )\r |
5d73d92f | 4167 | {\r |
4168 | //\r | |
4169 | // Print the binary value of register Command\r | |
4170 | //\r | |
47d20b54 | 4171 | ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r |
5d73d92f | 4172 | \r |
4173 | //\r | |
4174 | // Explain register Command bit by bit\r | |
4175 | //\r | |
47d20b54 MK |
4176 | ShellPrintHiiEx (\r |
4177 | -1,\r | |
4178 | -1,\r | |
4179 | NULL,\r | |
5d73d92f | 4180 | STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r |
4181 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4182 | (*Command & BIT0) != 0\r |
47d20b54 | 4183 | );\r |
5d73d92f | 4184 | \r |
47d20b54 MK |
4185 | ShellPrintHiiEx (\r |
4186 | -1,\r | |
4187 | -1,\r | |
4188 | NULL,\r | |
5d73d92f | 4189 | STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r |
4190 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4191 | (*Command & BIT1) != 0\r |
47d20b54 | 4192 | );\r |
5d73d92f | 4193 | \r |
47d20b54 MK |
4194 | ShellPrintHiiEx (\r |
4195 | -1,\r | |
4196 | -1,\r | |
4197 | NULL,\r | |
5d73d92f | 4198 | STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r |
4199 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4200 | (*Command & BIT2) != 0\r |
47d20b54 | 4201 | );\r |
5d73d92f | 4202 | \r |
47d20b54 MK |
4203 | ShellPrintHiiEx (\r |
4204 | -1,\r | |
4205 | -1,\r | |
4206 | NULL,\r | |
5d73d92f | 4207 | STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r |
4208 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4209 | (*Command & BIT3) != 0\r |
47d20b54 | 4210 | );\r |
5d73d92f | 4211 | \r |
47d20b54 MK |
4212 | ShellPrintHiiEx (\r |
4213 | -1,\r | |
4214 | -1,\r | |
4215 | NULL,\r | |
5d73d92f | 4216 | STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r |
4217 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4218 | (*Command & BIT4) != 0\r |
47d20b54 | 4219 | );\r |
5d73d92f | 4220 | \r |
47d20b54 MK |
4221 | ShellPrintHiiEx (\r |
4222 | -1,\r | |
4223 | -1,\r | |
4224 | NULL,\r | |
5d73d92f | 4225 | STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r |
4226 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4227 | (*Command & BIT5) != 0\r |
47d20b54 | 4228 | );\r |
5d73d92f | 4229 | \r |
47d20b54 MK |
4230 | ShellPrintHiiEx (\r |
4231 | -1,\r | |
4232 | -1,\r | |
4233 | NULL,\r | |
5d73d92f | 4234 | STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r |
4235 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4236 | (*Command & BIT6) != 0\r |
47d20b54 | 4237 | );\r |
5d73d92f | 4238 | \r |
47d20b54 MK |
4239 | ShellPrintHiiEx (\r |
4240 | -1,\r | |
4241 | -1,\r | |
4242 | NULL,\r | |
5d73d92f | 4243 | STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r |
4244 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4245 | (*Command & BIT7) != 0\r |
47d20b54 | 4246 | );\r |
5d73d92f | 4247 | \r |
47d20b54 MK |
4248 | ShellPrintHiiEx (\r |
4249 | -1,\r | |
4250 | -1,\r | |
4251 | NULL,\r | |
5d73d92f | 4252 | STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r |
4253 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4254 | (*Command & BIT8) != 0\r |
47d20b54 | 4255 | );\r |
5d73d92f | 4256 | \r |
47d20b54 MK |
4257 | ShellPrintHiiEx (\r |
4258 | -1,\r | |
4259 | -1,\r | |
4260 | NULL,\r | |
5d73d92f | 4261 | STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r |
4262 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4263 | (*Command & BIT9) != 0\r |
47d20b54 | 4264 | );\r |
5d73d92f | 4265 | \r |
4266 | return EFI_SUCCESS;\r | |
4267 | }\r | |
4268 | \r | |
a1d4bfcc | 4269 | /**\r |
4270 | Explain each meaningful bit of register Bridge Control.\r | |
4271 | \r | |
4272 | @param[in] BridgeControl Points to the content of register Bridge Control.\r | |
4273 | @param[in] HeaderType The headertype.\r | |
4274 | \r | |
4275 | @retval EFI_SUCCESS The command completed successfully.\r | |
4276 | **/\r | |
5d73d92f | 4277 | EFI_STATUS\r |
4278 | PciExplainBridgeControl (\r | |
47d20b54 MK |
4279 | IN UINT16 *BridgeControl,\r |
4280 | IN PCI_HEADER_TYPE HeaderType\r | |
5d73d92f | 4281 | )\r |
5d73d92f | 4282 | {\r |
47d20b54 MK |
4283 | ShellPrintHiiEx (\r |
4284 | -1,\r | |
4285 | -1,\r | |
4286 | NULL,\r | |
5d73d92f | 4287 | STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r |
4288 | gShellDebug1HiiHandle,\r | |
4289 | INDEX_OF (BridgeControl),\r | |
4290 | *BridgeControl\r | |
47d20b54 | 4291 | );\r |
5d73d92f | 4292 | \r |
47d20b54 MK |
4293 | ShellPrintHiiEx (\r |
4294 | -1,\r | |
4295 | -1,\r | |
4296 | NULL,\r | |
5d73d92f | 4297 | STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r |
4298 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4299 | (*BridgeControl & BIT0) != 0\r |
47d20b54 MK |
4300 | );\r |
4301 | ShellPrintHiiEx (\r | |
4302 | -1,\r | |
4303 | -1,\r | |
4304 | NULL,\r | |
5d73d92f | 4305 | STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r |
4306 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4307 | (*BridgeControl & BIT1) != 0\r |
47d20b54 MK |
4308 | );\r |
4309 | ShellPrintHiiEx (\r | |
4310 | -1,\r | |
4311 | -1,\r | |
4312 | NULL,\r | |
5d73d92f | 4313 | STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r |
4314 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4315 | (*BridgeControl & BIT2) != 0\r |
47d20b54 MK |
4316 | );\r |
4317 | ShellPrintHiiEx (\r | |
4318 | -1,\r | |
4319 | -1,\r | |
4320 | NULL,\r | |
5d73d92f | 4321 | STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r |
4322 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4323 | (*BridgeControl & BIT3) != 0\r |
47d20b54 MK |
4324 | );\r |
4325 | ShellPrintHiiEx (\r | |
4326 | -1,\r | |
4327 | -1,\r | |
4328 | NULL,\r | |
5d73d92f | 4329 | STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r |
4330 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4331 | (*BridgeControl & BIT5) != 0\r |
47d20b54 | 4332 | );\r |
5d73d92f | 4333 | \r |
4334 | //\r | |
4335 | // Register Bridge Control has some slight differences between P2P bridge\r | |
4336 | // and Cardbus bridge from bit 6 to bit 11.\r | |
4337 | //\r | |
4338 | if (HeaderType == PciP2pBridge) {\r | |
47d20b54 MK |
4339 | ShellPrintHiiEx (\r |
4340 | -1,\r | |
4341 | -1,\r | |
4342 | NULL,\r | |
5d73d92f | 4343 | STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r |
4344 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4345 | (*BridgeControl & BIT6) != 0\r |
47d20b54 MK |
4346 | );\r |
4347 | ShellPrintHiiEx (\r | |
4348 | -1,\r | |
4349 | -1,\r | |
4350 | NULL,\r | |
5d73d92f | 4351 | STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r |
4352 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4353 | (*BridgeControl & BIT7) != 0\r |
47d20b54 MK |
4354 | );\r |
4355 | ShellPrintHiiEx (\r | |
4356 | -1,\r | |
4357 | -1,\r | |
4358 | NULL,\r | |
5d73d92f | 4359 | STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r |
4360 | gShellDebug1HiiHandle,\r | |
47d20b54 MK |
4361 | (*BridgeControl & BIT8) != 0 ? L"2^10" : L"2^15"\r |
4362 | );\r | |
4363 | ShellPrintHiiEx (\r | |
4364 | -1,\r | |
4365 | -1,\r | |
4366 | NULL,\r | |
5d73d92f | 4367 | STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r |
4368 | gShellDebug1HiiHandle,\r | |
47d20b54 MK |
4369 | (*BridgeControl & BIT9) != 0 ? L"2^10" : L"2^15"\r |
4370 | );\r | |
4371 | ShellPrintHiiEx (\r | |
4372 | -1,\r | |
4373 | -1,\r | |
4374 | NULL,\r | |
5d73d92f | 4375 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r |
4376 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4377 | (*BridgeControl & BIT10) != 0\r |
47d20b54 MK |
4378 | );\r |
4379 | ShellPrintHiiEx (\r | |
4380 | -1,\r | |
4381 | -1,\r | |
4382 | NULL,\r | |
5d73d92f | 4383 | STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r |
4384 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4385 | (*BridgeControl & BIT11) != 0\r |
47d20b54 | 4386 | );\r |
5d73d92f | 4387 | } else {\r |
47d20b54 MK |
4388 | ShellPrintHiiEx (\r |
4389 | -1,\r | |
4390 | -1,\r | |
4391 | NULL,\r | |
5d73d92f | 4392 | STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r |
4393 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4394 | (*BridgeControl & BIT6) != 0\r |
47d20b54 MK |
4395 | );\r |
4396 | ShellPrintHiiEx (\r | |
4397 | -1,\r | |
4398 | -1,\r | |
4399 | NULL,\r | |
5d73d92f | 4400 | STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r |
4401 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4402 | (*BridgeControl & BIT7) != 0\r |
47d20b54 MK |
4403 | );\r |
4404 | ShellPrintHiiEx (\r | |
4405 | -1,\r | |
4406 | -1,\r | |
4407 | NULL,\r | |
5d73d92f | 4408 | STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r |
4409 | gShellDebug1HiiHandle,\r | |
0c84a69f | 4410 | (*BridgeControl & BIT10) != 0\r |
47d20b54 | 4411 | );\r |
5d73d92f | 4412 | }\r |
4413 | \r | |
4414 | return EFI_SUCCESS;\r | |
4415 | }\r | |
4416 | \r | |
a1d4bfcc | 4417 | /**\r |
33cc487c | 4418 | Locate capability register block per capability ID.\r |
a1d4bfcc | 4419 | \r |
33cc487c RN |
4420 | @param[in] ConfigSpace Data in PCI configuration space.\r |
4421 | @param[in] CapabilityId The capability ID.\r | |
a1d4bfcc | 4422 | \r |
33cc487c RN |
4423 | @return The offset of the register block per capability ID,\r |
4424 | or 0 if the register block cannot be found.\r | |
a1d4bfcc | 4425 | **/\r |
33cc487c RN |
4426 | UINT8\r |
4427 | LocatePciCapability (\r | |
47d20b54 MK |
4428 | IN PCI_CONFIG_SPACE *ConfigSpace,\r |
4429 | IN UINT8 CapabilityId\r | |
5d73d92f | 4430 | )\r |
4431 | {\r | |
33cc487c RN |
4432 | UINT8 CapabilityPtr;\r |
4433 | EFI_PCI_CAPABILITY_HDR *CapabilityEntry;\r | |
5d73d92f | 4434 | \r |
4435 | //\r | |
33cc487c | 4436 | // To check the cpability of this device supports\r |
5d73d92f | 4437 | //\r |
33cc487c RN |
4438 | if ((ConfigSpace->Common.Status & EFI_PCI_STATUS_CAPABILITY) == 0) {\r |
4439 | return 0;\r | |
4440 | }\r | |
5d73d92f | 4441 | \r |
33cc487c RN |
4442 | switch ((PCI_HEADER_TYPE)(ConfigSpace->Common.HeaderType & 0x7f)) {\r |
4443 | case PciDevice:\r | |
4444 | CapabilityPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;\r | |
4445 | break;\r | |
4446 | case PciP2pBridge:\r | |
4447 | CapabilityPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;\r | |
4448 | break;\r | |
4449 | case PciCardBusBridge:\r | |
4450 | CapabilityPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;\r | |
4451 | break;\r | |
4452 | default:\r | |
4453 | return 0;\r | |
4454 | }\r | |
5d73d92f | 4455 | \r |
33cc487c | 4456 | while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r |
47d20b54 | 4457 | CapabilityEntry = (EFI_PCI_CAPABILITY_HDR *)((UINT8 *)ConfigSpace + CapabilityPtr);\r |
33cc487c RN |
4458 | if (CapabilityEntry->CapabilityID == CapabilityId) {\r |
4459 | return CapabilityPtr;\r | |
5d73d92f | 4460 | }\r |
33cc487c | 4461 | \r |
5d73d92f | 4462 | //\r |
33cc487c RN |
4463 | // Certain PCI device may incorrectly have capability pointing to itself,\r |
4464 | // break to avoid dead loop.\r | |
5d73d92f | 4465 | //\r |
33cc487c RN |
4466 | if (CapabilityPtr == CapabilityEntry->NextItemPtr) {\r |
4467 | break;\r | |
4468 | }\r | |
4469 | \r | |
4470 | CapabilityPtr = CapabilityEntry->NextItemPtr;\r | |
5d73d92f | 4471 | }\r |
4472 | \r | |
33cc487c | 4473 | return 0;\r |
5d73d92f | 4474 | }\r |
4475 | \r | |
a1d4bfcc | 4476 | /**\r |
4477 | Print out information of the capability information.\r | |
4478 | \r | |
4479 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4480 | \r | |
4481 | @retval EFI_SUCCESS The operation was successful.\r | |
4482 | **/\r | |
5d73d92f | 4483 | EFI_STATUS\r |
4484 | ExplainPcieCapReg (\r | |
47d20b54 | 4485 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4486 | )\r |
5d73d92f | 4487 | {\r |
47d20b54 | 4488 | CHAR16 *DevicePortType;\r |
5d73d92f | 4489 | \r |
47d20b54 MK |
4490 | ShellPrintEx (\r |
4491 | -1,\r | |
4492 | -1,\r | |
c37e0f16 | 4493 | L" Capability Version(3:0): %E0x%04x%N\r\n",\r |
0c84a69f | 4494 | PciExpressCap->Capability.Bits.Version\r |
47d20b54 | 4495 | );\r |
0c84a69f RN |
4496 | if (PciExpressCap->Capability.Bits.DevicePortType < ARRAY_SIZE (DevicePortTypeTable)) {\r |
4497 | DevicePortType = DevicePortTypeTable[PciExpressCap->Capability.Bits.DevicePortType];\r | |
5d73d92f | 4498 | } else {\r |
4499 | DevicePortType = L"Unknown Type";\r | |
4500 | }\r | |
47d20b54 MK |
4501 | \r |
4502 | ShellPrintEx (\r | |
4503 | -1,\r | |
4504 | -1,\r | |
c37e0f16 | 4505 | L" Device/PortType(7:4): %E%s%N\r\n",\r |
5d73d92f | 4506 | DevicePortType\r |
47d20b54 | 4507 | );\r |
5d73d92f | 4508 | //\r |
4509 | // 'Slot Implemented' is only valid for:\r | |
4510 | // a) Root Port of PCI Express Root Complex, or\r | |
4511 | // b) Downstream Port of PCI Express Switch\r | |
4512 | //\r | |
47d20b54 MK |
4513 | if ((PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_PORT) ||\r |
4514 | (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT))\r | |
4515 | {\r | |
4516 | ShellPrintEx (\r | |
4517 | -1,\r | |
4518 | -1,\r | |
c37e0f16 | 4519 | L" Slot Implemented(8): %E%d%N\r\n",\r |
0c84a69f | 4520 | PciExpressCap->Capability.Bits.SlotImplemented\r |
47d20b54 | 4521 | );\r |
5d73d92f | 4522 | }\r |
47d20b54 MK |
4523 | \r |
4524 | ShellPrintEx (\r | |
4525 | -1,\r | |
4526 | -1,\r | |
c37e0f16 | 4527 | L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r |
0c84a69f | 4528 | PciExpressCap->Capability.Bits.InterruptMessageNumber\r |
47d20b54 | 4529 | );\r |
5d73d92f | 4530 | return EFI_SUCCESS;\r |
4531 | }\r | |
4532 | \r | |
a1d4bfcc | 4533 | /**\r |
4534 | Print out information of the device capability information.\r | |
4535 | \r | |
4536 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4537 | \r | |
4538 | @retval EFI_SUCCESS The operation was successful.\r | |
4539 | **/\r | |
5d73d92f | 4540 | EFI_STATUS\r |
4541 | ExplainPcieDeviceCap (\r | |
47d20b54 | 4542 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4543 | )\r |
5d73d92f | 4544 | {\r |
5d73d92f | 4545 | UINT8 DevicePortType;\r |
4546 | UINT8 L0sLatency;\r | |
4547 | UINT8 L1Latency;\r | |
4548 | \r | |
0c84a69f | 4549 | DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r |
c37e0f16 | 4550 | ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r |
0c84a69f RN |
4551 | if (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize < 6) {\r |
4552 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize + 7));\r | |
5d73d92f | 4553 | } else {\r |
c37e0f16 | 4554 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4555 | }\r |
47d20b54 MK |
4556 | \r |
4557 | ShellPrintEx (\r | |
4558 | -1,\r | |
4559 | -1,\r | |
c37e0f16 | 4560 | L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r |
0c84a69f | 4561 | PciExpressCap->DeviceCapability.Bits.PhantomFunctions\r |
47d20b54 MK |
4562 | );\r |
4563 | ShellPrintEx (\r | |
4564 | -1,\r | |
4565 | -1,\r | |
c37e0f16 | 4566 | L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r |
0c84a69f | 4567 | PciExpressCap->DeviceCapability.Bits.ExtendedTagField ? 8 : 5\r |
47d20b54 | 4568 | );\r |
5d73d92f | 4569 | //\r |
4570 | // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r | |
4571 | //\r | |
4572 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
0c84a69f RN |
4573 | L0sLatency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL0sAcceptableLatency;\r |
4574 | L1Latency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL1AcceptableLatency;\r | |
c37e0f16 | 4575 | ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r |
5d73d92f | 4576 | if (L0sLatency < 4) {\r |
c37e0f16 | 4577 | ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r |
5d73d92f | 4578 | } else {\r |
4579 | if (L0sLatency < 7) {\r | |
c37e0f16 | 4580 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r |
5d73d92f | 4581 | } else {\r |
c37e0f16 | 4582 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4583 | }\r |
4584 | }\r | |
47d20b54 | 4585 | \r |
c37e0f16 | 4586 | ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r |
5d73d92f | 4587 | if (L1Latency < 7) {\r |
c37e0f16 | 4588 | ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r |
5d73d92f | 4589 | } else {\r |
c37e0f16 | 4590 | ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r |
5d73d92f | 4591 | }\r |
4592 | }\r | |
47d20b54 MK |
4593 | \r |
4594 | ShellPrintEx (\r | |
4595 | -1,\r | |
4596 | -1,\r | |
c37e0f16 | 4597 | L" Role-based Error Reporting(15): %E%d%N\r\n",\r |
0c84a69f | 4598 | PciExpressCap->DeviceCapability.Bits.RoleBasedErrorReporting\r |
47d20b54 | 4599 | );\r |
5d73d92f | 4600 | //\r |
4601 | // Only valid for Upstream Port:\r | |
4602 | // a) Captured Slot Power Limit Value\r | |
4603 | // b) Captured Slot Power Scale\r | |
4604 | //\r | |
0c84a69f | 4605 | if (DevicePortType == PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) {\r |
47d20b54 MK |
4606 | ShellPrintEx (\r |
4607 | -1,\r | |
4608 | -1,\r | |
c37e0f16 | 4609 | L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r |
0c84a69f | 4610 | PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitValue\r |
47d20b54 MK |
4611 | );\r |
4612 | ShellPrintEx (\r | |
4613 | -1,\r | |
4614 | -1,\r | |
c37e0f16 | 4615 | L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r |
0c84a69f | 4616 | SlotPwrLmtScaleTable[PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitScale]\r |
47d20b54 | 4617 | );\r |
5d73d92f | 4618 | }\r |
47d20b54 | 4619 | \r |
5d73d92f | 4620 | //\r |
4621 | // Function Level Reset Capability is only valid for Endpoint\r | |
4622 | //\r | |
4623 | if (IS_PCIE_ENDPOINT (DevicePortType)) {\r | |
47d20b54 MK |
4624 | ShellPrintEx (\r |
4625 | -1,\r | |
4626 | -1,\r | |
c37e0f16 | 4627 | L" Function Level Reset Capability(28): %E%d%N\r\n",\r |
0c84a69f | 4628 | PciExpressCap->DeviceCapability.Bits.FunctionLevelReset\r |
47d20b54 | 4629 | );\r |
5d73d92f | 4630 | }\r |
47d20b54 | 4631 | \r |
5d73d92f | 4632 | return EFI_SUCCESS;\r |
4633 | }\r | |
4634 | \r | |
a1d4bfcc | 4635 | /**\r |
4636 | Print out information of the device control information.\r | |
4637 | \r | |
4638 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4639 | \r | |
4640 | @retval EFI_SUCCESS The operation was successful.\r | |
4641 | **/\r | |
5d73d92f | 4642 | EFI_STATUS\r |
4643 | ExplainPcieDeviceControl (\r | |
47d20b54 | 4644 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4645 | )\r |
5d73d92f | 4646 | {\r |
47d20b54 MK |
4647 | ShellPrintEx (\r |
4648 | -1,\r | |
4649 | -1,\r | |
c37e0f16 | 4650 | L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r |
0c84a69f RN |
4651 | PciExpressCap->DeviceControl.Bits.CorrectableError\r |
4652 | );\r | |
47d20b54 MK |
4653 | ShellPrintEx (\r |
4654 | -1,\r | |
4655 | -1,\r | |
c37e0f16 | 4656 | L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r |
0c84a69f | 4657 | PciExpressCap->DeviceControl.Bits.NonFatalError\r |
47d20b54 MK |
4658 | );\r |
4659 | ShellPrintEx (\r | |
4660 | -1,\r | |
4661 | -1,\r | |
c37e0f16 | 4662 | L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r |
0c84a69f | 4663 | PciExpressCap->DeviceControl.Bits.FatalError\r |
47d20b54 MK |
4664 | );\r |
4665 | ShellPrintEx (\r | |
4666 | -1,\r | |
4667 | -1,\r | |
c37e0f16 | 4668 | L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r |
0c84a69f | 4669 | PciExpressCap->DeviceControl.Bits.UnsupportedRequest\r |
47d20b54 MK |
4670 | );\r |
4671 | ShellPrintEx (\r | |
4672 | -1,\r | |
4673 | -1,\r | |
c37e0f16 | 4674 | L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r |
0c84a69f | 4675 | PciExpressCap->DeviceControl.Bits.RelaxedOrdering\r |
47d20b54 | 4676 | );\r |
c37e0f16 | 4677 | ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r |
0c84a69f RN |
4678 | if (PciExpressCap->DeviceControl.Bits.MaxPayloadSize < 6) {\r |
4679 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxPayloadSize + 7));\r | |
5d73d92f | 4680 | } else {\r |
c37e0f16 | 4681 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4682 | }\r |
47d20b54 MK |
4683 | \r |
4684 | ShellPrintEx (\r | |
4685 | -1,\r | |
4686 | -1,\r | |
c37e0f16 | 4687 | L" Extended Tag Field Enable(8): %E%d%N\r\n",\r |
0c84a69f | 4688 | PciExpressCap->DeviceControl.Bits.ExtendedTagField\r |
47d20b54 MK |
4689 | );\r |
4690 | ShellPrintEx (\r | |
4691 | -1,\r | |
4692 | -1,\r | |
c37e0f16 | 4693 | L" Phantom Functions Enable(9): %E%d%N\r\n",\r |
0c84a69f | 4694 | PciExpressCap->DeviceControl.Bits.PhantomFunctions\r |
47d20b54 MK |
4695 | );\r |
4696 | ShellPrintEx (\r | |
4697 | -1,\r | |
4698 | -1,\r | |
c37e0f16 | 4699 | L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r |
0c84a69f | 4700 | PciExpressCap->DeviceControl.Bits.AuxPower\r |
47d20b54 MK |
4701 | );\r |
4702 | ShellPrintEx (\r | |
4703 | -1,\r | |
4704 | -1,\r | |
c37e0f16 | 4705 | L" Enable No Snoop(11): %E%d%N\r\n",\r |
0c84a69f | 4706 | PciExpressCap->DeviceControl.Bits.NoSnoop\r |
47d20b54 | 4707 | );\r |
c37e0f16 | 4708 | ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r |
0c84a69f RN |
4709 | if (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize < 6) {\r |
4710 | ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize + 7));\r | |
5d73d92f | 4711 | } else {\r |
c37e0f16 | 4712 | ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r |
5d73d92f | 4713 | }\r |
47d20b54 | 4714 | \r |
5d73d92f | 4715 | //\r |
4716 | // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r | |
4717 | //\r | |
0c84a69f | 4718 | if (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r |
47d20b54 MK |
4719 | ShellPrintEx (\r |
4720 | -1,\r | |
4721 | -1,\r | |
c37e0f16 | 4722 | L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r |
0c84a69f | 4723 | PciExpressCap->DeviceControl.Bits.BridgeConfigurationRetryOrFunctionLevelReset\r |
47d20b54 | 4724 | );\r |
5d73d92f | 4725 | }\r |
47d20b54 | 4726 | \r |
5d73d92f | 4727 | return EFI_SUCCESS;\r |
4728 | }\r | |
4729 | \r | |
a1d4bfcc | 4730 | /**\r |
4731 | Print out information of the device status information.\r | |
4732 | \r | |
4733 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4734 | \r | |
4735 | @retval EFI_SUCCESS The operation was successful.\r | |
4736 | **/\r | |
5d73d92f | 4737 | EFI_STATUS\r |
4738 | ExplainPcieDeviceStatus (\r | |
47d20b54 | 4739 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4740 | )\r |
5d73d92f | 4741 | {\r |
47d20b54 MK |
4742 | ShellPrintEx (\r |
4743 | -1,\r | |
4744 | -1,\r | |
c37e0f16 | 4745 | L" Correctable Error Detected(0): %E%d%N\r\n",\r |
0c84a69f | 4746 | PciExpressCap->DeviceStatus.Bits.CorrectableError\r |
47d20b54 MK |
4747 | );\r |
4748 | ShellPrintEx (\r | |
4749 | -1,\r | |
4750 | -1,\r | |
c37e0f16 | 4751 | L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r |
0c84a69f | 4752 | PciExpressCap->DeviceStatus.Bits.NonFatalError\r |
47d20b54 MK |
4753 | );\r |
4754 | ShellPrintEx (\r | |
4755 | -1,\r | |
4756 | -1,\r | |
c37e0f16 | 4757 | L" Fatal Error Detected(2): %E%d%N\r\n",\r |
0c84a69f | 4758 | PciExpressCap->DeviceStatus.Bits.FatalError\r |
47d20b54 MK |
4759 | );\r |
4760 | ShellPrintEx (\r | |
4761 | -1,\r | |
4762 | -1,\r | |
c37e0f16 | 4763 | L" Unsupported Request Detected(3): %E%d%N\r\n",\r |
0c84a69f | 4764 | PciExpressCap->DeviceStatus.Bits.UnsupportedRequest\r |
47d20b54 MK |
4765 | );\r |
4766 | ShellPrintEx (\r | |
4767 | -1,\r | |
4768 | -1,\r | |
c37e0f16 | 4769 | L" AUX Power Detected(4): %E%d%N\r\n",\r |
0c84a69f | 4770 | PciExpressCap->DeviceStatus.Bits.AuxPower\r |
47d20b54 MK |
4771 | );\r |
4772 | ShellPrintEx (\r | |
4773 | -1,\r | |
4774 | -1,\r | |
c37e0f16 | 4775 | L" Transactions Pending(5): %E%d%N\r\n",\r |
0c84a69f | 4776 | PciExpressCap->DeviceStatus.Bits.TransactionsPending\r |
47d20b54 | 4777 | );\r |
5d73d92f | 4778 | return EFI_SUCCESS;\r |
4779 | }\r | |
4780 | \r | |
a1d4bfcc | 4781 | /**\r |
4782 | Print out information of the device link information.\r | |
4783 | \r | |
4784 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4785 | \r | |
4786 | @retval EFI_SUCCESS The operation was successful.\r | |
4787 | **/\r | |
5d73d92f | 4788 | EFI_STATUS\r |
4789 | ExplainPcieLinkCap (\r | |
47d20b54 | 4790 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4791 | )\r |
5d73d92f | 4792 | {\r |
47d20b54 MK |
4793 | CHAR16 *MaxLinkSpeed;\r |
4794 | CHAR16 *AspmValue;\r | |
5d73d92f | 4795 | \r |
0c84a69f | 4796 | switch (PciExpressCap->LinkCapability.Bits.MaxLinkSpeed) {\r |
5d73d92f | 4797 | case 1:\r |
541ddf44 | 4798 | MaxLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 4799 | break;\r |
4800 | case 2:\r | |
541ddf44 CP |
4801 | MaxLinkSpeed = L"5.0 GT/s";\r |
4802 | break;\r | |
4803 | case 3:\r | |
4804 | MaxLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 4805 | break;\r |
adb59b63 ZG |
4806 | case 4:\r |
4807 | MaxLinkSpeed = L"16.0 GT/s";\r | |
4808 | break;\r | |
4809 | case 5:\r | |
4810 | MaxLinkSpeed = L"32.0 GT/s";\r | |
4811 | break;\r | |
5d73d92f | 4812 | default:\r |
adb59b63 | 4813 | MaxLinkSpeed = L"Reserved";\r |
5d73d92f | 4814 | break;\r |
4815 | }\r | |
47d20b54 MK |
4816 | \r |
4817 | ShellPrintEx (\r | |
4818 | -1,\r | |
4819 | -1,\r | |
541ddf44 CP |
4820 | L" Maximum Link Speed(3:0): %E%s%N\r\n",\r |
4821 | MaxLinkSpeed\r | |
47d20b54 MK |
4822 | );\r |
4823 | ShellPrintEx (\r | |
4824 | -1,\r | |
4825 | -1,\r | |
c37e0f16 | 4826 | L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r |
0c84a69f | 4827 | PciExpressCap->LinkCapability.Bits.MaxLinkWidth\r |
47d20b54 | 4828 | );\r |
0c84a69f | 4829 | switch (PciExpressCap->LinkCapability.Bits.Aspm) {\r |
541ddf44 CP |
4830 | case 0:\r |
4831 | AspmValue = L"Not";\r | |
4832 | break;\r | |
5d73d92f | 4833 | case 1:\r |
541ddf44 CP |
4834 | AspmValue = L"L0s";\r |
4835 | break;\r | |
4836 | case 2:\r | |
4837 | AspmValue = L"L1";\r | |
5d73d92f | 4838 | break;\r |
4839 | case 3:\r | |
a1d4bfcc | 4840 | AspmValue = L"L0s and L1";\r |
5d73d92f | 4841 | break;\r |
4842 | default:\r | |
a1d4bfcc | 4843 | AspmValue = L"Reserved";\r |
5d73d92f | 4844 | break;\r |
4845 | }\r | |
47d20b54 MK |
4846 | \r |
4847 | ShellPrintEx (\r | |
4848 | -1,\r | |
4849 | -1,\r | |
c37e0f16 | 4850 | L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r |
a1d4bfcc | 4851 | AspmValue\r |
47d20b54 MK |
4852 | );\r |
4853 | ShellPrintEx (\r | |
4854 | -1,\r | |
4855 | -1,\r | |
c37e0f16 | 4856 | L" L0s Exit Latency(14:12): %E%s%N\r\n",\r |
0c84a69f | 4857 | L0sLatencyStrTable[PciExpressCap->LinkCapability.Bits.L0sExitLatency]\r |
47d20b54 MK |
4858 | );\r |
4859 | ShellPrintEx (\r | |
4860 | -1,\r | |
4861 | -1,\r | |
c37e0f16 | 4862 | L" L1 Exit Latency(17:15): %E%s%N\r\n",\r |
0c84a69f | 4863 | L1LatencyStrTable[PciExpressCap->LinkCapability.Bits.L1ExitLatency]\r |
47d20b54 MK |
4864 | );\r |
4865 | ShellPrintEx (\r | |
4866 | -1,\r | |
4867 | -1,\r | |
c37e0f16 | 4868 | L" Clock Power Management(18): %E%d%N\r\n",\r |
0c84a69f | 4869 | PciExpressCap->LinkCapability.Bits.ClockPowerManagement\r |
47d20b54 MK |
4870 | );\r |
4871 | ShellPrintEx (\r | |
4872 | -1,\r | |
4873 | -1,\r | |
c37e0f16 | 4874 | L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r |
0c84a69f | 4875 | PciExpressCap->LinkCapability.Bits.SurpriseDownError\r |
47d20b54 MK |
4876 | );\r |
4877 | ShellPrintEx (\r | |
4878 | -1,\r | |
4879 | -1,\r | |
c37e0f16 | 4880 | L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r |
0c84a69f | 4881 | PciExpressCap->LinkCapability.Bits.DataLinkLayerLinkActive\r |
47d20b54 MK |
4882 | );\r |
4883 | ShellPrintEx (\r | |
4884 | -1,\r | |
4885 | -1,\r | |
c37e0f16 | 4886 | L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r |
0c84a69f | 4887 | PciExpressCap->LinkCapability.Bits.LinkBandwidthNotification\r |
47d20b54 MK |
4888 | );\r |
4889 | ShellPrintEx (\r | |
4890 | -1,\r | |
4891 | -1,\r | |
c37e0f16 | 4892 | L" Port Number(31:24): %E0x%02x%N\r\n",\r |
0c84a69f | 4893 | PciExpressCap->LinkCapability.Bits.PortNumber\r |
47d20b54 | 4894 | );\r |
5d73d92f | 4895 | return EFI_SUCCESS;\r |
4896 | }\r | |
4897 | \r | |
a1d4bfcc | 4898 | /**\r |
4899 | Print out information of the device link control information.\r | |
4900 | \r | |
4901 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4902 | \r | |
4903 | @retval EFI_SUCCESS The operation was successful.\r | |
4904 | **/\r | |
5d73d92f | 4905 | EFI_STATUS\r |
4906 | ExplainPcieLinkControl (\r | |
47d20b54 | 4907 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4908 | )\r |
5d73d92f | 4909 | {\r |
5d73d92f | 4910 | UINT8 DevicePortType;\r |
4911 | \r | |
47d20b54 MK |
4912 | DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r |
4913 | ShellPrintEx (\r | |
4914 | -1,\r | |
4915 | -1,\r | |
c37e0f16 | 4916 | L" Active State Power Management Control(1:0): %E%s%N\r\n",\r |
0c84a69f | 4917 | ASPMCtrlStrTable[PciExpressCap->LinkControl.Bits.AspmControl]\r |
47d20b54 | 4918 | );\r |
5d73d92f | 4919 | //\r |
4920 | // RCB is not applicable to switches\r | |
4921 | //\r | |
47d20b54 MK |
4922 | if (!IS_PCIE_SWITCH (DevicePortType)) {\r |
4923 | ShellPrintEx (\r | |
4924 | -1,\r | |
4925 | -1,\r | |
c37e0f16 | 4926 | L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r |
0c84a69f | 4927 | 1 << (PciExpressCap->LinkControl.Bits.ReadCompletionBoundary + 6)\r |
47d20b54 | 4928 | );\r |
5d73d92f | 4929 | }\r |
47d20b54 | 4930 | \r |
5d73d92f | 4931 | //\r |
4932 | // Link Disable is reserved on\r | |
4933 | // a) Endpoints\r | |
4934 | // b) PCI Express to PCI/PCI-X bridges\r | |
4935 | // c) Upstream Ports of Switches\r | |
4936 | //\r | |
4937 | if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r | |
47d20b54 MK |
4938 | (DevicePortType != PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) &&\r |
4939 | (DevicePortType != PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE))\r | |
4940 | {\r | |
4941 | ShellPrintEx (\r | |
4942 | -1,\r | |
4943 | -1,\r | |
c37e0f16 | 4944 | L" Link Disable(4): %E%d%N\r\n",\r |
0c84a69f | 4945 | PciExpressCap->LinkControl.Bits.LinkDisable\r |
47d20b54 | 4946 | );\r |
5d73d92f | 4947 | }\r |
47d20b54 MK |
4948 | \r |
4949 | ShellPrintEx (\r | |
4950 | -1,\r | |
4951 | -1,\r | |
c37e0f16 | 4952 | L" Common Clock Configuration(6): %E%d%N\r\n",\r |
0c84a69f | 4953 | PciExpressCap->LinkControl.Bits.CommonClockConfiguration\r |
47d20b54 MK |
4954 | );\r |
4955 | ShellPrintEx (\r | |
4956 | -1,\r | |
4957 | -1,\r | |
c37e0f16 | 4958 | L" Extended Synch(7): %E%d%N\r\n",\r |
0c84a69f | 4959 | PciExpressCap->LinkControl.Bits.ExtendedSynch\r |
47d20b54 MK |
4960 | );\r |
4961 | ShellPrintEx (\r | |
4962 | -1,\r | |
4963 | -1,\r | |
c37e0f16 | 4964 | L" Enable Clock Power Management(8): %E%d%N\r\n",\r |
0c84a69f | 4965 | PciExpressCap->LinkControl.Bits.ClockPowerManagement\r |
47d20b54 MK |
4966 | );\r |
4967 | ShellPrintEx (\r | |
4968 | -1,\r | |
4969 | -1,\r | |
c37e0f16 | 4970 | L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r |
0c84a69f | 4971 | PciExpressCap->LinkControl.Bits.HardwareAutonomousWidthDisable\r |
47d20b54 MK |
4972 | );\r |
4973 | ShellPrintEx (\r | |
4974 | -1,\r | |
4975 | -1,\r | |
c37e0f16 | 4976 | L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r |
0c84a69f | 4977 | PciExpressCap->LinkControl.Bits.LinkBandwidthManagementInterrupt\r |
47d20b54 MK |
4978 | );\r |
4979 | ShellPrintEx (\r | |
4980 | -1,\r | |
4981 | -1,\r | |
c37e0f16 | 4982 | L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r |
0c84a69f | 4983 | PciExpressCap->LinkControl.Bits.LinkAutonomousBandwidthInterrupt\r |
47d20b54 | 4984 | );\r |
5d73d92f | 4985 | return EFI_SUCCESS;\r |
4986 | }\r | |
4987 | \r | |
a1d4bfcc | 4988 | /**\r |
4989 | Print out information of the device link status information.\r | |
4990 | \r | |
4991 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
4992 | \r | |
4993 | @retval EFI_SUCCESS The operation was successful.\r | |
4994 | **/\r | |
5d73d92f | 4995 | EFI_STATUS\r |
4996 | ExplainPcieLinkStatus (\r | |
47d20b54 | 4997 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 4998 | )\r |
5d73d92f | 4999 | {\r |
47d20b54 | 5000 | CHAR16 *CurLinkSpeed;\r |
5d73d92f | 5001 | \r |
0c84a69f | 5002 | switch (PciExpressCap->LinkStatus.Bits.CurrentLinkSpeed) {\r |
5d73d92f | 5003 | case 1:\r |
541ddf44 | 5004 | CurLinkSpeed = L"2.5 GT/s";\r |
5d73d92f | 5005 | break;\r |
5006 | case 2:\r | |
541ddf44 CP |
5007 | CurLinkSpeed = L"5.0 GT/s";\r |
5008 | break;\r | |
5009 | case 3:\r | |
5010 | CurLinkSpeed = L"8.0 GT/s";\r | |
5d73d92f | 5011 | break;\r |
adb59b63 ZG |
5012 | case 4:\r |
5013 | CurLinkSpeed = L"16.0 GT/s";\r | |
5014 | break;\r | |
5015 | case 5:\r | |
5016 | CurLinkSpeed = L"32.0 GT/s";\r | |
5017 | break;\r | |
5d73d92f | 5018 | default:\r |
541ddf44 | 5019 | CurLinkSpeed = L"Reserved";\r |
5d73d92f | 5020 | break;\r |
5021 | }\r | |
47d20b54 MK |
5022 | \r |
5023 | ShellPrintEx (\r | |
5024 | -1,\r | |
5025 | -1,\r | |
c37e0f16 | 5026 | L" Current Link Speed(3:0): %E%s%N\r\n",\r |
541ddf44 | 5027 | CurLinkSpeed\r |
47d20b54 MK |
5028 | );\r |
5029 | ShellPrintEx (\r | |
5030 | -1,\r | |
5031 | -1,\r | |
c37e0f16 | 5032 | L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r |
0c84a69f | 5033 | PciExpressCap->LinkStatus.Bits.NegotiatedLinkWidth\r |
47d20b54 MK |
5034 | );\r |
5035 | ShellPrintEx (\r | |
5036 | -1,\r | |
5037 | -1,\r | |
c37e0f16 | 5038 | L" Link Training(11): %E%d%N\r\n",\r |
0c84a69f | 5039 | PciExpressCap->LinkStatus.Bits.LinkTraining\r |
47d20b54 MK |
5040 | );\r |
5041 | ShellPrintEx (\r | |
5042 | -1,\r | |
5043 | -1,\r | |
c37e0f16 | 5044 | L" Slot Clock Configuration(12): %E%d%N\r\n",\r |
0c84a69f | 5045 | PciExpressCap->LinkStatus.Bits.SlotClockConfiguration\r |
47d20b54 MK |
5046 | );\r |
5047 | ShellPrintEx (\r | |
5048 | -1,\r | |
5049 | -1,\r | |
c37e0f16 | 5050 | L" Data Link Layer Link Active(13): %E%d%N\r\n",\r |
0c84a69f | 5051 | PciExpressCap->LinkStatus.Bits.DataLinkLayerLinkActive\r |
47d20b54 MK |
5052 | );\r |
5053 | ShellPrintEx (\r | |
5054 | -1,\r | |
5055 | -1,\r | |
c37e0f16 | 5056 | L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r |
0c84a69f | 5057 | PciExpressCap->LinkStatus.Bits.LinkBandwidthManagement\r |
47d20b54 MK |
5058 | );\r |
5059 | ShellPrintEx (\r | |
5060 | -1,\r | |
5061 | -1,\r | |
c37e0f16 | 5062 | L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r |
0c84a69f | 5063 | PciExpressCap->LinkStatus.Bits.LinkAutonomousBandwidth\r |
47d20b54 | 5064 | );\r |
5d73d92f | 5065 | return EFI_SUCCESS;\r |
5066 | }\r | |
5067 | \r | |
a1d4bfcc | 5068 | /**\r |
5069 | Print out information of the device slot information.\r | |
5070 | \r | |
5071 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5072 | \r | |
5073 | @retval EFI_SUCCESS The operation was successful.\r | |
5074 | **/\r | |
5d73d92f | 5075 | EFI_STATUS\r |
5076 | ExplainPcieSlotCap (\r | |
47d20b54 | 5077 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 5078 | )\r |
5d73d92f | 5079 | {\r |
47d20b54 MK |
5080 | ShellPrintEx (\r |
5081 | -1,\r | |
5082 | -1,\r | |
c37e0f16 | 5083 | L" Attention Button Present(0): %E%d%N\r\n",\r |
0c84a69f | 5084 | PciExpressCap->SlotCapability.Bits.AttentionButton\r |
47d20b54 MK |
5085 | );\r |
5086 | ShellPrintEx (\r | |
5087 | -1,\r | |
5088 | -1,\r | |
c37e0f16 | 5089 | L" Power Controller Present(1): %E%d%N\r\n",\r |
0c84a69f | 5090 | PciExpressCap->SlotCapability.Bits.PowerController\r |
47d20b54 MK |
5091 | );\r |
5092 | ShellPrintEx (\r | |
5093 | -1,\r | |
5094 | -1,\r | |
c37e0f16 | 5095 | L" MRL Sensor Present(2): %E%d%N\r\n",\r |
0c84a69f | 5096 | PciExpressCap->SlotCapability.Bits.MrlSensor\r |
47d20b54 MK |
5097 | );\r |
5098 | ShellPrintEx (\r | |
5099 | -1,\r | |
5100 | -1,\r | |
c37e0f16 | 5101 | L" Attention Indicator Present(3): %E%d%N\r\n",\r |
0c84a69f | 5102 | PciExpressCap->SlotCapability.Bits.AttentionIndicator\r |
47d20b54 MK |
5103 | );\r |
5104 | ShellPrintEx (\r | |
5105 | -1,\r | |
5106 | -1,\r | |
c37e0f16 | 5107 | L" Power Indicator Present(4): %E%d%N\r\n",\r |
0c84a69f | 5108 | PciExpressCap->SlotCapability.Bits.PowerIndicator\r |
47d20b54 MK |
5109 | );\r |
5110 | ShellPrintEx (\r | |
5111 | -1,\r | |
5112 | -1,\r | |
c37e0f16 | 5113 | L" Hot-Plug Surprise(5): %E%d%N\r\n",\r |
0c84a69f | 5114 | PciExpressCap->SlotCapability.Bits.HotPlugSurprise\r |
47d20b54 MK |
5115 | );\r |
5116 | ShellPrintEx (\r | |
5117 | -1,\r | |
5118 | -1,\r | |
c37e0f16 | 5119 | L" Hot-Plug Capable(6): %E%d%N\r\n",\r |
0c84a69f | 5120 | PciExpressCap->SlotCapability.Bits.HotPlugCapable\r |
47d20b54 MK |
5121 | );\r |
5122 | ShellPrintEx (\r | |
5123 | -1,\r | |
5124 | -1,\r | |
c37e0f16 | 5125 | L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r |
0c84a69f | 5126 | PciExpressCap->SlotCapability.Bits.SlotPowerLimitValue\r |
47d20b54 MK |
5127 | );\r |
5128 | ShellPrintEx (\r | |
5129 | -1,\r | |
5130 | -1,\r | |
c37e0f16 | 5131 | L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r |
0c84a69f | 5132 | SlotPwrLmtScaleTable[PciExpressCap->SlotCapability.Bits.SlotPowerLimitScale]\r |
47d20b54 MK |
5133 | );\r |
5134 | ShellPrintEx (\r | |
5135 | -1,\r | |
5136 | -1,\r | |
c37e0f16 | 5137 | L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r |
0c84a69f | 5138 | PciExpressCap->SlotCapability.Bits.ElectromechanicalInterlock\r |
47d20b54 MK |
5139 | );\r |
5140 | ShellPrintEx (\r | |
5141 | -1,\r | |
5142 | -1,\r | |
c37e0f16 | 5143 | L" No Command Completed Support(18): %E%d%N\r\n",\r |
0c84a69f | 5144 | PciExpressCap->SlotCapability.Bits.NoCommandCompleted\r |
47d20b54 MK |
5145 | );\r |
5146 | ShellPrintEx (\r | |
5147 | -1,\r | |
5148 | -1,\r | |
c37e0f16 | 5149 | L" Physical Slot Number(31:19): %E%d%N\r\n",\r |
0c84a69f | 5150 | PciExpressCap->SlotCapability.Bits.PhysicalSlotNumber\r |
47d20b54 | 5151 | );\r |
5d73d92f | 5152 | \r |
5153 | return EFI_SUCCESS;\r | |
5154 | }\r | |
5155 | \r | |
a1d4bfcc | 5156 | /**\r |
5157 | Print out information of the device slot control information.\r | |
5158 | \r | |
5159 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5160 | \r | |
5161 | @retval EFI_SUCCESS The operation was successful.\r | |
5162 | **/\r | |
5d73d92f | 5163 | EFI_STATUS\r |
5164 | ExplainPcieSlotControl (\r | |
47d20b54 | 5165 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 5166 | )\r |
5d73d92f | 5167 | {\r |
47d20b54 MK |
5168 | ShellPrintEx (\r |
5169 | -1,\r | |
5170 | -1,\r | |
c37e0f16 | 5171 | L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r |
0c84a69f | 5172 | PciExpressCap->SlotControl.Bits.AttentionButtonPressed\r |
47d20b54 MK |
5173 | );\r |
5174 | ShellPrintEx (\r | |
5175 | -1,\r | |
5176 | -1,\r | |
c37e0f16 | 5177 | L" Power Fault Detected Enable(1): %E%d%N\r\n",\r |
0c84a69f | 5178 | PciExpressCap->SlotControl.Bits.PowerFaultDetected\r |
47d20b54 MK |
5179 | );\r |
5180 | ShellPrintEx (\r | |
5181 | -1,\r | |
5182 | -1,\r | |
c37e0f16 | 5183 | L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r |
0c84a69f | 5184 | PciExpressCap->SlotControl.Bits.MrlSensorChanged\r |
47d20b54 MK |
5185 | );\r |
5186 | ShellPrintEx (\r | |
5187 | -1,\r | |
5188 | -1,\r | |
c37e0f16 | 5189 | L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r |
0c84a69f | 5190 | PciExpressCap->SlotControl.Bits.PresenceDetectChanged\r |
47d20b54 MK |
5191 | );\r |
5192 | ShellPrintEx (\r | |
5193 | -1,\r | |
5194 | -1,\r | |
c37e0f16 | 5195 | L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r |
0c84a69f | 5196 | PciExpressCap->SlotControl.Bits.CommandCompletedInterrupt\r |
47d20b54 MK |
5197 | );\r |
5198 | ShellPrintEx (\r | |
5199 | -1,\r | |
5200 | -1,\r | |
c37e0f16 | 5201 | L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r |
0c84a69f | 5202 | PciExpressCap->SlotControl.Bits.HotPlugInterrupt\r |
47d20b54 MK |
5203 | );\r |
5204 | ShellPrintEx (\r | |
5205 | -1,\r | |
5206 | -1,\r | |
c37e0f16 | 5207 | L" Attention Indicator Control(7:6): %E%s%N\r\n",\r |
0c84a69f | 5208 | IndicatorTable[\r |
47d20b54 MK |
5209 | PciExpressCap->SlotControl.Bits.AttentionIndicator]\r |
5210 | );\r | |
5211 | ShellPrintEx (\r | |
5212 | -1,\r | |
5213 | -1,\r | |
c37e0f16 | 5214 | L" Power Indicator Control(9:8): %E%s%N\r\n",\r |
0c84a69f | 5215 | IndicatorTable[PciExpressCap->SlotControl.Bits.PowerIndicator]\r |
47d20b54 | 5216 | );\r |
c37e0f16 | 5217 | ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r |
0c84a69f | 5218 | if (\r |
47d20b54 MK |
5219 | PciExpressCap->SlotControl.Bits.PowerController)\r |
5220 | {\r | |
c37e0f16 | 5221 | ShellPrintEx (-1, -1, L"Off%N\r\n");\r |
5d73d92f | 5222 | } else {\r |
c37e0f16 | 5223 | ShellPrintEx (-1, -1, L"On%N\r\n");\r |
5d73d92f | 5224 | }\r |
47d20b54 MK |
5225 | \r |
5226 | ShellPrintEx (\r | |
5227 | -1,\r | |
5228 | -1,\r | |
c37e0f16 | 5229 | L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r |
0c84a69f | 5230 | PciExpressCap->SlotControl.Bits.ElectromechanicalInterlock\r |
47d20b54 MK |
5231 | );\r |
5232 | ShellPrintEx (\r | |
5233 | -1,\r | |
5234 | -1,\r | |
c37e0f16 | 5235 | L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r |
0c84a69f | 5236 | PciExpressCap->SlotControl.Bits.DataLinkLayerStateChanged\r |
47d20b54 | 5237 | );\r |
5d73d92f | 5238 | return EFI_SUCCESS;\r |
5239 | }\r | |
5240 | \r | |
a1d4bfcc | 5241 | /**\r |
5242 | Print out information of the device slot status information.\r | |
5243 | \r | |
5244 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5245 | \r | |
5246 | @retval EFI_SUCCESS The operation was successful.\r | |
5247 | **/\r | |
5d73d92f | 5248 | EFI_STATUS\r |
5249 | ExplainPcieSlotStatus (\r | |
47d20b54 | 5250 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 5251 | )\r |
5d73d92f | 5252 | {\r |
47d20b54 MK |
5253 | ShellPrintEx (\r |
5254 | -1,\r | |
5255 | -1,\r | |
c37e0f16 | 5256 | L" Attention Button Pressed(0): %E%d%N\r\n",\r |
0c84a69f | 5257 | PciExpressCap->SlotStatus.Bits.AttentionButtonPressed\r |
47d20b54 MK |
5258 | );\r |
5259 | ShellPrintEx (\r | |
5260 | -1,\r | |
5261 | -1,\r | |
c37e0f16 | 5262 | L" Power Fault Detected(1): %E%d%N\r\n",\r |
0c84a69f | 5263 | PciExpressCap->SlotStatus.Bits.PowerFaultDetected\r |
47d20b54 MK |
5264 | );\r |
5265 | ShellPrintEx (\r | |
5266 | -1,\r | |
5267 | -1,\r | |
c37e0f16 | 5268 | L" MRL Sensor Changed(2): %E%d%N\r\n",\r |
0c84a69f | 5269 | PciExpressCap->SlotStatus.Bits.MrlSensorChanged\r |
47d20b54 MK |
5270 | );\r |
5271 | ShellPrintEx (\r | |
5272 | -1,\r | |
5273 | -1,\r | |
c37e0f16 | 5274 | L" Presence Detect Changed(3): %E%d%N\r\n",\r |
0c84a69f | 5275 | PciExpressCap->SlotStatus.Bits.PresenceDetectChanged\r |
47d20b54 MK |
5276 | );\r |
5277 | ShellPrintEx (\r | |
5278 | -1,\r | |
5279 | -1,\r | |
c37e0f16 | 5280 | L" Command Completed(4): %E%d%N\r\n",\r |
0c84a69f | 5281 | PciExpressCap->SlotStatus.Bits.CommandCompleted\r |
47d20b54 | 5282 | );\r |
c37e0f16 | 5283 | ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r |
0c84a69f | 5284 | if (\r |
47d20b54 MK |
5285 | PciExpressCap->SlotStatus.Bits.MrlSensor)\r |
5286 | {\r | |
c37e0f16 | 5287 | ShellPrintEx (-1, -1, L" Opened%N\r\n");\r |
5d73d92f | 5288 | } else {\r |
c37e0f16 | 5289 | ShellPrintEx (-1, -1, L" Closed%N\r\n");\r |
5d73d92f | 5290 | }\r |
47d20b54 | 5291 | \r |
c37e0f16 | 5292 | ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r |
0c84a69f | 5293 | if (\r |
47d20b54 MK |
5294 | PciExpressCap->SlotStatus.Bits.PresenceDetect)\r |
5295 | {\r | |
c37e0f16 | 5296 | ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r |
5d73d92f | 5297 | } else {\r |
c37e0f16 | 5298 | ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r |
5d73d92f | 5299 | }\r |
47d20b54 | 5300 | \r |
c37e0f16 | 5301 | ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r |
0c84a69f | 5302 | if (\r |
47d20b54 MK |
5303 | PciExpressCap->SlotStatus.Bits.ElectromechanicalInterlock)\r |
5304 | {\r | |
c37e0f16 | 5305 | ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r |
5d73d92f | 5306 | } else {\r |
c37e0f16 | 5307 | ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r |
5d73d92f | 5308 | }\r |
47d20b54 MK |
5309 | \r |
5310 | ShellPrintEx (\r | |
5311 | -1,\r | |
5312 | -1,\r | |
c37e0f16 | 5313 | L" Data Link Layer State Changed(8): %E%d%N\r\n",\r |
0c84a69f | 5314 | PciExpressCap->SlotStatus.Bits.DataLinkLayerStateChanged\r |
47d20b54 | 5315 | );\r |
5d73d92f | 5316 | return EFI_SUCCESS;\r |
5317 | }\r | |
5318 | \r | |
a1d4bfcc | 5319 | /**\r |
5320 | Print out information of the device root information.\r | |
5321 | \r | |
5322 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5323 | \r | |
5324 | @retval EFI_SUCCESS The operation was successful.\r | |
5325 | **/\r | |
5d73d92f | 5326 | EFI_STATUS\r |
5327 | ExplainPcieRootControl (\r | |
47d20b54 | 5328 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 5329 | )\r |
5d73d92f | 5330 | {\r |
47d20b54 MK |
5331 | ShellPrintEx (\r |
5332 | -1,\r | |
5333 | -1,\r | |
c37e0f16 | 5334 | L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r |
0c84a69f | 5335 | PciExpressCap->RootControl.Bits.SystemErrorOnCorrectableError\r |
47d20b54 MK |
5336 | );\r |
5337 | ShellPrintEx (\r | |
5338 | -1,\r | |
5339 | -1,\r | |
c37e0f16 | 5340 | L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r |
0c84a69f | 5341 | PciExpressCap->RootControl.Bits.SystemErrorOnNonFatalError\r |
47d20b54 MK |
5342 | );\r |
5343 | ShellPrintEx (\r | |
5344 | -1,\r | |
5345 | -1,\r | |
c37e0f16 | 5346 | L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r |
0c84a69f | 5347 | PciExpressCap->RootControl.Bits.SystemErrorOnFatalError\r |
47d20b54 MK |
5348 | );\r |
5349 | ShellPrintEx (\r | |
5350 | -1,\r | |
5351 | -1,\r | |
c37e0f16 | 5352 | L" PME Interrupt Enable(3): %E%d%N\r\n",\r |
0c84a69f | 5353 | PciExpressCap->RootControl.Bits.PmeInterrupt\r |
47d20b54 MK |
5354 | );\r |
5355 | ShellPrintEx (\r | |
5356 | -1,\r | |
5357 | -1,\r | |
c37e0f16 | 5358 | L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r |
0c84a69f | 5359 | PciExpressCap->RootControl.Bits.CrsSoftwareVisibility\r |
47d20b54 | 5360 | );\r |
5d73d92f | 5361 | \r |
5362 | return EFI_SUCCESS;\r | |
5363 | }\r | |
5364 | \r | |
a1d4bfcc | 5365 | /**\r |
5366 | Print out information of the device root capability information.\r | |
5367 | \r | |
5368 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5369 | \r | |
5370 | @retval EFI_SUCCESS The operation was successful.\r | |
5371 | **/\r | |
5d73d92f | 5372 | EFI_STATUS\r |
5373 | ExplainPcieRootCap (\r | |
47d20b54 | 5374 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 5375 | )\r |
5d73d92f | 5376 | {\r |
47d20b54 MK |
5377 | ShellPrintEx (\r |
5378 | -1,\r | |
5379 | -1,\r | |
c37e0f16 | 5380 | L" CRS Software Visibility(0): %E%d%N\r\n",\r |
0c84a69f | 5381 | PciExpressCap->RootCapability.Bits.CrsSoftwareVisibility\r |
47d20b54 | 5382 | );\r |
5d73d92f | 5383 | \r |
5384 | return EFI_SUCCESS;\r | |
5385 | }\r | |
5386 | \r | |
a1d4bfcc | 5387 | /**\r |
5388 | Print out information of the device root status information.\r | |
5389 | \r | |
5390 | @param[in] PciExpressCap The pointer to the structure about the device.\r | |
5391 | \r | |
5392 | @retval EFI_SUCCESS The operation was successful.\r | |
5393 | **/\r | |
5d73d92f | 5394 | EFI_STATUS\r |
5395 | ExplainPcieRootStatus (\r | |
47d20b54 | 5396 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r |
a1d4bfcc | 5397 | )\r |
5d73d92f | 5398 | {\r |
47d20b54 MK |
5399 | ShellPrintEx (\r |
5400 | -1,\r | |
5401 | -1,\r | |
c37e0f16 | 5402 | L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r |
0c84a69f | 5403 | PciExpressCap->RootStatus.Bits.PmeRequesterId\r |
47d20b54 MK |
5404 | );\r |
5405 | ShellPrintEx (\r | |
5406 | -1,\r | |
5407 | -1,\r | |
c37e0f16 | 5408 | L" PME Status(16): %E%d%N\r\n",\r |
0c84a69f | 5409 | PciExpressCap->RootStatus.Bits.PmeStatus\r |
47d20b54 MK |
5410 | );\r |
5411 | ShellPrintEx (\r | |
5412 | -1,\r | |
5413 | -1,\r | |
c37e0f16 | 5414 | L" PME Pending(17): %E%d%N\r\n",\r |
0c84a69f | 5415 | PciExpressCap->RootStatus.Bits.PmePending\r |
47d20b54 | 5416 | );\r |
5d73d92f | 5417 | return EFI_SUCCESS;\r |
5418 | }\r | |
5419 | \r | |
705bffb5 JC |
5420 | /**\r |
5421 | Function to interpret and print out the link control structure\r | |
5422 | \r | |
5423 | @param[in] HeaderAddress The Address of this capability header.\r | |
5424 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5425 | **/\r | |
5426 | EFI_STATUS\r | |
705bffb5 | 5427 | PrintInterpretedExtendedCompatibilityLinkControl (\r |
47d20b54 MK |
5428 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5429 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5430 | )\r |
5431 | {\r | |
47d20b54 MK |
5432 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r |
5433 | \r | |
5434 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *)HeaderAddress;\r | |
705bffb5 | 5435 | \r |
47d20b54 MK |
5436 | ShellPrintHiiEx (\r |
5437 | -1,\r | |
5438 | -1,\r | |
5439 | NULL,\r | |
ba0014b9 LG |
5440 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL),\r |
5441 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5442 | Header->RootComplexLinkCapabilities,\r |
5443 | Header->RootComplexLinkControl,\r | |
5444 | Header->RootComplexLinkStatus\r | |
ba0014b9 | 5445 | );\r |
705bffb5 JC |
5446 | DumpHex (\r |
5447 | 4,\r | |
47d20b54 MK |
5448 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5449 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r | |
5450 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5451 | );\r |
5452 | return (EFI_SUCCESS);\r | |
5453 | }\r | |
5454 | \r | |
5455 | /**\r | |
5456 | Function to interpret and print out the power budgeting structure\r | |
5457 | \r | |
5458 | @param[in] HeaderAddress The Address of this capability header.\r | |
5459 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5460 | **/\r | |
5461 | EFI_STATUS\r | |
705bffb5 | 5462 | PrintInterpretedExtendedCompatibilityPowerBudgeting (\r |
47d20b54 MK |
5463 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5464 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5465 | )\r |
5466 | {\r | |
47d20b54 MK |
5467 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r |
5468 | \r | |
5469 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *)HeaderAddress;\r | |
705bffb5 | 5470 | \r |
47d20b54 MK |
5471 | ShellPrintHiiEx (\r |
5472 | -1,\r | |
5473 | -1,\r | |
5474 | NULL,\r | |
ba0014b9 LG |
5475 | STRING_TOKEN (STR_PCI_EXT_CAP_POWER),\r |
5476 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5477 | Header->DataSelect,\r |
5478 | Header->Data,\r | |
5479 | Header->PowerBudgetCapability\r | |
ba0014b9 | 5480 | );\r |
705bffb5 JC |
5481 | DumpHex (\r |
5482 | 4,\r | |
47d20b54 MK |
5483 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5484 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r | |
5485 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5486 | );\r |
5487 | return (EFI_SUCCESS);\r | |
5488 | }\r | |
5489 | \r | |
5490 | /**\r | |
5491 | Function to interpret and print out the ACS structure\r | |
5492 | \r | |
5493 | @param[in] HeaderAddress The Address of this capability header.\r | |
5494 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5495 | **/\r | |
5496 | EFI_STATUS\r | |
705bffb5 | 5497 | PrintInterpretedExtendedCompatibilityAcs (\r |
47d20b54 MK |
5498 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5499 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5500 | )\r |
5501 | {\r | |
5502 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r | |
5503 | UINT16 VectorSize;\r | |
5504 | UINT16 LoopCounter;\r | |
5505 | \r | |
47d20b54 MK |
5506 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *)HeaderAddress;\r |
5507 | VectorSize = 0;\r | |
705bffb5 | 5508 | \r |
47d20b54 MK |
5509 | ShellPrintHiiEx (\r |
5510 | -1,\r | |
5511 | -1,\r | |
5512 | NULL,\r | |
ba0014b9 LG |
5513 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS),\r |
5514 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5515 | Header->AcsCapability,\r |
5516 | Header->AcsControl\r | |
ba0014b9 | 5517 | );\r |
47d20b54 MK |
5518 | if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL (Header)) {\r |
5519 | VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE (Header);\r | |
705bffb5 JC |
5520 | if (VectorSize == 0) {\r |
5521 | VectorSize = 256;\r | |
5522 | }\r | |
47d20b54 MK |
5523 | \r |
5524 | for (LoopCounter = 0; LoopCounter * 8 < VectorSize; LoopCounter++) {\r | |
5525 | ShellPrintHiiEx (\r | |
5526 | -1,\r | |
5527 | -1,\r | |
5528 | NULL,\r | |
ba0014b9 LG |
5529 | STRING_TOKEN (STR_PCI_EXT_CAP_ACS2),\r |
5530 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5531 | LoopCounter + 1,\r |
5532 | Header->EgressControlVectorArray[LoopCounter]\r | |
ba0014b9 | 5533 | );\r |
705bffb5 JC |
5534 | }\r |
5535 | }\r | |
47d20b54 | 5536 | \r |
705bffb5 JC |
5537 | DumpHex (\r |
5538 | 4,\r | |
47d20b54 MK |
5539 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5540 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r | |
5541 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5542 | );\r |
5543 | return (EFI_SUCCESS);\r | |
5544 | }\r | |
5545 | \r | |
5546 | /**\r | |
5547 | Function to interpret and print out the latency tolerance reporting structure\r | |
5548 | \r | |
5549 | @param[in] HeaderAddress The Address of this capability header.\r | |
5550 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5551 | **/\r | |
5552 | EFI_STATUS\r | |
705bffb5 | 5553 | PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r |
47d20b54 MK |
5554 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5555 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5556 | )\r |
5557 | {\r | |
47d20b54 MK |
5558 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r |
5559 | \r | |
5560 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *)HeaderAddress;\r | |
705bffb5 | 5561 | \r |
47d20b54 MK |
5562 | ShellPrintHiiEx (\r |
5563 | -1,\r | |
5564 | -1,\r | |
5565 | NULL,\r | |
ba0014b9 LG |
5566 | STRING_TOKEN (STR_PCI_EXT_CAP_LAT),\r |
5567 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5568 | Header->MaxSnoopLatency,\r |
5569 | Header->MaxNoSnoopLatency\r | |
ba0014b9 | 5570 | );\r |
705bffb5 JC |
5571 | DumpHex (\r |
5572 | 4,\r | |
47d20b54 MK |
5573 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5574 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r | |
5575 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5576 | );\r |
5577 | return (EFI_SUCCESS);\r | |
5578 | }\r | |
5579 | \r | |
5580 | /**\r | |
5581 | Function to interpret and print out the serial number structure\r | |
5582 | \r | |
5583 | @param[in] HeaderAddress The Address of this capability header.\r | |
5584 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5585 | **/\r | |
5586 | EFI_STATUS\r | |
705bffb5 | 5587 | PrintInterpretedExtendedCompatibilitySerialNumber (\r |
47d20b54 MK |
5588 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5589 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5590 | )\r |
5591 | {\r | |
47d20b54 MK |
5592 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r |
5593 | \r | |
5594 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *)HeaderAddress;\r | |
705bffb5 | 5595 | \r |
47d20b54 MK |
5596 | ShellPrintHiiEx (\r |
5597 | -1,\r | |
5598 | -1,\r | |
5599 | NULL,\r | |
ba0014b9 LG |
5600 | STRING_TOKEN (STR_PCI_EXT_CAP_SN),\r |
5601 | gShellDebug1HiiHandle,\r | |
705bffb5 | 5602 | Header->SerialNumber\r |
ba0014b9 | 5603 | );\r |
705bffb5 JC |
5604 | DumpHex (\r |
5605 | 4,\r | |
47d20b54 MK |
5606 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5607 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r | |
5608 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5609 | );\r |
5610 | return (EFI_SUCCESS);\r | |
5611 | }\r | |
5612 | \r | |
5613 | /**\r | |
5614 | Function to interpret and print out the RCRB structure\r | |
5615 | \r | |
5616 | @param[in] HeaderAddress The Address of this capability header.\r | |
5617 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5618 | **/\r | |
5619 | EFI_STATUS\r | |
705bffb5 | 5620 | PrintInterpretedExtendedCompatibilityRcrb (\r |
47d20b54 MK |
5621 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5622 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5623 | )\r |
5624 | {\r | |
47d20b54 MK |
5625 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r |
5626 | \r | |
5627 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *)HeaderAddress;\r | |
705bffb5 | 5628 | \r |
47d20b54 MK |
5629 | ShellPrintHiiEx (\r |
5630 | -1,\r | |
5631 | -1,\r | |
5632 | NULL,\r | |
ba0014b9 LG |
5633 | STRING_TOKEN (STR_PCI_EXT_CAP_RCRB),\r |
5634 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5635 | Header->VendorId,\r |
5636 | Header->DeviceId,\r | |
5637 | Header->RcrbCapabilities,\r | |
5638 | Header->RcrbControl\r | |
ba0014b9 | 5639 | );\r |
705bffb5 JC |
5640 | DumpHex (\r |
5641 | 4,\r | |
47d20b54 MK |
5642 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5643 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r | |
5644 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5645 | );\r |
5646 | return (EFI_SUCCESS);\r | |
5647 | }\r | |
5648 | \r | |
5649 | /**\r | |
5650 | Function to interpret and print out the vendor specific structure\r | |
5651 | \r | |
5652 | @param[in] HeaderAddress The Address of this capability header.\r | |
5653 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5654 | **/\r | |
5655 | EFI_STATUS\r | |
705bffb5 | 5656 | PrintInterpretedExtendedCompatibilityVendorSpecific (\r |
47d20b54 MK |
5657 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5658 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5659 | )\r |
5660 | {\r | |
47d20b54 MK |
5661 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r |
5662 | \r | |
5663 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *)HeaderAddress;\r | |
705bffb5 | 5664 | \r |
47d20b54 MK |
5665 | ShellPrintHiiEx (\r |
5666 | -1,\r | |
5667 | -1,\r | |
5668 | NULL,\r | |
ba0014b9 LG |
5669 | STRING_TOKEN (STR_PCI_EXT_CAP_VEN),\r |
5670 | gShellDebug1HiiHandle,\r | |
705bffb5 | 5671 | Header->VendorSpecificHeader\r |
ba0014b9 | 5672 | );\r |
705bffb5 JC |
5673 | DumpHex (\r |
5674 | 4,\r | |
47d20b54 MK |
5675 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5676 | PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE (Header),\r | |
5677 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5678 | );\r |
5679 | return (EFI_SUCCESS);\r | |
5680 | }\r | |
5681 | \r | |
5682 | /**\r | |
5683 | Function to interpret and print out the Event Collector Endpoint Association structure\r | |
5684 | \r | |
5685 | @param[in] HeaderAddress The Address of this capability header.\r | |
5686 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5687 | **/\r | |
5688 | EFI_STATUS\r | |
705bffb5 | 5689 | PrintInterpretedExtendedCompatibilityECEA (\r |
47d20b54 MK |
5690 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5691 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5692 | )\r |
5693 | {\r | |
47d20b54 MK |
5694 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r |
5695 | \r | |
5696 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *)HeaderAddress;\r | |
705bffb5 | 5697 | \r |
47d20b54 MK |
5698 | ShellPrintHiiEx (\r |
5699 | -1,\r | |
5700 | -1,\r | |
5701 | NULL,\r | |
ba0014b9 LG |
5702 | STRING_TOKEN (STR_PCI_EXT_CAP_ECEA),\r |
5703 | gShellDebug1HiiHandle,\r | |
705bffb5 | 5704 | Header->AssociationBitmap\r |
ba0014b9 | 5705 | );\r |
705bffb5 JC |
5706 | DumpHex (\r |
5707 | 4,\r | |
47d20b54 MK |
5708 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5709 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r | |
5710 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5711 | );\r |
5712 | return (EFI_SUCCESS);\r | |
5713 | }\r | |
5714 | \r | |
5715 | /**\r | |
5716 | Function to interpret and print out the ARI structure\r | |
5717 | \r | |
5718 | @param[in] HeaderAddress The Address of this capability header.\r | |
5719 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5720 | **/\r | |
5721 | EFI_STATUS\r | |
705bffb5 | 5722 | PrintInterpretedExtendedCompatibilityAri (\r |
47d20b54 MK |
5723 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5724 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5725 | )\r |
5726 | {\r | |
47d20b54 MK |
5727 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r |
5728 | \r | |
5729 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *)HeaderAddress;\r | |
705bffb5 | 5730 | \r |
47d20b54 MK |
5731 | ShellPrintHiiEx (\r |
5732 | -1,\r | |
5733 | -1,\r | |
5734 | NULL,\r | |
ba0014b9 LG |
5735 | STRING_TOKEN (STR_PCI_EXT_CAP_ARI),\r |
5736 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5737 | Header->AriCapability,\r |
5738 | Header->AriControl\r | |
ba0014b9 | 5739 | );\r |
705bffb5 JC |
5740 | DumpHex (\r |
5741 | 4,\r | |
47d20b54 MK |
5742 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5743 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r | |
5744 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5745 | );\r |
5746 | return (EFI_SUCCESS);\r | |
5747 | }\r | |
5748 | \r | |
5749 | /**\r | |
5750 | Function to interpret and print out the DPA structure\r | |
5751 | \r | |
5752 | @param[in] HeaderAddress The Address of this capability header.\r | |
5753 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5754 | **/\r | |
5755 | EFI_STATUS\r | |
705bffb5 | 5756 | PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r |
47d20b54 MK |
5757 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5758 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5759 | )\r |
5760 | {\r | |
47d20b54 MK |
5761 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r |
5762 | UINT8 LinkCount;\r | |
705bffb5 | 5763 | \r |
47d20b54 MK |
5764 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *)HeaderAddress;\r |
5765 | \r | |
5766 | ShellPrintHiiEx (\r | |
5767 | -1,\r | |
5768 | -1,\r | |
5769 | NULL,\r | |
ba0014b9 LG |
5770 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA),\r |
5771 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5772 | Header->DpaCapability,\r |
5773 | Header->DpaLatencyIndicator,\r | |
5774 | Header->DpaStatus,\r | |
5775 | Header->DpaControl\r | |
ba0014b9 | 5776 | );\r |
47d20b54 MK |
5777 | for (LinkCount = 0; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header) + 1; LinkCount++) {\r |
5778 | ShellPrintHiiEx (\r | |
5779 | -1,\r | |
5780 | -1,\r | |
5781 | NULL,\r | |
ba0014b9 LG |
5782 | STRING_TOKEN (STR_PCI_EXT_CAP_DPA2),\r |
5783 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5784 | LinkCount+1,\r |
5785 | Header->DpaPowerAllocationArray[LinkCount]\r | |
5786 | );\r | |
5787 | }\r | |
47d20b54 | 5788 | \r |
705bffb5 JC |
5789 | DumpHex (\r |
5790 | 4,\r | |
47d20b54 MK |
5791 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5792 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header),\r | |
5793 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5794 | );\r |
5795 | return (EFI_SUCCESS);\r | |
5796 | }\r | |
5797 | \r | |
5798 | /**\r | |
5799 | Function to interpret and print out the link declaration structure\r | |
5800 | \r | |
5801 | @param[in] HeaderAddress The Address of this capability header.\r | |
5802 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5803 | **/\r | |
5804 | EFI_STATUS\r | |
705bffb5 | 5805 | PrintInterpretedExtendedCompatibilityLinkDeclaration (\r |
47d20b54 MK |
5806 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5807 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5808 | )\r |
5809 | {\r | |
5810 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r | |
5811 | UINT8 LinkCount;\r | |
705bffb5 | 5812 | \r |
47d20b54 MK |
5813 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *)HeaderAddress;\r |
5814 | \r | |
5815 | ShellPrintHiiEx (\r | |
5816 | -1,\r | |
5817 | -1,\r | |
5818 | NULL,\r | |
ba0014b9 LG |
5819 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR),\r |
5820 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5821 | Header->ElementSelfDescription\r |
5822 | );\r | |
5823 | \r | |
47d20b54 MK |
5824 | for (LinkCount = 0; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header); LinkCount++) {\r |
5825 | ShellPrintHiiEx (\r | |
5826 | -1,\r | |
5827 | -1,\r | |
5828 | NULL,\r | |
ba0014b9 LG |
5829 | STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2),\r |
5830 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5831 | LinkCount+1,\r |
5832 | Header->LinkEntry[LinkCount]\r | |
5833 | );\r | |
5834 | }\r | |
47d20b54 | 5835 | \r |
705bffb5 JC |
5836 | DumpHex (\r |
5837 | 4,\r | |
47d20b54 MK |
5838 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5839 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header)-1)*sizeof (UINT32),\r | |
5840 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5841 | );\r |
5842 | return (EFI_SUCCESS);\r | |
5843 | }\r | |
5844 | \r | |
5845 | /**\r | |
5846 | Function to interpret and print out the Advanced Error Reporting structure\r | |
5847 | \r | |
5848 | @param[in] HeaderAddress The Address of this capability header.\r | |
5849 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5850 | **/\r | |
5851 | EFI_STATUS\r | |
705bffb5 | 5852 | PrintInterpretedExtendedCompatibilityAer (\r |
47d20b54 MK |
5853 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5854 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
705bffb5 JC |
5855 | )\r |
5856 | {\r | |
47d20b54 MK |
5857 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r |
5858 | \r | |
5859 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *)HeaderAddress;\r | |
705bffb5 | 5860 | \r |
47d20b54 MK |
5861 | ShellPrintHiiEx (\r |
5862 | -1,\r | |
5863 | -1,\r | |
5864 | NULL,\r | |
ba0014b9 LG |
5865 | STRING_TOKEN (STR_PCI_EXT_CAP_AER),\r |
5866 | gShellDebug1HiiHandle,\r | |
705bffb5 JC |
5867 | Header->UncorrectableErrorStatus,\r |
5868 | Header->UncorrectableErrorMask,\r | |
5869 | Header->UncorrectableErrorSeverity,\r | |
5870 | Header->CorrectableErrorStatus,\r | |
5871 | Header->CorrectableErrorMask,\r | |
5872 | Header->AdvancedErrorCapabilitiesAndControl,\r | |
231ad7d8 QS |
5873 | Header->HeaderLog[0],\r |
5874 | Header->HeaderLog[1],\r | |
5875 | Header->HeaderLog[2],\r | |
5876 | Header->HeaderLog[3],\r | |
705bffb5 JC |
5877 | Header->RootErrorCommand,\r |
5878 | Header->RootErrorStatus,\r | |
5879 | Header->ErrorSourceIdentification,\r | |
5880 | Header->CorrectableErrorSourceIdentification,\r | |
5881 | Header->TlpPrefixLog[0],\r | |
5882 | Header->TlpPrefixLog[1],\r | |
5883 | Header->TlpPrefixLog[2],\r | |
5884 | Header->TlpPrefixLog[3]\r | |
5885 | );\r | |
5886 | DumpHex (\r | |
5887 | 4,\r | |
47d20b54 MK |
5888 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5889 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r | |
5890 | (VOID *)(HeaderAddress)\r | |
705bffb5 JC |
5891 | );\r |
5892 | return (EFI_SUCCESS);\r | |
5893 | }\r | |
5894 | \r | |
9f7f0697 JC |
5895 | /**\r |
5896 | Function to interpret and print out the multicast structure\r | |
5897 | \r | |
5898 | @param[in] HeaderAddress The Address of this capability header.\r | |
5899 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5900 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
5901 | **/\r | |
5902 | EFI_STATUS\r | |
9f7f0697 | 5903 | PrintInterpretedExtendedCompatibilityMulticast (\r |
47d20b54 MK |
5904 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5905 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
5906 | IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r | |
9f7f0697 JC |
5907 | )\r |
5908 | {\r | |
47d20b54 | 5909 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r |
9f7f0697 | 5910 | \r |
47d20b54 MK |
5911 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *)HeaderAddress;\r |
5912 | \r | |
5913 | ShellPrintHiiEx (\r | |
5914 | -1,\r | |
5915 | -1,\r | |
5916 | NULL,\r | |
ba0014b9 LG |
5917 | STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST),\r |
5918 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5919 | Header->MultiCastCapability,\r |
5920 | Header->MulticastControl,\r | |
5921 | Header->McBaseAddress,\r | |
5922 | Header->McReceiveAddress,\r | |
5923 | Header->McBlockAll,\r | |
5924 | Header->McBlockUntranslated,\r | |
5925 | Header->McOverlayBar\r | |
5926 | );\r | |
5927 | \r | |
5928 | DumpHex (\r | |
5929 | 4,\r | |
47d20b54 MK |
5930 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
5931 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r | |
5932 | (VOID *)(HeaderAddress)\r | |
9f7f0697 JC |
5933 | );\r |
5934 | \r | |
5935 | return (EFI_SUCCESS);\r | |
5936 | }\r | |
5937 | \r | |
5938 | /**\r | |
5939 | Function to interpret and print out the virtual channel and multi virtual channel structure\r | |
5940 | \r | |
5941 | @param[in] HeaderAddress The Address of this capability header.\r | |
5942 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
5943 | **/\r | |
5944 | EFI_STATUS\r | |
9f7f0697 | 5945 | PrintInterpretedExtendedCompatibilityVirtualChannel (\r |
47d20b54 MK |
5946 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
5947 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
9f7f0697 JC |
5948 | )\r |
5949 | {\r | |
5950 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r | |
5951 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r | |
5952 | UINT32 ItemCount;\r | |
9f7f0697 | 5953 | \r |
47d20b54 MK |
5954 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *)HeaderAddress;\r |
5955 | \r | |
5956 | ShellPrintHiiEx (\r | |
5957 | -1,\r | |
5958 | -1,\r | |
5959 | NULL,\r | |
ba0014b9 LG |
5960 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE),\r |
5961 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5962 | Header->ExtendedVcCount,\r |
5963 | Header->PortVcCapability1,\r | |
5964 | Header->PortVcCapability2,\r | |
5965 | Header->VcArbTableOffset,\r | |
5966 | Header->PortVcControl,\r | |
5967 | Header->PortVcStatus\r | |
5968 | );\r | |
47d20b54 | 5969 | for (ItemCount = 0; ItemCount < Header->ExtendedVcCount; ItemCount++) {\r |
9f7f0697 | 5970 | CapabilityItem = &Header->Capability[ItemCount];\r |
47d20b54 MK |
5971 | ShellPrintHiiEx (\r |
5972 | -1,\r | |
5973 | -1,\r | |
5974 | NULL,\r | |
ba0014b9 LG |
5975 | STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM),\r |
5976 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
5977 | ItemCount+1,\r |
5978 | CapabilityItem->VcResourceCapability,\r | |
5979 | CapabilityItem->PortArbTableOffset,\r | |
5980 | CapabilityItem->VcResourceControl,\r | |
5981 | CapabilityItem->VcResourceStatus\r | |
5982 | );\r | |
5983 | }\r | |
5984 | \r | |
5985 | DumpHex (\r | |
5986 | 4,\r | |
47d20b54 | 5987 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
26ca6f7e RN |
5988 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY)\r |
5989 | + Header->ExtendedVcCount * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC),\r | |
47d20b54 | 5990 | (VOID *)(HeaderAddress)\r |
9f7f0697 JC |
5991 | );\r |
5992 | \r | |
5993 | return (EFI_SUCCESS);\r | |
5994 | }\r | |
5995 | \r | |
5996 | /**\r | |
5997 | Function to interpret and print out the resizeable bar structure\r | |
5998 | \r | |
5999 | @param[in] HeaderAddress The Address of this capability header.\r | |
6000 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
6001 | **/\r | |
6002 | EFI_STATUS\r | |
9f7f0697 | 6003 | PrintInterpretedExtendedCompatibilityResizeableBar (\r |
47d20b54 MK |
6004 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
6005 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
9f7f0697 JC |
6006 | )\r |
6007 | {\r | |
47d20b54 MK |
6008 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r |
6009 | UINT32 ItemCount;\r | |
9f7f0697 | 6010 | \r |
47d20b54 MK |
6011 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *)HeaderAddress;\r |
6012 | \r | |
6013 | for (ItemCount = 0; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS (Header); ItemCount++) {\r | |
6014 | ShellPrintHiiEx (\r | |
6015 | -1,\r | |
6016 | -1,\r | |
6017 | NULL,\r | |
ba0014b9 LG |
6018 | STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR),\r |
6019 | gShellDebug1HiiHandle,\r | |
9f7f0697 | 6020 | ItemCount+1,\r |
42fe8ca4 LH |
6021 | Header->Capability[ItemCount].ResizableBarCapability.Uint32,\r |
6022 | Header->Capability[ItemCount].ResizableBarControl.Uint32\r | |
9f7f0697 JC |
6023 | );\r |
6024 | }\r | |
6025 | \r | |
6026 | DumpHex (\r | |
6027 | 4,\r | |
47d20b54 MK |
6028 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
6029 | (UINT32)GET_NUMBER_RESIZABLE_BARS (Header) * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r | |
6030 | (VOID *)(HeaderAddress)\r | |
9f7f0697 JC |
6031 | );\r |
6032 | \r | |
6033 | return (EFI_SUCCESS);\r | |
6034 | }\r | |
6035 | \r | |
6036 | /**\r | |
6037 | Function to interpret and print out the TPH structure\r | |
6038 | \r | |
6039 | @param[in] HeaderAddress The Address of this capability header.\r | |
6040 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
6041 | **/\r | |
6042 | EFI_STATUS\r | |
9f7f0697 | 6043 | PrintInterpretedExtendedCompatibilityTph (\r |
47d20b54 MK |
6044 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
6045 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r | |
9f7f0697 JC |
6046 | )\r |
6047 | {\r | |
47d20b54 | 6048 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r |
9f7f0697 | 6049 | \r |
47d20b54 MK |
6050 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *)HeaderAddress;\r |
6051 | \r | |
6052 | ShellPrintHiiEx (\r | |
6053 | -1,\r | |
6054 | -1,\r | |
6055 | NULL,\r | |
ba0014b9 LG |
6056 | STRING_TOKEN (STR_PCI_EXT_CAP_TPH),\r |
6057 | gShellDebug1HiiHandle,\r | |
9f7f0697 JC |
6058 | Header->TphRequesterCapability,\r |
6059 | Header->TphRequesterControl\r | |
6060 | );\r | |
6061 | DumpHex (\r | |
6062 | 8,\r | |
47d20b54 MK |
6063 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)Header->TphStTable - (UINT8 *)HeadersBaseAddress),\r |
6064 | GET_TPH_TABLE_SIZE (Header),\r | |
9f7f0697 JC |
6065 | (VOID *)Header->TphStTable\r |
6066 | );\r | |
6067 | \r | |
6068 | DumpHex (\r | |
6069 | 4,\r | |
47d20b54 MK |
6070 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
6071 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE (Header) - sizeof (UINT16),\r | |
6072 | (VOID *)(HeaderAddress)\r | |
9f7f0697 JC |
6073 | );\r |
6074 | \r | |
6075 | return (EFI_SUCCESS);\r | |
6076 | }\r | |
6077 | \r | |
6078 | /**\r | |
6079 | Function to interpret and print out the secondary PCIe capability structure\r | |
6080 | \r | |
6081 | @param[in] HeaderAddress The Address of this capability header.\r | |
6082 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
6083 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
6084 | **/\r | |
6085 | EFI_STATUS\r | |
9f7f0697 | 6086 | PrintInterpretedExtendedCompatibilitySecondary (\r |
47d20b54 MK |
6087 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r |
6088 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
6089 | IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCap\r | |
9f7f0697 JC |
6090 | )\r |
6091 | {\r | |
47d20b54 MK |
6092 | CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r |
6093 | \r | |
6094 | Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *)HeaderAddress;\r | |
9f7f0697 | 6095 | \r |
47d20b54 MK |
6096 | ShellPrintHiiEx (\r |
6097 | -1,\r | |
6098 | -1,\r | |
6099 | NULL,\r | |
ba0014b9 LG |
6100 | STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY),\r |
6101 | gShellDebug1HiiHandle,\r | |
0c84a69f | 6102 | Header->LinkControl3.Uint32,\r |
9f7f0697 JC |
6103 | Header->LaneErrorStatus\r |
6104 | );\r | |
6105 | DumpHex (\r | |
6106 | 8,\r | |
47d20b54 | 6107 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)Header->EqualizationControl - (UINT8 *)HeadersBaseAddress),\r |
0c84a69f | 6108 | PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r |
9f7f0697 JC |
6109 | (VOID *)Header->EqualizationControl\r |
6110 | );\r | |
6111 | \r | |
6112 | DumpHex (\r | |
6113 | 4,\r | |
47d20b54 | 6114 | EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8 *)HeaderAddress - (UINT8 *)HeadersBaseAddress),\r |
0c84a69f | 6115 | sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE) - sizeof (Header->EqualizationControl)\r |
47d20b54 MK |
6116 | + PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r |
6117 | (VOID *)(HeaderAddress)\r | |
9f7f0697 JC |
6118 | );\r |
6119 | \r | |
6120 | return (EFI_SUCCESS);\r | |
6121 | }\r | |
6122 | \r | |
705bffb5 JC |
6123 | /**\r |
6124 | Display Pcie extended capability details\r | |
6125 | \r | |
6126 | @param[in] HeadersBaseAddress The address of all the extended capability headers.\r | |
6127 | @param[in] HeaderAddress The address of this capability header.\r | |
6128 | @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r | |
6129 | **/\r | |
6130 | EFI_STATUS\r | |
47d20b54 MK |
6131 | PrintPciExtendedCapabilityDetails (\r |
6132 | IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r | |
6133 | IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r | |
6134 | IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r | |
705bffb5 JC |
6135 | )\r |
6136 | {\r | |
47d20b54 | 6137 | switch (HeaderAddress->CapabilityId) {\r |
705bffb5 | 6138 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r |
47d20b54 | 6139 | return PrintInterpretedExtendedCompatibilityAer (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6140 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r |
47d20b54 | 6141 | return PrintInterpretedExtendedCompatibilityLinkControl (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6142 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r |
47d20b54 | 6143 | return PrintInterpretedExtendedCompatibilityLinkDeclaration (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6144 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r |
47d20b54 | 6145 | return PrintInterpretedExtendedCompatibilitySerialNumber (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6146 | case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r |
47d20b54 | 6147 | return PrintInterpretedExtendedCompatibilityPowerBudgeting (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6148 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r |
47d20b54 | 6149 | return PrintInterpretedExtendedCompatibilityAcs (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6150 | case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r |
47d20b54 | 6151 | return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6152 | case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r |
47d20b54 | 6153 | return PrintInterpretedExtendedCompatibilityAri (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6154 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r |
47d20b54 | 6155 | return PrintInterpretedExtendedCompatibilityRcrb (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6156 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r |
47d20b54 | 6157 | return PrintInterpretedExtendedCompatibilityVendorSpecific (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6158 | case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r |
47d20b54 | 6159 | return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6160 | case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r |
47d20b54 | 6161 | return PrintInterpretedExtendedCompatibilityECEA (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 JC |
6162 | case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r |
6163 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r | |
47d20b54 | 6164 | return PrintInterpretedExtendedCompatibilityVirtualChannel (HeaderAddress, HeadersBaseAddress);\r |
ba0014b9 | 6165 | case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:\r |
9f7f0697 JC |
6166 | //\r |
6167 | // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r | |
6168 | //\r | |
47d20b54 | 6169 | return PrintInterpretedExtendedCompatibilityMulticast (HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r |
705bffb5 | 6170 | case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r |
47d20b54 | 6171 | return PrintInterpretedExtendedCompatibilityResizeableBar (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6172 | case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r |
47d20b54 | 6173 | return PrintInterpretedExtendedCompatibilityTph (HeaderAddress, HeadersBaseAddress);\r |
705bffb5 | 6174 | case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r |
47d20b54 | 6175 | return PrintInterpretedExtendedCompatibilitySecondary (HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r |
705bffb5 | 6176 | default:\r |
47d20b54 MK |
6177 | ShellPrintEx (\r |
6178 | -1,\r | |
6179 | -1,\r | |
705bffb5 JC |
6180 | L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r |
6181 | HeaderAddress->CapabilityId\r | |
6182 | );\r | |
6183 | return EFI_SUCCESS;\r | |
47d20b54 | 6184 | }\r |
705bffb5 JC |
6185 | }\r |
6186 | \r | |
a1d4bfcc | 6187 | /**\r |
6188 | Display Pcie device structure.\r | |
6189 | \r | |
33cc487c RN |
6190 | @param[in] PciExpressCap PCI Express capability buffer.\r |
6191 | @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r | |
3d0df0f0 | 6192 | @param[in] ExtendedConfigSize PCI Express extended configuration size.\r |
33cc487c | 6193 | @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r |
a1d4bfcc | 6194 | **/\r |
33cc487c | 6195 | VOID\r |
5d73d92f | 6196 | PciExplainPciExpress (\r |
47d20b54 MK |
6197 | IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r |
6198 | IN UINT8 *ExtendedConfigSpace,\r | |
6199 | IN UINTN ExtendedConfigSize,\r | |
6200 | IN CONST UINT16 ExtendedCapability\r | |
5d73d92f | 6201 | )\r |
6202 | {\r | |
47d20b54 MK |
6203 | UINT8 DevicePortType;\r |
6204 | UINTN Index;\r | |
6205 | UINT8 *RegAddr;\r | |
6206 | UINTN RegValue;\r | |
6207 | PCI_EXP_EXT_HDR *ExtHdr;\r | |
5d73d92f | 6208 | \r |
33cc487c | 6209 | DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r |
5d73d92f | 6210 | \r |
c37e0f16 | 6211 | ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r |
5d73d92f | 6212 | \r |
6213 | for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r | |
47d20b54 | 6214 | if (ShellGetExecutionBreakFlag ()) {\r |
33cc487c | 6215 | return;\r |
5d73d92f | 6216 | }\r |
47d20b54 MK |
6217 | \r |
6218 | RegAddr = (UINT8 *)PciExpressCap + PcieExplainList[Index].Offset;\r | |
5d73d92f | 6219 | switch (PcieExplainList[Index].Width) {\r |
6220 | case FieldWidthUINT8:\r | |
47d20b54 | 6221 | RegValue = *(UINT8 *)RegAddr;\r |
5d73d92f | 6222 | break;\r |
6223 | case FieldWidthUINT16:\r | |
47d20b54 | 6224 | RegValue = *(UINT16 *)RegAddr;\r |
5d73d92f | 6225 | break;\r |
6226 | case FieldWidthUINT32:\r | |
47d20b54 | 6227 | RegValue = *(UINT32 *)RegAddr;\r |
5d73d92f | 6228 | break;\r |
6229 | default:\r | |
6230 | RegValue = 0;\r | |
6231 | break;\r | |
6232 | }\r | |
47d20b54 MK |
6233 | \r |
6234 | ShellPrintHiiEx (\r | |
6235 | -1,\r | |
6236 | -1,\r | |
6237 | NULL,\r | |
5d73d92f | 6238 | PcieExplainList[Index].Token,\r |
6239 | gShellDebug1HiiHandle,\r | |
6240 | PcieExplainList[Index].Offset,\r | |
6241 | RegValue\r | |
47d20b54 | 6242 | );\r |
5d73d92f | 6243 | if (PcieExplainList[Index].Func == NULL) {\r |
6244 | continue;\r | |
6245 | }\r | |
47d20b54 | 6246 | \r |
5d73d92f | 6247 | switch (PcieExplainList[Index].Type) {\r |
6248 | case PcieExplainTypeLink:\r | |
6249 | //\r | |
6250 | // Link registers should not be used by\r | |
6251 | // a) Root Complex Integrated Endpoint\r | |
6252 | // b) Root Complex Event Collector\r | |
6253 | //\r | |
47d20b54 MK |
6254 | if ((DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) ||\r |
6255 | (DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR))\r | |
6256 | {\r | |
5d73d92f | 6257 | continue;\r |
6258 | }\r | |
47d20b54 | 6259 | \r |
5d73d92f | 6260 | break;\r |
6261 | case PcieExplainTypeSlot:\r | |
6262 | //\r | |
6263 | // Slot registers are only valid for\r | |
6264 | // a) Root Port of PCI Express Root Complex\r | |
6265 | // b) Downstream Port of PCI Express Switch\r | |
6266 | // and when SlotImplemented bit is set in PCIE cap register.\r | |
6267 | //\r | |
47d20b54 MK |
6268 | if (((DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) &&\r |
6269 | (DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT)) ||\r | |
6270 | !PciExpressCap->Capability.Bits.SlotImplemented)\r | |
6271 | {\r | |
5d73d92f | 6272 | continue;\r |
6273 | }\r | |
47d20b54 | 6274 | \r |
5d73d92f | 6275 | break;\r |
6276 | case PcieExplainTypeRoot:\r | |
6277 | //\r | |
6278 | // Root registers are only valid for\r | |
6279 | // Root Port of PCI Express Root Complex\r | |
6280 | //\r | |
0c84a69f | 6281 | if (DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) {\r |
5d73d92f | 6282 | continue;\r |
6283 | }\r | |
47d20b54 | 6284 | \r |
5d73d92f | 6285 | break;\r |
6286 | default:\r | |
6287 | break;\r | |
6288 | }\r | |
47d20b54 | 6289 | \r |
33cc487c | 6290 | PcieExplainList[Index].Func (PciExpressCap);\r |
5d73d92f | 6291 | }\r |
6292 | \r | |
47d20b54 | 6293 | ExtHdr = (PCI_EXP_EXT_HDR *)ExtendedConfigSpace;\r |
3d0df0f0 | 6294 | while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0 && ExtHdr->CapabilityId != 0xFFFF) {\r |
705bffb5 | 6295 | //\r |
c831a2c3 | 6296 | // Process this item\r |
705bffb5 | 6297 | //\r |
47d20b54 | 6298 | if ((ExtendedCapability == 0xFFFF) || (ExtendedCapability == ExtHdr->CapabilityId)) {\r |
705bffb5 | 6299 | //\r |
c831a2c3 | 6300 | // Print this item\r |
705bffb5 | 6301 | //\r |
47d20b54 | 6302 | PrintPciExtendedCapabilityDetails ((PCI_EXP_EXT_HDR *)ExtendedConfigSpace, ExtHdr, PciExpressCap);\r |
c831a2c3 | 6303 | }\r |
5d73d92f | 6304 | \r |
c831a2c3 RN |
6305 | //\r |
6306 | // Advance to the next item if it exists\r | |
6307 | //\r | |
47d20b54 MK |
6308 | if ((ExtHdr->NextCapabilityOffset != 0) &&\r |
6309 | (ExtHdr->NextCapabilityOffset <= (UINT32)(ExtendedConfigSize + EFI_PCIE_CAPABILITY_BASE_OFFSET - sizeof (PCI_EXP_EXT_HDR))))\r | |
6310 | {\r | |
6311 | ExtHdr = (PCI_EXP_EXT_HDR *)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r | |
c831a2c3 RN |
6312 | } else {\r |
6313 | break;\r | |
705bffb5 | 6314 | }\r |
d8f8021c | 6315 | }\r |
5d73d92f | 6316 | }\r |