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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
0c84a69f 4 Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>\r
231ad7d8
QS		 5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r
5d73d92f 7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include "UefiShellDebug1CommandsLib.h"\r
18#include <Protocol/PciRootBridgeIo.h>\r
19#include <Library/ShellLib.h>\r
20#include <IndustryStandard/Pci.h>\r
21#include <IndustryStandard/Acpi.h>\r
22#include "Pci.h"\r
23\r
5d73d92f 24//\r
25// Printable strings for Pci class code\r
26//\r
27typedef struct {\r
28 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
29 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
30 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
31} PCI_CLASS_STRINGS;\r
32\r
33//\r
34// a structure holding a single entry, which also points to its lower level\r
35// class\r
36//\r
37typedef struct PCI_CLASS_ENTRY_TAG {\r
38 UINT8 Code; // Class, subclass or I/F code\r
39 CHAR16 *DescText; // Description string\r
40 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
41} PCI_CLASS_ENTRY;\r
42\r
43//\r
44// Declarations of entries which contain printable strings for class codes\r
45// in PCI configuration space\r
46//\r
47PCI_CLASS_ENTRY PCIBlankEntry[];\r
48PCI_CLASS_ENTRY PCISubClass_00[];\r
49PCI_CLASS_ENTRY PCISubClass_01[];\r
50PCI_CLASS_ENTRY PCISubClass_02[];\r
51PCI_CLASS_ENTRY PCISubClass_03[];\r
52PCI_CLASS_ENTRY PCISubClass_04[];\r
53PCI_CLASS_ENTRY PCISubClass_05[];\r
54PCI_CLASS_ENTRY PCISubClass_06[];\r
55PCI_CLASS_ENTRY PCISubClass_07[];\r
56PCI_CLASS_ENTRY PCISubClass_08[];\r
57PCI_CLASS_ENTRY PCISubClass_09[];\r
58PCI_CLASS_ENTRY PCISubClass_0a[];\r
59PCI_CLASS_ENTRY PCISubClass_0b[];\r
60PCI_CLASS_ENTRY PCISubClass_0c[];\r
61PCI_CLASS_ENTRY PCISubClass_0d[];\r
62PCI_CLASS_ENTRY PCISubClass_0e[];\r
63PCI_CLASS_ENTRY PCISubClass_0f[];\r
64PCI_CLASS_ENTRY PCISubClass_10[];\r
65PCI_CLASS_ENTRY PCISubClass_11[];\r
f056e4c1
JC		 66PCI_CLASS_ENTRY PCISubClass_12[];\r
67PCI_CLASS_ENTRY PCISubClass_13[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0100[];\r
5d73d92f 69PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
f056e4c1
JC		 70PCI_CLASS_ENTRY PCIPIFClass_0105[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0106[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0107[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0108[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0109[];\r
5d73d92f 75PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
f056e4c1
JC		 77PCI_CLASS_ENTRY PCIPIFClass_0609[];\r
78PCI_CLASS_ENTRY PCIPIFClass_060b[];\r
5d73d92f 79PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
80PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
81PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
82PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
83PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
84PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
85PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
86PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
87PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
88PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
f056e4c1
JC		 89PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r
90PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r
5d73d92f 91PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
92\r
93//\r
94// Base class strings entries\r
95//\r
96PCI_CLASS_ENTRY gClassStringList[] = {\r
97 {\r
98 0x00,\r
99 L"Pre 2.0 device",\r
100 PCISubClass_00\r
101 },\r
102 {\r
103 0x01,\r
104 L"Mass Storage Controller",\r
105 PCISubClass_01\r
106 },\r
107 {\r
108 0x02,\r
109 L"Network Controller",\r
110 PCISubClass_02\r
111 },\r
112 {\r
113 0x03,\r
114 L"Display Controller",\r
115 PCISubClass_03\r
116 },\r
117 {\r
118 0x04,\r
119 L"Multimedia Device",\r
120 PCISubClass_04\r
121 },\r
122 {\r
123 0x05,\r
124 L"Memory Controller",\r
125 PCISubClass_05\r
126 },\r
127 {\r
128 0x06,\r
129 L"Bridge Device",\r
130 PCISubClass_06\r
131 },\r
132 {\r
133 0x07,\r
134 L"Simple Communications Controllers",\r
135 PCISubClass_07\r
136 },\r
137 {\r
138 0x08,\r
139 L"Base System Peripherals",\r
140 PCISubClass_08\r
141 },\r
142 {\r
143 0x09,\r
144 L"Input Devices",\r
145 PCISubClass_09\r
146 },\r
147 {\r
148 0x0a,\r
149 L"Docking Stations",\r
150 PCISubClass_0a\r
151 },\r
152 {\r
153 0x0b,\r
154 L"Processors",\r
155 PCISubClass_0b\r
156 },\r
157 {\r
158 0x0c,\r
159 L"Serial Bus Controllers",\r
160 PCISubClass_0c\r
161 },\r
162 {\r
163 0x0d,\r
164 L"Wireless Controllers",\r
165 PCISubClass_0d\r
166 },\r
167 {\r
168 0x0e,\r
169 L"Intelligent IO Controllers",\r
170 PCISubClass_0e\r
171 },\r
172 {\r
173 0x0f,\r
174 L"Satellite Communications Controllers",\r
175 PCISubClass_0f\r
176 },\r
177 {\r
178 0x10,\r
179 L"Encryption/Decryption Controllers",\r
180 PCISubClass_10\r
181 },\r
182 {\r
183 0x11,\r
184 L"Data Acquisition & Signal Processing Controllers",\r
185 PCISubClass_11\r
186 },\r
f056e4c1
JC		 187 {\r
188 0x12,\r
189 L"Processing Accelerators",\r
190 PCISubClass_12\r
191 },\r
192 {\r
193 0x13,\r
194 L"Non-Essential Instrumentation",\r
195 PCISubClass_13\r
196 },\r
5d73d92f 197 {\r
198 0xff,\r
199 L"Device does not fit in any defined classes",\r
200 PCIBlankEntry\r
201 },\r
202 {\r
203 0x00,\r
204 NULL,\r
205 /* null string ends the list */NULL\r
206 }\r
207};\r
208\r
209//\r
210// Subclass strings entries\r
211//\r
212PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
213 {\r
214 0x00,\r
215 L"",\r
216 PCIBlankEntry\r
217 },\r
218 {\r
219 0x00,\r
220 NULL,\r
221 /* null string ends the list */NULL\r
222 }\r
223};\r
224\r
225PCI_CLASS_ENTRY PCISubClass_00[] = {\r
226 {\r
227 0x00,\r
228 L"All devices other than VGA",\r
229 PCIBlankEntry\r
230 },\r
231 {\r
232 0x01,\r
233 L"VGA-compatible devices",\r
234 PCIBlankEntry\r
235 },\r
236 {\r
237 0x00,\r
238 NULL,\r
239 /* null string ends the list */NULL\r
240 }\r
241};\r
242\r
243PCI_CLASS_ENTRY PCISubClass_01[] = {\r
244 {\r
245 0x00,\r
f056e4c1
JC		 246 L"SCSI",\r
247 PCIPIFClass_0100\r
5d73d92f 248 },\r
249 {\r
250 0x01,\r
251 L"IDE controller",\r
252 PCIPIFClass_0101\r
253 },\r
254 {\r
255 0x02,\r
256 L"Floppy disk controller",\r
257 PCIBlankEntry\r
258 },\r
259 {\r
260 0x03,\r
261 L"IPI controller",\r
262 PCIBlankEntry\r
263 },\r
264 {\r
265 0x04,\r
266 L"RAID controller",\r
267 PCIBlankEntry\r
268 },\r
f056e4c1
JC		 269 {\r
270 0x05,\r
271 L"ATA controller with ADMA interface",\r
272 PCIPIFClass_0105\r
273 },\r
274 {\r
275 0x06,\r
276 L"Serial ATA controller",\r
277 PCIPIFClass_0106\r
278 },\r
279 {\r
280 0x07,\r
281 L"Serial Attached SCSI (SAS) controller ",\r
282 PCIPIFClass_0107\r
283 },\r
284 {\r
285 0x08,\r
286 L"Non-volatile memory subsystem",\r
287 PCIPIFClass_0108\r
288 },\r
289 {\r
290 0x09,\r
291 L"Universal Flash Storage (UFS) controller ",\r
292 PCIPIFClass_0109\r
293 },\r
5d73d92f 294 {\r
295 0x80,\r
296 L"Other mass storage controller",\r
297 PCIBlankEntry\r
298 },\r
299 {\r
300 0x00,\r
301 NULL,\r
302 /* null string ends the list */NULL\r
303 }\r
304};\r
305\r
306PCI_CLASS_ENTRY PCISubClass_02[] = {\r
307 {\r
308 0x00,\r
309 L"Ethernet controller",\r
310 PCIBlankEntry\r
311 },\r
312 {\r
313 0x01,\r
314 L"Token ring controller",\r
315 PCIBlankEntry\r
316 },\r
317 {\r
318 0x02,\r
319 L"FDDI controller",\r
320 PCIBlankEntry\r
321 },\r
322 {\r
323 0x03,\r
324 L"ATM controller",\r
325 PCIBlankEntry\r
326 },\r
327 {\r
328 0x04,\r
329 L"ISDN controller",\r
330 PCIBlankEntry\r
331 },\r
f056e4c1
JC		 332 {\r
333 0x05,\r
334 L"WorldFip controller",\r
335 PCIBlankEntry\r
336 },\r
337 {\r
338 0x06,\r
339 L"PICMG 2.14 Multi Computing",\r
340 PCIBlankEntry\r
341 },\r
342 {\r
343 0x07,\r
344 L"InfiniBand controller",\r
345 PCIBlankEntry\r
346 },\r
5d73d92f 347 {\r
348 0x80,\r
349 L"Other network controller",\r
350 PCIBlankEntry\r
351 },\r
352 {\r
353 0x00,\r
354 NULL,\r
355 /* null string ends the list */NULL\r
356 }\r
357};\r
358\r
359PCI_CLASS_ENTRY PCISubClass_03[] = {\r
360 {\r
361 0x00,\r
362 L"VGA/8514 controller",\r
363 PCIPIFClass_0300\r
364 },\r
365 {\r
366 0x01,\r
367 L"XGA controller",\r
368 PCIBlankEntry\r
369 },\r
370 {\r
371 0x02,\r
372 L"3D controller",\r
373 PCIBlankEntry\r
374 },\r
375 {\r
376 0x80,\r
377 L"Other display controller",\r
378 PCIBlankEntry\r
379 },\r
380 {\r
381 0x00,\r
382 NULL,\r
383 /* null string ends the list */PCIBlankEntry\r
384 }\r
385};\r
386\r
387PCI_CLASS_ENTRY PCISubClass_04[] = {\r
388 {\r
389 0x00,\r
390 L"Video device",\r
391 PCIBlankEntry\r
392 },\r
393 {\r
394 0x01,\r
395 L"Audio device",\r
396 PCIBlankEntry\r
397 },\r
398 {\r
399 0x02,\r
400 L"Computer Telephony device",\r
401 PCIBlankEntry\r
402 },\r
f056e4c1
JC		 403 {\r
404 0x03,\r
405 L"Mixed mode device",\r
406 PCIBlankEntry\r
407 },\r
5d73d92f 408 {\r
409 0x80,\r
410 L"Other multimedia device",\r
411 PCIBlankEntry\r
412 },\r
413 {\r
414 0x00,\r
415 NULL,\r
416 /* null string ends the list */NULL\r
417 }\r
418};\r
419\r
420PCI_CLASS_ENTRY PCISubClass_05[] = {\r
421 {\r
422 0x00,\r
423 L"RAM memory controller",\r
424 PCIBlankEntry\r
425 },\r
426 {\r
427 0x01,\r
428 L"Flash memory controller",\r
429 PCIBlankEntry\r
430 },\r
431 {\r
432 0x80,\r
433 L"Other memory controller",\r
434 PCIBlankEntry\r
435 },\r
436 {\r
437 0x00,\r
438 NULL,\r
439 /* null string ends the list */NULL\r
440 }\r
441};\r
442\r
443PCI_CLASS_ENTRY PCISubClass_06[] = {\r
444 {\r
445 0x00,\r
446 L"Host/PCI bridge",\r
447 PCIBlankEntry\r
448 },\r
449 {\r
450 0x01,\r
451 L"PCI/ISA bridge",\r
452 PCIBlankEntry\r
453 },\r
454 {\r
455 0x02,\r
456 L"PCI/EISA bridge",\r
457 PCIBlankEntry\r
458 },\r
459 {\r
460 0x03,\r
461 L"PCI/Micro Channel bridge",\r
462 PCIBlankEntry\r
463 },\r
464 {\r
465 0x04,\r
466 L"PCI/PCI bridge",\r
467 PCIPIFClass_0604\r
468 },\r
469 {\r
470 0x05,\r
471 L"PCI/PCMCIA bridge",\r
472 PCIBlankEntry\r
473 },\r
474 {\r
475 0x06,\r
476 L"NuBus bridge",\r
477 PCIBlankEntry\r
478 },\r
479 {\r
480 0x07,\r
481 L"CardBus bridge",\r
482 PCIBlankEntry\r
483 },\r
484 {\r
485 0x08,\r
486 L"RACEway bridge",\r
487 PCIBlankEntry\r
488 },\r
f056e4c1
JC		 489 {\r
490 0x09,\r
491 L"Semi-transparent PCI-to-PCI bridge",\r
492 PCIPIFClass_0609\r
493 },\r
494 {\r
495 0x0A,\r
496 L"InfiniBand-to-PCI host bridge",\r
497 PCIBlankEntry\r
498 },\r
499 {\r
500 0x0B,\r
501 L"Advanced Switching to PCI host bridge",\r
502 PCIPIFClass_060b\r
503 },\r
5d73d92f 504 {\r
505 0x80,\r
506 L"Other bridge type",\r
507 PCIBlankEntry\r
508 },\r
509 {\r
510 0x00,\r
511 NULL,\r
512 /* null string ends the list */NULL\r
513 }\r
514};\r
515\r
516PCI_CLASS_ENTRY PCISubClass_07[] = {\r
517 {\r
518 0x00,\r
519 L"Serial controller",\r
520 PCIPIFClass_0700\r
521 },\r
522 {\r
523 0x01,\r
524 L"Parallel port",\r
525 PCIPIFClass_0701\r
526 },\r
527 {\r
528 0x02,\r
529 L"Multiport serial controller",\r
530 PCIBlankEntry\r
531 },\r
532 {\r
533 0x03,\r
534 L"Modem",\r
535 PCIPIFClass_0703\r
536 },\r
f056e4c1
JC		 537 {\r
538 0x04,\r
539 L"GPIB (IEEE 488.1/2) controller",\r
540 PCIBlankEntry\r
541 },\r
542 {\r
543 0x05,\r
544 L"Smart Card",\r
545 PCIBlankEntry\r
546 },\r
5d73d92f 547 {\r
548 0x80,\r
549 L"Other communication device",\r
550 PCIBlankEntry\r
551 },\r
552 {\r
553 0x00,\r
554 NULL,\r
555 /* null string ends the list */NULL\r
556 }\r
557};\r
558\r
559PCI_CLASS_ENTRY PCISubClass_08[] = {\r
560 {\r
561 0x00,\r
562 L"PIC",\r
563 PCIPIFClass_0800\r
564 },\r
565 {\r
566 0x01,\r
567 L"DMA controller",\r
568 PCIPIFClass_0801\r
569 },\r
570 {\r
571 0x02,\r
572 L"System timer",\r
573 PCIPIFClass_0802\r
574 },\r
575 {\r
576 0x03,\r
577 L"RTC controller",\r
578 PCIPIFClass_0803\r
579 },\r
580 {\r
581 0x04,\r
582 L"Generic PCI Hot-Plug controller",\r
583 PCIBlankEntry\r
584 },\r
f056e4c1
JC		 585 {\r
586 0x05,\r
587 L"SD Host controller",\r
588 PCIBlankEntry\r
589 },\r
590 {\r
591 0x06,\r
592 L"IOMMU",\r
593 PCIBlankEntry\r
594 },\r
595 {\r
596 0x07,\r
597 L"Root Complex Event Collector",\r
598 PCIBlankEntry\r
599 },\r
5d73d92f 600 {\r
601 0x80,\r
602 L"Other system peripheral",\r
603 PCIBlankEntry\r
604 },\r
605 {\r
606 0x00,\r
607 NULL,\r
608 /* null string ends the list */NULL\r
609 }\r
610};\r
611\r
612PCI_CLASS_ENTRY PCISubClass_09[] = {\r
613 {\r
614 0x00,\r
615 L"Keyboard controller",\r
616 PCIBlankEntry\r
617 },\r
618 {\r
619 0x01,\r
620 L"Digitizer (pen)",\r
621 PCIBlankEntry\r
622 },\r
623 {\r
624 0x02,\r
625 L"Mouse controller",\r
626 PCIBlankEntry\r
627 },\r
628 {\r
629 0x03,\r
630 L"Scanner controller",\r
631 PCIBlankEntry\r
632 },\r
633 {\r
634 0x04,\r
635 L"Gameport controller",\r
636 PCIPIFClass_0904\r
637 },\r
638 {\r
639 0x80,\r
640 L"Other input controller",\r
641 PCIBlankEntry\r
642 },\r
643 {\r
644 0x00,\r
645 NULL,\r
646 /* null string ends the list */NULL\r
647 }\r
648};\r
649\r
650PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
651 {\r
652 0x00,\r
653 L"Generic docking station",\r
654 PCIBlankEntry\r
655 },\r
656 {\r
657 0x80,\r
658 L"Other type of docking station",\r
659 PCIBlankEntry\r
660 },\r
661 {\r
662 0x00,\r
663 NULL,\r
664 /* null string ends the list */NULL\r
665 }\r
666};\r
667\r
668PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
669 {\r
670 0x00,\r
671 L"386",\r
672 PCIBlankEntry\r
673 },\r
674 {\r
675 0x01,\r
676 L"486",\r
677 PCIBlankEntry\r
678 },\r
679 {\r
680 0x02,\r
681 L"Pentium",\r
682 PCIBlankEntry\r
683 },\r
684 {\r
685 0x10,\r
686 L"Alpha",\r
687 PCIBlankEntry\r
688 },\r
689 {\r
690 0x20,\r
691 L"PowerPC",\r
692 PCIBlankEntry\r
693 },\r
694 {\r
695 0x30,\r
696 L"MIPS",\r
697 PCIBlankEntry\r
698 },\r
699 {\r
700 0x40,\r
701 L"Co-processor",\r
702 PCIBlankEntry\r
703 },\r
704 {\r
705 0x80,\r
706 L"Other processor",\r
707 PCIBlankEntry\r
708 },\r
709 {\r
710 0x00,\r
711 NULL,\r
712 /* null string ends the list */NULL\r
713 }\r
714};\r
715\r
716PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
717 {\r
718 0x00,\r
f056e4c1
JC		 719 L"IEEE 1394",\r
720 PCIPIFClass_0c00\r
5d73d92f 721 },\r
722 {\r
723 0x01,\r
724 L"ACCESS.bus",\r
725 PCIBlankEntry\r
726 },\r
727 {\r
728 0x02,\r
729 L"SSA",\r
730 PCIBlankEntry\r
731 },\r
732 {\r
733 0x03,\r
734 L"USB",\r
f056e4c1 735 PCIPIFClass_0c03\r
5d73d92f 736 },\r
737 {\r
738 0x04,\r
739 L"Fibre Channel",\r
740 PCIBlankEntry\r
741 },\r
742 {\r
743 0x05,\r
744 L"System Management Bus",\r
745 PCIBlankEntry\r
746 },\r
f056e4c1
JC		 747 {\r
748 0x06,\r
749 L"InfiniBand",\r
750 PCIBlankEntry\r
751 },\r
752 {\r
753 0x07,\r
754 L"IPMI",\r
755 PCIPIFClass_0c07\r
756 },\r
757 {\r
758 0x08,\r
759 L"SERCOS Interface Standard (IEC 61491)",\r
760 PCIBlankEntry\r
761 },\r
762 {\r
763 0x09,\r
764 L"CANbus",\r
765 PCIBlankEntry\r
766 },\r
5d73d92f 767 {\r
768 0x80,\r
769 L"Other bus type",\r
770 PCIBlankEntry\r
771 },\r
772 {\r
773 0x00,\r
774 NULL,\r
775 /* null string ends the list */NULL\r
776 }\r
777};\r
778\r
779PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
780 {\r
781 0x00,\r
782 L"iRDA compatible controller",\r
783 PCIBlankEntry\r
784 },\r
785 {\r
786 0x01,\r
f056e4c1
JC		 787 L"",\r
788 PCIPIFClass_0d01\r
5d73d92f 789 },\r
790 {\r
791 0x10,\r
792 L"RF controller",\r
793 PCIBlankEntry\r
794 },\r
f056e4c1
JC		 795 {\r
796 0x11,\r
797 L"Bluetooth",\r
798 PCIBlankEntry\r
799 },\r
800 {\r
801 0x12,\r
802 L"Broadband",\r
803 PCIBlankEntry\r
804 },\r
805 {\r
806 0x20,\r
59577231 807 L"Ethernet (802.11a - 5 GHz)",\r
f056e4c1
JC		 808 PCIBlankEntry\r
809 },\r
810 {\r
811 0x21,\r
59577231 812 L"Ethernet (802.11b - 2.4 GHz)",\r
f056e4c1
JC		 813 PCIBlankEntry\r
814 },\r
5d73d92f 815 {\r
816 0x80,\r
817 L"Other type of wireless controller",\r
818 PCIBlankEntry\r
819 },\r
820 {\r
821 0x00,\r
822 NULL,\r
823 /* null string ends the list */NULL\r
824 }\r
825};\r
826\r
827PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
828 {\r
829 0x00,\r
830 L"I2O Architecture",\r
831 PCIPIFClass_0e00\r
832 },\r
833 {\r
834 0x00,\r
835 NULL,\r
836 /* null string ends the list */NULL\r
837 }\r
838};\r
839\r
840PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
841 {\r
f056e4c1 842 0x01,\r
5d73d92f 843 L"TV",\r
844 PCIBlankEntry\r
845 },\r
846 {\r
f056e4c1 847 0x02,\r
5d73d92f 848 L"Audio",\r
849 PCIBlankEntry\r
850 },\r
851 {\r
f056e4c1 852 0x03,\r
5d73d92f 853 L"Voice",\r
854 PCIBlankEntry\r
855 },\r
856 {\r
f056e4c1 857 0x04,\r
5d73d92f 858 L"Data",\r
859 PCIBlankEntry\r
860 },\r
f056e4c1
JC		 861 {\r
862 0x80,\r
863 L"Other satellite communication controller",\r
864 PCIBlankEntry\r
865 },\r
5d73d92f 866 {\r
867 0x00,\r
868 NULL,\r
869 /* null string ends the list */NULL\r
870 }\r
871};\r
872\r
873PCI_CLASS_ENTRY PCISubClass_10[] = {\r
874 {\r
875 0x00,\r
876 L"Network & computing Encrypt/Decrypt",\r
877 PCIBlankEntry\r
878 },\r
879 {\r
880 0x01,\r
881 L"Entertainment Encrypt/Decrypt",\r
882 PCIBlankEntry\r
883 },\r
884 {\r
885 0x80,\r
886 L"Other Encrypt/Decrypt",\r
887 PCIBlankEntry\r
888 },\r
889 {\r
890 0x00,\r
891 NULL,\r
892 /* null string ends the list */NULL\r
893 }\r
894};\r
895\r
896PCI_CLASS_ENTRY PCISubClass_11[] = {\r
897 {\r
898 0x00,\r
899 L"DPIO modules",\r
900 PCIBlankEntry\r
901 },\r
f056e4c1
JC		 902 {\r
903 0x01,\r
904 L"Performance Counters",\r
905 PCIBlankEntry\r
906 },\r
907 {\r
908 0x10,\r
909 L"Communications synchronization plus time and frequency test/measurement ",\r
910 PCIBlankEntry\r
911 },\r
912 {\r
913 0x20,\r
914 L"Management card",\r
915 PCIBlankEntry\r
916 },\r
5d73d92f 917 {\r
918 0x80,\r
919 L"Other DAQ & SP controllers",\r
920 PCIBlankEntry\r
921 },\r
922 {\r
923 0x00,\r
924 NULL,\r
925 /* null string ends the list */NULL\r
926 }\r
927};\r
928\r
f056e4c1
JC		 929PCI_CLASS_ENTRY PCISubClass_12[] = {\r
930 {\r
931 0x00,\r
932 L"Processing Accelerator",\r
933 PCIBlankEntry\r
934 },\r
935 {\r
936 0x00,\r
937 NULL,\r
938 /* null string ends the list */NULL\r
939 }\r
940};\r
941\r
942PCI_CLASS_ENTRY PCISubClass_13[] = {\r
943 {\r
944 0x00,\r
945 L"Non-Essential Instrumentation Function",\r
946 PCIBlankEntry\r
947 },\r
948 {\r
949 0x00,\r
950 NULL,\r
951 /* null string ends the list */NULL\r
952 }\r
953};\r
954\r
5d73d92f 955//\r
956// Programming Interface entries\r
957//\r
f056e4c1
JC		 958PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r
959 {\r
960 0x00,\r
961 L"SCSI controller",\r
962 PCIBlankEntry\r
963 },\r
964 {\r
965 0x11,\r
966 L"SCSI storage device SOP using PQI",\r
967 PCIBlankEntry\r
968 },\r
969 {\r
970 0x12,\r
971 L"SCSI controller SOP using PQI",\r
972 PCIBlankEntry\r
973 },\r
974 {\r
975 0x13,\r
976 L"SCSI storage device and controller SOP using PQI",\r
977 PCIBlankEntry\r
978 },\r
979 {\r
980 0x21,\r
981 L"SCSI storage device SOP using NVMe",\r
982 PCIBlankEntry\r
983 },\r
984 {\r
985 0x00,\r
986 NULL,\r
987 /* null string ends the list */NULL\r
988 }\r
989};\r
990\r
5d73d92f 991PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
992 {\r
993 0x00,\r
994 L"",\r
995 PCIBlankEntry\r
996 },\r
997 {\r
998 0x01,\r
999 L"OM-primary",\r
1000 PCIBlankEntry\r
1001 },\r
1002 {\r
1003 0x02,\r
1004 L"PI-primary",\r
1005 PCIBlankEntry\r
1006 },\r
1007 {\r
1008 0x03,\r
1009 L"OM/PI-primary",\r
1010 PCIBlankEntry\r
1011 },\r
1012 {\r
1013 0x04,\r
1014 L"OM-secondary",\r
1015 PCIBlankEntry\r
1016 },\r
1017 {\r
1018 0x05,\r
1019 L"OM-primary, OM-secondary",\r
1020 PCIBlankEntry\r
1021 },\r
1022 {\r
1023 0x06,\r
1024 L"PI-primary, OM-secondary",\r
1025 PCIBlankEntry\r
1026 },\r
1027 {\r
1028 0x07,\r
1029 L"OM/PI-primary, OM-secondary",\r
1030 PCIBlankEntry\r
1031 },\r
1032 {\r
1033 0x08,\r
1034 L"OM-secondary",\r
1035 PCIBlankEntry\r
1036 },\r
1037 {\r
1038 0x09,\r
1039 L"OM-primary, PI-secondary",\r
1040 PCIBlankEntry\r
1041 },\r
1042 {\r
1043 0x0a,\r
1044 L"PI-primary, PI-secondary",\r
1045 PCIBlankEntry\r
1046 },\r
1047 {\r
1048 0x0b,\r
1049 L"OM/PI-primary, PI-secondary",\r
1050 PCIBlankEntry\r
1051 },\r
1052 {\r
1053 0x0c,\r
1054 L"OM-secondary",\r
1055 PCIBlankEntry\r
1056 },\r
1057 {\r
1058 0x0d,\r
1059 L"OM-primary, OM/PI-secondary",\r
1060 PCIBlankEntry\r
1061 },\r
1062 {\r
1063 0x0e,\r
1064 L"PI-primary, OM/PI-secondary",\r
1065 PCIBlankEntry\r
1066 },\r
1067 {\r
1068 0x0f,\r
1069 L"OM/PI-primary, OM/PI-secondary",\r
1070 PCIBlankEntry\r
1071 },\r
1072 {\r
1073 0x80,\r
1074 L"Master",\r
1075 PCIBlankEntry\r
1076 },\r
1077 {\r
1078 0x81,\r
1079 L"Master, OM-primary",\r
1080 PCIBlankEntry\r
1081 },\r
1082 {\r
1083 0x82,\r
1084 L"Master, PI-primary",\r
1085 PCIBlankEntry\r
1086 },\r
1087 {\r
1088 0x83,\r
1089 L"Master, OM/PI-primary",\r
1090 PCIBlankEntry\r
1091 },\r
1092 {\r
1093 0x84,\r
1094 L"Master, OM-secondary",\r
1095 PCIBlankEntry\r
1096 },\r
1097 {\r
1098 0x85,\r
1099 L"Master, OM-primary, OM-secondary",\r
1100 PCIBlankEntry\r
1101 },\r
1102 {\r
1103 0x86,\r
1104 L"Master, PI-primary, OM-secondary",\r
1105 PCIBlankEntry\r
1106 },\r
1107 {\r
1108 0x87,\r
1109 L"Master, OM/PI-primary, OM-secondary",\r
1110 PCIBlankEntry\r
1111 },\r
1112 {\r
1113 0x88,\r
1114 L"Master, OM-secondary",\r
1115 PCIBlankEntry\r
1116 },\r
1117 {\r
1118 0x89,\r
1119 L"Master, OM-primary, PI-secondary",\r
1120 PCIBlankEntry\r
1121 },\r
1122 {\r
1123 0x8a,\r
1124 L"Master, PI-primary, PI-secondary",\r
1125 PCIBlankEntry\r
1126 },\r
1127 {\r
1128 0x8b,\r
1129 L"Master, OM/PI-primary, PI-secondary",\r
1130 PCIBlankEntry\r
1131 },\r
1132 {\r
1133 0x8c,\r
1134 L"Master, OM-secondary",\r
1135 PCIBlankEntry\r
1136 },\r
1137 {\r
1138 0x8d,\r
1139 L"Master, OM-primary, OM/PI-secondary",\r
1140 PCIBlankEntry\r
1141 },\r
1142 {\r
1143 0x8e,\r
1144 L"Master, PI-primary, OM/PI-secondary",\r
1145 PCIBlankEntry\r
1146 },\r
1147 {\r
1148 0x8f,\r
1149 L"Master, OM/PI-primary, OM/PI-secondary",\r
1150 PCIBlankEntry\r
1151 },\r
1152 {\r
1153 0x00,\r
1154 NULL,\r
1155 /* null string ends the list */NULL\r
1156 }\r
1157};\r
1158\r
f056e4c1
JC		 1159PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r
1160 {\r
1161 0x20,\r
1162 L"Single stepping",\r
1163 PCIBlankEntry\r
1164 },\r
1165 {\r
1166 0x30,\r
1167 L"Continuous operation",\r
1168 PCIBlankEntry\r
1169 },\r
1170 {\r
1171 0x00,\r
1172 NULL,\r
1173 /* null string ends the list */NULL\r
1174 }\r
1175};\r
1176\r
1177PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r
1178 {\r
1179 0x00,\r
1180 L"",\r
1181 PCIBlankEntry\r
1182 },\r
1183 {\r
1184 0x01,\r
1185 L"AHCI",\r
1186 PCIBlankEntry\r
1187 },\r
1188 {\r
1189 0x02,\r
1190 L"Serial Storage Bus",\r
1191 PCIBlankEntry\r
1192 },\r
1193 {\r
1194 0x00,\r
1195 NULL,\r
1196 /* null string ends the list */NULL\r
1197 }\r
1198};\r
1199\r
1200PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r
1201 {\r
1202 0x00,\r
1203 L"",\r
1204 PCIBlankEntry\r
1205 },\r
1206 {\r
1207 0x01,\r
1208 L"Obsolete",\r
1209 PCIBlankEntry\r
1210 },\r
1211 {\r
1212 0x00,\r
1213 NULL,\r
1214 /* null string ends the list */NULL\r
1215 }\r
1216};\r
1217\r
1218PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r
1219 {\r
1220 0x00,\r
1221 L"",\r
1222 PCIBlankEntry\r
1223 },\r
1224 {\r
1225 0x01,\r
1226 L"NVMHCI",\r
1227 PCIBlankEntry\r
1228 },\r
1229 {\r
1230 0x02,\r
1231 L"NVM Express",\r
1232 PCIBlankEntry\r
1233 },\r
1234 {\r
1235 0x00,\r
1236 NULL,\r
1237 /* null string ends the list */NULL\r
1238 }\r
1239};\r
1240\r
1241PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r
1242 {\r
1243 0x00,\r
1244 L"",\r
1245 PCIBlankEntry\r
1246 },\r
1247 {\r
1248 0x01,\r
1249 L"UFSHCI",\r
1250 PCIBlankEntry\r
1251 },\r
1252 {\r
1253 0x00,\r
1254 NULL,\r
1255 /* null string ends the list */NULL\r
1256 }\r
1257};\r
1258\r
5d73d92f 1259PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
1260 {\r
1261 0x00,\r
1262 L"VGA compatible",\r
1263 PCIBlankEntry\r
1264 },\r
1265 {\r
1266 0x01,\r
1267 L"8514 compatible",\r
1268 PCIBlankEntry\r
1269 },\r
1270 {\r
1271 0x00,\r
1272 NULL,\r
1273 /* null string ends the list */NULL\r
1274 }\r
1275};\r
1276\r
1277PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
1278 {\r
1279 0x00,\r
1280 L"",\r
1281 PCIBlankEntry\r
1282 },\r
1283 {\r
1284 0x01,\r
1285 L"Subtractive decode",\r
1286 PCIBlankEntry\r
1287 },\r
1288 {\r
1289 0x00,\r
1290 NULL,\r
1291 /* null string ends the list */NULL\r
1292 }\r
1293};\r
1294\r
f056e4c1
JC		 1295PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r
1296 {\r
1297 0x40,\r
1298 L"Primary PCI bus side facing the system host processor",\r
1299 PCIBlankEntry\r
1300 },\r
1301 {\r
1302 0x80,\r
1303 L"Secondary PCI bus side facing the system host processor",\r
1304 PCIBlankEntry\r
1305 },\r
1306 {\r
1307 0x00,\r
1308 NULL,\r
1309 /* null string ends the list */NULL\r
1310 }\r
1311};\r
1312\r
1313PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r
1314 {\r
1315 0x00,\r
1316 L"Custom",\r
1317 PCIBlankEntry\r
1318 },\r
1319 {\r
1320 0x01,\r
1321 L"ASI-SIG Defined Portal",\r
1322 PCIBlankEntry\r
1323 },\r
1324 {\r
1325 0x00,\r
1326 NULL,\r
1327 /* null string ends the list */NULL\r
1328 }\r
1329};\r
1330\r
5d73d92f 1331PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
1332 {\r
1333 0x00,\r
1334 L"Generic XT-compatible",\r
1335 PCIBlankEntry\r
1336 },\r
1337 {\r
1338 0x01,\r
1339 L"16450-compatible",\r
1340 PCIBlankEntry\r
1341 },\r
1342 {\r
1343 0x02,\r
1344 L"16550-compatible",\r
1345 PCIBlankEntry\r
1346 },\r
1347 {\r
1348 0x03,\r
1349 L"16650-compatible",\r
1350 PCIBlankEntry\r
1351 },\r
1352 {\r
1353 0x04,\r
1354 L"16750-compatible",\r
1355 PCIBlankEntry\r
1356 },\r
1357 {\r
1358 0x05,\r
1359 L"16850-compatible",\r
1360 PCIBlankEntry\r
1361 },\r
1362 {\r
1363 0x06,\r
1364 L"16950-compatible",\r
1365 PCIBlankEntry\r
1366 },\r
1367 {\r
1368 0x00,\r
1369 NULL,\r
1370 /* null string ends the list */NULL\r
1371 }\r
1372};\r
1373\r
1374PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1375 {\r
1376 0x00,\r
1377 L"",\r
1378 PCIBlankEntry\r
1379 },\r
1380 {\r
1381 0x01,\r
1382 L"Bi-directional",\r
1383 PCIBlankEntry\r
1384 },\r
1385 {\r
1386 0x02,\r
1387 L"ECP 1.X-compliant",\r
1388 PCIBlankEntry\r
1389 },\r
1390 {\r
1391 0x03,\r
1392 L"IEEE 1284",\r
1393 PCIBlankEntry\r
1394 },\r
1395 {\r
1396 0xfe,\r
1397 L"IEEE 1284 target (not a controller)",\r
1398 PCIBlankEntry\r
1399 },\r
1400 {\r
1401 0x00,\r
1402 NULL,\r
1403 /* null string ends the list */NULL\r
1404 }\r
1405};\r
1406\r
1407PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1408 {\r
1409 0x00,\r
1410 L"Generic",\r
1411 PCIBlankEntry\r
1412 },\r
1413 {\r
1414 0x01,\r
1415 L"Hayes-compatible 16450",\r
1416 PCIBlankEntry\r
1417 },\r
1418 {\r
1419 0x02,\r
1420 L"Hayes-compatible 16550",\r
1421 PCIBlankEntry\r
1422 },\r
1423 {\r
1424 0x03,\r
1425 L"Hayes-compatible 16650",\r
1426 PCIBlankEntry\r
1427 },\r
1428 {\r
1429 0x04,\r
1430 L"Hayes-compatible 16750",\r
1431 PCIBlankEntry\r
1432 },\r
1433 {\r
1434 0x00,\r
1435 NULL,\r
1436 /* null string ends the list */NULL\r
1437 }\r
1438};\r
1439\r
1440PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1441 {\r
1442 0x00,\r
1443 L"Generic 8259",\r
1444 PCIBlankEntry\r
1445 },\r
1446 {\r
1447 0x01,\r
1448 L"ISA",\r
1449 PCIBlankEntry\r
1450 },\r
1451 {\r
1452 0x02,\r
1453 L"EISA",\r
1454 PCIBlankEntry\r
1455 },\r
1456 {\r
1457 0x10,\r
1458 L"IO APIC",\r
1459 PCIBlankEntry\r
1460 },\r
1461 {\r
1462 0x20,\r
1463 L"IO(x) APIC interrupt controller",\r
1464 PCIBlankEntry\r
1465 },\r
1466 {\r
1467 0x00,\r
1468 NULL,\r
1469 /* null string ends the list */NULL\r
1470 }\r
1471};\r
1472\r
1473PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1474 {\r
1475 0x00,\r
1476 L"Generic 8237",\r
1477 PCIBlankEntry\r
1478 },\r
1479 {\r
1480 0x01,\r
1481 L"ISA",\r
1482 PCIBlankEntry\r
1483 },\r
1484 {\r
1485 0x02,\r
1486 L"EISA",\r
1487 PCIBlankEntry\r
1488 },\r
1489 {\r
1490 0x00,\r
1491 NULL,\r
1492 /* null string ends the list */NULL\r
1493 }\r
1494};\r
1495\r
1496PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1497 {\r
1498 0x00,\r
1499 L"Generic 8254",\r
1500 PCIBlankEntry\r
1501 },\r
1502 {\r
1503 0x01,\r
1504 L"ISA",\r
1505 PCIBlankEntry\r
1506 },\r
1507 {\r
1508 0x02,\r
1509 L"EISA",\r
1510 PCIBlankEntry\r
1511 },\r
1512 {\r
1513 0x00,\r
1514 NULL,\r
1515 /* null string ends the list */NULL\r
1516 }\r
1517};\r
1518\r
1519PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1520 {\r
1521 0x00,\r
1522 L"Generic",\r
1523 PCIBlankEntry\r
1524 },\r
1525 {\r
1526 0x01,\r
1527 L"ISA",\r
1528 PCIBlankEntry\r
1529 },\r
1530 {\r
1531 0x02,\r
1532 L"EISA",\r
1533 PCIBlankEntry\r
1534 },\r
1535 {\r
1536 0x00,\r
1537 NULL,\r
1538 /* null string ends the list */NULL\r
1539 }\r
1540};\r
1541\r
1542PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1543 {\r
1544 0x00,\r
1545 L"Generic",\r
1546 PCIBlankEntry\r
1547 },\r
1548 {\r
1549 0x10,\r
1550 L"",\r
1551 PCIBlankEntry\r
1552 },\r
1553 {\r
1554 0x00,\r
1555 NULL,\r
1556 /* null string ends the list */NULL\r
1557 }\r
1558};\r
1559\r
1560PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1561 {\r
1562 0x00,\r
f056e4c1
JC		 1563 L"",\r
1564 PCIBlankEntry\r
1565 },\r
1566 {\r
1567 0x10,\r
1568 L"Using 1394 OpenHCI spec",\r
1569 PCIBlankEntry\r
1570 },\r
1571 {\r
1572 0x00,\r
1573 NULL,\r
1574 /* null string ends the list */NULL\r
1575 }\r
1576};\r
1577\r
1578PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1579 {\r
1580 0x00,\r
1581 L"UHCI",\r
5d73d92f 1582 PCIBlankEntry\r
1583 },\r
1584 {\r
1585 0x10,\r
f056e4c1
JC		 1586 L"OHCI",\r
1587 PCIBlankEntry\r
1588 },\r
1589 {\r
1590 0x20,\r
1591 L"EHCI",\r
1592 PCIBlankEntry\r
1593 },\r
1594 {\r
1595 0x30,\r
1596 L"xHCI",\r
5d73d92f 1597 PCIBlankEntry\r
1598 },\r
1599 {\r
1600 0x80,\r
1601 L"No specific programming interface",\r
1602 PCIBlankEntry\r
1603 },\r
1604 {\r
1605 0xfe,\r
1606 L"(Not Host Controller)",\r
1607 PCIBlankEntry\r
1608 },\r
1609 {\r
1610 0x00,\r
1611 NULL,\r
1612 /* null string ends the list */NULL\r
1613 }\r
1614};\r
1615\r
f056e4c1 1616PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r
5d73d92f 1617 {\r
1618 0x00,\r
f056e4c1
JC		 1619 L"SMIC",\r
1620 PCIBlankEntry\r
1621 },\r
1622 {\r
1623 0x01,\r
1624 L"Keyboard Controller Style",\r
1625 PCIBlankEntry\r
1626 },\r
1627 {\r
1628 0x02,\r
1629 L"Block Transfer",\r
1630 PCIBlankEntry\r
1631 },\r
1632 {\r
1633 0x00,\r
1634 NULL,\r
1635 /* null string ends the list */NULL\r
1636 }\r
1637};\r
1638\r
1639PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r
1640 {\r
1641 0x00,\r
1642 L"Consumer IR controller",\r
5d73d92f 1643 PCIBlankEntry\r
1644 },\r
1645 {\r
1646 0x10,\r
f056e4c1 1647 L"UWB Radio controller",\r
5d73d92f 1648 PCIBlankEntry\r
1649 },\r
1650 {\r
1651 0x00,\r
1652 NULL,\r
1653 /* null string ends the list */NULL\r
1654 }\r
1655};\r
1656\r
1657PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1658 {\r
1659 0x00,\r
1660 L"Message FIFO at offset 40h",\r
1661 PCIBlankEntry\r
1662 },\r
1663 {\r
1664 0x01,\r
1665 L"",\r
1666 PCIBlankEntry\r
1667 },\r
1668 {\r
1669 0x00,\r
1670 NULL,\r
1671 /* null string ends the list */NULL\r
1672 }\r
1673};\r
1674\r
5d73d92f 1675\r
a1d4bfcc 1676/**\r
5d73d92f 1677 Generates printable Unicode strings that represent PCI device class,\r
1678 subclass and programmed I/F based on a value passed to the function.\r
1679\r
a1d4bfcc 1680 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
5d73d92f 1681 PCI device. The encodings are:\r
1682 bits 23:16 - Base Class Code\r
1683 bits 15:8 - Sub-Class Code\r
1684 bits 7:0 - Programming Interface\r
4ff7e37b 1685 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
5d73d92f 1686 printable class strings corresponding to ClassCode. The\r
1687 caller must not modify the strings that are pointed by\r
1688 the fields in ClassStrings.\r
5d73d92f 1689**/\r
a1d4bfcc 1690VOID\r
1691PciGetClassStrings (\r
1692 IN UINT32 ClassCode,\r
1693 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1694 )\r
5d73d92f 1695{\r
1696 INTN Index;\r
1697 UINT8 Code;\r
1698 PCI_CLASS_ENTRY *CurrentClass;\r
1699\r
1700 //\r
1701 // Assume no strings found\r
1702 //\r
1703 ClassStrings->BaseClass = L"UNDEFINED";\r
1704 ClassStrings->SubClass = L"UNDEFINED";\r
1705 ClassStrings->PIFClass = L"UNDEFINED";\r
1706\r
1707 CurrentClass = gClassStringList;\r
1708 Code = (UINT8) (ClassCode >> 16);\r
1709 Index = 0;\r
1710\r
1711 //\r
1712 // Go through all entries of the base class, until the entry with a matching\r
1713 // base class code is found. If reaches an entry with a null description\r
1714 // text, the last entry is met, which means no text for the base class was\r
1715 // found, so no more action is needed.\r
1716 //\r
1717 while (Code != CurrentClass[Index].Code) {\r
1718 if (NULL == CurrentClass[Index].DescText) {\r
1719 return ;\r
1720 }\r
1721\r
1722 Index++;\r
1723 }\r
1724 //\r
1725 // A base class was found. Assign description, and check if this class has\r
1726 // sub-class defined. If sub-class defined, no more action is needed,\r
1727 // otherwise, continue to find description for the sub-class code.\r
1728 //\r
1729 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1730 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1731 return ;\r
1732 }\r
1733 //\r
1734 // find Subclass entry\r
1735 //\r
1736 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1737 Code = (UINT8) (ClassCode >> 8);\r
1738 Index = 0;\r
1739\r
1740 //\r
1741 // Go through all entries of the sub-class, until the entry with a matching\r
1742 // sub-class code is found. If reaches an entry with a null description\r
1743 // text, the last entry is met, which means no text for the sub-class was\r
1744 // found, so no more action is needed.\r
1745 //\r
1746 while (Code != CurrentClass[Index].Code) {\r
1747 if (NULL == CurrentClass[Index].DescText) {\r
1748 return ;\r
1749 }\r
1750\r
1751 Index++;\r
1752 }\r
1753 //\r
1754 // A class was found for the sub-class code. Assign description, and check if\r
1755 // this sub-class has programming interface defined. If no, no more action is\r
1756 // needed, otherwise, continue to find description for the programming\r
1757 // interface.\r
1758 //\r
1759 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1760 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1761 return ;\r
1762 }\r
1763 //\r
1764 // Find programming interface entry\r
1765 //\r
1766 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1767 Code = (UINT8) ClassCode;\r
1768 Index = 0;\r
1769\r
1770 //\r
1771 // Go through all entries of the I/F entries, until the entry with a\r
1772 // matching I/F code is found. If reaches an entry with a null description\r
1773 // text, the last entry is met, which means no text was found, so no more\r
1774 // action is needed.\r
1775 //\r
1776 while (Code != CurrentClass[Index].Code) {\r
1777 if (NULL == CurrentClass[Index].DescText) {\r
1778 return ;\r
1779 }\r
1780\r
1781 Index++;\r
1782 }\r
1783 //\r
1784 // A class was found for the I/F code. Assign description, done!\r
1785 //\r
1786 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1787 return ;\r
1788}\r
1789\r
a1d4bfcc 1790/**\r
1791 Print strings that represent PCI device class, subclass and programmed I/F.\r
1792\r
1793 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
e8a57ade 1794 configuration space.\r
a1d4bfcc 1795 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1796**/\r
5d73d92f 1797VOID\r
1798PciPrintClassCode (\r
1799 IN UINT8 *ClassCodePtr,\r
1800 IN BOOLEAN IncludePIF\r
1801 )\r
5d73d92f 1802{\r
1803 UINT32 ClassCode;\r
1804 PCI_CLASS_STRINGS ClassStrings;\r
5d73d92f 1805\r
1806 ClassCode = 0;\r
e8a57ade
JC		 1807 ClassCode |= (UINT32)ClassCodePtr[0];\r
1808 ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r
1809 ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r
5d73d92f 1810\r
1811 //\r
1812 // Get name from class code\r
1813 //\r
1814 PciGetClassStrings (ClassCode, &ClassStrings);\r
1815\r
1816 if (IncludePIF) {\r
1817 //\r
c37e0f16 1818 // Print base class, sub class, and programming inferface name\r
5d73d92f 1819 //\r
c37e0f16 1820 ShellPrintEx (-1, -1, L"%s - %s - %s",\r
5d73d92f 1821 ClassStrings.BaseClass,\r
1822 ClassStrings.SubClass,\r
1823 ClassStrings.PIFClass\r
1824 );\r
1825\r
1826 } else {\r
1827 //\r
c37e0f16 1828 // Only print base class and sub class name\r
5d73d92f 1829 //\r
c37e0f16 1830 ShellPrintEx (-1, -1, L"%s - %s",\r
5d73d92f 1831 ClassStrings.BaseClass,\r
1832 ClassStrings.SubClass\r
c37e0f16 1833 );\r
5d73d92f 1834 }\r
1835}\r
1836\r
a1d4bfcc 1837/**\r
1838 This function finds out the protocol which is in charge of the given\r
1839 segment, and its bus range covers the current bus number. It lookes\r
1840 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1841 criteria is found.\r
1842\r
1843 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1844 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1845 @param[in] Segment Segment number of device we are dealing with.\r
1846 @param[in] Bus Bus number of device we are dealing with.\r
1847 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1848\r
1849 @retval EFI_SUCCESS The command completed successfully.\r
1850 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 1851\r
a1d4bfcc 1852**/\r
5d73d92f 1853EFI_STATUS\r
1854PciFindProtocolInterface (\r
1855 IN EFI_HANDLE *HandleBuf,\r
1856 IN UINTN HandleCount,\r
1857 IN UINT16 Segment,\r
1858 IN UINT16 Bus,\r
1859 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1860 );\r
1861\r
a1d4bfcc 1862/**\r
1863 This function gets the protocol interface from the given handle, and\r
1864 obtains its address space descriptors.\r
1865\r
1866 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1867 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1868 @param[out] Descriptors Points to the address space descriptors.\r
1869\r
1870 @retval EFI_SUCCESS The command completed successfully\r
1871**/\r
5d73d92f 1872EFI_STATUS\r
1873PciGetProtocolAndResource (\r
1874 IN EFI_HANDLE Handle,\r
1875 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1876 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1877 );\r
1878\r
a1d4bfcc 1879/**\r
1880 This function get the next bus range of given address space descriptors.\r
1881 It also moves the pointer backward a node, to get prepared to be called\r
1882 again.\r
1883\r
4ff7e37b
ED		 1884 @param[in, out] Descriptors Points to current position of a serial of address space\r
1885 descriptors.\r
1886 @param[out] MinBus The lower range of bus number.\r
1887 @param[out] MaxBus The upper range of bus number.\r
1888 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 1889\r
1890 @retval EFI_SUCCESS The command completed successfully.\r
1891**/\r
5d73d92f 1892EFI_STATUS\r
1893PciGetNextBusRange (\r
1894 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1895 OUT UINT16 *MinBus,\r
1896 OUT UINT16 *MaxBus,\r
1897 OUT BOOLEAN *IsEnd\r
1898 );\r
1899\r
a1d4bfcc 1900/**\r
1901 Explain the data in PCI configuration space. The part which is common for\r
1902 PCI device and bridge is interpreted in this function. It calls other\r
1903 functions to interpret data unique for device or bridge.\r
1904\r
1905 @param[in] ConfigSpace Data in PCI configuration space.\r
1906 @param[in] Address Address used to access configuration space of this PCI device.\r
1907 @param[in] IoDev Handle used to access configuration space of PCI device.\r
a1d4bfcc 1908**/\r
33cc487c
RN		 1909VOID\r
1910PciExplainPci (\r
5d73d92f 1911 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1912 IN UINT64 Address,\r
33cc487c 1913 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
5d73d92f 1914 );\r
1915\r
a1d4bfcc 1916/**\r
1917 Explain the device specific part of data in PCI configuration space.\r
1918\r
1919 @param[in] Device Data in PCI configuration space.\r
1920 @param[in] Address Address used to access configuration space of this PCI device.\r
1921 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1922\r
1923 @retval EFI_SUCCESS The command completed successfully.\r
1924**/\r
5d73d92f 1925EFI_STATUS\r
1926PciExplainDeviceData (\r
0c84a69f 1927 IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r
5d73d92f 1928 IN UINT64 Address,\r
1929 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1930 );\r
1931\r
a1d4bfcc 1932/**\r
1933 Explain the bridge specific part of data in PCI configuration space.\r
1934\r
1935 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1936 @param[in] Address Address used to access configuration space of this PCI device.\r
1937 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1938\r
1939 @retval EFI_SUCCESS The command completed successfully.\r
1940**/\r
5d73d92f 1941EFI_STATUS\r
1942PciExplainBridgeData (\r
0c84a69f 1943 IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r
a1d4bfcc 1944 IN UINT64 Address,\r
1945 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
5d73d92f 1946 );\r
1947\r
a1d4bfcc 1948/**\r
1949 Explain the Base Address Register(Bar) in PCI configuration space.\r
1950\r
4ff7e37b
ED		 1951 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1952 @param[in] Command Points to the register Command.\r
1953 @param[in] Address Address used to access configuration space of this PCI device.\r
1954 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1955 @param[in, out] Index The Index.\r
a1d4bfcc 1956\r
1957 @retval EFI_SUCCESS The command completed successfully.\r
1958**/\r
5d73d92f 1959EFI_STATUS\r
1960PciExplainBar (\r
1961 IN UINT32 *Bar,\r
1962 IN UINT16 *Command,\r
1963 IN UINT64 Address,\r
1964 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1965 IN OUT UINTN *Index\r
1966 );\r
1967\r
a1d4bfcc 1968/**\r
1969 Explain the cardbus specific part of data in PCI configuration space.\r
1970\r
1971 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1972 @param[in] Address Address used to access configuration space of this PCI device.\r
1973 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1974\r
1975 @retval EFI_SUCCESS The command completed successfully.\r
1976**/\r
5d73d92f 1977EFI_STATUS\r
1978PciExplainCardBusData (\r
0c84a69f 1979 IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r
5d73d92f 1980 IN UINT64 Address,\r
1981 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1982 );\r
1983\r
a1d4bfcc 1984/**\r
1985 Explain each meaningful bit of register Status. The definition of Status is\r
1986 slightly different depending on the PCI header type.\r
1987\r
1988 @param[in] Status Points to the content of register Status.\r
1989 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1990 status).\r
1991 @param[in] HeaderType Header type of this PCI device.\r
1992\r
1993 @retval EFI_SUCCESS The command completed successfully.\r
1994**/\r
5d73d92f 1995EFI_STATUS\r
1996PciExplainStatus (\r
1997 IN UINT16 *Status,\r
1998 IN BOOLEAN MainStatus,\r
1999 IN PCI_HEADER_TYPE HeaderType\r
2000 );\r
2001\r
a1d4bfcc 2002/**\r
2003 Explain each meaningful bit of register Command.\r
2004\r
2005 @param[in] Command Points to the content of register Command.\r
2006\r
2007 @retval EFI_SUCCESS The command completed successfully.\r
2008**/\r
5d73d92f 2009EFI_STATUS\r
2010PciExplainCommand (\r
2011 IN UINT16 *Command\r
2012 );\r
2013\r
a1d4bfcc 2014/**\r
2015 Explain each meaningful bit of register Bridge Control.\r
2016\r
2017 @param[in] BridgeControl Points to the content of register Bridge Control.\r
2018 @param[in] HeaderType The headertype.\r
2019\r
2020 @retval EFI_SUCCESS The command completed successfully.\r
2021**/\r
5d73d92f 2022EFI_STATUS\r
2023PciExplainBridgeControl (\r
2024 IN UINT16 *BridgeControl,\r
2025 IN PCI_HEADER_TYPE HeaderType\r
2026 );\r
2027\r
a1d4bfcc 2028/**\r
33cc487c 2029 Locate capability register block per capability ID.\r
a1d4bfcc 2030\r
33cc487c
RN		 2031 @param[in] ConfigSpace Data in PCI configuration space.\r
2032 @param[in] CapabilityId The capability ID.\r
a1d4bfcc 2033\r
33cc487c 2034 @return The offset of the register block per capability ID.\r
a1d4bfcc 2035**/\r
33cc487c
RN		 2036UINT8\r
2037LocatePciCapability (\r
2038 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2039 IN UINT8 CapabilityId\r
5d73d92f 2040 );\r
2041\r
a1d4bfcc 2042/**\r
2043 Display Pcie device structure.\r
2044\r
33cc487c
RN		 2045 @param[in] PciExpressCap PCI Express capability buffer.\r
2046 @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
2047 @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
a1d4bfcc 2048**/\r
33cc487c 2049VOID\r
5d73d92f 2050PciExplainPciExpress (\r
33cc487c
RN		 2051 IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
2052 IN UINT8 *ExtendedConfigSpace,\r
2053 IN CONST UINT16 ExtendedCapability\r
5d73d92f 2054 );\r
2055\r
a1d4bfcc 2056/**\r
2057 Print out information of the capability information.\r
2058\r
2059 @param[in] PciExpressCap The pointer to the structure about the device.\r
2060\r
2061 @retval EFI_SUCCESS The operation was successful.\r
2062**/\r
5d73d92f 2063EFI_STATUS\r
2064ExplainPcieCapReg (\r
0c84a69f 2065 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2066 );\r
2067\r
2068/**\r
2069 Print out information of the device capability information.\r
2070\r
2071 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2072\r
a1d4bfcc 2073 @retval EFI_SUCCESS The operation was successful.\r
2074**/\r
5d73d92f 2075EFI_STATUS\r
2076ExplainPcieDeviceCap (\r
0c84a69f 2077 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2078 );\r
2079\r
2080/**\r
2081 Print out information of the device control information.\r
5d73d92f 2082\r
a1d4bfcc 2083 @param[in] PciExpressCap The pointer to the structure about the device.\r
2084\r
2085 @retval EFI_SUCCESS The operation was successful.\r
2086**/\r
5d73d92f 2087EFI_STATUS\r
2088ExplainPcieDeviceControl (\r
0c84a69f 2089 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2090 );\r
5d73d92f 2091\r
a1d4bfcc 2092/**\r
2093 Print out information of the device status information.\r
2094\r
2095 @param[in] PciExpressCap The pointer to the structure about the device.\r
2096\r
2097 @retval EFI_SUCCESS The operation was successful.\r
2098**/\r
5d73d92f 2099EFI_STATUS\r
2100ExplainPcieDeviceStatus (\r
0c84a69f 2101 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2102 );\r
2103\r
2104/**\r
2105 Print out information of the device link information.\r
2106\r
2107 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2108\r
a1d4bfcc 2109 @retval EFI_SUCCESS The operation was successful.\r
2110**/\r
5d73d92f 2111EFI_STATUS\r
2112ExplainPcieLinkCap (\r
0c84a69f 2113 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2114 );\r
2115\r
2116/**\r
2117 Print out information of the device link control information.\r
5d73d92f 2118\r
a1d4bfcc 2119 @param[in] PciExpressCap The pointer to the structure about the device.\r
2120\r
2121 @retval EFI_SUCCESS The operation was successful.\r
2122**/\r
5d73d92f 2123EFI_STATUS\r
2124ExplainPcieLinkControl (\r
0c84a69f 2125 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2126 );\r
5d73d92f 2127\r
a1d4bfcc 2128/**\r
2129 Print out information of the device link status information.\r
2130\r
2131 @param[in] PciExpressCap The pointer to the structure about the device.\r
2132\r
2133 @retval EFI_SUCCESS The operation was successful.\r
2134**/\r
5d73d92f 2135EFI_STATUS\r
2136ExplainPcieLinkStatus (\r
0c84a69f 2137 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2138 );\r
2139\r
2140/**\r
2141 Print out information of the device slot information.\r
2142\r
2143 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2144\r
a1d4bfcc 2145 @retval EFI_SUCCESS The operation was successful.\r
2146**/\r
5d73d92f 2147EFI_STATUS\r
2148ExplainPcieSlotCap (\r
0c84a69f 2149 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2150 );\r
2151\r
2152/**\r
2153 Print out information of the device slot control information.\r
5d73d92f 2154\r
a1d4bfcc 2155 @param[in] PciExpressCap The pointer to the structure about the device.\r
2156\r
2157 @retval EFI_SUCCESS The operation was successful.\r
2158**/\r
5d73d92f 2159EFI_STATUS\r
2160ExplainPcieSlotControl (\r
0c84a69f 2161 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2162 );\r
5d73d92f 2163\r
a1d4bfcc 2164/**\r
2165 Print out information of the device slot status information.\r
2166\r
2167 @param[in] PciExpressCap The pointer to the structure about the device.\r
2168\r
2169 @retval EFI_SUCCESS The operation was successful.\r
2170**/\r
5d73d92f 2171EFI_STATUS\r
2172ExplainPcieSlotStatus (\r
0c84a69f 2173 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2174 );\r
2175\r
2176/**\r
2177 Print out information of the device root information.\r
2178\r
2179 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2180\r
a1d4bfcc 2181 @retval EFI_SUCCESS The operation was successful.\r
2182**/\r
5d73d92f 2183EFI_STATUS\r
2184ExplainPcieRootControl (\r
0c84a69f 2185 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2186 );\r
2187\r
2188/**\r
2189 Print out information of the device root capability information.\r
5d73d92f 2190\r
a1d4bfcc 2191 @param[in] PciExpressCap The pointer to the structure about the device.\r
2192\r
2193 @retval EFI_SUCCESS The operation was successful.\r
2194**/\r
5d73d92f 2195EFI_STATUS\r
2196ExplainPcieRootCap (\r
0c84a69f 2197 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2198 );\r
5d73d92f 2199\r
a1d4bfcc 2200/**\r
2201 Print out information of the device root status information.\r
2202\r
2203 @param[in] PciExpressCap The pointer to the structure about the device.\r
2204\r
2205 @retval EFI_SUCCESS The operation was successful.\r
2206**/\r
5d73d92f 2207EFI_STATUS\r
2208ExplainPcieRootStatus (\r
0c84a69f 2209 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 2210 );\r
5d73d92f 2211\r
0c84a69f 2212typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCI_CAPABILITY_PCIEXP *PciExpressCap);\r
5d73d92f 2213\r
2214typedef enum {\r
2215 FieldWidthUINT8,\r
2216 FieldWidthUINT16,\r
2217 FieldWidthUINT32\r
2218} PCIE_CAPREG_FIELD_WIDTH;\r
2219\r
2220typedef enum {\r
2221 PcieExplainTypeCommon,\r
2222 PcieExplainTypeDevice,\r
2223 PcieExplainTypeLink,\r
2224 PcieExplainTypeSlot,\r
2225 PcieExplainTypeRoot,\r
2226 PcieExplainTypeMax\r
2227} PCIE_EXPLAIN_TYPE;\r
2228\r
2229typedef struct\r
2230{\r
2231 UINT16 Token;\r
2232 UINTN Offset;\r
2233 PCIE_CAPREG_FIELD_WIDTH Width;\r
2234 PCIE_EXPLAIN_FUNCTION Func;\r
2235 PCIE_EXPLAIN_TYPE Type;\r
2236} PCIE_EXPLAIN_STRUCT;\r
2237\r
2238PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
2239 {\r
2240 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
2241 0x00,\r
2242 FieldWidthUINT8,\r
2243 NULL,\r
2244 PcieExplainTypeCommon\r
2245 },\r
2246 {\r
2247 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
2248 0x01,\r
2249 FieldWidthUINT8,\r
2250 NULL,\r
2251 PcieExplainTypeCommon\r
2252 },\r
2253 {\r
2254 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
2255 0x02,\r
2256 FieldWidthUINT16,\r
2257 ExplainPcieCapReg,\r
2258 PcieExplainTypeCommon\r
2259 },\r
2260 {\r
2261 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
2262 0x04,\r
2263 FieldWidthUINT32,\r
2264 ExplainPcieDeviceCap,\r
2265 PcieExplainTypeDevice\r
2266 },\r
2267 {\r
2268 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
2269 0x08,\r
2270 FieldWidthUINT16,\r
2271 ExplainPcieDeviceControl,\r
2272 PcieExplainTypeDevice\r
2273 },\r
2274 {\r
2275 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
2276 0x0a,\r
2277 FieldWidthUINT16,\r
2278 ExplainPcieDeviceStatus,\r
2279 PcieExplainTypeDevice\r
2280 },\r
2281 {\r
2282 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
2283 0x0c,\r
2284 FieldWidthUINT32,\r
2285 ExplainPcieLinkCap,\r
2286 PcieExplainTypeLink\r
2287 },\r
2288 {\r
2289 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
2290 0x10,\r
2291 FieldWidthUINT16,\r
2292 ExplainPcieLinkControl,\r
2293 PcieExplainTypeLink\r
2294 },\r
2295 {\r
2296 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
2297 0x12,\r
2298 FieldWidthUINT16,\r
2299 ExplainPcieLinkStatus,\r
2300 PcieExplainTypeLink\r
2301 },\r
2302 {\r
2303 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
2304 0x14,\r
2305 FieldWidthUINT32,\r
2306 ExplainPcieSlotCap,\r
2307 PcieExplainTypeSlot\r
2308 },\r
2309 {\r
2310 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
2311 0x18,\r
2312 FieldWidthUINT16,\r
2313 ExplainPcieSlotControl,\r
2314 PcieExplainTypeSlot\r
2315 },\r
2316 {\r
2317 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
2318 0x1a,\r
2319 FieldWidthUINT16,\r
2320 ExplainPcieSlotStatus,\r
2321 PcieExplainTypeSlot\r
2322 },\r
2323 {\r
2324 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
2325 0x1c,\r
2326 FieldWidthUINT16,\r
2327 ExplainPcieRootControl,\r
2328 PcieExplainTypeRoot\r
2329 },\r
2330 {\r
2331 STRING_TOKEN (STR_PCIEX_RSVDP),\r
2332 0x1e,\r
2333 FieldWidthUINT16,\r
2334 ExplainPcieRootCap,\r
2335 PcieExplainTypeRoot\r
2336 },\r
2337 {\r
2338 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
2339 0x20,\r
2340 FieldWidthUINT32,\r
2341 ExplainPcieRootStatus,\r
2342 PcieExplainTypeRoot\r
2343 },\r
2344 {\r
2345 0,\r
2346 0,\r
2347 (PCIE_CAPREG_FIELD_WIDTH)0,\r
2348 NULL,\r
2349 PcieExplainTypeMax\r
2350 }\r
2351};\r
2352\r
2353//\r
2354// Global Variables\r
2355//\r
2356PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
2357STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
2358 {L"-s", TypeValue},\r
2359 {L"-i", TypeFlag},\r
c831a2c3 2360 {L"-ec", TypeValue},\r
5d73d92f 2361 {NULL, TypeMax}\r
2362 };\r
2363\r
2364CHAR16 *DevicePortTypeTable[] = {\r
2365 L"PCI Express Endpoint",\r
2366 L"Legacy PCI Express Endpoint",\r
2367 L"Unknown Type",\r
2368 L"Unknonw Type",\r
2369 L"Root Port of PCI Express Root Complex",\r
2370 L"Upstream Port of PCI Express Switch",\r
2371 L"Downstream Port of PCI Express Switch",\r
2372 L"PCI Express to PCI/PCI-X Bridge",\r
2373 L"PCI/PCI-X to PCI Express Bridge",\r
2374 L"Root Complex Integrated Endpoint",\r
2375 L"Root Complex Event Collector"\r
2376};\r
2377\r
2378CHAR16 *L0sLatencyStrTable[] = {\r
2379 L"Less than 64ns",\r
2380 L"64ns to less than 128ns",\r
2381 L"128ns to less than 256ns",\r
2382 L"256ns to less than 512ns",\r
2383 L"512ns to less than 1us",\r
2384 L"1us to less than 2us",\r
2385 L"2us-4us",\r
2386 L"More than 4us"\r
2387};\r
2388\r
2389CHAR16 *L1LatencyStrTable[] = {\r
2390 L"Less than 1us",\r
2391 L"1us to less than 2us",\r
2392 L"2us to less than 4us",\r
2393 L"4us to less than 8us",\r
2394 L"8us to less than 16us",\r
2395 L"16us to less than 32us",\r
2396 L"32us-64us",\r
2397 L"More than 64us"\r
2398};\r
2399\r
2400CHAR16 *ASPMCtrlStrTable[] = {\r
2401 L"Disabled",\r
2402 L"L0s Entry Enabled",\r
2403 L"L1 Entry Enabled",\r
2404 L"L0s and L1 Entry Enabled"\r
2405};\r
2406\r
2407CHAR16 *SlotPwrLmtScaleTable[] = {\r
2408 L"1.0x",\r
2409 L"0.1x",\r
2410 L"0.01x",\r
2411 L"0.001x"\r
2412};\r
2413\r
2414CHAR16 *IndicatorTable[] = {\r
2415 L"Reserved",\r
2416 L"On",\r
2417 L"Blink",\r
2418 L"Off"\r
2419};\r
2420\r
2421\r
a1d4bfcc 2422/**\r
2423 Function for 'pci' command.\r
2424\r
2425 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2426 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2427**/\r
5d73d92f 2428SHELL_STATUS\r
2429EFIAPI\r
2430ShellCommandRunPci (\r
2431 IN EFI_HANDLE ImageHandle,\r
2432 IN EFI_SYSTEM_TABLE *SystemTable\r
2433 )\r
2434{\r
2435 UINT16 Segment;\r
2436 UINT16 Bus;\r
2437 UINT16 Device;\r
2438 UINT16 Func;\r
2439 UINT64 Address;\r
2440 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2441 EFI_STATUS Status;\r
0c84a69f 2442 PCI_DEVICE_INDEPENDENT_REGION PciHeader;\r
5d73d92f 2443 PCI_CONFIG_SPACE ConfigSpace;\r
2444 UINTN ScreenCount;\r
2445 UINTN TempColumn;\r
2446 UINTN ScreenSize;\r
2447 BOOLEAN ExplainData;\r
2448 UINTN Index;\r
2449 UINTN SizeOfHeader;\r
2450 BOOLEAN PrintTitle;\r
2451 UINTN HandleBufSize;\r
2452 EFI_HANDLE *HandleBuf;\r
2453 UINTN HandleCount;\r
2454 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2455 UINT16 MinBus;\r
2456 UINT16 MaxBus;\r
2457 BOOLEAN IsEnd;\r
2458 LIST_ENTRY *Package;\r
2459 CHAR16 *ProblemParam;\r
2460 SHELL_STATUS ShellStatus;\r
5d73d92f 2461 CONST CHAR16 *Temp;\r
6855763e 2462 UINT64 RetVal;\r
33cc487c
RN		 2463 UINT16 ExtendedCapability;\r
2464 UINT8 PcieCapabilityPtr;\r
2465 UINT8 *ExtendedConfigSpace;\r
2466 UINTN ExtendedConfigSize;\r
5d73d92f 2467\r
2468 ShellStatus = SHELL_SUCCESS;\r
2469 Status = EFI_SUCCESS;\r
2470 Address = 0;\r
5d73d92f 2471 IoDev = NULL;\r
2472 HandleBuf = NULL;\r
2473 Package = NULL;\r
2474\r
2475 //\r
2476 // initialize the shell lib (we must be in non-auto-init...)\r
2477 //\r
2478 Status = ShellInitialize();\r
2479 ASSERT_EFI_ERROR(Status);\r
2480\r
2481 Status = CommandInit();\r
2482 ASSERT_EFI_ERROR(Status);\r
2483\r
2484 //\r
2485 // parse the command line\r
2486 //\r
2487 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2488 if (EFI_ERROR(Status)) {\r
2489 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
4092a8f6 2490 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam); \r
5d73d92f 2491 FreePool(ProblemParam);\r
2492 ShellStatus = SHELL_INVALID_PARAMETER;\r
2493 } else {\r
2494 ASSERT(FALSE);\r
2495 }\r
2496 } else {\r
2497\r
3737ac2b 2498 if (ShellCommandLineGetCount(Package) == 2) {\r
4092a8f6 2499 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci"); \r
3737ac2b 2500 ShellStatus = SHELL_INVALID_PARAMETER;\r
2501 goto Done;\r
2502 }\r
5d73d92f 2503\r
3737ac2b 2504 if (ShellCommandLineGetCount(Package) > 4) {\r
4092a8f6 2505 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci"); \r
3737ac2b 2506 ShellStatus = SHELL_INVALID_PARAMETER;\r
2507 goto Done;\r
2508 }\r
c831a2c3
RN		 2509 if (ShellCommandLineGetFlag(Package, L"-ec") && ShellCommandLineGetValue(Package, L"-ec") == NULL) {\r
2510 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-ec"); \r
2511 ShellStatus = SHELL_INVALID_PARAMETER;\r
2512 goto Done;\r
2513 }\r
3737ac2b 2514 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
4092a8f6 2515 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s"); \r
3737ac2b 2516 ShellStatus = SHELL_INVALID_PARAMETER;\r
2517 goto Done;\r
2518 }\r
5d73d92f 2519 //\r
2520 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2521 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2522 // space for handles and call it again.\r
2523 //\r
2524 HandleBufSize = sizeof (EFI_HANDLE);\r
3737ac2b 2525 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
5d73d92f 2526 if (HandleBuf == NULL) {\r
4092a8f6 2527 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2528 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2529 goto Done;\r
2530 }\r
2531\r
2532 Status = gBS->LocateHandle (\r
2533 ByProtocol,\r
2534 &gEfiPciRootBridgeIoProtocolGuid,\r
2535 NULL,\r
2536 &HandleBufSize,\r
2537 HandleBuf\r
2538 );\r
2539\r
2540 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2541 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2542 if (HandleBuf == NULL) {\r
4092a8f6 2543 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2544 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2545 goto Done;\r
2546 }\r
2547\r
2548 Status = gBS->LocateHandle (\r
2549 ByProtocol,\r
2550 &gEfiPciRootBridgeIoProtocolGuid,\r
2551 NULL,\r
2552 &HandleBufSize,\r
2553 HandleBuf\r
2554 );\r
2555 }\r
2556\r
2557 if (EFI_ERROR (Status)) {\r
4092a8f6 2558 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2559 ShellStatus = SHELL_NOT_FOUND;\r
2560 goto Done;\r
2561 }\r
2562\r
2563 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2564 //\r
2565 // Argument Count == 1(no other argument): enumerate all pci functions\r
2566 //\r
3737ac2b 2567 if (ShellCommandLineGetCount(Package) == 1) {\r
5d73d92f 2568 gST->ConOut->QueryMode (\r
2569 gST->ConOut,\r
2570 gST->ConOut->Mode->Mode,\r
2571 &TempColumn,\r
2572 &ScreenSize\r
2573 );\r
2574\r
2575 ScreenCount = 0;\r
2576 ScreenSize -= 4;\r
2577 if ((ScreenSize & 1) == 1) {\r
2578 ScreenSize -= 1;\r
2579 }\r
2580\r
2581 PrintTitle = TRUE;\r
2582\r
2583 //\r
2584 // For each handle, which decides a segment and a bus number range,\r
2585 // enumerate all devices on it.\r
2586 //\r
2587 for (Index = 0; Index < HandleCount; Index++) {\r
2588 Status = PciGetProtocolAndResource (\r
2589 HandleBuf[Index],\r
2590 &IoDev,\r
2591 &Descriptors\r
2592 );\r
2593 if (EFI_ERROR (Status)) {\r
4092a8f6 2594 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2595 ShellStatus = SHELL_NOT_FOUND;\r
2596 goto Done;\r
2597 }\r
2598 //\r
2599 // No document say it's impossible for a RootBridgeIo protocol handle\r
2600 // to have more than one address space descriptors, so find out every\r
2601 // bus range and for each of them do device enumeration.\r
2602 //\r
2603 while (TRUE) {\r
2604 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2605\r
2606 if (EFI_ERROR (Status)) {\r
4092a8f6 2607 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2608 ShellStatus = SHELL_NOT_FOUND;\r
2609 goto Done;\r
2610 }\r
2611\r
2612 if (IsEnd) {\r
2613 break;\r
2614 }\r
2615\r
2616 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2617 //\r
2618 // For each devices, enumerate all functions it contains\r
2619 //\r
2620 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2621 //\r
2622 // For each function, read its configuration space and print summary\r
2623 //\r
2624 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2625 if (ShellGetExecutionBreakFlag ()) {\r
2626 ShellStatus = SHELL_ABORTED;\r
2627 goto Done;\r
2628 }\r
0c84a69f 2629 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
5d73d92f 2630 IoDev->Pci.Read (\r
2631 IoDev,\r
2632 EfiPciWidthUint16,\r
2633 Address,\r
2634 1,\r
2635 &PciHeader.VendorId\r
2636 );\r
2637\r
2638 //\r
2639 // If VendorId = 0xffff, there does not exist a device at this\r
2640 // location. For each device, if there is any function on it,\r
2641 // there must be 1 function at Function 0. So if Func = 0, there\r
2642 // will be no more functions in the same device, so we can break\r
2643 // loop to deal with the next device.\r
2644 //\r
2645 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2646 break;\r
2647 }\r
2648\r
2649 if (PciHeader.VendorId != 0xffff) {\r
2650\r
2651 if (PrintTitle) {\r
2652 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2653 PrintTitle = FALSE;\r
2654 }\r
2655\r
2656 IoDev->Pci.Read (\r
2657 IoDev,\r
2658 EfiPciWidthUint32,\r
2659 Address,\r
2660 sizeof (PciHeader) / sizeof (UINT32),\r
2661 &PciHeader\r
2662 );\r
2663\r
2664 ShellPrintHiiEx(\r
2665 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2666 IoDev->SegmentNumber,\r
2667 Bus,\r
2668 Device,\r
2669 Func\r
2670 );\r
2671\r
2672 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2673 ShellPrintHiiEx(\r
2674 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2675 PciHeader.VendorId,\r
2676 PciHeader.DeviceId,\r
2677 PciHeader.ClassCode[0]\r
2678 );\r
2679\r
2680 ScreenCount += 2;\r
2681 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2682 //\r
2683 // If ScreenSize == 0 we have the console redirected so don't\r
2684 // block updates\r
2685 //\r
2686 ScreenCount = 0;\r
2687 }\r
2688 //\r
2689 // If this is not a multi-function device, we can leave the loop\r
2690 // to deal with the next device.\r
2691 //\r
2692 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2693 break;\r
2694 }\r
2695 }\r
2696 }\r
2697 }\r
2698 }\r
2699 //\r
2700 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2701 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2702 // devices on all bus, we can leave loop.\r
2703 //\r
2704 if (Descriptors == NULL) {\r
2705 break;\r
2706 }\r
2707 }\r
2708 }\r
2709\r
2710 Status = EFI_SUCCESS;\r
2711 goto Done;\r
2712 }\r
2713\r
5d73d92f 2714 ExplainData = FALSE;\r
2715 Segment = 0;\r
2716 Bus = 0;\r
2717 Device = 0;\r
2718 Func = 0;\r
33cc487c 2719 ExtendedCapability = 0xFFFF;\r
5d73d92f 2720 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2721 ExplainData = TRUE;\r
2722 }\r
2723\r
2724 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2725 if (Temp != NULL) {\r
6855763e
CP		 2726 //\r
2727 // Input converted to hexadecimal number.\r
2728 //\r
2729 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2730 Segment = (UINT16) RetVal;\r
2731 } else {\r
4092a8f6 2732 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2733 ShellStatus = SHELL_INVALID_PARAMETER;\r
2734 goto Done;\r
2735 }\r
5d73d92f 2736 }\r
2737\r
2738 //\r
2739 // The first Argument(except "-i") is assumed to be Bus number, second\r
2740 // to be Device number, and third to be Func number.\r
2741 //\r
2742 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2743 if (Temp != NULL) {\r
6855763e
CP		 2744 //\r
2745 // Input converted to hexadecimal number.\r
2746 //\r
2747 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2748 Bus = (UINT16) RetVal;\r
2749 } else {\r
4092a8f6 2750 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2751 ShellStatus = SHELL_INVALID_PARAMETER;\r
2752 goto Done;\r
2753 }\r
2754\r
0c84a69f 2755 if (Bus > PCI_MAX_BUS) {\r
4092a8f6 2756 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
5d73d92f 2757 ShellStatus = SHELL_INVALID_PARAMETER;\r
2758 goto Done;\r
2759 }\r
2760 }\r
2761 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2762 if (Temp != NULL) {\r
6855763e
CP		 2763 //\r
2764 // Input converted to hexadecimal number.\r
2765 //\r
2766 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2767 Device = (UINT16) RetVal;\r
2768 } else {\r
4092a8f6 2769 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2770 ShellStatus = SHELL_INVALID_PARAMETER;\r
2771 goto Done;\r
2772 }\r
2773\r
0c84a69f 2774 if (Device > PCI_MAX_DEVICE){\r
4092a8f6 2775 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
5d73d92f 2776 ShellStatus = SHELL_INVALID_PARAMETER;\r
2777 goto Done;\r
2778 }\r
2779 }\r
2780\r
2781 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2782 if (Temp != NULL) {\r
6855763e
CP		 2783 //\r
2784 // Input converted to hexadecimal number.\r
2785 //\r
2786 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2787 Func = (UINT16) RetVal;\r
2788 } else {\r
4092a8f6 2789 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2790 ShellStatus = SHELL_INVALID_PARAMETER;\r
2791 goto Done;\r
2792 }\r
2793\r
0c84a69f 2794 if (Func > PCI_MAX_FUNC){\r
4092a8f6 2795 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
5d73d92f 2796 ShellStatus = SHELL_INVALID_PARAMETER;\r
2797 goto Done;\r
2798 }\r
2799 }\r
2800\r
31d7be01
RN		 2801 Temp = ShellCommandLineGetValue (Package, L"-ec");\r
2802 if (Temp != NULL) {\r
2803 //\r
2804 // Input converted to hexadecimal number.\r
2805 //\r
2806 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
33cc487c 2807 ExtendedCapability = (UINT16) RetVal;\r
31d7be01
RN		 2808 } else {\r
2809 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
2810 ShellStatus = SHELL_INVALID_PARAMETER;\r
2811 goto Done;\r
2812 }\r
2813 }\r
2814\r
5d73d92f 2815 //\r
2816 // Find the protocol interface who's in charge of current segment, and its\r
2817 // bus range covers the current bus\r
2818 //\r
2819 Status = PciFindProtocolInterface (\r
2820 HandleBuf,\r
2821 HandleCount,\r
2822 Segment,\r
2823 Bus,\r
2824 &IoDev\r
2825 );\r
2826\r
2827 if (EFI_ERROR (Status)) {\r
2828 ShellPrintHiiEx(\r
4092a8f6 2829 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci", \r
5d73d92f 2830 Segment,\r
2831 Bus\r
2832 );\r
2833 ShellStatus = SHELL_NOT_FOUND;\r
2834 goto Done;\r
2835 }\r
2836\r
0c84a69f 2837 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
5d73d92f 2838 Status = IoDev->Pci.Read (\r
2839 IoDev,\r
2840 EfiPciWidthUint8,\r
2841 Address,\r
2842 sizeof (ConfigSpace),\r
2843 &ConfigSpace\r
2844 );\r
2845\r
2846 if (EFI_ERROR (Status)) {\r
4092a8f6 2847 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2848 ShellStatus = SHELL_ACCESS_DENIED;\r
2849 goto Done;\r
2850 }\r
2851\r
2852 mConfigSpace = &ConfigSpace;\r
2853 ShellPrintHiiEx(\r
2854 -1,\r
2855 -1,\r
2856 NULL,\r
2857 STRING_TOKEN (STR_PCI_INFO),\r
2858 gShellDebug1HiiHandle,\r
2859 Segment,\r
2860 Bus,\r
2861 Device,\r
2862 Func,\r
2863 Segment,\r
2864 Bus,\r
2865 Device,\r
2866 Func\r
2867 );\r
2868\r
2869 //\r
2870 // Dump standard header of configuration space\r
2871 //\r
2872 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2873\r
a1d4bfcc 2874 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
5d73d92f 2875 ShellPrintEx(-1,-1, L"\r\n");\r
2876\r
2877 //\r
2878 // Dump device dependent Part of configuration space\r
2879 //\r
a1d4bfcc 2880 DumpHex (\r
5d73d92f 2881 2,\r
2882 SizeOfHeader,\r
2883 sizeof (ConfigSpace) - SizeOfHeader,\r
2884 ConfigSpace.Data\r
2885 );\r
2886\r
33cc487c 2887 ExtendedConfigSpace = NULL;\r
f1894fa2 2888 ExtendedConfigSize = 0;\r
33cc487c
RN		 2889 PcieCapabilityPtr = LocatePciCapability (&ConfigSpace, EFI_PCI_CAPABILITY_ID_PCIEXP);\r
2890 if (PcieCapabilityPtr != 0) {\r
2891 ExtendedConfigSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
2892 ExtendedConfigSpace = AllocatePool (ExtendedConfigSize);\r
2893 if (ExtendedConfigSpace != NULL) {\r
2894 Status = IoDev->Pci.Read (\r
2895 IoDev,\r
2896 EfiPciWidthUint32,\r
2897 EFI_PCI_ADDRESS (Bus, Device, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET),\r
2898 ExtendedConfigSize / sizeof (UINT32),\r
2899 ExtendedConfigSpace\r
2900 );\r
2901 if (EFI_ERROR (Status)) {\r
2902 SHELL_FREE_NON_NULL (ExtendedConfigSpace);\r
2903 }\r
2904 }\r
2905 }\r
2906\r
2907 if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
2908 //\r
2909 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
2910 //\r
2911 ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
2912\r
2913 DumpHex (\r
2914 2,\r
2915 EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
2916 ExtendedConfigSize,\r
2917 ExtendedConfigSpace\r
2918 );\r
2919 }\r
2920\r
5d73d92f 2921 //\r
2922 // If "-i" appears in command line, interpret data in configuration space\r
2923 //\r
2924 if (ExplainData) {\r
33cc487c 2925 PciExplainPci (&ConfigSpace, Address, IoDev);\r
f1894fa2 2926 if ((ExtendedConfigSpace != NULL) && !ShellGetExecutionBreakFlag ()) {\r
33cc487c
RN		 2927 PciExplainPciExpress (\r
2928 (PCI_CAPABILITY_PCIEXP *) ((UINT8 *) &ConfigSpace + PcieCapabilityPtr),\r
2929 ExtendedConfigSpace,\r
2930 ExtendedCapability\r
2931 );\r
2932 }\r
5d73d92f 2933 }\r
2934 }\r
2935Done:\r
2936 if (HandleBuf != NULL) {\r
2937 FreePool (HandleBuf);\r
2938 }\r
2939 if (Package != NULL) {\r
2940 ShellCommandLineFreeVarList (Package);\r
2941 }\r
2942 mConfigSpace = NULL;\r
2943 return ShellStatus;\r
2944}\r
2945\r
a1d4bfcc 2946/**\r
5d73d92f 2947 This function finds out the protocol which is in charge of the given\r
2948 segment, and its bus range covers the current bus number. It lookes\r
2949 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2950 criteria is found.\r
2951\r
a1d4bfcc 2952 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2953 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2954 @param[in] Segment Segment number of device we are dealing with.\r
2955 @param[in] Bus Bus number of device we are dealing with.\r
2956 @param[out] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2957\r
a1d4bfcc 2958 @retval EFI_SUCCESS The command completed successfully.\r
2959 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 2960\r
2961**/\r
a1d4bfcc 2962EFI_STATUS\r
2963PciFindProtocolInterface (\r
2964 IN EFI_HANDLE *HandleBuf,\r
2965 IN UINTN HandleCount,\r
2966 IN UINT16 Segment,\r
2967 IN UINT16 Bus,\r
2968 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2969 )\r
5d73d92f 2970{\r
2971 UINTN Index;\r
2972 EFI_STATUS Status;\r
5d73d92f 2973 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2974 UINT16 MinBus;\r
2975 UINT16 MaxBus;\r
2976 BOOLEAN IsEnd;\r
2977\r
5d73d92f 2978 //\r
2979 // Go through all handles, until the one meets the criteria is found\r
2980 //\r
2981 for (Index = 0; Index < HandleCount; Index++) {\r
2982 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2983 if (EFI_ERROR (Status)) {\r
2984 return Status;\r
2985 }\r
2986 //\r
2987 // When Descriptors == NULL, the Configuration() is not implemented,\r
2988 // so we only check the Segment number\r
2989 //\r
2990 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2991 return EFI_SUCCESS;\r
2992 }\r
2993\r
2994 if ((*IoDev)->SegmentNumber != Segment) {\r
2995 continue;\r
2996 }\r
2997\r
2998 while (TRUE) {\r
2999 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
3000 if (EFI_ERROR (Status)) {\r
3001 return Status;\r
3002 }\r
3003\r
3004 if (IsEnd) {\r
3005 break;\r
3006 }\r
3007\r
3008 if (MinBus <= Bus && MaxBus >= Bus) {\r
2c46dd23 3009 return EFI_SUCCESS;\r
5d73d92f 3010 }\r
3011 }\r
3012 }\r
3013\r
2c46dd23 3014 return EFI_NOT_FOUND;\r
5d73d92f 3015}\r
3016\r
a1d4bfcc 3017/**\r
3018 This function gets the protocol interface from the given handle, and\r
3019 obtains its address space descriptors.\r
3020\r
3021 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
3022 @param[out] IoDev Handle used to access configuration space of PCI device.\r
3023 @param[out] Descriptors Points to the address space descriptors.\r
3024\r
3025 @retval EFI_SUCCESS The command completed successfully\r
3026**/\r
5d73d92f 3027EFI_STATUS\r
3028PciGetProtocolAndResource (\r
3029 IN EFI_HANDLE Handle,\r
3030 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
3031 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
3032 )\r
5d73d92f 3033{\r
3034 EFI_STATUS Status;\r
3035\r
3036 //\r
3037 // Get inferface from protocol\r
3038 //\r
3039 Status = gBS->HandleProtocol (\r
3040 Handle,\r
3041 &gEfiPciRootBridgeIoProtocolGuid,\r
3042 (VOID**)IoDev\r
3043 );\r
3044\r
3045 if (EFI_ERROR (Status)) {\r
3046 return Status;\r
3047 }\r
3048 //\r
3049 // Call Configuration() to get address space descriptors\r
3050 //\r
3051 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
3052 if (Status == EFI_UNSUPPORTED) {\r
3053 *Descriptors = NULL;\r
3054 return EFI_SUCCESS;\r
3055\r
3056 } else {\r
3057 return Status;\r
3058 }\r
3059}\r
3060\r
a1d4bfcc 3061/**\r
3062 This function get the next bus range of given address space descriptors.\r
3063 It also moves the pointer backward a node, to get prepared to be called\r
3064 again.\r
3065\r
4ff7e37b
ED		 3066 @param[in, out] Descriptors Points to current position of a serial of address space\r
3067 descriptors.\r
3068 @param[out] MinBus The lower range of bus number.\r
3069 @param[out] MaxBus The upper range of bus number.\r
3070 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 3071\r
3072 @retval EFI_SUCCESS The command completed successfully.\r
3073**/\r
5d73d92f 3074EFI_STATUS\r
3075PciGetNextBusRange (\r
3076 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
3077 OUT UINT16 *MinBus,\r
3078 OUT UINT16 *MaxBus,\r
3079 OUT BOOLEAN *IsEnd\r
3080 )\r
5d73d92f 3081{\r
3082 *IsEnd = FALSE;\r
3083\r
3084 //\r
3085 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
3086 // range is 0~PCI_MAX_BUS\r
3087 //\r
3088 if ((*Descriptors) == NULL) {\r
3089 *MinBus = 0;\r
3090 *MaxBus = PCI_MAX_BUS;\r
3091 return EFI_SUCCESS;\r
3092 }\r
3093 //\r
3094 // *Descriptors points to one or more address space descriptors, which\r
3095 // ends with a end tagged descriptor. Examine each of the descriptors,\r
3096 // if a bus typed one is found and its bus range covers bus, this handle\r
3097 // is the handle we are looking for.\r
3098 //\r
5d73d92f 3099\r
3100 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
3101 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
3102 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
3103 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
3104 (*Descriptors)++;\r
3737ac2b 3105 return (EFI_SUCCESS);\r
5d73d92f 3106 }\r
3107\r
3108 (*Descriptors)++;\r
3109 }\r
3110\r
3737ac2b 3111 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
3112 *IsEnd = TRUE;\r
3113 }\r
3114\r
5d73d92f 3115 return EFI_SUCCESS;\r
3116}\r
3117\r
a1d4bfcc 3118/**\r
5d73d92f 3119 Explain the data in PCI configuration space. The part which is common for\r
3120 PCI device and bridge is interpreted in this function. It calls other\r
3121 functions to interpret data unique for device or bridge.\r
3122\r
a1d4bfcc 3123 @param[in] ConfigSpace Data in PCI configuration space.\r
3124 @param[in] Address Address used to access configuration space of this PCI device.\r
3125 @param[in] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 3126**/\r
33cc487c
RN		 3127VOID\r
3128PciExplainPci (\r
a1d4bfcc 3129 IN PCI_CONFIG_SPACE *ConfigSpace,\r
3130 IN UINT64 Address,\r
33cc487c 3131 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
a1d4bfcc 3132 )\r
5d73d92f 3133{\r
0c84a69f
RN		 3134 PCI_DEVICE_INDEPENDENT_REGION *Common;\r
3135 PCI_HEADER_TYPE HeaderType;\r
5d73d92f 3136\r
3137 Common = &(ConfigSpace->Common);\r
3138\r
c37e0f16 3139 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 3140\r
3141 //\r
3142 // Print Vendor Id and Device Id\r
3143 //\r
3144 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
3145 INDEX_OF (&(Common->VendorId)),\r
3146 Common->VendorId,\r
3147 INDEX_OF (&(Common->DeviceId)),\r
3148 Common->DeviceId\r
3149 );\r
3150\r
3151 //\r
3152 // Print register Command\r
3153 //\r
3154 PciExplainCommand (&(Common->Command));\r
3155\r
3156 //\r
3157 // Print register Status\r
3158 //\r
3159 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
3160\r
3161 //\r
3162 // Print register Revision ID\r
3163 //\r
14b5e3fd 3164 ShellPrintEx(-1, -1, L"\r\n");\r
5d73d92f 3165 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
0c84a69f
RN		 3166 INDEX_OF (&(Common->RevisionID)),\r
3167 Common->RevisionID\r
5d73d92f 3168 );\r
3169\r
3170 //\r
3171 // Print register BIST\r
3172 //\r
0c84a69f
RN		 3173 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r
3174 if ((Common->BIST & BIT7) != 0) {\r
3175 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r
5d73d92f 3176 } else {\r
3177 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
3178 }\r
3179 //\r
3180 // Print register Cache Line Size\r
3181 //\r
3182 ShellPrintHiiEx(-1, -1, NULL,\r
3183 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
3184 gShellDebug1HiiHandle,\r
3185 INDEX_OF (&(Common->CacheLineSize)),\r
3186 Common->CacheLineSize\r
3187 );\r
3188\r
3189 //\r
3190 // Print register Latency Timer\r
3191 //\r
3192 ShellPrintHiiEx(-1, -1, NULL,\r
3193 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
3194 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3195 INDEX_OF (&(Common->LatencyTimer)),\r
3196 Common->LatencyTimer\r
5d73d92f 3197 );\r
3198\r
3199 //\r
3200 // Print register Header Type\r
3201 //\r
3202 ShellPrintHiiEx(-1, -1, NULL,\r
3203 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
3204 gShellDebug1HiiHandle,\r
3205 INDEX_OF (&(Common->HeaderType)),\r
3206 Common->HeaderType\r
3207 );\r
3208\r
0c84a69f 3209 if ((Common->HeaderType & BIT7) != 0) {\r
5d73d92f 3210 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
3211\r
3212 } else {\r
3213 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
3214 }\r
3215\r
3216 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
3217 switch (HeaderType) {\r
3218 case PciDevice:\r
3219 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
3220 break;\r
3221\r
3222 case PciP2pBridge:\r
3223 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
3224 break;\r
3225\r
3226 case PciCardBusBridge:\r
3227 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
3228 break;\r
3229\r
3230 default:\r
3231 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
3232 HeaderType = PciUndefined;\r
3233 }\r
3234\r
3235 //\r
3236 // Print register Class Code\r
3237 //\r
3238 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
3239 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
c37e0f16 3240 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 3241}\r
3242\r
a1d4bfcc 3243/**\r
3244 Explain the device specific part of data in PCI configuration space.\r
3245\r
3246 @param[in] Device Data in PCI configuration space.\r
3247 @param[in] Address Address used to access configuration space of this PCI device.\r
3248 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3249\r
3250 @retval EFI_SUCCESS The command completed successfully.\r
3251**/\r
5d73d92f 3252EFI_STATUS\r
3253PciExplainDeviceData (\r
0c84a69f 3254 IN PCI_DEVICE_HEADER_TYPE_REGION *Device,\r
5d73d92f 3255 IN UINT64 Address,\r
3256 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3257 )\r
5d73d92f 3258{\r
3259 UINTN Index;\r
3260 BOOLEAN BarExist;\r
3261 EFI_STATUS Status;\r
3262 UINTN BarCount;\r
3263\r
3264 //\r
3265 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
3266 // exist. If these no Bar for this function, print "none", otherwise\r
3267 // list detail information about this Bar.\r
3268 //\r
3269 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
3270\r
3271 BarExist = FALSE;\r
3272 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
3273 for (Index = 0; Index < BarCount; Index++) {\r
3274 if (Device->Bar[Index] == 0) {\r
3275 continue;\r
3276 }\r
3277\r
3278 if (!BarExist) {\r
3279 BarExist = TRUE;\r
3280 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 3281 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 3282 }\r
3283\r
3284 Status = PciExplainBar (\r
3285 &(Device->Bar[Index]),\r
3286 &(mConfigSpace->Common.Command),\r
3287 Address,\r
3288 IoDev,\r
3289 &Index\r
3290 );\r
3291\r
3292 if (EFI_ERROR (Status)) {\r
3293 break;\r
3294 }\r
3295 }\r
3296\r
3297 if (!BarExist) {\r
3298 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3299\r
3300 } else {\r
c37e0f16 3301 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 3302 }\r
3303\r
3304 //\r
3305 // Print register Expansion ROM Base Address\r
3306 //\r
0c84a69f
RN		 3307 if ((Device->ExpansionRomBar & BIT0) == 0) {\r
3308 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ExpansionRomBar)));\r
5d73d92f 3309\r
3310 } else {\r
3311 ShellPrintHiiEx(-1, -1, NULL,\r
3312 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
3313 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3314 INDEX_OF (&(Device->ExpansionRomBar)),\r
3315 Device->ExpansionRomBar\r
5d73d92f 3316 );\r
3317 }\r
3318 //\r
3319 // Print register Cardbus CIS ptr\r
3320 //\r
3321 ShellPrintHiiEx(-1, -1, NULL,\r
3322 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
3323 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3324 INDEX_OF (&(Device->CISPtr)),\r
3325 Device->CISPtr\r
5d73d92f 3326 );\r
3327\r
3328 //\r
3329 // Print register Sub-vendor ID and subsystem ID\r
3330 //\r
3331 ShellPrintHiiEx(-1, -1, NULL,\r
3332 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
3333 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3334 INDEX_OF (&(Device->SubsystemVendorID)),\r
3335 Device->SubsystemVendorID\r
5d73d92f 3336 );\r
3337\r
3338 ShellPrintHiiEx(-1, -1, NULL,\r
3339 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
3340 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3341 INDEX_OF (&(Device->SubsystemID)),\r
3342 Device->SubsystemID\r
5d73d92f 3343 );\r
3344\r
3345 //\r
3346 // Print register Capabilities Ptr\r
3347 //\r
3348 ShellPrintHiiEx(-1, -1, NULL,\r
3349 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
3350 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3351 INDEX_OF (&(Device->CapabilityPtr)),\r
3352 Device->CapabilityPtr\r
5d73d92f 3353 );\r
3354\r
3355 //\r
3356 // Print register Interrupt Line and interrupt pin\r
3357 //\r
3358 ShellPrintHiiEx(-1, -1, NULL,\r
3359 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
3360 gShellDebug1HiiHandle,\r
3361 INDEX_OF (&(Device->InterruptLine)),\r
3362 Device->InterruptLine\r
3363 );\r
3364\r
3365 ShellPrintHiiEx(-1, -1, NULL,\r
3366 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3367 gShellDebug1HiiHandle,\r
3368 INDEX_OF (&(Device->InterruptPin)),\r
3369 Device->InterruptPin\r
3370 );\r
3371\r
3372 //\r
3373 // Print register Min_Gnt and Max_Lat\r
3374 //\r
3375 ShellPrintHiiEx(-1, -1, NULL,\r
3376 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
3377 gShellDebug1HiiHandle,\r
3378 INDEX_OF (&(Device->MinGnt)),\r
3379 Device->MinGnt\r
3380 );\r
3381\r
3382 ShellPrintHiiEx(-1, -1, NULL,\r
3383 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
3384 gShellDebug1HiiHandle,\r
3385 INDEX_OF (&(Device->MaxLat)),\r
3386 Device->MaxLat\r
3387 );\r
3388\r
3389 return EFI_SUCCESS;\r
3390}\r
3391\r
a1d4bfcc 3392/**\r
3393 Explain the bridge specific part of data in PCI configuration space.\r
3394\r
3395 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
3396 @param[in] Address Address used to access configuration space of this PCI device.\r
3397 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3398\r
3399 @retval EFI_SUCCESS The command completed successfully.\r
3400**/\r
5d73d92f 3401EFI_STATUS\r
3402PciExplainBridgeData (\r
0c84a69f 3403 IN PCI_BRIDGE_CONTROL_REGISTER *Bridge,\r
5d73d92f 3404 IN UINT64 Address,\r
3405 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3406 )\r
5d73d92f 3407{\r
3408 UINTN Index;\r
3409 BOOLEAN BarExist;\r
3410 UINTN BarCount;\r
3411 UINT32 IoAddress32;\r
3412 EFI_STATUS Status;\r
3413\r
3414 //\r
3415 // Print Base Address Registers. When Bar = 0, this Bar does not\r
3416 // exist. If these no Bar for this function, print "none", otherwise\r
3417 // list detail information about this Bar.\r
3418 //\r
3419 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
3420\r
3421 BarExist = FALSE;\r
3422 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
3423\r
3424 for (Index = 0; Index < BarCount; Index++) {\r
3425 if (Bridge->Bar[Index] == 0) {\r
3426 continue;\r
3427 }\r
3428\r
3429 if (!BarExist) {\r
3430 BarExist = TRUE;\r
3431 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 3432 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 3433 }\r
3434\r
3435 Status = PciExplainBar (\r
3436 &(Bridge->Bar[Index]),\r
3437 &(mConfigSpace->Common.Command),\r
3438 Address,\r
3439 IoDev,\r
3440 &Index\r
3441 );\r
3442\r
3443 if (EFI_ERROR (Status)) {\r
3444 break;\r
3445 }\r
3446 }\r
3447\r
3448 if (!BarExist) {\r
3449 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3450 } else {\r
c37e0f16 3451 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 3452 }\r
3453\r
3454 //\r
3455 // Expansion register ROM Base Address\r
3456 //\r
0c84a69f
RN		 3457 if ((Bridge->ExpansionRomBAR & BIT0) == 0) {\r
3458 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ExpansionRomBAR)));\r
5d73d92f 3459\r
3460 } else {\r
3461 ShellPrintHiiEx(-1, -1, NULL,\r
3462 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3463 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3464 INDEX_OF (&(Bridge->ExpansionRomBAR)),\r
3465 Bridge->ExpansionRomBAR\r
5d73d92f 3466 );\r
3467 }\r
3468 //\r
3469 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3470 //\r
3471 ShellPrintHiiEx(-1, -1, NULL,\r
3472 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3473 gShellDebug1HiiHandle,\r
3474 INDEX_OF (&(Bridge->PrimaryBus)),\r
3475 INDEX_OF (&(Bridge->SecondaryBus)),\r
3476 INDEX_OF (&(Bridge->SubordinateBus))\r
3477 );\r
3478\r
c37e0f16 3479 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3480\r
3481 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3482 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3483 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3484\r
3485 //\r
3486 // Print register Secondary Latency Timer\r
3487 //\r
3488 ShellPrintHiiEx(-1, -1, NULL,\r
3489 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3490 gShellDebug1HiiHandle,\r
3491 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3492 Bridge->SecondaryLatencyTimer\r
3493 );\r
3494\r
3495 //\r
3496 // Print register Secondary Status\r
3497 //\r
3498 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3499\r
3500 //\r
3501 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3502 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3503 // base and limit address are listed.\r
3504 //\r
3505 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 3506 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3507\r
3508 //\r
3509 // IO Base & Limit\r
3510 //\r
0c84a69f 3511 IoAddress32 = (Bridge->IoBaseUpper16 << 16 | Bridge->IoBase << 8);\r
5d73d92f 3512 IoAddress32 &= 0xfffff000;\r
3513 ShellPrintHiiEx(-1, -1, NULL,\r
3514 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3515 gShellDebug1HiiHandle,\r
3516 INDEX_OF (&(Bridge->IoBase)),\r
3517 IoAddress32\r
3518 );\r
3519\r
0c84a69f 3520 IoAddress32 = (Bridge->IoLimitUpper16 << 16 | Bridge->IoLimit << 8);\r
5d73d92f 3521 IoAddress32 |= 0x00000fff;\r
3522 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3523\r
3524 //\r
3525 // Memory Base & Limit\r
3526 //\r
3527 ShellPrintHiiEx(-1, -1, NULL,\r
3528 STRING_TOKEN (STR_PCI2_MEMORY),\r
3529 gShellDebug1HiiHandle,\r
3530 INDEX_OF (&(Bridge->MemoryBase)),\r
3531 (Bridge->MemoryBase << 16) & 0xfff00000\r
3532 );\r
3533\r
3534 ShellPrintHiiEx(-1, -1, NULL,\r
3535 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3536 gShellDebug1HiiHandle,\r
3537 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3538 );\r
3539\r
3540 //\r
3541 // Pre-fetch-able Memory Base & Limit\r
3542 //\r
3543 ShellPrintHiiEx(-1, -1, NULL,\r
3544 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3545 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3546 INDEX_OF (&(Bridge->PrefetchableMemoryBase)),\r
3547 Bridge->PrefetchableBaseUpper32,\r
3548 (Bridge->PrefetchableMemoryBase << 16) & 0xfff00000\r
5d73d92f 3549 );\r
3550\r
3551 ShellPrintHiiEx(-1, -1, NULL,\r
3552 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3553 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3554 Bridge->PrefetchableLimitUpper32,\r
3555 (Bridge->PrefetchableMemoryLimit << 16) | 0x000fffff\r
5d73d92f 3556 );\r
3557\r
3558 //\r
3559 // Print register Capabilities Pointer\r
3560 //\r
3561 ShellPrintHiiEx(-1, -1, NULL,\r
3562 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3563 gShellDebug1HiiHandle,\r
0c84a69f
RN		 3564 INDEX_OF (&(Bridge->CapabilityPtr)),\r
3565 Bridge->CapabilityPtr\r
5d73d92f 3566 );\r
3567\r
3568 //\r
3569 // Print register Bridge Control\r
3570 //\r
3571 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3572\r
3573 //\r
3574 // Print register Interrupt Line & PIN\r
3575 //\r
3576 ShellPrintHiiEx(-1, -1, NULL,\r
3577 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3578 gShellDebug1HiiHandle,\r
3579 INDEX_OF (&(Bridge->InterruptLine)),\r
3580 Bridge->InterruptLine\r
3581 );\r
3582\r
3583 ShellPrintHiiEx(-1, -1, NULL,\r
3584 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3585 gShellDebug1HiiHandle,\r
3586 INDEX_OF (&(Bridge->InterruptPin)),\r
3587 Bridge->InterruptPin\r
3588 );\r
3589\r
3590 return EFI_SUCCESS;\r
3591}\r
3592\r
a1d4bfcc 3593/**\r
3594 Explain the Base Address Register(Bar) in PCI configuration space.\r
3595\r
4ff7e37b
ED		 3596 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3597 @param[in] Command Points to the register Command.\r
3598 @param[in] Address Address used to access configuration space of this PCI device.\r
3599 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3600 @param[in, out] Index The Index.\r
a1d4bfcc 3601\r
3602 @retval EFI_SUCCESS The command completed successfully.\r
3603**/\r
5d73d92f 3604EFI_STATUS\r
3605PciExplainBar (\r
3606 IN UINT32 *Bar,\r
3607 IN UINT16 *Command,\r
3608 IN UINT64 Address,\r
3609 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3610 IN OUT UINTN *Index\r
3611 )\r
5d73d92f 3612{\r
3613 UINT16 OldCommand;\r
3614 UINT16 NewCommand;\r
3615 UINT64 Bar64;\r
3616 UINT32 OldBar32;\r
3617 UINT32 NewBar32;\r
3618 UINT64 OldBar64;\r
3619 UINT64 NewBar64;\r
3620 BOOLEAN IsMem;\r
3621 BOOLEAN IsBar32;\r
3622 UINT64 RegAddress;\r
3623\r
3624 IsBar32 = TRUE;\r
3625 Bar64 = 0;\r
3626 NewBar32 = 0;\r
3627 NewBar64 = 0;\r
3628\r
3629 //\r
3630 // According the bar type, list detail about this bar, for example: 32 or\r
3631 // 64 bits; pre-fetchable or not.\r
3632 //\r
0c84a69f 3633 if ((*Bar & BIT0) == 0) {\r
5d73d92f 3634 //\r
3635 // This bar is of memory type\r
3636 //\r
3637 IsMem = TRUE;\r
3638\r
0c84a69f 3639 if ((*Bar & BIT1) == 0 && (*Bar & BIT2) == 0) {\r
5d73d92f 3640 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3641 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3642 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3643\r
0c84a69f 3644 } else if ((*Bar & BIT1) == 0 && (*Bar & BIT2) != 0) {\r
5d73d92f 3645 Bar64 = 0x0;\r
3646 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
46cb4043 3647 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
2b578de0 3648 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
5d73d92f 3649 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3650 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3651 IsBar32 = FALSE;\r
3652 *Index += 1;\r
3653\r
3654 } else {\r
3655 //\r
3656 // Reserved\r
3657 //\r
3658 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3659 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3660 }\r
3661\r
0c84a69f 3662 if ((*Bar & BIT3) == 0) {\r
5d73d92f 3663 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3664\r
3665 } else {\r
3666 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3667 }\r
3668\r
3669 } else {\r
3670 //\r
3671 // This bar is of io type\r
3672 //\r
3673 IsMem = FALSE;\r
3674 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
c37e0f16 3675 ShellPrintEx (-1, -1, L"I/O ");\r
5d73d92f 3676 }\r
3677\r
3678 //\r
3679 // Get BAR length(or the amount of resource this bar demands for). To get\r
3680 // Bar length, first we should temporarily disable I/O and memory access\r
3681 // of this function(by set bits in the register Command), then write all\r
3682 // "1"s to this bar. The bar value read back is the amount of resource\r
3683 // this bar demands for.\r
3684 //\r
3685 //\r
3686 // Disable io & mem access\r
3687 //\r
3688 OldCommand = *Command;\r
3689 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3690 RegAddress = Address | INDEX_OF (Command);\r
3691 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3692\r
3693 RegAddress = Address | INDEX_OF (Bar);\r
3694\r
3695 //\r
3696 // Read after write the BAR to get the size\r
3697 //\r
3698 if (IsBar32) {\r
3699 OldBar32 = *Bar;\r
3700 NewBar32 = 0xffffffff;\r
3701\r
3702 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3703 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3704 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3705\r
3706 if (IsMem) {\r
3707 NewBar32 = NewBar32 & 0xfffffff0;\r
3708 NewBar32 = (~NewBar32) + 1;\r
3709\r
3710 } else {\r
3711 NewBar32 = NewBar32 & 0xfffffffc;\r
3712 NewBar32 = (~NewBar32) + 1;\r
3713 NewBar32 = NewBar32 & 0x0000ffff;\r
3714 }\r
3715 } else {\r
3716\r
3717 OldBar64 = 0x0;\r
3718 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
2b578de0 3719 NewBar64 = 0xffffffffffffffffULL;\r
5d73d92f 3720\r
3721 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3722 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3723 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3724\r
3725 if (IsMem) {\r
2b578de0 3726 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
5d73d92f 3727 NewBar64 = (~NewBar64) + 1;\r
3728\r
3729 } else {\r
2b578de0 3730 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
5d73d92f 3731 NewBar64 = (~NewBar64) + 1;\r
3732 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3733 }\r
3734 }\r
3735 //\r
3736 // Enable io & mem access\r
3737 //\r
3738 RegAddress = Address | INDEX_OF (Command);\r
3739 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3740\r
3741 if (IsMem) {\r
3742 if (IsBar32) {\r
3743 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3744 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3745\r
3746 } else {\r
46cb4043 3747 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
5d73d92f 3748 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
c37e0f16 3749 ShellPrintEx (-1, -1, L" ");\r
5d73d92f 3750 ShellPrintHiiEx(-1, -1, NULL,\r
3751 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3752 gShellDebug1HiiHandle,\r
46cb4043 3753 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
5d73d92f 3754 );\r
2b578de0 3755 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
5d73d92f 3756\r
3757 }\r
3758 } else {\r
3759 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3760 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3761 }\r
3762\r
3763 return EFI_SUCCESS;\r
3764}\r
3765\r
a1d4bfcc 3766/**\r
3767 Explain the cardbus specific part of data in PCI configuration space.\r
3768\r
3769 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3770 @param[in] Address Address used to access configuration space of this PCI device.\r
3771 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3772\r
3773 @retval EFI_SUCCESS The command completed successfully.\r
3774**/\r
5d73d92f 3775EFI_STATUS\r
3776PciExplainCardBusData (\r
0c84a69f 3777 IN PCI_CARDBUS_CONTROL_REGISTER *CardBus,\r
5d73d92f 3778 IN UINT64 Address,\r
3779 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3780 )\r
5d73d92f 3781{\r
3782 BOOLEAN Io32Bit;\r
3783 PCI_CARDBUS_DATA *CardBusData;\r
3784\r
3785 ShellPrintHiiEx(-1, -1, NULL,\r
3786 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3787 gShellDebug1HiiHandle,\r
3788 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3789 CardBus->CardBusSocketReg\r
3790 );\r
3791\r
3792 //\r
3793 // Print Secondary Status\r
3794 //\r
3795 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3796\r
3797 //\r
3798 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3799 // Subordinate bus number\r
3800 //\r
3801 ShellPrintHiiEx(-1, -1, NULL,\r
3802 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3803 gShellDebug1HiiHandle,\r
3804 INDEX_OF (&(CardBus->PciBusNumber)),\r
3805 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3806 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3807 );\r
3808\r
c37e0f16 3809 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3810\r
3811 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3812 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3813 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3814\r
3815 //\r
3816 // Print CardBus Latency Timer\r
3817 //\r
3818 ShellPrintHiiEx(-1, -1, NULL,\r
3819 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3820 gShellDebug1HiiHandle,\r
3821 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3822 CardBus->CardBusLatencyTimer\r
3823 );\r
3824\r
3825 //\r
3826 // Print Memory/Io ranges this cardbus bridge forwards\r
3827 //\r
3828 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 3829 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3830\r
3831 ShellPrintHiiEx(-1, -1, NULL,\r
3832 STRING_TOKEN (STR_PCI2_MEM_3),\r
3833 gShellDebug1HiiHandle,\r
3834 INDEX_OF (&(CardBus->MemoryBase0)),\r
0c84a69f 3835 CardBus->BridgeControl & BIT8 ? L" Prefetchable" : L"Non-Prefetchable",\r
5d73d92f 3836 CardBus->MemoryBase0 & 0xfffff000,\r
3837 CardBus->MemoryLimit0 | 0x00000fff\r
3838 );\r
3839\r
3840 ShellPrintHiiEx(-1, -1, NULL,\r
3841 STRING_TOKEN (STR_PCI2_MEM_3),\r
3842 gShellDebug1HiiHandle,\r
3843 INDEX_OF (&(CardBus->MemoryBase1)),\r
0c84a69f 3844 CardBus->BridgeControl & BIT9 ? L" Prefetchable" : L"Non-Prefetchable",\r
5d73d92f 3845 CardBus->MemoryBase1 & 0xfffff000,\r
3846 CardBus->MemoryLimit1 | 0x00000fff\r
3847 );\r
3848\r
0c84a69f 3849 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & BIT0);\r
5d73d92f 3850 ShellPrintHiiEx(-1, -1, NULL,\r
3851 STRING_TOKEN (STR_PCI2_IO_2),\r
3852 gShellDebug1HiiHandle,\r
3853 INDEX_OF (&(CardBus->IoBase0)),\r
3854 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3855 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3856 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3857 );\r
3858\r
0c84a69f 3859 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & BIT0);\r
5d73d92f 3860 ShellPrintHiiEx(-1, -1, NULL,\r
3861 STRING_TOKEN (STR_PCI2_IO_2),\r
3862 gShellDebug1HiiHandle,\r
3863 INDEX_OF (&(CardBus->IoBase1)),\r
3864 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3865 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3866 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3867 );\r
3868\r
3869 //\r
3870 // Print register Interrupt Line & PIN\r
3871 //\r
3872 ShellPrintHiiEx(-1, -1, NULL,\r
3873 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3874 gShellDebug1HiiHandle,\r
3875 INDEX_OF (&(CardBus->InterruptLine)),\r
3876 CardBus->InterruptLine,\r
3877 INDEX_OF (&(CardBus->InterruptPin)),\r
3878 CardBus->InterruptPin\r
3879 );\r
3880\r
3881 //\r
3882 // Print register Bridge Control\r
3883 //\r
3884 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3885\r
3886 //\r
3887 // Print some registers in data region of PCI configuration space for cardbus\r
3888 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3889 // Address.\r
3890 //\r
0c84a69f 3891 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_CONTROL_REGISTER));\r
5d73d92f 3892\r
3893 ShellPrintHiiEx(-1, -1, NULL,\r
3894 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3895 gShellDebug1HiiHandle,\r
3896 INDEX_OF (&(CardBusData->SubVendorId)),\r
3897 CardBusData->SubVendorId,\r
3898 INDEX_OF (&(CardBusData->SubSystemId)),\r
3899 CardBusData->SubSystemId\r
3900 );\r
3901\r
3902 ShellPrintHiiEx(-1, -1, NULL,\r
3903 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3904 gShellDebug1HiiHandle,\r
3905 INDEX_OF (&(CardBusData->LegacyBase)),\r
3906 CardBusData->LegacyBase\r
3907 );\r
3908\r
3909 return EFI_SUCCESS;\r
3910}\r
3911\r
a1d4bfcc 3912/**\r
3913 Explain each meaningful bit of register Status. The definition of Status is\r
3914 slightly different depending on the PCI header type.\r
3915\r
3916 @param[in] Status Points to the content of register Status.\r
3917 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3918 status).\r
3919 @param[in] HeaderType Header type of this PCI device.\r
3920\r
3921 @retval EFI_SUCCESS The command completed successfully.\r
3922**/\r
5d73d92f 3923EFI_STATUS\r
3924PciExplainStatus (\r
3925 IN UINT16 *Status,\r
3926 IN BOOLEAN MainStatus,\r
3927 IN PCI_HEADER_TYPE HeaderType\r
3928 )\r
5d73d92f 3929{\r
3930 if (MainStatus) {\r
3931 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3932\r
3933 } else {\r
3934 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3935 }\r
3936\r
0c84a69f 3937 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & BIT4) != 0);\r
5d73d92f 3938\r
3939 //\r
3940 // Bit 5 is meaningless for CardBus Bridge\r
3941 //\r
3942 if (HeaderType == PciCardBusBridge) {\r
0c84a69f 3943 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r
5d73d92f 3944\r
3945 } else {\r
0c84a69f 3946 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & BIT5) != 0);\r
5d73d92f 3947 }\r
3948\r
0c84a69f 3949 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & BIT7) != 0);\r
5d73d92f 3950\r
0c84a69f 3951 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & BIT8) != 0);\r
5d73d92f 3952 //\r
3953 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3954 //\r
3955 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
0c84a69f 3956 if ((*Status & BIT9) == 0 && (*Status & BIT10) == 0) {\r
5d73d92f 3957 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3958\r
0c84a69f 3959 } else if ((*Status & BIT9) != 0 && (*Status & BIT10) == 0) {\r
5d73d92f 3960 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3961\r
0c84a69f 3962 } else if ((*Status & BIT9) == 0 && (*Status & BIT10) != 0) {\r
5d73d92f 3963 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3964\r
3965 } else {\r
3966 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3967 }\r
3968\r
3969 ShellPrintHiiEx(-1, -1, NULL,\r
3970 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3971 gShellDebug1HiiHandle,\r
0c84a69f 3972 (*Status & BIT11) != 0\r
5d73d92f 3973 );\r
3974\r
3975 ShellPrintHiiEx(-1, -1, NULL,\r
3976 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3977 gShellDebug1HiiHandle,\r
0c84a69f 3978 (*Status & BIT12) != 0\r
5d73d92f 3979 );\r
3980\r
3981 ShellPrintHiiEx(-1, -1, NULL,\r
3982 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3983 gShellDebug1HiiHandle,\r
0c84a69f 3984 (*Status & BIT13) != 0\r
5d73d92f 3985 );\r
3986\r
3987 if (MainStatus) {\r
3988 ShellPrintHiiEx(-1, -1, NULL,\r
3989 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3990 gShellDebug1HiiHandle,\r
0c84a69f 3991 (*Status & BIT14) != 0\r
5d73d92f 3992 );\r
3993\r
3994 } else {\r
3995 ShellPrintHiiEx(-1, -1, NULL,\r
3996 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3997 gShellDebug1HiiHandle,\r
0c84a69f 3998 (*Status & BIT14) != 0\r
5d73d92f 3999 );\r
4000 }\r
4001\r
4002 ShellPrintHiiEx(-1, -1, NULL,\r
4003 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
4004 gShellDebug1HiiHandle,\r
0c84a69f 4005 (*Status & BIT15) != 0\r
5d73d92f 4006 );\r
4007\r
4008 return EFI_SUCCESS;\r
4009}\r
4010\r
a1d4bfcc 4011/**\r
5d73d92f 4012 Explain each meaningful bit of register Command.\r
4013\r
a1d4bfcc 4014 @param[in] Command Points to the content of register Command.\r
5d73d92f 4015\r
a1d4bfcc 4016 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 4017**/\r
a1d4bfcc 4018EFI_STATUS\r
4019PciExplainCommand (\r
4020 IN UINT16 *Command\r
4021 )\r
5d73d92f 4022{\r
4023 //\r
4024 // Print the binary value of register Command\r
4025 //\r
4026 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
4027\r
4028 //\r
4029 // Explain register Command bit by bit\r
4030 //\r
4031 ShellPrintHiiEx(-1, -1, NULL,\r
4032 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
4033 gShellDebug1HiiHandle,\r
0c84a69f 4034 (*Command & BIT0) != 0\r
5d73d92f 4035 );\r
4036\r
4037 ShellPrintHiiEx(-1, -1, NULL,\r
4038 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
4039 gShellDebug1HiiHandle,\r
0c84a69f 4040 (*Command & BIT1) != 0\r
5d73d92f 4041 );\r
4042\r
4043 ShellPrintHiiEx(-1, -1, NULL,\r
4044 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
4045 gShellDebug1HiiHandle,\r
0c84a69f 4046 (*Command & BIT2) != 0\r
5d73d92f 4047 );\r
4048\r
4049 ShellPrintHiiEx(-1, -1, NULL,\r
4050 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
4051 gShellDebug1HiiHandle,\r
0c84a69f 4052 (*Command & BIT3) != 0\r
5d73d92f 4053 );\r
4054\r
4055 ShellPrintHiiEx(-1, -1, NULL,\r
4056 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
4057 gShellDebug1HiiHandle,\r
0c84a69f 4058 (*Command & BIT4) != 0\r
5d73d92f 4059 );\r
4060\r
4061 ShellPrintHiiEx(-1, -1, NULL,\r
4062 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
4063 gShellDebug1HiiHandle,\r
0c84a69f 4064 (*Command & BIT5) != 0\r
5d73d92f 4065 );\r
4066\r
4067 ShellPrintHiiEx(-1, -1, NULL,\r
4068 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
4069 gShellDebug1HiiHandle,\r
0c84a69f 4070 (*Command & BIT6) != 0\r
5d73d92f 4071 );\r
4072\r
4073 ShellPrintHiiEx(-1, -1, NULL,\r
4074 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
4075 gShellDebug1HiiHandle,\r
0c84a69f 4076 (*Command & BIT7) != 0\r
5d73d92f 4077 );\r
4078\r
4079 ShellPrintHiiEx(-1, -1, NULL,\r
4080 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
4081 gShellDebug1HiiHandle,\r
0c84a69f 4082 (*Command & BIT8) != 0\r
5d73d92f 4083 );\r
4084\r
4085 ShellPrintHiiEx(-1, -1, NULL,\r
4086 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
4087 gShellDebug1HiiHandle,\r
0c84a69f 4088 (*Command & BIT9) != 0\r
5d73d92f 4089 );\r
4090\r
4091 return EFI_SUCCESS;\r
4092}\r
4093\r
a1d4bfcc 4094/**\r
4095 Explain each meaningful bit of register Bridge Control.\r
4096\r
4097 @param[in] BridgeControl Points to the content of register Bridge Control.\r
4098 @param[in] HeaderType The headertype.\r
4099\r
4100 @retval EFI_SUCCESS The command completed successfully.\r
4101**/\r
5d73d92f 4102EFI_STATUS\r
4103PciExplainBridgeControl (\r
4104 IN UINT16 *BridgeControl,\r
4105 IN PCI_HEADER_TYPE HeaderType\r
4106 )\r
5d73d92f 4107{\r
4108 ShellPrintHiiEx(-1, -1, NULL,\r
4109 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
4110 gShellDebug1HiiHandle,\r
4111 INDEX_OF (BridgeControl),\r
4112 *BridgeControl\r
4113 );\r
4114\r
4115 ShellPrintHiiEx(-1, -1, NULL,\r
4116 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
4117 gShellDebug1HiiHandle,\r
0c84a69f 4118 (*BridgeControl & BIT0) != 0\r
5d73d92f 4119 );\r
4120 ShellPrintHiiEx(-1, -1, NULL,\r
4121 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
4122 gShellDebug1HiiHandle,\r
0c84a69f 4123 (*BridgeControl & BIT1) != 0\r
5d73d92f 4124 );\r
4125 ShellPrintHiiEx(-1, -1, NULL,\r
4126 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
4127 gShellDebug1HiiHandle,\r
0c84a69f 4128 (*BridgeControl & BIT2) != 0\r
5d73d92f 4129 );\r
4130 ShellPrintHiiEx(-1, -1, NULL,\r
4131 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
4132 gShellDebug1HiiHandle,\r
0c84a69f 4133 (*BridgeControl & BIT3) != 0\r
5d73d92f 4134 );\r
4135 ShellPrintHiiEx(-1, -1, NULL,\r
4136 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
4137 gShellDebug1HiiHandle,\r
0c84a69f 4138 (*BridgeControl & BIT5) != 0\r
5d73d92f 4139 );\r
4140\r
4141 //\r
4142 // Register Bridge Control has some slight differences between P2P bridge\r
4143 // and Cardbus bridge from bit 6 to bit 11.\r
4144 //\r
4145 if (HeaderType == PciP2pBridge) {\r
4146 ShellPrintHiiEx(-1, -1, NULL,\r
4147 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
4148 gShellDebug1HiiHandle,\r
0c84a69f 4149 (*BridgeControl & BIT6) != 0\r
5d73d92f 4150 );\r
4151 ShellPrintHiiEx(-1, -1, NULL,\r
4152 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
4153 gShellDebug1HiiHandle,\r
0c84a69f 4154 (*BridgeControl & BIT7) != 0\r
5d73d92f 4155 );\r
4156 ShellPrintHiiEx(-1, -1, NULL,\r
4157 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
4158 gShellDebug1HiiHandle,\r
0c84a69f 4159 (*BridgeControl & BIT8)!=0 ? L"2^10" : L"2^15"\r
5d73d92f 4160 );\r
4161 ShellPrintHiiEx(-1, -1, NULL,\r
4162 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
4163 gShellDebug1HiiHandle,\r
0c84a69f 4164 (*BridgeControl & BIT9)!=0 ? L"2^10" : L"2^15"\r
5d73d92f 4165 );\r
4166 ShellPrintHiiEx(-1, -1, NULL,\r
4167 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
4168 gShellDebug1HiiHandle,\r
0c84a69f 4169 (*BridgeControl & BIT10) != 0\r
5d73d92f 4170 );\r
4171 ShellPrintHiiEx(-1, -1, NULL,\r
4172 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
4173 gShellDebug1HiiHandle,\r
0c84a69f 4174 (*BridgeControl & BIT11) != 0\r
5d73d92f 4175 );\r
4176\r
4177 } else {\r
4178 ShellPrintHiiEx(-1, -1, NULL,\r
4179 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
4180 gShellDebug1HiiHandle,\r
0c84a69f 4181 (*BridgeControl & BIT6) != 0\r
5d73d92f 4182 );\r
4183 ShellPrintHiiEx(-1, -1, NULL,\r
4184 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
4185 gShellDebug1HiiHandle,\r
0c84a69f 4186 (*BridgeControl & BIT7) != 0\r
5d73d92f 4187 );\r
4188 ShellPrintHiiEx(-1, -1, NULL,\r
4189 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
4190 gShellDebug1HiiHandle,\r
0c84a69f 4191 (*BridgeControl & BIT10) != 0\r
5d73d92f 4192 );\r
4193 }\r
4194\r
4195 return EFI_SUCCESS;\r
4196}\r
4197\r
a1d4bfcc 4198/**\r
33cc487c 4199 Locate capability register block per capability ID.\r
a1d4bfcc 4200\r
33cc487c
RN		 4201 @param[in] ConfigSpace Data in PCI configuration space.\r
4202 @param[in] CapabilityId The capability ID.\r
a1d4bfcc 4203\r
33cc487c
RN		 4204 @return The offset of the register block per capability ID,\r
4205 or 0 if the register block cannot be found.\r
a1d4bfcc 4206**/\r
33cc487c
RN		 4207UINT8\r
4208LocatePciCapability (\r
4209 IN PCI_CONFIG_SPACE *ConfigSpace,\r
4210 IN UINT8 CapabilityId\r
5d73d92f 4211 )\r
4212{\r
33cc487c
RN		 4213 UINT8 CapabilityPtr;\r
4214 EFI_PCI_CAPABILITY_HDR *CapabilityEntry;\r
5d73d92f 4215\r
4216 //\r
33cc487c 4217 // To check the cpability of this device supports\r
5d73d92f 4218 //\r
33cc487c
RN		 4219 if ((ConfigSpace->Common.Status & EFI_PCI_STATUS_CAPABILITY) == 0) {\r
4220 return 0;\r
4221 }\r
5d73d92f 4222\r
33cc487c
RN		 4223 switch ((PCI_HEADER_TYPE)(ConfigSpace->Common.HeaderType & 0x7f)) {\r
4224 case PciDevice:\r
4225 CapabilityPtr = ConfigSpace->NonCommon.Device.CapabilityPtr;\r
4226 break;\r
4227 case PciP2pBridge:\r
4228 CapabilityPtr = ConfigSpace->NonCommon.Bridge.CapabilityPtr;\r
4229 break;\r
4230 case PciCardBusBridge:\r
4231 CapabilityPtr = ConfigSpace->NonCommon.CardBus.Cap_Ptr;\r
4232 break;\r
4233 default:\r
4234 return 0;\r
4235 }\r
5d73d92f 4236\r
33cc487c
RN		 4237 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
4238 CapabilityEntry = (EFI_PCI_CAPABILITY_HDR *) ((UINT8 *) ConfigSpace + CapabilityPtr);\r
4239 if (CapabilityEntry->CapabilityID == CapabilityId) {\r
4240 return CapabilityPtr;\r
5d73d92f 4241 }\r
33cc487c 4242\r
5d73d92f 4243 //\r
33cc487c
RN		 4244 // Certain PCI device may incorrectly have capability pointing to itself,\r
4245 // break to avoid dead loop.\r
5d73d92f 4246 //\r
33cc487c
RN		 4247 if (CapabilityPtr == CapabilityEntry->NextItemPtr) {\r
4248 break;\r
4249 }\r
4250\r
4251 CapabilityPtr = CapabilityEntry->NextItemPtr;\r
5d73d92f 4252 }\r
4253\r
33cc487c 4254 return 0;\r
5d73d92f 4255}\r
4256\r
a1d4bfcc 4257/**\r
4258 Print out information of the capability information.\r
4259\r
4260 @param[in] PciExpressCap The pointer to the structure about the device.\r
4261\r
4262 @retval EFI_SUCCESS The operation was successful.\r
4263**/\r
5d73d92f 4264EFI_STATUS\r
4265ExplainPcieCapReg (\r
0c84a69f 4266 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4267 )\r
5d73d92f 4268{\r
5d73d92f 4269 CHAR16 *DevicePortType;\r
4270\r
c37e0f16
CP		 4271 ShellPrintEx (-1, -1,\r
4272 L" Capability Version(3:0): %E0x%04x%N\r\n",\r
0c84a69f 4273 PciExpressCap->Capability.Bits.Version\r
5d73d92f 4274 );\r
0c84a69f
RN		 4275 if (PciExpressCap->Capability.Bits.DevicePortType < ARRAY_SIZE (DevicePortTypeTable)) {\r
4276 DevicePortType = DevicePortTypeTable[PciExpressCap->Capability.Bits.DevicePortType];\r
5d73d92f 4277 } else {\r
4278 DevicePortType = L"Unknown Type";\r
4279 }\r
c37e0f16
CP		 4280 ShellPrintEx (-1, -1,\r
4281 L" Device/PortType(7:4): %E%s%N\r\n",\r
5d73d92f 4282 DevicePortType\r
4283 );\r
4284 //\r
4285 // 'Slot Implemented' is only valid for:\r
4286 // a) Root Port of PCI Express Root Complex, or\r
4287 // b) Downstream Port of PCI Express Switch\r
4288 //\r
0c84a69f
RN		 4289 if (PciExpressCap->Capability.Bits.DevicePortType== PCIE_DEVICE_PORT_TYPE_ROOT_PORT ||\r
4290 PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) {\r
c37e0f16
CP		 4291 ShellPrintEx (-1, -1,\r
4292 L" Slot Implemented(8): %E%d%N\r\n",\r
0c84a69f 4293 PciExpressCap->Capability.Bits.SlotImplemented\r
5d73d92f 4294 );\r
4295 }\r
c37e0f16
CP		 4296 ShellPrintEx (-1, -1,\r
4297 L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
0c84a69f 4298 PciExpressCap->Capability.Bits.InterruptMessageNumber\r
5d73d92f 4299 );\r
4300 return EFI_SUCCESS;\r
4301}\r
4302\r
a1d4bfcc 4303/**\r
4304 Print out information of the device capability information.\r
4305\r
4306 @param[in] PciExpressCap The pointer to the structure about the device.\r
4307\r
4308 @retval EFI_SUCCESS The operation was successful.\r
4309**/\r
5d73d92f 4310EFI_STATUS\r
4311ExplainPcieDeviceCap (\r
0c84a69f 4312 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4313 )\r
5d73d92f 4314{\r
5d73d92f 4315 UINT8 DevicePortType;\r
4316 UINT8 L0sLatency;\r
4317 UINT8 L1Latency;\r
4318\r
0c84a69f 4319 DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
c37e0f16 4320 ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
0c84a69f
RN		 4321 if (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize < 6) {\r
4322 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceCapability.Bits.MaxPayloadSize + 7));\r
5d73d92f 4323 } else {\r
c37e0f16 4324 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4325 }\r
c37e0f16
CP		 4326 ShellPrintEx (-1, -1,\r
4327 L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
0c84a69f 4328 PciExpressCap->DeviceCapability.Bits.PhantomFunctions\r
5d73d92f 4329 );\r
c37e0f16
CP		 4330 ShellPrintEx (-1, -1,\r
4331 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
0c84a69f 4332 PciExpressCap->DeviceCapability.Bits.ExtendedTagField ? 8 : 5\r
5d73d92f 4333 );\r
4334 //\r
4335 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
4336 //\r
4337 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
0c84a69f
RN		 4338 L0sLatency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL0sAcceptableLatency;\r
4339 L1Latency = (UINT8)PciExpressCap->DeviceCapability.Bits.EndpointL1AcceptableLatency;\r
c37e0f16 4340 ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
5d73d92f 4341 if (L0sLatency < 4) {\r
c37e0f16 4342 ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
5d73d92f 4343 } else {\r
4344 if (L0sLatency < 7) {\r
c37e0f16 4345 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
5d73d92f 4346 } else {\r
c37e0f16 4347 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 4348 }\r
4349 }\r
c37e0f16 4350 ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
5d73d92f 4351 if (L1Latency < 7) {\r
c37e0f16 4352 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
5d73d92f 4353 } else {\r
c37e0f16 4354 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 4355 }\r
4356 }\r
c37e0f16
CP		 4357 ShellPrintEx (-1, -1,\r
4358 L" Role-based Error Reporting(15): %E%d%N\r\n",\r
0c84a69f 4359 PciExpressCap->DeviceCapability.Bits.RoleBasedErrorReporting\r
5d73d92f 4360 );\r
4361 //\r
4362 // Only valid for Upstream Port:\r
4363 // a) Captured Slot Power Limit Value\r
4364 // b) Captured Slot Power Scale\r
4365 //\r
0c84a69f 4366 if (DevicePortType == PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) {\r
c37e0f16
CP		 4367 ShellPrintEx (-1, -1,\r
4368 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
0c84a69f 4369 PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitValue\r
5d73d92f 4370 );\r
c37e0f16
CP		 4371 ShellPrintEx (-1, -1,\r
4372 L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
0c84a69f 4373 SlotPwrLmtScaleTable[PciExpressCap->DeviceCapability.Bits.CapturedSlotPowerLimitScale]\r
5d73d92f 4374 );\r
4375 }\r
4376 //\r
4377 // Function Level Reset Capability is only valid for Endpoint\r
4378 //\r
4379 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
c37e0f16
CP		 4380 ShellPrintEx (-1, -1,\r
4381 L" Function Level Reset Capability(28): %E%d%N\r\n",\r
0c84a69f 4382 PciExpressCap->DeviceCapability.Bits.FunctionLevelReset\r
5d73d92f 4383 );\r
4384 }\r
4385 return EFI_SUCCESS;\r
4386}\r
4387\r
a1d4bfcc 4388/**\r
4389 Print out information of the device control information.\r
4390\r
4391 @param[in] PciExpressCap The pointer to the structure about the device.\r
4392\r
4393 @retval EFI_SUCCESS The operation was successful.\r
4394**/\r
5d73d92f 4395EFI_STATUS\r
4396ExplainPcieDeviceControl (\r
0c84a69f 4397 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4398 )\r
5d73d92f 4399{\r
c37e0f16
CP		 4400 ShellPrintEx (-1, -1,\r
4401 L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
0c84a69f
RN		 4402 PciExpressCap->DeviceControl.Bits.CorrectableError\r
4403 );\r
c37e0f16
CP		 4404 ShellPrintEx (-1, -1,\r
4405 L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
0c84a69f 4406 PciExpressCap->DeviceControl.Bits.NonFatalError\r
5d73d92f 4407 );\r
c37e0f16
CP		 4408 ShellPrintEx (-1, -1,\r
4409 L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
0c84a69f 4410 PciExpressCap->DeviceControl.Bits.FatalError\r
5d73d92f 4411 );\r
c37e0f16
CP		 4412 ShellPrintEx (-1, -1,\r
4413 L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
0c84a69f 4414 PciExpressCap->DeviceControl.Bits.UnsupportedRequest\r
5d73d92f 4415 );\r
c37e0f16
CP		 4416 ShellPrintEx (-1, -1,\r
4417 L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
0c84a69f 4418 PciExpressCap->DeviceControl.Bits.RelaxedOrdering\r
5d73d92f 4419 );\r
c37e0f16 4420 ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
0c84a69f
RN		 4421 if (PciExpressCap->DeviceControl.Bits.MaxPayloadSize < 6) {\r
4422 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxPayloadSize + 7));\r
5d73d92f 4423 } else {\r
c37e0f16 4424 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4425 }\r
c37e0f16
CP		 4426 ShellPrintEx (-1, -1,\r
4427 L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
0c84a69f 4428 PciExpressCap->DeviceControl.Bits.ExtendedTagField\r
5d73d92f 4429 );\r
c37e0f16
CP		 4430 ShellPrintEx (-1, -1,\r
4431 L" Phantom Functions Enable(9): %E%d%N\r\n",\r
0c84a69f 4432 PciExpressCap->DeviceControl.Bits.PhantomFunctions\r
5d73d92f 4433 );\r
c37e0f16
CP		 4434 ShellPrintEx (-1, -1,\r
4435 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
0c84a69f 4436 PciExpressCap->DeviceControl.Bits.AuxPower\r
5d73d92f 4437 );\r
c37e0f16
CP		 4438 ShellPrintEx (-1, -1,\r
4439 L" Enable No Snoop(11): %E%d%N\r\n",\r
0c84a69f 4440 PciExpressCap->DeviceControl.Bits.NoSnoop\r
5d73d92f 4441 );\r
c37e0f16 4442 ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
0c84a69f
RN		 4443 if (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize < 6) {\r
4444 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PciExpressCap->DeviceControl.Bits.MaxReadRequestSize + 7));\r
5d73d92f 4445 } else {\r
c37e0f16 4446 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4447 }\r
4448 //\r
4449 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
4450 //\r
0c84a69f 4451 if (PciExpressCap->Capability.Bits.DevicePortType == PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r
c37e0f16
CP		 4452 ShellPrintEx (-1, -1,\r
4453 L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
0c84a69f 4454 PciExpressCap->DeviceControl.Bits.BridgeConfigurationRetryOrFunctionLevelReset\r
5d73d92f 4455 );\r
4456 }\r
4457 return EFI_SUCCESS;\r
4458}\r
4459\r
a1d4bfcc 4460/**\r
4461 Print out information of the device status information.\r
4462\r
4463 @param[in] PciExpressCap The pointer to the structure about the device.\r
4464\r
4465 @retval EFI_SUCCESS The operation was successful.\r
4466**/\r
5d73d92f 4467EFI_STATUS\r
4468ExplainPcieDeviceStatus (\r
0c84a69f 4469 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4470 )\r
5d73d92f 4471{\r
c37e0f16
CP		 4472 ShellPrintEx (-1, -1,\r
4473 L" Correctable Error Detected(0): %E%d%N\r\n",\r
0c84a69f 4474 PciExpressCap->DeviceStatus.Bits.CorrectableError\r
5d73d92f 4475 );\r
c37e0f16
CP		 4476 ShellPrintEx (-1, -1,\r
4477 L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
0c84a69f 4478 PciExpressCap->DeviceStatus.Bits.NonFatalError\r
5d73d92f 4479 );\r
c37e0f16
CP		 4480 ShellPrintEx (-1, -1,\r
4481 L" Fatal Error Detected(2): %E%d%N\r\n",\r
0c84a69f 4482 PciExpressCap->DeviceStatus.Bits.FatalError\r
5d73d92f 4483 );\r
c37e0f16
CP		 4484 ShellPrintEx (-1, -1,\r
4485 L" Unsupported Request Detected(3): %E%d%N\r\n",\r
0c84a69f 4486 PciExpressCap->DeviceStatus.Bits.UnsupportedRequest\r
5d73d92f 4487 );\r
c37e0f16
CP		 4488 ShellPrintEx (-1, -1,\r
4489 L" AUX Power Detected(4): %E%d%N\r\n",\r
0c84a69f 4490 PciExpressCap->DeviceStatus.Bits.AuxPower\r
5d73d92f 4491 );\r
c37e0f16
CP		 4492 ShellPrintEx (-1, -1,\r
4493 L" Transactions Pending(5): %E%d%N\r\n",\r
0c84a69f 4494 PciExpressCap->DeviceStatus.Bits.TransactionsPending\r
5d73d92f 4495 );\r
4496 return EFI_SUCCESS;\r
4497}\r
4498\r
a1d4bfcc 4499/**\r
4500 Print out information of the device link information.\r
4501\r
4502 @param[in] PciExpressCap The pointer to the structure about the device.\r
4503\r
4504 @retval EFI_SUCCESS The operation was successful.\r
4505**/\r
5d73d92f 4506EFI_STATUS\r
4507ExplainPcieLinkCap (\r
0c84a69f 4508 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4509 )\r
5d73d92f 4510{\r
541ddf44 4511 CHAR16 *MaxLinkSpeed;\r
a1d4bfcc 4512 CHAR16 *AspmValue;\r
5d73d92f 4513\r
0c84a69f 4514 switch (PciExpressCap->LinkCapability.Bits.MaxLinkSpeed) {\r
5d73d92f 4515 case 1:\r
541ddf44 4516 MaxLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4517 break;\r
4518 case 2:\r
541ddf44
CP		 4519 MaxLinkSpeed = L"5.0 GT/s";\r
4520 break;\r
4521 case 3:\r
4522 MaxLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4523 break;\r
4524 default:\r
541ddf44 4525 MaxLinkSpeed = L"Unknown";\r
5d73d92f 4526 break;\r
4527 }\r
c37e0f16 4528 ShellPrintEx (-1, -1,\r
541ddf44
CP		 4529 L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
4530 MaxLinkSpeed\r
5d73d92f 4531 );\r
c37e0f16
CP		 4532 ShellPrintEx (-1, -1,\r
4533 L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
0c84a69f 4534 PciExpressCap->LinkCapability.Bits.MaxLinkWidth\r
5d73d92f 4535 );\r
0c84a69f 4536 switch (PciExpressCap->LinkCapability.Bits.Aspm) {\r
541ddf44
CP		 4537 case 0:\r
4538 AspmValue = L"Not";\r
4539 break;\r
5d73d92f 4540 case 1:\r
541ddf44
CP		 4541 AspmValue = L"L0s";\r
4542 break;\r
4543 case 2:\r
4544 AspmValue = L"L1";\r
5d73d92f 4545 break;\r
4546 case 3:\r
a1d4bfcc 4547 AspmValue = L"L0s and L1";\r
5d73d92f 4548 break;\r
4549 default:\r
a1d4bfcc 4550 AspmValue = L"Reserved";\r
5d73d92f 4551 break;\r
4552 }\r
c37e0f16
CP		 4553 ShellPrintEx (-1, -1,\r
4554 L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
a1d4bfcc 4555 AspmValue\r
5d73d92f 4556 );\r
c37e0f16
CP		 4557 ShellPrintEx (-1, -1,\r
4558 L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
0c84a69f 4559 L0sLatencyStrTable[PciExpressCap->LinkCapability.Bits.L0sExitLatency]\r
5d73d92f 4560 );\r
c37e0f16
CP		 4561 ShellPrintEx (-1, -1,\r
4562 L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
0c84a69f 4563 L1LatencyStrTable[PciExpressCap->LinkCapability.Bits.L1ExitLatency]\r
5d73d92f 4564 );\r
c37e0f16
CP		 4565 ShellPrintEx (-1, -1,\r
4566 L" Clock Power Management(18): %E%d%N\r\n",\r
0c84a69f 4567 PciExpressCap->LinkCapability.Bits.ClockPowerManagement\r
5d73d92f 4568 );\r
c37e0f16
CP		 4569 ShellPrintEx (-1, -1,\r
4570 L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
0c84a69f 4571 PciExpressCap->LinkCapability.Bits.SurpriseDownError\r
5d73d92f 4572 );\r
c37e0f16
CP		 4573 ShellPrintEx (-1, -1,\r
4574 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
0c84a69f 4575 PciExpressCap->LinkCapability.Bits.DataLinkLayerLinkActive\r
5d73d92f 4576 );\r
c37e0f16
CP		 4577 ShellPrintEx (-1, -1,\r
4578 L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
0c84a69f 4579 PciExpressCap->LinkCapability.Bits.LinkBandwidthNotification\r
5d73d92f 4580 );\r
c37e0f16
CP		 4581 ShellPrintEx (-1, -1,\r
4582 L" Port Number(31:24): %E0x%02x%N\r\n",\r
0c84a69f 4583 PciExpressCap->LinkCapability.Bits.PortNumber\r
5d73d92f 4584 );\r
4585 return EFI_SUCCESS;\r
4586}\r
4587\r
a1d4bfcc 4588/**\r
4589 Print out information of the device link control information.\r
4590\r
4591 @param[in] PciExpressCap The pointer to the structure about the device.\r
4592\r
4593 @retval EFI_SUCCESS The operation was successful.\r
4594**/\r
5d73d92f 4595EFI_STATUS\r
4596ExplainPcieLinkControl (\r
0c84a69f 4597 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4598 )\r
5d73d92f 4599{\r
5d73d92f 4600 UINT8 DevicePortType;\r
4601\r
0c84a69f 4602 DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
c37e0f16
CP		 4603 ShellPrintEx (-1, -1,\r
4604 L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
0c84a69f 4605 ASPMCtrlStrTable[PciExpressCap->LinkControl.Bits.AspmControl]\r
5d73d92f 4606 );\r
4607 //\r
4608 // RCB is not applicable to switches\r
4609 //\r
4610 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
c37e0f16
CP		 4611 ShellPrintEx (-1, -1,\r
4612 L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
0c84a69f 4613 1 << (PciExpressCap->LinkControl.Bits.ReadCompletionBoundary + 6)\r
5d73d92f 4614 );\r
4615 }\r
4616 //\r
4617 // Link Disable is reserved on\r
4618 // a) Endpoints\r
4619 // b) PCI Express to PCI/PCI-X bridges\r
4620 // c) Upstream Ports of Switches\r
4621 //\r
4622 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
0c84a69f
RN		 4623 DevicePortType != PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT &&\r
4624 DevicePortType != PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE) {\r
c37e0f16
CP		 4625 ShellPrintEx (-1, -1,\r
4626 L" Link Disable(4): %E%d%N\r\n",\r
0c84a69f 4627 PciExpressCap->LinkControl.Bits.LinkDisable\r
5d73d92f 4628 );\r
4629 }\r
c37e0f16
CP		 4630 ShellPrintEx (-1, -1,\r
4631 L" Common Clock Configuration(6): %E%d%N\r\n",\r
0c84a69f 4632 PciExpressCap->LinkControl.Bits.CommonClockConfiguration\r
5d73d92f 4633 );\r
c37e0f16
CP		 4634 ShellPrintEx (-1, -1,\r
4635 L" Extended Synch(7): %E%d%N\r\n",\r
0c84a69f 4636 PciExpressCap->LinkControl.Bits.ExtendedSynch\r
5d73d92f 4637 );\r
c37e0f16
CP		 4638 ShellPrintEx (-1, -1,\r
4639 L" Enable Clock Power Management(8): %E%d%N\r\n",\r
0c84a69f 4640 PciExpressCap->LinkControl.Bits.ClockPowerManagement\r
5d73d92f 4641 );\r
c37e0f16
CP		 4642 ShellPrintEx (-1, -1,\r
4643 L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
0c84a69f 4644 PciExpressCap->LinkControl.Bits.HardwareAutonomousWidthDisable\r
5d73d92f 4645 );\r
c37e0f16
CP		 4646 ShellPrintEx (-1, -1,\r
4647 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
0c84a69f 4648 PciExpressCap->LinkControl.Bits.LinkBandwidthManagementInterrupt\r
5d73d92f 4649 );\r
c37e0f16
CP		 4650 ShellPrintEx (-1, -1,\r
4651 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
0c84a69f 4652 PciExpressCap->LinkControl.Bits.LinkAutonomousBandwidthInterrupt\r
5d73d92f 4653 );\r
4654 return EFI_SUCCESS;\r
4655}\r
4656\r
a1d4bfcc 4657/**\r
4658 Print out information of the device link status information.\r
4659\r
4660 @param[in] PciExpressCap The pointer to the structure about the device.\r
4661\r
4662 @retval EFI_SUCCESS The operation was successful.\r
4663**/\r
5d73d92f 4664EFI_STATUS\r
4665ExplainPcieLinkStatus (\r
0c84a69f 4666 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4667 )\r
5d73d92f 4668{\r
541ddf44 4669 CHAR16 *CurLinkSpeed;\r
5d73d92f 4670\r
0c84a69f 4671 switch (PciExpressCap->LinkStatus.Bits.CurrentLinkSpeed) {\r
5d73d92f 4672 case 1:\r
541ddf44 4673 CurLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4674 break;\r
4675 case 2:\r
541ddf44
CP		 4676 CurLinkSpeed = L"5.0 GT/s";\r
4677 break;\r
4678 case 3:\r
4679 CurLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4680 break;\r
4681 default:\r
541ddf44 4682 CurLinkSpeed = L"Reserved";\r
5d73d92f 4683 break;\r
4684 }\r
c37e0f16
CP		 4685 ShellPrintEx (-1, -1,\r
4686 L" Current Link Speed(3:0): %E%s%N\r\n",\r
541ddf44 4687 CurLinkSpeed\r
5d73d92f 4688 );\r
c37e0f16
CP		 4689 ShellPrintEx (-1, -1,\r
4690 L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
0c84a69f 4691 PciExpressCap->LinkStatus.Bits.NegotiatedLinkWidth\r
5d73d92f 4692 );\r
c37e0f16
CP		 4693 ShellPrintEx (-1, -1,\r
4694 L" Link Training(11): %E%d%N\r\n",\r
0c84a69f 4695 PciExpressCap->LinkStatus.Bits.LinkTraining\r
5d73d92f 4696 );\r
c37e0f16
CP		 4697 ShellPrintEx (-1, -1,\r
4698 L" Slot Clock Configuration(12): %E%d%N\r\n",\r
0c84a69f 4699 PciExpressCap->LinkStatus.Bits.SlotClockConfiguration\r
5d73d92f 4700 );\r
c37e0f16
CP		 4701 ShellPrintEx (-1, -1,\r
4702 L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
0c84a69f 4703 PciExpressCap->LinkStatus.Bits.DataLinkLayerLinkActive\r
5d73d92f 4704 );\r
c37e0f16
CP		 4705 ShellPrintEx (-1, -1,\r
4706 L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
0c84a69f 4707 PciExpressCap->LinkStatus.Bits.LinkBandwidthManagement\r
5d73d92f 4708 );\r
c37e0f16
CP		 4709 ShellPrintEx (-1, -1,\r
4710 L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
0c84a69f 4711 PciExpressCap->LinkStatus.Bits.LinkAutonomousBandwidth\r
5d73d92f 4712 );\r
4713 return EFI_SUCCESS;\r
4714}\r
4715\r
a1d4bfcc 4716/**\r
4717 Print out information of the device slot information.\r
4718\r
4719 @param[in] PciExpressCap The pointer to the structure about the device.\r
4720\r
4721 @retval EFI_SUCCESS The operation was successful.\r
4722**/\r
5d73d92f 4723EFI_STATUS\r
4724ExplainPcieSlotCap (\r
0c84a69f 4725 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4726 )\r
5d73d92f 4727{\r
c37e0f16
CP		 4728 ShellPrintEx (-1, -1,\r
4729 L" Attention Button Present(0): %E%d%N\r\n",\r
0c84a69f 4730 PciExpressCap->SlotCapability.Bits.AttentionButton\r
5d73d92f 4731 );\r
c37e0f16
CP		 4732 ShellPrintEx (-1, -1,\r
4733 L" Power Controller Present(1): %E%d%N\r\n",\r
0c84a69f 4734 PciExpressCap->SlotCapability.Bits.PowerController\r
5d73d92f 4735 );\r
c37e0f16
CP		 4736 ShellPrintEx (-1, -1,\r
4737 L" MRL Sensor Present(2): %E%d%N\r\n",\r
0c84a69f 4738 PciExpressCap->SlotCapability.Bits.MrlSensor\r
5d73d92f 4739 );\r
c37e0f16
CP		 4740 ShellPrintEx (-1, -1,\r
4741 L" Attention Indicator Present(3): %E%d%N\r\n",\r
0c84a69f 4742 PciExpressCap->SlotCapability.Bits.AttentionIndicator\r
5d73d92f 4743 );\r
c37e0f16
CP		 4744 ShellPrintEx (-1, -1,\r
4745 L" Power Indicator Present(4): %E%d%N\r\n",\r
0c84a69f 4746 PciExpressCap->SlotCapability.Bits.PowerIndicator\r
5d73d92f 4747 );\r
c37e0f16
CP		 4748 ShellPrintEx (-1, -1,\r
4749 L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
0c84a69f 4750 PciExpressCap->SlotCapability.Bits.HotPlugSurprise\r
5d73d92f 4751 );\r
c37e0f16
CP		 4752 ShellPrintEx (-1, -1,\r
4753 L" Hot-Plug Capable(6): %E%d%N\r\n",\r
0c84a69f 4754 PciExpressCap->SlotCapability.Bits.HotPlugCapable\r
5d73d92f 4755 );\r
c37e0f16
CP		 4756 ShellPrintEx (-1, -1,\r
4757 L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
0c84a69f 4758 PciExpressCap->SlotCapability.Bits.SlotPowerLimitValue\r
5d73d92f 4759 );\r
c37e0f16
CP		 4760 ShellPrintEx (-1, -1,\r
4761 L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
0c84a69f 4762 SlotPwrLmtScaleTable[PciExpressCap->SlotCapability.Bits.SlotPowerLimitScale]\r
5d73d92f 4763 );\r
c37e0f16
CP		 4764 ShellPrintEx (-1, -1,\r
4765 L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
0c84a69f 4766 PciExpressCap->SlotCapability.Bits.ElectromechanicalInterlock\r
5d73d92f 4767 );\r
c37e0f16
CP		 4768 ShellPrintEx (-1, -1,\r
4769 L" No Command Completed Support(18): %E%d%N\r\n",\r
0c84a69f 4770 PciExpressCap->SlotCapability.Bits.NoCommandCompleted\r
5d73d92f 4771 );\r
c37e0f16
CP		 4772 ShellPrintEx (-1, -1,\r
4773 L" Physical Slot Number(31:19): %E%d%N\r\n",\r
0c84a69f 4774 PciExpressCap->SlotCapability.Bits.PhysicalSlotNumber\r
5d73d92f 4775 );\r
4776\r
4777 return EFI_SUCCESS;\r
4778}\r
4779\r
a1d4bfcc 4780/**\r
4781 Print out information of the device slot control information.\r
4782\r
4783 @param[in] PciExpressCap The pointer to the structure about the device.\r
4784\r
4785 @retval EFI_SUCCESS The operation was successful.\r
4786**/\r
5d73d92f 4787EFI_STATUS\r
4788ExplainPcieSlotControl (\r
0c84a69f 4789 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4790 )\r
5d73d92f 4791{\r
c37e0f16
CP		 4792 ShellPrintEx (-1, -1,\r
4793 L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
0c84a69f 4794 PciExpressCap->SlotControl.Bits.AttentionButtonPressed\r
5d73d92f 4795 );\r
c37e0f16
CP		 4796 ShellPrintEx (-1, -1,\r
4797 L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
0c84a69f 4798 PciExpressCap->SlotControl.Bits.PowerFaultDetected\r
5d73d92f 4799 );\r
c37e0f16
CP		 4800 ShellPrintEx (-1, -1,\r
4801 L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
0c84a69f 4802 PciExpressCap->SlotControl.Bits.MrlSensorChanged\r
5d73d92f 4803 );\r
c37e0f16
CP		 4804 ShellPrintEx (-1, -1,\r
4805 L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
0c84a69f 4806 PciExpressCap->SlotControl.Bits.PresenceDetectChanged\r
5d73d92f 4807 );\r
c37e0f16
CP		 4808 ShellPrintEx (-1, -1,\r
4809 L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
0c84a69f 4810 PciExpressCap->SlotControl.Bits.CommandCompletedInterrupt\r
5d73d92f 4811 );\r
c37e0f16
CP		 4812 ShellPrintEx (-1, -1,\r
4813 L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
0c84a69f 4814 PciExpressCap->SlotControl.Bits.HotPlugInterrupt\r
5d73d92f 4815 );\r
c37e0f16
CP		 4816 ShellPrintEx (-1, -1,\r
4817 L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
0c84a69f
RN		 4818 IndicatorTable[\r
4819 PciExpressCap->SlotControl.Bits.AttentionIndicator]\r
5d73d92f 4820 );\r
c37e0f16
CP		 4821 ShellPrintEx (-1, -1,\r
4822 L" Power Indicator Control(9:8): %E%s%N\r\n",\r
0c84a69f 4823 IndicatorTable[PciExpressCap->SlotControl.Bits.PowerIndicator]\r
5d73d92f 4824 );\r
c37e0f16 4825 ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
0c84a69f
RN		 4826 if (\r
4827 PciExpressCap->SlotControl.Bits.PowerController) {\r
c37e0f16 4828 ShellPrintEx (-1, -1, L"Off%N\r\n");\r
5d73d92f 4829 } else {\r
c37e0f16 4830 ShellPrintEx (-1, -1, L"On%N\r\n");\r
5d73d92f 4831 }\r
c37e0f16
CP		 4832 ShellPrintEx (-1, -1,\r
4833 L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
0c84a69f 4834 PciExpressCap->SlotControl.Bits.ElectromechanicalInterlock\r
5d73d92f 4835 );\r
c37e0f16
CP		 4836 ShellPrintEx (-1, -1,\r
4837 L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
0c84a69f 4838 PciExpressCap->SlotControl.Bits.DataLinkLayerStateChanged\r
5d73d92f 4839 );\r
4840 return EFI_SUCCESS;\r
4841}\r
4842\r
a1d4bfcc 4843/**\r
4844 Print out information of the device slot status information.\r
4845\r
4846 @param[in] PciExpressCap The pointer to the structure about the device.\r
4847\r
4848 @retval EFI_SUCCESS The operation was successful.\r
4849**/\r
5d73d92f 4850EFI_STATUS\r
4851ExplainPcieSlotStatus (\r
0c84a69f 4852 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4853 )\r
5d73d92f 4854{\r
c37e0f16
CP		 4855 ShellPrintEx (-1, -1,\r
4856 L" Attention Button Pressed(0): %E%d%N\r\n",\r
0c84a69f 4857 PciExpressCap->SlotStatus.Bits.AttentionButtonPressed\r
5d73d92f 4858 );\r
c37e0f16
CP		 4859 ShellPrintEx (-1, -1,\r
4860 L" Power Fault Detected(1): %E%d%N\r\n",\r
0c84a69f 4861 PciExpressCap->SlotStatus.Bits.PowerFaultDetected\r
5d73d92f 4862 );\r
c37e0f16
CP		 4863 ShellPrintEx (-1, -1,\r
4864 L" MRL Sensor Changed(2): %E%d%N\r\n",\r
0c84a69f 4865 PciExpressCap->SlotStatus.Bits.MrlSensorChanged\r
5d73d92f 4866 );\r
c37e0f16
CP		 4867 ShellPrintEx (-1, -1,\r
4868 L" Presence Detect Changed(3): %E%d%N\r\n",\r
0c84a69f 4869 PciExpressCap->SlotStatus.Bits.PresenceDetectChanged\r
5d73d92f 4870 );\r
c37e0f16
CP		 4871 ShellPrintEx (-1, -1,\r
4872 L" Command Completed(4): %E%d%N\r\n",\r
0c84a69f 4873 PciExpressCap->SlotStatus.Bits.CommandCompleted\r
5d73d92f 4874 );\r
c37e0f16 4875 ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
0c84a69f
RN		 4876 if (\r
4877 PciExpressCap->SlotStatus.Bits.MrlSensor) {\r
c37e0f16 4878 ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
5d73d92f 4879 } else {\r
c37e0f16 4880 ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
5d73d92f 4881 }\r
c37e0f16 4882 ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
0c84a69f
RN		 4883 if (\r
4884 PciExpressCap->SlotStatus.Bits.PresenceDetect) {\r
c37e0f16 4885 ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
5d73d92f 4886 } else {\r
c37e0f16 4887 ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
5d73d92f 4888 }\r
c37e0f16 4889 ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
0c84a69f
RN		 4890 if (\r
4891 PciExpressCap->SlotStatus.Bits.ElectromechanicalInterlock) {\r
c37e0f16 4892 ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
5d73d92f 4893 } else {\r
c37e0f16 4894 ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
5d73d92f 4895 }\r
c37e0f16
CP		 4896 ShellPrintEx (-1, -1,\r
4897 L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
0c84a69f 4898 PciExpressCap->SlotStatus.Bits.DataLinkLayerStateChanged\r
5d73d92f 4899 );\r
4900 return EFI_SUCCESS;\r
4901}\r
4902\r
a1d4bfcc 4903/**\r
4904 Print out information of the device root information.\r
4905\r
4906 @param[in] PciExpressCap The pointer to the structure about the device.\r
4907\r
4908 @retval EFI_SUCCESS The operation was successful.\r
4909**/\r
5d73d92f 4910EFI_STATUS\r
4911ExplainPcieRootControl (\r
0c84a69f 4912 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4913 )\r
5d73d92f 4914{\r
c37e0f16
CP		 4915 ShellPrintEx (-1, -1,\r
4916 L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
0c84a69f 4917 PciExpressCap->RootControl.Bits.SystemErrorOnCorrectableError\r
5d73d92f 4918 );\r
c37e0f16
CP		 4919 ShellPrintEx (-1, -1,\r
4920 L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
0c84a69f 4921 PciExpressCap->RootControl.Bits.SystemErrorOnNonFatalError\r
5d73d92f 4922 );\r
c37e0f16
CP		 4923 ShellPrintEx (-1, -1,\r
4924 L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
0c84a69f 4925 PciExpressCap->RootControl.Bits.SystemErrorOnFatalError\r
5d73d92f 4926 );\r
c37e0f16
CP		 4927 ShellPrintEx (-1, -1,\r
4928 L" PME Interrupt Enable(3): %E%d%N\r\n",\r
0c84a69f 4929 PciExpressCap->RootControl.Bits.PmeInterrupt\r
5d73d92f 4930 );\r
c37e0f16
CP		 4931 ShellPrintEx (-1, -1,\r
4932 L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
0c84a69f 4933 PciExpressCap->RootControl.Bits.CrsSoftwareVisibility\r
5d73d92f 4934 );\r
4935\r
4936 return EFI_SUCCESS;\r
4937}\r
4938\r
a1d4bfcc 4939/**\r
4940 Print out information of the device root capability information.\r
4941\r
4942 @param[in] PciExpressCap The pointer to the structure about the device.\r
4943\r
4944 @retval EFI_SUCCESS The operation was successful.\r
4945**/\r
5d73d92f 4946EFI_STATUS\r
4947ExplainPcieRootCap (\r
0c84a69f 4948 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4949 )\r
5d73d92f 4950{\r
c37e0f16
CP		 4951 ShellPrintEx (-1, -1,\r
4952 L" CRS Software Visibility(0): %E%d%N\r\n",\r
0c84a69f 4953 PciExpressCap->RootCapability.Bits.CrsSoftwareVisibility\r
5d73d92f 4954 );\r
4955\r
4956 return EFI_SUCCESS;\r
4957}\r
4958\r
a1d4bfcc 4959/**\r
4960 Print out information of the device root status information.\r
4961\r
4962 @param[in] PciExpressCap The pointer to the structure about the device.\r
4963\r
4964 @retval EFI_SUCCESS The operation was successful.\r
4965**/\r
5d73d92f 4966EFI_STATUS\r
4967ExplainPcieRootStatus (\r
0c84a69f 4968 IN PCI_CAPABILITY_PCIEXP *PciExpressCap\r
a1d4bfcc 4969 )\r
5d73d92f 4970{\r
c37e0f16
CP		 4971 ShellPrintEx (-1, -1,\r
4972 L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
0c84a69f 4973 PciExpressCap->RootStatus.Bits.PmeRequesterId\r
5d73d92f 4974 );\r
c37e0f16
CP		 4975 ShellPrintEx (-1, -1,\r
4976 L" PME Status(16): %E%d%N\r\n",\r
0c84a69f 4977 PciExpressCap->RootStatus.Bits.PmeStatus\r
5d73d92f 4978 );\r
c37e0f16
CP		 4979 ShellPrintEx (-1, -1,\r
4980 L" PME Pending(17): %E%d%N\r\n",\r
0c84a69f 4981 PciExpressCap->RootStatus.Bits.PmePending\r
5d73d92f 4982 );\r
4983 return EFI_SUCCESS;\r
4984}\r
4985\r
705bffb5
JC		 4986/**\r
4987 Function to interpret and print out the link control structure\r
4988\r
4989 @param[in] HeaderAddress The Address of this capability header.\r
4990 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4991**/\r
4992EFI_STATUS\r
705bffb5
JC		 4993PrintInterpretedExtendedCompatibilityLinkControl (\r
4994 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4995 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4996 )\r
4997{\r
4998 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
4999 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
5000\r
5001 ShellPrintHiiEx(\r
5002 -1, -1, NULL, \r
5003 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
5004 gShellDebug1HiiHandle, \r
5005 Header->RootComplexLinkCapabilities,\r
5006 Header->RootComplexLinkControl,\r
5007 Header->RootComplexLinkStatus\r
5008 ); \r
5009 DumpHex (\r
5010 4,\r
5011 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5012 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
5013 (VOID *) (HeaderAddress)\r
5014 );\r
5015 return (EFI_SUCCESS);\r
5016}\r
5017\r
5018/**\r
5019 Function to interpret and print out the power budgeting structure\r
5020\r
5021 @param[in] HeaderAddress The Address of this capability header.\r
5022 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5023**/\r
5024EFI_STATUS\r
705bffb5
JC		 5025PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
5026 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5027 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5028 )\r
5029{\r
5030 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
5031 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
5032\r
5033 ShellPrintHiiEx(\r
5034 -1, -1, NULL, \r
5035 STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
5036 gShellDebug1HiiHandle, \r
5037 Header->DataSelect,\r
5038 Header->Data,\r
5039 Header->PowerBudgetCapability\r
5040 ); \r
5041 DumpHex (\r
5042 4,\r
5043 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5044 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
5045 (VOID *) (HeaderAddress)\r
5046 );\r
5047 return (EFI_SUCCESS);\r
5048}\r
5049\r
5050/**\r
5051 Function to interpret and print out the ACS structure\r
5052\r
5053 @param[in] HeaderAddress The Address of this capability header.\r
5054 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5055**/\r
5056EFI_STATUS\r
705bffb5
JC		 5057PrintInterpretedExtendedCompatibilityAcs (\r
5058 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5059 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5060 )\r
5061{\r
5062 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r
5063 UINT16 VectorSize;\r
5064 UINT16 LoopCounter;\r
5065\r
5066 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r
5067 VectorSize = 0;\r
5068\r
5069 ShellPrintHiiEx(\r
5070 -1, -1, NULL, \r
5071 STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
5072 gShellDebug1HiiHandle, \r
5073 Header->AcsCapability,\r
5074 Header->AcsControl\r
5075 ); \r
5076 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
5077 VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
5078 if (VectorSize == 0) {\r
5079 VectorSize = 256;\r
5080 }\r
5081 for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
5082 ShellPrintHiiEx(\r
5083 -1, -1, NULL, \r
5084 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
5085 gShellDebug1HiiHandle, \r
5086 LoopCounter + 1,\r
5087 Header->EgressControlVectorArray[LoopCounter]\r
5088 ); \r
5089 }\r
5090 }\r
5091 DumpHex (\r
5092 4,\r
5093 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5094 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
5095 (VOID *) (HeaderAddress)\r
5096 );\r
5097 return (EFI_SUCCESS);\r
5098}\r
5099\r
5100/**\r
5101 Function to interpret and print out the latency tolerance reporting structure\r
5102\r
5103 @param[in] HeaderAddress The Address of this capability header.\r
5104 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5105**/\r
5106EFI_STATUS\r
705bffb5
JC		 5107PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
5108 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5109 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5110 )\r
5111{\r
5112 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
5113 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
5114\r
5115 ShellPrintHiiEx(\r
5116 -1, -1, NULL, \r
5117 STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
5118 gShellDebug1HiiHandle, \r
5119 Header->MaxSnoopLatency,\r
5120 Header->MaxNoSnoopLatency\r
5121 ); \r
5122 DumpHex (\r
5123 4,\r
5124 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5125 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
5126 (VOID *) (HeaderAddress)\r
5127 );\r
5128 return (EFI_SUCCESS);\r
5129}\r
5130\r
5131/**\r
5132 Function to interpret and print out the serial number structure\r
5133\r
5134 @param[in] HeaderAddress The Address of this capability header.\r
5135 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5136**/\r
5137EFI_STATUS\r
705bffb5
JC		 5138PrintInterpretedExtendedCompatibilitySerialNumber (\r
5139 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5140 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5141 )\r
5142{\r
5143 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
5144 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
5145\r
5146 ShellPrintHiiEx(\r
5147 -1, -1, NULL, \r
5148 STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
5149 gShellDebug1HiiHandle, \r
5150 Header->SerialNumber\r
5151 ); \r
5152 DumpHex (\r
5153 4,\r
5154 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5155 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
5156 (VOID *) (HeaderAddress)\r
5157 );\r
5158 return (EFI_SUCCESS);\r
5159}\r
5160\r
5161/**\r
5162 Function to interpret and print out the RCRB structure\r
5163\r
5164 @param[in] HeaderAddress The Address of this capability header.\r
5165 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5166**/\r
5167EFI_STATUS\r
705bffb5
JC		 5168PrintInterpretedExtendedCompatibilityRcrb (\r
5169 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5170 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5171 )\r
5172{\r
5173 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
5174 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
5175\r
5176 ShellPrintHiiEx(\r
5177 -1, -1, NULL, \r
5178 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
5179 gShellDebug1HiiHandle, \r
5180 Header->VendorId,\r
5181 Header->DeviceId,\r
5182 Header->RcrbCapabilities,\r
5183 Header->RcrbControl\r
5184 ); \r
5185 DumpHex (\r
5186 4,\r
5187 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5188 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
5189 (VOID *) (HeaderAddress)\r
5190 );\r
5191 return (EFI_SUCCESS);\r
5192}\r
5193\r
5194/**\r
5195 Function to interpret and print out the vendor specific structure\r
5196\r
5197 @param[in] HeaderAddress The Address of this capability header.\r
5198 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5199**/\r
5200EFI_STATUS\r
705bffb5
JC		 5201PrintInterpretedExtendedCompatibilityVendorSpecific (\r
5202 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5203 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5204 )\r
5205{\r
5206 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
5207 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
5208\r
5209 ShellPrintHiiEx(\r
5210 -1, -1, NULL, \r
5211 STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
5212 gShellDebug1HiiHandle, \r
5213 Header->VendorSpecificHeader\r
5214 ); \r
5215 DumpHex (\r
5216 4,\r
5217 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5218 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r
5219 (VOID *) (HeaderAddress)\r
5220 );\r
5221 return (EFI_SUCCESS);\r
5222}\r
5223\r
5224/**\r
5225 Function to interpret and print out the Event Collector Endpoint Association structure\r
5226\r
5227 @param[in] HeaderAddress The Address of this capability header.\r
5228 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5229**/\r
5230EFI_STATUS\r
705bffb5
JC		 5231PrintInterpretedExtendedCompatibilityECEA (\r
5232 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5233 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5234 )\r
5235{\r
5236 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
5237 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
5238\r
5239 ShellPrintHiiEx(\r
5240 -1, -1, NULL, \r
5241 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
5242 gShellDebug1HiiHandle, \r
5243 Header->AssociationBitmap\r
5244 ); \r
5245 DumpHex (\r
5246 4,\r
5247 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5248 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
5249 (VOID *) (HeaderAddress)\r
5250 );\r
5251 return (EFI_SUCCESS);\r
5252}\r
5253\r
5254/**\r
5255 Function to interpret and print out the ARI structure\r
5256\r
5257 @param[in] HeaderAddress The Address of this capability header.\r
5258 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5259**/\r
5260EFI_STATUS\r
705bffb5
JC		 5261PrintInterpretedExtendedCompatibilityAri (\r
5262 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5263 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5264 )\r
5265{\r
5266 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
5267 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
5268\r
5269 ShellPrintHiiEx(\r
5270 -1, -1, NULL, \r
5271 STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
5272 gShellDebug1HiiHandle, \r
5273 Header->AriCapability,\r
5274 Header->AriControl\r
5275 ); \r
5276 DumpHex (\r
5277 4,\r
5278 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5279 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
5280 (VOID *) (HeaderAddress)\r
5281 );\r
5282 return (EFI_SUCCESS);\r
5283}\r
5284\r
5285/**\r
5286 Function to interpret and print out the DPA structure\r
5287\r
5288 @param[in] HeaderAddress The Address of this capability header.\r
5289 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5290**/\r
5291EFI_STATUS\r
705bffb5
JC		 5292PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
5293 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5294 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5295 )\r
5296{\r
5297 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
5298 UINT8 LinkCount;\r
5299 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
5300\r
5301 ShellPrintHiiEx(\r
5302 -1, -1, NULL, \r
5303 STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
5304 gShellDebug1HiiHandle, \r
5305 Header->DpaCapability,\r
5306 Header->DpaLatencyIndicator,\r
5307 Header->DpaStatus,\r
5308 Header->DpaControl\r
5309 ); \r
5310 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
5311 ShellPrintHiiEx(\r
5312 -1, -1, NULL, \r
5313 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
5314 gShellDebug1HiiHandle, \r
5315 LinkCount+1,\r
5316 Header->DpaPowerAllocationArray[LinkCount]\r
5317 );\r
5318 }\r
5319 DumpHex (\r
5320 4,\r
5321 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5322 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r
5323 (VOID *) (HeaderAddress)\r
5324 );\r
5325 return (EFI_SUCCESS);\r
5326}\r
5327\r
5328/**\r
5329 Function to interpret and print out the link declaration structure\r
5330\r
5331 @param[in] HeaderAddress The Address of this capability header.\r
5332 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5333**/\r
5334EFI_STATUS\r
705bffb5
JC		 5335PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
5336 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5337 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5338 )\r
5339{\r
5340 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r
5341 UINT8 LinkCount;\r
5342 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
5343\r
5344 ShellPrintHiiEx(\r
5345 -1, -1, NULL, \r
5346 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
5347 gShellDebug1HiiHandle, \r
5348 Header->ElementSelfDescription\r
5349 );\r
5350\r
5351 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
5352 ShellPrintHiiEx(\r
5353 -1, -1, NULL, \r
5354 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
5355 gShellDebug1HiiHandle, \r
5356 LinkCount+1,\r
5357 Header->LinkEntry[LinkCount]\r
5358 );\r
5359 }\r
5360 DumpHex (\r
5361 4,\r
5362 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5363 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r
5364 (VOID *) (HeaderAddress)\r
5365 );\r
5366 return (EFI_SUCCESS);\r
5367}\r
5368\r
5369/**\r
5370 Function to interpret and print out the Advanced Error Reporting structure\r
5371\r
5372 @param[in] HeaderAddress The Address of this capability header.\r
5373 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5374**/\r
5375EFI_STATUS\r
705bffb5
JC		 5376PrintInterpretedExtendedCompatibilityAer (\r
5377 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5378 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5379 )\r
5380{\r
5381 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
5382 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
5383\r
5384 ShellPrintHiiEx(\r
5385 -1, -1, NULL, \r
5386 STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
5387 gShellDebug1HiiHandle, \r
5388 Header->UncorrectableErrorStatus,\r
5389 Header->UncorrectableErrorMask,\r
5390 Header->UncorrectableErrorSeverity,\r
5391 Header->CorrectableErrorStatus,\r
5392 Header->CorrectableErrorMask,\r
5393 Header->AdvancedErrorCapabilitiesAndControl,\r
231ad7d8
QS		 5394 Header->HeaderLog[0],\r
5395 Header->HeaderLog[1],\r
5396 Header->HeaderLog[2],\r
5397 Header->HeaderLog[3],\r
705bffb5
JC		 5398 Header->RootErrorCommand,\r
5399 Header->RootErrorStatus,\r
5400 Header->ErrorSourceIdentification,\r
5401 Header->CorrectableErrorSourceIdentification,\r
5402 Header->TlpPrefixLog[0],\r
5403 Header->TlpPrefixLog[1],\r
5404 Header->TlpPrefixLog[2],\r
5405 Header->TlpPrefixLog[3]\r
5406 );\r
5407 DumpHex (\r
5408 4,\r
5409 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5410 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
5411 (VOID *) (HeaderAddress)\r
5412 );\r
5413 return (EFI_SUCCESS);\r
5414}\r
5415\r
9f7f0697
JC		 5416/**\r
5417 Function to interpret and print out the multicast structure\r
5418\r
5419 @param[in] HeaderAddress The Address of this capability header.\r
5420 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5421 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5422**/\r
5423EFI_STATUS\r
9f7f0697
JC		 5424PrintInterpretedExtendedCompatibilityMulticast (\r
5425 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5426 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
0c84a69f 5427 IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r
9f7f0697
JC		 5428 )\r
5429{\r
5430 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
5431 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
5432\r
5433 ShellPrintHiiEx(\r
5434 -1, -1, NULL, \r
5435 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
5436 gShellDebug1HiiHandle, \r
5437 Header->MultiCastCapability,\r
5438 Header->MulticastControl,\r
5439 Header->McBaseAddress,\r
5440 Header->McReceiveAddress,\r
5441 Header->McBlockAll,\r
5442 Header->McBlockUntranslated,\r
5443 Header->McOverlayBar\r
5444 );\r
5445\r
5446 DumpHex (\r
5447 4,\r
5448 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5449 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
5450 (VOID *) (HeaderAddress)\r
5451 );\r
5452\r
5453 return (EFI_SUCCESS);\r
5454}\r
5455\r
5456/**\r
5457 Function to interpret and print out the virtual channel and multi virtual channel structure\r
5458\r
5459 @param[in] HeaderAddress The Address of this capability header.\r
5460 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5461**/\r
5462EFI_STATUS\r
9f7f0697
JC		 5463PrintInterpretedExtendedCompatibilityVirtualChannel (\r
5464 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5465 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5466 )\r
5467{\r
5468 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
5469 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
5470 UINT32 ItemCount;\r
5471 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
5472\r
5473 ShellPrintHiiEx(\r
5474 -1, -1, NULL, \r
5475 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
5476 gShellDebug1HiiHandle, \r
5477 Header->ExtendedVcCount,\r
5478 Header->PortVcCapability1,\r
5479 Header->PortVcCapability2,\r
5480 Header->VcArbTableOffset,\r
5481 Header->PortVcControl,\r
5482 Header->PortVcStatus\r
5483 );\r
5484 for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
5485 CapabilityItem = &Header->Capability[ItemCount];\r
5486 ShellPrintHiiEx(\r
5487 -1, -1, NULL, \r
5488 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
5489 gShellDebug1HiiHandle, \r
5490 ItemCount+1,\r
5491 CapabilityItem->VcResourceCapability,\r
5492 CapabilityItem->PortArbTableOffset,\r
5493 CapabilityItem->VcResourceControl,\r
5494 CapabilityItem->VcResourceStatus\r
5495 );\r
5496 }\r
5497\r
5498 DumpHex (\r
5499 4,\r
5500 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
26ca6f7e
RN		 5501 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY)\r
5502 + Header->ExtendedVcCount * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC),\r
9f7f0697
JC		 5503 (VOID *) (HeaderAddress)\r
5504 );\r
5505\r
5506 return (EFI_SUCCESS);\r
5507}\r
5508\r
5509/**\r
5510 Function to interpret and print out the resizeable bar structure\r
5511\r
5512 @param[in] HeaderAddress The Address of this capability header.\r
5513 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5514**/\r
5515EFI_STATUS\r
9f7f0697
JC		 5516PrintInterpretedExtendedCompatibilityResizeableBar (\r
5517 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5518 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5519 )\r
5520{\r
5521 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
5522 UINT32 ItemCount;\r
5523 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
5524\r
5525 for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
5526 ShellPrintHiiEx(\r
5527 -1, -1, NULL, \r
5528 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
5529 gShellDebug1HiiHandle, \r
5530 ItemCount+1,\r
5531 Header->Capability[ItemCount].ResizableBarCapability,\r
5532 Header->Capability[ItemCount].ResizableBarControl\r
5533 );\r
5534 }\r
5535\r
5536 DumpHex (\r
5537 4,\r
5538 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5539 (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
5540 (VOID *) (HeaderAddress)\r
5541 );\r
5542\r
5543 return (EFI_SUCCESS);\r
5544}\r
5545\r
5546/**\r
5547 Function to interpret and print out the TPH structure\r
5548\r
5549 @param[in] HeaderAddress The Address of this capability header.\r
5550 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5551**/\r
5552EFI_STATUS\r
9f7f0697
JC		 5553PrintInterpretedExtendedCompatibilityTph (\r
5554 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5555 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5556 )\r
5557{\r
5558 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
5559 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
5560\r
5561 ShellPrintHiiEx(\r
5562 -1, -1, NULL, \r
5563 STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
5564 gShellDebug1HiiHandle, \r
5565 Header->TphRequesterCapability,\r
5566 Header->TphRequesterControl\r
5567 );\r
5568 DumpHex (\r
5569 8,\r
5570 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
5571 GET_TPH_TABLE_SIZE(Header),\r
5572 (VOID *)Header->TphStTable\r
5573 );\r
5574\r
5575 DumpHex (\r
5576 4,\r
5577 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5578 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
5579 (VOID *) (HeaderAddress)\r
5580 );\r
5581\r
5582 return (EFI_SUCCESS);\r
5583}\r
5584\r
5585/**\r
5586 Function to interpret and print out the secondary PCIe capability structure\r
5587\r
5588 @param[in] HeaderAddress The Address of this capability header.\r
5589 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5590 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5591**/\r
5592EFI_STATUS\r
9f7f0697
JC		 5593PrintInterpretedExtendedCompatibilitySecondary (\r
5594 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5595 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
0c84a69f 5596 IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCap\r
9f7f0697
JC		 5597 )\r
5598{\r
5599 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
5600 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
5601\r
5602 ShellPrintHiiEx(\r
5603 -1, -1, NULL, \r
5604 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
5605 gShellDebug1HiiHandle, \r
0c84a69f 5606 Header->LinkControl3.Uint32,\r
9f7f0697
JC		 5607 Header->LaneErrorStatus\r
5608 );\r
5609 DumpHex (\r
5610 8,\r
5611 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
0c84a69f 5612 PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r
9f7f0697
JC		 5613 (VOID *)Header->EqualizationControl\r
5614 );\r
5615\r
5616 DumpHex (\r
5617 4,\r
5618 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
0c84a69f
RN		 5619 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE) - sizeof (Header->EqualizationControl)\r
5620 + PciExpressCap->LinkCapability.Bits.MaxLinkWidth * sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL),\r
9f7f0697
JC		 5621 (VOID *) (HeaderAddress)\r
5622 );\r
5623\r
5624 return (EFI_SUCCESS);\r
5625}\r
5626\r
705bffb5
JC		 5627/**\r
5628 Display Pcie extended capability details\r
5629\r
5630 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5631 @param[in] HeaderAddress The address of this capability header.\r
5632 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5633**/\r
5634EFI_STATUS\r
705bffb5
JC		 5635PrintPciExtendedCapabilityDetails(\r
5636 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
5637 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
0c84a69f 5638 IN CONST PCI_CAPABILITY_PCIEXP *PciExpressCapPtr\r
705bffb5
JC		 5639 )\r
5640{\r
5641 switch (HeaderAddress->CapabilityId){\r
5642 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
5643 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5644 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
5645 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5646 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
5647 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5648 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
5649 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5650 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
5651 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5652 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
5653 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5654 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
5655 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5656 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
5657 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5658 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
5659 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5660 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
5661 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5662 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
5663 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5664 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
5665 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5666 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
5667 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
9f7f0697 5668 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
705bffb5 5669 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
9f7f0697
JC		 5670 //\r
5671 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
5672 //\r
5673 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
705bffb5 5674 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
9f7f0697 5675 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
705bffb5 5676 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
9f7f0697 5677 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
705bffb5 5678 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
9f7f0697 5679 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
705bffb5
JC		 5680 default:\r
5681 ShellPrintEx (-1, -1,\r
5682 L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
5683 HeaderAddress->CapabilityId\r
5684 );\r
5685 return EFI_SUCCESS;\r
705bffb5
JC		 5686 };\r
5687\r
5688}\r
5689\r
a1d4bfcc 5690/**\r
5691 Display Pcie device structure.\r
5692\r
33cc487c
RN		 5693 @param[in] PciExpressCap PCI Express capability buffer.\r
5694 @param[in] ExtendedConfigSpace PCI Express extended configuration space.\r
5695 @param[in] ExtendedCapability PCI Express extended capability ID to explain.\r
a1d4bfcc 5696**/\r
33cc487c 5697VOID\r
5d73d92f 5698PciExplainPciExpress (\r
33cc487c
RN		 5699 IN PCI_CAPABILITY_PCIEXP *PciExpressCap,\r
5700 IN UINT8 *ExtendedConfigSpace,\r
5701 IN CONST UINT16 ExtendedCapability\r
5d73d92f 5702 )\r
5703{\r
0c84a69f
RN		 5704 UINT8 DevicePortType;\r
5705 UINTN Index;\r
5706 UINT8 *RegAddr;\r
5707 UINTN RegValue;\r
5708 PCI_EXP_EXT_HDR *ExtHdr;\r
5d73d92f 5709\r
33cc487c 5710 DevicePortType = (UINT8)PciExpressCap->Capability.Bits.DevicePortType;\r
5d73d92f 5711\r
c37e0f16 5712 ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
5d73d92f 5713\r
5714 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
5715 if (ShellGetExecutionBreakFlag()) {\r
33cc487c 5716 return;\r
5d73d92f 5717 }\r
33cc487c 5718 RegAddr = (UINT8 *) PciExpressCap + PcieExplainList[Index].Offset;\r
5d73d92f 5719 switch (PcieExplainList[Index].Width) {\r
5720 case FieldWidthUINT8:\r
5721 RegValue = *(UINT8 *) RegAddr;\r
5722 break;\r
5723 case FieldWidthUINT16:\r
5724 RegValue = *(UINT16 *) RegAddr;\r
5725 break;\r
5726 case FieldWidthUINT32:\r
5727 RegValue = *(UINT32 *) RegAddr;\r
5728 break;\r
5729 default:\r
5730 RegValue = 0;\r
5731 break;\r
5732 }\r
5733 ShellPrintHiiEx(-1, -1, NULL,\r
5734 PcieExplainList[Index].Token,\r
5735 gShellDebug1HiiHandle,\r
5736 PcieExplainList[Index].Offset,\r
5737 RegValue\r
5738 );\r
5739 if (PcieExplainList[Index].Func == NULL) {\r
5740 continue;\r
5741 }\r
5742 switch (PcieExplainList[Index].Type) {\r
5743 case PcieExplainTypeLink:\r
5744 //\r
5745 // Link registers should not be used by\r
5746 // a) Root Complex Integrated Endpoint\r
5747 // b) Root Complex Event Collector\r
5748 //\r
0c84a69f
RN		 5749 if (DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT ||\r
5750 DevicePortType == PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
5d73d92f 5751 continue;\r
5752 }\r
5753 break;\r
5754 case PcieExplainTypeSlot:\r
5755 //\r
5756 // Slot registers are only valid for\r
5757 // a) Root Port of PCI Express Root Complex\r
5758 // b) Downstream Port of PCI Express Switch\r
5759 // and when SlotImplemented bit is set in PCIE cap register.\r
5760 //\r
0c84a69f
RN		 5761 if ((DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT &&\r
5762 DevicePortType != PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT) ||\r
33cc487c 5763 !PciExpressCap->Capability.Bits.SlotImplemented) {\r
5d73d92f 5764 continue;\r
5765 }\r
5766 break;\r
5767 case PcieExplainTypeRoot:\r
5768 //\r
5769 // Root registers are only valid for\r
5770 // Root Port of PCI Express Root Complex\r
5771 //\r
0c84a69f 5772 if (DevicePortType != PCIE_DEVICE_PORT_TYPE_ROOT_PORT) {\r
5d73d92f 5773 continue;\r
5774 }\r
5775 break;\r
5776 default:\r
5777 break;\r
5778 }\r
33cc487c 5779 PcieExplainList[Index].Func (PciExpressCap);\r
5d73d92f 5780 }\r
5781\r
33cc487c 5782 ExtHdr = (PCI_EXP_EXT_HDR*)ExtendedConfigSpace;\r
c831a2c3 5783 while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
705bffb5 5784 //\r
c831a2c3 5785 // Process this item\r
705bffb5 5786 //\r
33cc487c 5787 if (ExtendedCapability == 0xFFFF || ExtendedCapability == ExtHdr->CapabilityId) {\r
705bffb5 5788 //\r
c831a2c3 5789 // Print this item\r
705bffb5 5790 //\r
33cc487c 5791 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExtendedConfigSpace, ExtHdr, PciExpressCap);\r
c831a2c3 5792 }\r
5d73d92f 5793\r
c831a2c3
RN		 5794 //\r
5795 // Advance to the next item if it exists\r
5796 //\r
5797 if (ExtHdr->NextCapabilityOffset != 0) {\r
33cc487c 5798 ExtHdr = (PCI_EXP_EXT_HDR*)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
c831a2c3
RN		 5799 } else {\r
5800 break;\r
705bffb5 5801 }\r
d8f8021c 5802 }\r
5d73d92f 5803}\r
EFI Development Kit II mirror for PVE