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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
231ad7d8
QS		 4 Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>\r
5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r
5d73d92f 7 This program and the accompanying materials\r
8 are licensed and made available under the terms and conditions of the BSD License\r
9 which accompanies this distribution. The full text of the license may be found at\r
10 http://opensource.org/licenses/bsd-license.php\r
11\r
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#include "UefiShellDebug1CommandsLib.h"\r
18#include <Protocol/PciRootBridgeIo.h>\r
19#include <Library/ShellLib.h>\r
20#include <IndustryStandard/Pci.h>\r
21#include <IndustryStandard/Acpi.h>\r
22#include "Pci.h"\r
23\r
5d73d92f 24//\r
25// Printable strings for Pci class code\r
26//\r
27typedef struct {\r
28 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
29 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
30 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
31} PCI_CLASS_STRINGS;\r
32\r
33//\r
34// a structure holding a single entry, which also points to its lower level\r
35// class\r
36//\r
37typedef struct PCI_CLASS_ENTRY_TAG {\r
38 UINT8 Code; // Class, subclass or I/F code\r
39 CHAR16 *DescText; // Description string\r
40 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
41} PCI_CLASS_ENTRY;\r
42\r
43//\r
44// Declarations of entries which contain printable strings for class codes\r
45// in PCI configuration space\r
46//\r
47PCI_CLASS_ENTRY PCIBlankEntry[];\r
48PCI_CLASS_ENTRY PCISubClass_00[];\r
49PCI_CLASS_ENTRY PCISubClass_01[];\r
50PCI_CLASS_ENTRY PCISubClass_02[];\r
51PCI_CLASS_ENTRY PCISubClass_03[];\r
52PCI_CLASS_ENTRY PCISubClass_04[];\r
53PCI_CLASS_ENTRY PCISubClass_05[];\r
54PCI_CLASS_ENTRY PCISubClass_06[];\r
55PCI_CLASS_ENTRY PCISubClass_07[];\r
56PCI_CLASS_ENTRY PCISubClass_08[];\r
57PCI_CLASS_ENTRY PCISubClass_09[];\r
58PCI_CLASS_ENTRY PCISubClass_0a[];\r
59PCI_CLASS_ENTRY PCISubClass_0b[];\r
60PCI_CLASS_ENTRY PCISubClass_0c[];\r
61PCI_CLASS_ENTRY PCISubClass_0d[];\r
62PCI_CLASS_ENTRY PCISubClass_0e[];\r
63PCI_CLASS_ENTRY PCISubClass_0f[];\r
64PCI_CLASS_ENTRY PCISubClass_10[];\r
65PCI_CLASS_ENTRY PCISubClass_11[];\r
f056e4c1
JC		 66PCI_CLASS_ENTRY PCISubClass_12[];\r
67PCI_CLASS_ENTRY PCISubClass_13[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0100[];\r
5d73d92f 69PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
f056e4c1
JC		 70PCI_CLASS_ENTRY PCIPIFClass_0105[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0106[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0107[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0108[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0109[];\r
5d73d92f 75PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
f056e4c1
JC		 77PCI_CLASS_ENTRY PCIPIFClass_0609[];\r
78PCI_CLASS_ENTRY PCIPIFClass_060b[];\r
5d73d92f 79PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
80PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
81PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
82PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
83PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
84PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
85PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
86PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
87PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
88PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
f056e4c1
JC		 89PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r
90PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r
5d73d92f 91PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
92\r
93//\r
94// Base class strings entries\r
95//\r
96PCI_CLASS_ENTRY gClassStringList[] = {\r
97 {\r
98 0x00,\r
99 L"Pre 2.0 device",\r
100 PCISubClass_00\r
101 },\r
102 {\r
103 0x01,\r
104 L"Mass Storage Controller",\r
105 PCISubClass_01\r
106 },\r
107 {\r
108 0x02,\r
109 L"Network Controller",\r
110 PCISubClass_02\r
111 },\r
112 {\r
113 0x03,\r
114 L"Display Controller",\r
115 PCISubClass_03\r
116 },\r
117 {\r
118 0x04,\r
119 L"Multimedia Device",\r
120 PCISubClass_04\r
121 },\r
122 {\r
123 0x05,\r
124 L"Memory Controller",\r
125 PCISubClass_05\r
126 },\r
127 {\r
128 0x06,\r
129 L"Bridge Device",\r
130 PCISubClass_06\r
131 },\r
132 {\r
133 0x07,\r
134 L"Simple Communications Controllers",\r
135 PCISubClass_07\r
136 },\r
137 {\r
138 0x08,\r
139 L"Base System Peripherals",\r
140 PCISubClass_08\r
141 },\r
142 {\r
143 0x09,\r
144 L"Input Devices",\r
145 PCISubClass_09\r
146 },\r
147 {\r
148 0x0a,\r
149 L"Docking Stations",\r
150 PCISubClass_0a\r
151 },\r
152 {\r
153 0x0b,\r
154 L"Processors",\r
155 PCISubClass_0b\r
156 },\r
157 {\r
158 0x0c,\r
159 L"Serial Bus Controllers",\r
160 PCISubClass_0c\r
161 },\r
162 {\r
163 0x0d,\r
164 L"Wireless Controllers",\r
165 PCISubClass_0d\r
166 },\r
167 {\r
168 0x0e,\r
169 L"Intelligent IO Controllers",\r
170 PCISubClass_0e\r
171 },\r
172 {\r
173 0x0f,\r
174 L"Satellite Communications Controllers",\r
175 PCISubClass_0f\r
176 },\r
177 {\r
178 0x10,\r
179 L"Encryption/Decryption Controllers",\r
180 PCISubClass_10\r
181 },\r
182 {\r
183 0x11,\r
184 L"Data Acquisition & Signal Processing Controllers",\r
185 PCISubClass_11\r
186 },\r
f056e4c1
JC		 187 {\r
188 0x12,\r
189 L"Processing Accelerators",\r
190 PCISubClass_12\r
191 },\r
192 {\r
193 0x13,\r
194 L"Non-Essential Instrumentation",\r
195 PCISubClass_13\r
196 },\r
5d73d92f 197 {\r
198 0xff,\r
199 L"Device does not fit in any defined classes",\r
200 PCIBlankEntry\r
201 },\r
202 {\r
203 0x00,\r
204 NULL,\r
205 /* null string ends the list */NULL\r
206 }\r
207};\r
208\r
209//\r
210// Subclass strings entries\r
211//\r
212PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
213 {\r
214 0x00,\r
215 L"",\r
216 PCIBlankEntry\r
217 },\r
218 {\r
219 0x00,\r
220 NULL,\r
221 /* null string ends the list */NULL\r
222 }\r
223};\r
224\r
225PCI_CLASS_ENTRY PCISubClass_00[] = {\r
226 {\r
227 0x00,\r
228 L"All devices other than VGA",\r
229 PCIBlankEntry\r
230 },\r
231 {\r
232 0x01,\r
233 L"VGA-compatible devices",\r
234 PCIBlankEntry\r
235 },\r
236 {\r
237 0x00,\r
238 NULL,\r
239 /* null string ends the list */NULL\r
240 }\r
241};\r
242\r
243PCI_CLASS_ENTRY PCISubClass_01[] = {\r
244 {\r
245 0x00,\r
f056e4c1
JC		 246 L"SCSI",\r
247 PCIPIFClass_0100\r
5d73d92f 248 },\r
249 {\r
250 0x01,\r
251 L"IDE controller",\r
252 PCIPIFClass_0101\r
253 },\r
254 {\r
255 0x02,\r
256 L"Floppy disk controller",\r
257 PCIBlankEntry\r
258 },\r
259 {\r
260 0x03,\r
261 L"IPI controller",\r
262 PCIBlankEntry\r
263 },\r
264 {\r
265 0x04,\r
266 L"RAID controller",\r
267 PCIBlankEntry\r
268 },\r
f056e4c1
JC		 269 {\r
270 0x05,\r
271 L"ATA controller with ADMA interface",\r
272 PCIPIFClass_0105\r
273 },\r
274 {\r
275 0x06,\r
276 L"Serial ATA controller",\r
277 PCIPIFClass_0106\r
278 },\r
279 {\r
280 0x07,\r
281 L"Serial Attached SCSI (SAS) controller ",\r
282 PCIPIFClass_0107\r
283 },\r
284 {\r
285 0x08,\r
286 L"Non-volatile memory subsystem",\r
287 PCIPIFClass_0108\r
288 },\r
289 {\r
290 0x09,\r
291 L"Universal Flash Storage (UFS) controller ",\r
292 PCIPIFClass_0109\r
293 },\r
5d73d92f 294 {\r
295 0x80,\r
296 L"Other mass storage controller",\r
297 PCIBlankEntry\r
298 },\r
299 {\r
300 0x00,\r
301 NULL,\r
302 /* null string ends the list */NULL\r
303 }\r
304};\r
305\r
306PCI_CLASS_ENTRY PCISubClass_02[] = {\r
307 {\r
308 0x00,\r
309 L"Ethernet controller",\r
310 PCIBlankEntry\r
311 },\r
312 {\r
313 0x01,\r
314 L"Token ring controller",\r
315 PCIBlankEntry\r
316 },\r
317 {\r
318 0x02,\r
319 L"FDDI controller",\r
320 PCIBlankEntry\r
321 },\r
322 {\r
323 0x03,\r
324 L"ATM controller",\r
325 PCIBlankEntry\r
326 },\r
327 {\r
328 0x04,\r
329 L"ISDN controller",\r
330 PCIBlankEntry\r
331 },\r
f056e4c1
JC		 332 {\r
333 0x05,\r
334 L"WorldFip controller",\r
335 PCIBlankEntry\r
336 },\r
337 {\r
338 0x06,\r
339 L"PICMG 2.14 Multi Computing",\r
340 PCIBlankEntry\r
341 },\r
342 {\r
343 0x07,\r
344 L"InfiniBand controller",\r
345 PCIBlankEntry\r
346 },\r
5d73d92f 347 {\r
348 0x80,\r
349 L"Other network controller",\r
350 PCIBlankEntry\r
351 },\r
352 {\r
353 0x00,\r
354 NULL,\r
355 /* null string ends the list */NULL\r
356 }\r
357};\r
358\r
359PCI_CLASS_ENTRY PCISubClass_03[] = {\r
360 {\r
361 0x00,\r
362 L"VGA/8514 controller",\r
363 PCIPIFClass_0300\r
364 },\r
365 {\r
366 0x01,\r
367 L"XGA controller",\r
368 PCIBlankEntry\r
369 },\r
370 {\r
371 0x02,\r
372 L"3D controller",\r
373 PCIBlankEntry\r
374 },\r
375 {\r
376 0x80,\r
377 L"Other display controller",\r
378 PCIBlankEntry\r
379 },\r
380 {\r
381 0x00,\r
382 NULL,\r
383 /* null string ends the list */PCIBlankEntry\r
384 }\r
385};\r
386\r
387PCI_CLASS_ENTRY PCISubClass_04[] = {\r
388 {\r
389 0x00,\r
390 L"Video device",\r
391 PCIBlankEntry\r
392 },\r
393 {\r
394 0x01,\r
395 L"Audio device",\r
396 PCIBlankEntry\r
397 },\r
398 {\r
399 0x02,\r
400 L"Computer Telephony device",\r
401 PCIBlankEntry\r
402 },\r
f056e4c1
JC		 403 {\r
404 0x03,\r
405 L"Mixed mode device",\r
406 PCIBlankEntry\r
407 },\r
5d73d92f 408 {\r
409 0x80,\r
410 L"Other multimedia device",\r
411 PCIBlankEntry\r
412 },\r
413 {\r
414 0x00,\r
415 NULL,\r
416 /* null string ends the list */NULL\r
417 }\r
418};\r
419\r
420PCI_CLASS_ENTRY PCISubClass_05[] = {\r
421 {\r
422 0x00,\r
423 L"RAM memory controller",\r
424 PCIBlankEntry\r
425 },\r
426 {\r
427 0x01,\r
428 L"Flash memory controller",\r
429 PCIBlankEntry\r
430 },\r
431 {\r
432 0x80,\r
433 L"Other memory controller",\r
434 PCIBlankEntry\r
435 },\r
436 {\r
437 0x00,\r
438 NULL,\r
439 /* null string ends the list */NULL\r
440 }\r
441};\r
442\r
443PCI_CLASS_ENTRY PCISubClass_06[] = {\r
444 {\r
445 0x00,\r
446 L"Host/PCI bridge",\r
447 PCIBlankEntry\r
448 },\r
449 {\r
450 0x01,\r
451 L"PCI/ISA bridge",\r
452 PCIBlankEntry\r
453 },\r
454 {\r
455 0x02,\r
456 L"PCI/EISA bridge",\r
457 PCIBlankEntry\r
458 },\r
459 {\r
460 0x03,\r
461 L"PCI/Micro Channel bridge",\r
462 PCIBlankEntry\r
463 },\r
464 {\r
465 0x04,\r
466 L"PCI/PCI bridge",\r
467 PCIPIFClass_0604\r
468 },\r
469 {\r
470 0x05,\r
471 L"PCI/PCMCIA bridge",\r
472 PCIBlankEntry\r
473 },\r
474 {\r
475 0x06,\r
476 L"NuBus bridge",\r
477 PCIBlankEntry\r
478 },\r
479 {\r
480 0x07,\r
481 L"CardBus bridge",\r
482 PCIBlankEntry\r
483 },\r
484 {\r
485 0x08,\r
486 L"RACEway bridge",\r
487 PCIBlankEntry\r
488 },\r
f056e4c1
JC		 489 {\r
490 0x09,\r
491 L"Semi-transparent PCI-to-PCI bridge",\r
492 PCIPIFClass_0609\r
493 },\r
494 {\r
495 0x0A,\r
496 L"InfiniBand-to-PCI host bridge",\r
497 PCIBlankEntry\r
498 },\r
499 {\r
500 0x0B,\r
501 L"Advanced Switching to PCI host bridge",\r
502 PCIPIFClass_060b\r
503 },\r
5d73d92f 504 {\r
505 0x80,\r
506 L"Other bridge type",\r
507 PCIBlankEntry\r
508 },\r
509 {\r
510 0x00,\r
511 NULL,\r
512 /* null string ends the list */NULL\r
513 }\r
514};\r
515\r
516PCI_CLASS_ENTRY PCISubClass_07[] = {\r
517 {\r
518 0x00,\r
519 L"Serial controller",\r
520 PCIPIFClass_0700\r
521 },\r
522 {\r
523 0x01,\r
524 L"Parallel port",\r
525 PCIPIFClass_0701\r
526 },\r
527 {\r
528 0x02,\r
529 L"Multiport serial controller",\r
530 PCIBlankEntry\r
531 },\r
532 {\r
533 0x03,\r
534 L"Modem",\r
535 PCIPIFClass_0703\r
536 },\r
f056e4c1
JC		 537 {\r
538 0x04,\r
539 L"GPIB (IEEE 488.1/2) controller",\r
540 PCIBlankEntry\r
541 },\r
542 {\r
543 0x05,\r
544 L"Smart Card",\r
545 PCIBlankEntry\r
546 },\r
5d73d92f 547 {\r
548 0x80,\r
549 L"Other communication device",\r
550 PCIBlankEntry\r
551 },\r
552 {\r
553 0x00,\r
554 NULL,\r
555 /* null string ends the list */NULL\r
556 }\r
557};\r
558\r
559PCI_CLASS_ENTRY PCISubClass_08[] = {\r
560 {\r
561 0x00,\r
562 L"PIC",\r
563 PCIPIFClass_0800\r
564 },\r
565 {\r
566 0x01,\r
567 L"DMA controller",\r
568 PCIPIFClass_0801\r
569 },\r
570 {\r
571 0x02,\r
572 L"System timer",\r
573 PCIPIFClass_0802\r
574 },\r
575 {\r
576 0x03,\r
577 L"RTC controller",\r
578 PCIPIFClass_0803\r
579 },\r
580 {\r
581 0x04,\r
582 L"Generic PCI Hot-Plug controller",\r
583 PCIBlankEntry\r
584 },\r
f056e4c1
JC		 585 {\r
586 0x05,\r
587 L"SD Host controller",\r
588 PCIBlankEntry\r
589 },\r
590 {\r
591 0x06,\r
592 L"IOMMU",\r
593 PCIBlankEntry\r
594 },\r
595 {\r
596 0x07,\r
597 L"Root Complex Event Collector",\r
598 PCIBlankEntry\r
599 },\r
5d73d92f 600 {\r
601 0x80,\r
602 L"Other system peripheral",\r
603 PCIBlankEntry\r
604 },\r
605 {\r
606 0x00,\r
607 NULL,\r
608 /* null string ends the list */NULL\r
609 }\r
610};\r
611\r
612PCI_CLASS_ENTRY PCISubClass_09[] = {\r
613 {\r
614 0x00,\r
615 L"Keyboard controller",\r
616 PCIBlankEntry\r
617 },\r
618 {\r
619 0x01,\r
620 L"Digitizer (pen)",\r
621 PCIBlankEntry\r
622 },\r
623 {\r
624 0x02,\r
625 L"Mouse controller",\r
626 PCIBlankEntry\r
627 },\r
628 {\r
629 0x03,\r
630 L"Scanner controller",\r
631 PCIBlankEntry\r
632 },\r
633 {\r
634 0x04,\r
635 L"Gameport controller",\r
636 PCIPIFClass_0904\r
637 },\r
638 {\r
639 0x80,\r
640 L"Other input controller",\r
641 PCIBlankEntry\r
642 },\r
643 {\r
644 0x00,\r
645 NULL,\r
646 /* null string ends the list */NULL\r
647 }\r
648};\r
649\r
650PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
651 {\r
652 0x00,\r
653 L"Generic docking station",\r
654 PCIBlankEntry\r
655 },\r
656 {\r
657 0x80,\r
658 L"Other type of docking station",\r
659 PCIBlankEntry\r
660 },\r
661 {\r
662 0x00,\r
663 NULL,\r
664 /* null string ends the list */NULL\r
665 }\r
666};\r
667\r
668PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
669 {\r
670 0x00,\r
671 L"386",\r
672 PCIBlankEntry\r
673 },\r
674 {\r
675 0x01,\r
676 L"486",\r
677 PCIBlankEntry\r
678 },\r
679 {\r
680 0x02,\r
681 L"Pentium",\r
682 PCIBlankEntry\r
683 },\r
684 {\r
685 0x10,\r
686 L"Alpha",\r
687 PCIBlankEntry\r
688 },\r
689 {\r
690 0x20,\r
691 L"PowerPC",\r
692 PCIBlankEntry\r
693 },\r
694 {\r
695 0x30,\r
696 L"MIPS",\r
697 PCIBlankEntry\r
698 },\r
699 {\r
700 0x40,\r
701 L"Co-processor",\r
702 PCIBlankEntry\r
703 },\r
704 {\r
705 0x80,\r
706 L"Other processor",\r
707 PCIBlankEntry\r
708 },\r
709 {\r
710 0x00,\r
711 NULL,\r
712 /* null string ends the list */NULL\r
713 }\r
714};\r
715\r
716PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
717 {\r
718 0x00,\r
f056e4c1
JC		 719 L"IEEE 1394",\r
720 PCIPIFClass_0c00\r
5d73d92f 721 },\r
722 {\r
723 0x01,\r
724 L"ACCESS.bus",\r
725 PCIBlankEntry\r
726 },\r
727 {\r
728 0x02,\r
729 L"SSA",\r
730 PCIBlankEntry\r
731 },\r
732 {\r
733 0x03,\r
734 L"USB",\r
f056e4c1 735 PCIPIFClass_0c03\r
5d73d92f 736 },\r
737 {\r
738 0x04,\r
739 L"Fibre Channel",\r
740 PCIBlankEntry\r
741 },\r
742 {\r
743 0x05,\r
744 L"System Management Bus",\r
745 PCIBlankEntry\r
746 },\r
f056e4c1
JC		 747 {\r
748 0x06,\r
749 L"InfiniBand",\r
750 PCIBlankEntry\r
751 },\r
752 {\r
753 0x07,\r
754 L"IPMI",\r
755 PCIPIFClass_0c07\r
756 },\r
757 {\r
758 0x08,\r
759 L"SERCOS Interface Standard (IEC 61491)",\r
760 PCIBlankEntry\r
761 },\r
762 {\r
763 0x09,\r
764 L"CANbus",\r
765 PCIBlankEntry\r
766 },\r
5d73d92f 767 {\r
768 0x80,\r
769 L"Other bus type",\r
770 PCIBlankEntry\r
771 },\r
772 {\r
773 0x00,\r
774 NULL,\r
775 /* null string ends the list */NULL\r
776 }\r
777};\r
778\r
779PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
780 {\r
781 0x00,\r
782 L"iRDA compatible controller",\r
783 PCIBlankEntry\r
784 },\r
785 {\r
786 0x01,\r
f056e4c1
JC		 787 L"",\r
788 PCIPIFClass_0d01\r
5d73d92f 789 },\r
790 {\r
791 0x10,\r
792 L"RF controller",\r
793 PCIBlankEntry\r
794 },\r
f056e4c1
JC		 795 {\r
796 0x11,\r
797 L"Bluetooth",\r
798 PCIBlankEntry\r
799 },\r
800 {\r
801 0x12,\r
802 L"Broadband",\r
803 PCIBlankEntry\r
804 },\r
805 {\r
806 0x20,\r
59577231 807 L"Ethernet (802.11a - 5 GHz)",\r
f056e4c1
JC		 808 PCIBlankEntry\r
809 },\r
810 {\r
811 0x21,\r
59577231 812 L"Ethernet (802.11b - 2.4 GHz)",\r
f056e4c1
JC		 813 PCIBlankEntry\r
814 },\r
5d73d92f 815 {\r
816 0x80,\r
817 L"Other type of wireless controller",\r
818 PCIBlankEntry\r
819 },\r
820 {\r
821 0x00,\r
822 NULL,\r
823 /* null string ends the list */NULL\r
824 }\r
825};\r
826\r
827PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
828 {\r
829 0x00,\r
830 L"I2O Architecture",\r
831 PCIPIFClass_0e00\r
832 },\r
833 {\r
834 0x00,\r
835 NULL,\r
836 /* null string ends the list */NULL\r
837 }\r
838};\r
839\r
840PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
841 {\r
f056e4c1 842 0x01,\r
5d73d92f 843 L"TV",\r
844 PCIBlankEntry\r
845 },\r
846 {\r
f056e4c1 847 0x02,\r
5d73d92f 848 L"Audio",\r
849 PCIBlankEntry\r
850 },\r
851 {\r
f056e4c1 852 0x03,\r
5d73d92f 853 L"Voice",\r
854 PCIBlankEntry\r
855 },\r
856 {\r
f056e4c1 857 0x04,\r
5d73d92f 858 L"Data",\r
859 PCIBlankEntry\r
860 },\r
f056e4c1
JC		 861 {\r
862 0x80,\r
863 L"Other satellite communication controller",\r
864 PCIBlankEntry\r
865 },\r
5d73d92f 866 {\r
867 0x00,\r
868 NULL,\r
869 /* null string ends the list */NULL\r
870 }\r
871};\r
872\r
873PCI_CLASS_ENTRY PCISubClass_10[] = {\r
874 {\r
875 0x00,\r
876 L"Network & computing Encrypt/Decrypt",\r
877 PCIBlankEntry\r
878 },\r
879 {\r
880 0x01,\r
881 L"Entertainment Encrypt/Decrypt",\r
882 PCIBlankEntry\r
883 },\r
884 {\r
885 0x80,\r
886 L"Other Encrypt/Decrypt",\r
887 PCIBlankEntry\r
888 },\r
889 {\r
890 0x00,\r
891 NULL,\r
892 /* null string ends the list */NULL\r
893 }\r
894};\r
895\r
896PCI_CLASS_ENTRY PCISubClass_11[] = {\r
897 {\r
898 0x00,\r
899 L"DPIO modules",\r
900 PCIBlankEntry\r
901 },\r
f056e4c1
JC		 902 {\r
903 0x01,\r
904 L"Performance Counters",\r
905 PCIBlankEntry\r
906 },\r
907 {\r
908 0x10,\r
909 L"Communications synchronization plus time and frequency test/measurement ",\r
910 PCIBlankEntry\r
911 },\r
912 {\r
913 0x20,\r
914 L"Management card",\r
915 PCIBlankEntry\r
916 },\r
5d73d92f 917 {\r
918 0x80,\r
919 L"Other DAQ & SP controllers",\r
920 PCIBlankEntry\r
921 },\r
922 {\r
923 0x00,\r
924 NULL,\r
925 /* null string ends the list */NULL\r
926 }\r
927};\r
928\r
f056e4c1
JC		 929PCI_CLASS_ENTRY PCISubClass_12[] = {\r
930 {\r
931 0x00,\r
932 L"Processing Accelerator",\r
933 PCIBlankEntry\r
934 },\r
935 {\r
936 0x00,\r
937 NULL,\r
938 /* null string ends the list */NULL\r
939 }\r
940};\r
941\r
942PCI_CLASS_ENTRY PCISubClass_13[] = {\r
943 {\r
944 0x00,\r
945 L"Non-Essential Instrumentation Function",\r
946 PCIBlankEntry\r
947 },\r
948 {\r
949 0x00,\r
950 NULL,\r
951 /* null string ends the list */NULL\r
952 }\r
953};\r
954\r
5d73d92f 955//\r
956// Programming Interface entries\r
957//\r
f056e4c1
JC		 958PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r
959 {\r
960 0x00,\r
961 L"SCSI controller",\r
962 PCIBlankEntry\r
963 },\r
964 {\r
965 0x11,\r
966 L"SCSI storage device SOP using PQI",\r
967 PCIBlankEntry\r
968 },\r
969 {\r
970 0x12,\r
971 L"SCSI controller SOP using PQI",\r
972 PCIBlankEntry\r
973 },\r
974 {\r
975 0x13,\r
976 L"SCSI storage device and controller SOP using PQI",\r
977 PCIBlankEntry\r
978 },\r
979 {\r
980 0x21,\r
981 L"SCSI storage device SOP using NVMe",\r
982 PCIBlankEntry\r
983 },\r
984 {\r
985 0x00,\r
986 NULL,\r
987 /* null string ends the list */NULL\r
988 }\r
989};\r
990\r
5d73d92f 991PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
992 {\r
993 0x00,\r
994 L"",\r
995 PCIBlankEntry\r
996 },\r
997 {\r
998 0x01,\r
999 L"OM-primary",\r
1000 PCIBlankEntry\r
1001 },\r
1002 {\r
1003 0x02,\r
1004 L"PI-primary",\r
1005 PCIBlankEntry\r
1006 },\r
1007 {\r
1008 0x03,\r
1009 L"OM/PI-primary",\r
1010 PCIBlankEntry\r
1011 },\r
1012 {\r
1013 0x04,\r
1014 L"OM-secondary",\r
1015 PCIBlankEntry\r
1016 },\r
1017 {\r
1018 0x05,\r
1019 L"OM-primary, OM-secondary",\r
1020 PCIBlankEntry\r
1021 },\r
1022 {\r
1023 0x06,\r
1024 L"PI-primary, OM-secondary",\r
1025 PCIBlankEntry\r
1026 },\r
1027 {\r
1028 0x07,\r
1029 L"OM/PI-primary, OM-secondary",\r
1030 PCIBlankEntry\r
1031 },\r
1032 {\r
1033 0x08,\r
1034 L"OM-secondary",\r
1035 PCIBlankEntry\r
1036 },\r
1037 {\r
1038 0x09,\r
1039 L"OM-primary, PI-secondary",\r
1040 PCIBlankEntry\r
1041 },\r
1042 {\r
1043 0x0a,\r
1044 L"PI-primary, PI-secondary",\r
1045 PCIBlankEntry\r
1046 },\r
1047 {\r
1048 0x0b,\r
1049 L"OM/PI-primary, PI-secondary",\r
1050 PCIBlankEntry\r
1051 },\r
1052 {\r
1053 0x0c,\r
1054 L"OM-secondary",\r
1055 PCIBlankEntry\r
1056 },\r
1057 {\r
1058 0x0d,\r
1059 L"OM-primary, OM/PI-secondary",\r
1060 PCIBlankEntry\r
1061 },\r
1062 {\r
1063 0x0e,\r
1064 L"PI-primary, OM/PI-secondary",\r
1065 PCIBlankEntry\r
1066 },\r
1067 {\r
1068 0x0f,\r
1069 L"OM/PI-primary, OM/PI-secondary",\r
1070 PCIBlankEntry\r
1071 },\r
1072 {\r
1073 0x80,\r
1074 L"Master",\r
1075 PCIBlankEntry\r
1076 },\r
1077 {\r
1078 0x81,\r
1079 L"Master, OM-primary",\r
1080 PCIBlankEntry\r
1081 },\r
1082 {\r
1083 0x82,\r
1084 L"Master, PI-primary",\r
1085 PCIBlankEntry\r
1086 },\r
1087 {\r
1088 0x83,\r
1089 L"Master, OM/PI-primary",\r
1090 PCIBlankEntry\r
1091 },\r
1092 {\r
1093 0x84,\r
1094 L"Master, OM-secondary",\r
1095 PCIBlankEntry\r
1096 },\r
1097 {\r
1098 0x85,\r
1099 L"Master, OM-primary, OM-secondary",\r
1100 PCIBlankEntry\r
1101 },\r
1102 {\r
1103 0x86,\r
1104 L"Master, PI-primary, OM-secondary",\r
1105 PCIBlankEntry\r
1106 },\r
1107 {\r
1108 0x87,\r
1109 L"Master, OM/PI-primary, OM-secondary",\r
1110 PCIBlankEntry\r
1111 },\r
1112 {\r
1113 0x88,\r
1114 L"Master, OM-secondary",\r
1115 PCIBlankEntry\r
1116 },\r
1117 {\r
1118 0x89,\r
1119 L"Master, OM-primary, PI-secondary",\r
1120 PCIBlankEntry\r
1121 },\r
1122 {\r
1123 0x8a,\r
1124 L"Master, PI-primary, PI-secondary",\r
1125 PCIBlankEntry\r
1126 },\r
1127 {\r
1128 0x8b,\r
1129 L"Master, OM/PI-primary, PI-secondary",\r
1130 PCIBlankEntry\r
1131 },\r
1132 {\r
1133 0x8c,\r
1134 L"Master, OM-secondary",\r
1135 PCIBlankEntry\r
1136 },\r
1137 {\r
1138 0x8d,\r
1139 L"Master, OM-primary, OM/PI-secondary",\r
1140 PCIBlankEntry\r
1141 },\r
1142 {\r
1143 0x8e,\r
1144 L"Master, PI-primary, OM/PI-secondary",\r
1145 PCIBlankEntry\r
1146 },\r
1147 {\r
1148 0x8f,\r
1149 L"Master, OM/PI-primary, OM/PI-secondary",\r
1150 PCIBlankEntry\r
1151 },\r
1152 {\r
1153 0x00,\r
1154 NULL,\r
1155 /* null string ends the list */NULL\r
1156 }\r
1157};\r
1158\r
f056e4c1
JC		 1159PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r
1160 {\r
1161 0x20,\r
1162 L"Single stepping",\r
1163 PCIBlankEntry\r
1164 },\r
1165 {\r
1166 0x30,\r
1167 L"Continuous operation",\r
1168 PCIBlankEntry\r
1169 },\r
1170 {\r
1171 0x00,\r
1172 NULL,\r
1173 /* null string ends the list */NULL\r
1174 }\r
1175};\r
1176\r
1177PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r
1178 {\r
1179 0x00,\r
1180 L"",\r
1181 PCIBlankEntry\r
1182 },\r
1183 {\r
1184 0x01,\r
1185 L"AHCI",\r
1186 PCIBlankEntry\r
1187 },\r
1188 {\r
1189 0x02,\r
1190 L"Serial Storage Bus",\r
1191 PCIBlankEntry\r
1192 },\r
1193 {\r
1194 0x00,\r
1195 NULL,\r
1196 /* null string ends the list */NULL\r
1197 }\r
1198};\r
1199\r
1200PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r
1201 {\r
1202 0x00,\r
1203 L"",\r
1204 PCIBlankEntry\r
1205 },\r
1206 {\r
1207 0x01,\r
1208 L"Obsolete",\r
1209 PCIBlankEntry\r
1210 },\r
1211 {\r
1212 0x00,\r
1213 NULL,\r
1214 /* null string ends the list */NULL\r
1215 }\r
1216};\r
1217\r
1218PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r
1219 {\r
1220 0x00,\r
1221 L"",\r
1222 PCIBlankEntry\r
1223 },\r
1224 {\r
1225 0x01,\r
1226 L"NVMHCI",\r
1227 PCIBlankEntry\r
1228 },\r
1229 {\r
1230 0x02,\r
1231 L"NVM Express",\r
1232 PCIBlankEntry\r
1233 },\r
1234 {\r
1235 0x00,\r
1236 NULL,\r
1237 /* null string ends the list */NULL\r
1238 }\r
1239};\r
1240\r
1241PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r
1242 {\r
1243 0x00,\r
1244 L"",\r
1245 PCIBlankEntry\r
1246 },\r
1247 {\r
1248 0x01,\r
1249 L"UFSHCI",\r
1250 PCIBlankEntry\r
1251 },\r
1252 {\r
1253 0x00,\r
1254 NULL,\r
1255 /* null string ends the list */NULL\r
1256 }\r
1257};\r
1258\r
5d73d92f 1259PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
1260 {\r
1261 0x00,\r
1262 L"VGA compatible",\r
1263 PCIBlankEntry\r
1264 },\r
1265 {\r
1266 0x01,\r
1267 L"8514 compatible",\r
1268 PCIBlankEntry\r
1269 },\r
1270 {\r
1271 0x00,\r
1272 NULL,\r
1273 /* null string ends the list */NULL\r
1274 }\r
1275};\r
1276\r
1277PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
1278 {\r
1279 0x00,\r
1280 L"",\r
1281 PCIBlankEntry\r
1282 },\r
1283 {\r
1284 0x01,\r
1285 L"Subtractive decode",\r
1286 PCIBlankEntry\r
1287 },\r
1288 {\r
1289 0x00,\r
1290 NULL,\r
1291 /* null string ends the list */NULL\r
1292 }\r
1293};\r
1294\r
f056e4c1
JC		 1295PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r
1296 {\r
1297 0x40,\r
1298 L"Primary PCI bus side facing the system host processor",\r
1299 PCIBlankEntry\r
1300 },\r
1301 {\r
1302 0x80,\r
1303 L"Secondary PCI bus side facing the system host processor",\r
1304 PCIBlankEntry\r
1305 },\r
1306 {\r
1307 0x00,\r
1308 NULL,\r
1309 /* null string ends the list */NULL\r
1310 }\r
1311};\r
1312\r
1313PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r
1314 {\r
1315 0x00,\r
1316 L"Custom",\r
1317 PCIBlankEntry\r
1318 },\r
1319 {\r
1320 0x01,\r
1321 L"ASI-SIG Defined Portal",\r
1322 PCIBlankEntry\r
1323 },\r
1324 {\r
1325 0x00,\r
1326 NULL,\r
1327 /* null string ends the list */NULL\r
1328 }\r
1329};\r
1330\r
5d73d92f 1331PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
1332 {\r
1333 0x00,\r
1334 L"Generic XT-compatible",\r
1335 PCIBlankEntry\r
1336 },\r
1337 {\r
1338 0x01,\r
1339 L"16450-compatible",\r
1340 PCIBlankEntry\r
1341 },\r
1342 {\r
1343 0x02,\r
1344 L"16550-compatible",\r
1345 PCIBlankEntry\r
1346 },\r
1347 {\r
1348 0x03,\r
1349 L"16650-compatible",\r
1350 PCIBlankEntry\r
1351 },\r
1352 {\r
1353 0x04,\r
1354 L"16750-compatible",\r
1355 PCIBlankEntry\r
1356 },\r
1357 {\r
1358 0x05,\r
1359 L"16850-compatible",\r
1360 PCIBlankEntry\r
1361 },\r
1362 {\r
1363 0x06,\r
1364 L"16950-compatible",\r
1365 PCIBlankEntry\r
1366 },\r
1367 {\r
1368 0x00,\r
1369 NULL,\r
1370 /* null string ends the list */NULL\r
1371 }\r
1372};\r
1373\r
1374PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1375 {\r
1376 0x00,\r
1377 L"",\r
1378 PCIBlankEntry\r
1379 },\r
1380 {\r
1381 0x01,\r
1382 L"Bi-directional",\r
1383 PCIBlankEntry\r
1384 },\r
1385 {\r
1386 0x02,\r
1387 L"ECP 1.X-compliant",\r
1388 PCIBlankEntry\r
1389 },\r
1390 {\r
1391 0x03,\r
1392 L"IEEE 1284",\r
1393 PCIBlankEntry\r
1394 },\r
1395 {\r
1396 0xfe,\r
1397 L"IEEE 1284 target (not a controller)",\r
1398 PCIBlankEntry\r
1399 },\r
1400 {\r
1401 0x00,\r
1402 NULL,\r
1403 /* null string ends the list */NULL\r
1404 }\r
1405};\r
1406\r
1407PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1408 {\r
1409 0x00,\r
1410 L"Generic",\r
1411 PCIBlankEntry\r
1412 },\r
1413 {\r
1414 0x01,\r
1415 L"Hayes-compatible 16450",\r
1416 PCIBlankEntry\r
1417 },\r
1418 {\r
1419 0x02,\r
1420 L"Hayes-compatible 16550",\r
1421 PCIBlankEntry\r
1422 },\r
1423 {\r
1424 0x03,\r
1425 L"Hayes-compatible 16650",\r
1426 PCIBlankEntry\r
1427 },\r
1428 {\r
1429 0x04,\r
1430 L"Hayes-compatible 16750",\r
1431 PCIBlankEntry\r
1432 },\r
1433 {\r
1434 0x00,\r
1435 NULL,\r
1436 /* null string ends the list */NULL\r
1437 }\r
1438};\r
1439\r
1440PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1441 {\r
1442 0x00,\r
1443 L"Generic 8259",\r
1444 PCIBlankEntry\r
1445 },\r
1446 {\r
1447 0x01,\r
1448 L"ISA",\r
1449 PCIBlankEntry\r
1450 },\r
1451 {\r
1452 0x02,\r
1453 L"EISA",\r
1454 PCIBlankEntry\r
1455 },\r
1456 {\r
1457 0x10,\r
1458 L"IO APIC",\r
1459 PCIBlankEntry\r
1460 },\r
1461 {\r
1462 0x20,\r
1463 L"IO(x) APIC interrupt controller",\r
1464 PCIBlankEntry\r
1465 },\r
1466 {\r
1467 0x00,\r
1468 NULL,\r
1469 /* null string ends the list */NULL\r
1470 }\r
1471};\r
1472\r
1473PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1474 {\r
1475 0x00,\r
1476 L"Generic 8237",\r
1477 PCIBlankEntry\r
1478 },\r
1479 {\r
1480 0x01,\r
1481 L"ISA",\r
1482 PCIBlankEntry\r
1483 },\r
1484 {\r
1485 0x02,\r
1486 L"EISA",\r
1487 PCIBlankEntry\r
1488 },\r
1489 {\r
1490 0x00,\r
1491 NULL,\r
1492 /* null string ends the list */NULL\r
1493 }\r
1494};\r
1495\r
1496PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1497 {\r
1498 0x00,\r
1499 L"Generic 8254",\r
1500 PCIBlankEntry\r
1501 },\r
1502 {\r
1503 0x01,\r
1504 L"ISA",\r
1505 PCIBlankEntry\r
1506 },\r
1507 {\r
1508 0x02,\r
1509 L"EISA",\r
1510 PCIBlankEntry\r
1511 },\r
1512 {\r
1513 0x00,\r
1514 NULL,\r
1515 /* null string ends the list */NULL\r
1516 }\r
1517};\r
1518\r
1519PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1520 {\r
1521 0x00,\r
1522 L"Generic",\r
1523 PCIBlankEntry\r
1524 },\r
1525 {\r
1526 0x01,\r
1527 L"ISA",\r
1528 PCIBlankEntry\r
1529 },\r
1530 {\r
1531 0x02,\r
1532 L"EISA",\r
1533 PCIBlankEntry\r
1534 },\r
1535 {\r
1536 0x00,\r
1537 NULL,\r
1538 /* null string ends the list */NULL\r
1539 }\r
1540};\r
1541\r
1542PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1543 {\r
1544 0x00,\r
1545 L"Generic",\r
1546 PCIBlankEntry\r
1547 },\r
1548 {\r
1549 0x10,\r
1550 L"",\r
1551 PCIBlankEntry\r
1552 },\r
1553 {\r
1554 0x00,\r
1555 NULL,\r
1556 /* null string ends the list */NULL\r
1557 }\r
1558};\r
1559\r
1560PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1561 {\r
1562 0x00,\r
f056e4c1
JC		 1563 L"",\r
1564 PCIBlankEntry\r
1565 },\r
1566 {\r
1567 0x10,\r
1568 L"Using 1394 OpenHCI spec",\r
1569 PCIBlankEntry\r
1570 },\r
1571 {\r
1572 0x00,\r
1573 NULL,\r
1574 /* null string ends the list */NULL\r
1575 }\r
1576};\r
1577\r
1578PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1579 {\r
1580 0x00,\r
1581 L"UHCI",\r
5d73d92f 1582 PCIBlankEntry\r
1583 },\r
1584 {\r
1585 0x10,\r
f056e4c1
JC		 1586 L"OHCI",\r
1587 PCIBlankEntry\r
1588 },\r
1589 {\r
1590 0x20,\r
1591 L"EHCI",\r
1592 PCIBlankEntry\r
1593 },\r
1594 {\r
1595 0x30,\r
1596 L"xHCI",\r
5d73d92f 1597 PCIBlankEntry\r
1598 },\r
1599 {\r
1600 0x80,\r
1601 L"No specific programming interface",\r
1602 PCIBlankEntry\r
1603 },\r
1604 {\r
1605 0xfe,\r
1606 L"(Not Host Controller)",\r
1607 PCIBlankEntry\r
1608 },\r
1609 {\r
1610 0x00,\r
1611 NULL,\r
1612 /* null string ends the list */NULL\r
1613 }\r
1614};\r
1615\r
f056e4c1 1616PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r
5d73d92f 1617 {\r
1618 0x00,\r
f056e4c1
JC		 1619 L"SMIC",\r
1620 PCIBlankEntry\r
1621 },\r
1622 {\r
1623 0x01,\r
1624 L"Keyboard Controller Style",\r
1625 PCIBlankEntry\r
1626 },\r
1627 {\r
1628 0x02,\r
1629 L"Block Transfer",\r
1630 PCIBlankEntry\r
1631 },\r
1632 {\r
1633 0x00,\r
1634 NULL,\r
1635 /* null string ends the list */NULL\r
1636 }\r
1637};\r
1638\r
1639PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r
1640 {\r
1641 0x00,\r
1642 L"Consumer IR controller",\r
5d73d92f 1643 PCIBlankEntry\r
1644 },\r
1645 {\r
1646 0x10,\r
f056e4c1 1647 L"UWB Radio controller",\r
5d73d92f 1648 PCIBlankEntry\r
1649 },\r
1650 {\r
1651 0x00,\r
1652 NULL,\r
1653 /* null string ends the list */NULL\r
1654 }\r
1655};\r
1656\r
1657PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1658 {\r
1659 0x00,\r
1660 L"Message FIFO at offset 40h",\r
1661 PCIBlankEntry\r
1662 },\r
1663 {\r
1664 0x01,\r
1665 L"",\r
1666 PCIBlankEntry\r
1667 },\r
1668 {\r
1669 0x00,\r
1670 NULL,\r
1671 /* null string ends the list */NULL\r
1672 }\r
1673};\r
1674\r
5d73d92f 1675\r
a1d4bfcc 1676/**\r
5d73d92f 1677 Generates printable Unicode strings that represent PCI device class,\r
1678 subclass and programmed I/F based on a value passed to the function.\r
1679\r
a1d4bfcc 1680 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
5d73d92f 1681 PCI device. The encodings are:\r
1682 bits 23:16 - Base Class Code\r
1683 bits 15:8 - Sub-Class Code\r
1684 bits 7:0 - Programming Interface\r
4ff7e37b 1685 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
5d73d92f 1686 printable class strings corresponding to ClassCode. The\r
1687 caller must not modify the strings that are pointed by\r
1688 the fields in ClassStrings.\r
5d73d92f 1689**/\r
a1d4bfcc 1690VOID\r
1691PciGetClassStrings (\r
1692 IN UINT32 ClassCode,\r
1693 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1694 )\r
5d73d92f 1695{\r
1696 INTN Index;\r
1697 UINT8 Code;\r
1698 PCI_CLASS_ENTRY *CurrentClass;\r
1699\r
1700 //\r
1701 // Assume no strings found\r
1702 //\r
1703 ClassStrings->BaseClass = L"UNDEFINED";\r
1704 ClassStrings->SubClass = L"UNDEFINED";\r
1705 ClassStrings->PIFClass = L"UNDEFINED";\r
1706\r
1707 CurrentClass = gClassStringList;\r
1708 Code = (UINT8) (ClassCode >> 16);\r
1709 Index = 0;\r
1710\r
1711 //\r
1712 // Go through all entries of the base class, until the entry with a matching\r
1713 // base class code is found. If reaches an entry with a null description\r
1714 // text, the last entry is met, which means no text for the base class was\r
1715 // found, so no more action is needed.\r
1716 //\r
1717 while (Code != CurrentClass[Index].Code) {\r
1718 if (NULL == CurrentClass[Index].DescText) {\r
1719 return ;\r
1720 }\r
1721\r
1722 Index++;\r
1723 }\r
1724 //\r
1725 // A base class was found. Assign description, and check if this class has\r
1726 // sub-class defined. If sub-class defined, no more action is needed,\r
1727 // otherwise, continue to find description for the sub-class code.\r
1728 //\r
1729 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1730 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1731 return ;\r
1732 }\r
1733 //\r
1734 // find Subclass entry\r
1735 //\r
1736 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1737 Code = (UINT8) (ClassCode >> 8);\r
1738 Index = 0;\r
1739\r
1740 //\r
1741 // Go through all entries of the sub-class, until the entry with a matching\r
1742 // sub-class code is found. If reaches an entry with a null description\r
1743 // text, the last entry is met, which means no text for the sub-class was\r
1744 // found, so no more action is needed.\r
1745 //\r
1746 while (Code != CurrentClass[Index].Code) {\r
1747 if (NULL == CurrentClass[Index].DescText) {\r
1748 return ;\r
1749 }\r
1750\r
1751 Index++;\r
1752 }\r
1753 //\r
1754 // A class was found for the sub-class code. Assign description, and check if\r
1755 // this sub-class has programming interface defined. If no, no more action is\r
1756 // needed, otherwise, continue to find description for the programming\r
1757 // interface.\r
1758 //\r
1759 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1760 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1761 return ;\r
1762 }\r
1763 //\r
1764 // Find programming interface entry\r
1765 //\r
1766 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1767 Code = (UINT8) ClassCode;\r
1768 Index = 0;\r
1769\r
1770 //\r
1771 // Go through all entries of the I/F entries, until the entry with a\r
1772 // matching I/F code is found. If reaches an entry with a null description\r
1773 // text, the last entry is met, which means no text was found, so no more\r
1774 // action is needed.\r
1775 //\r
1776 while (Code != CurrentClass[Index].Code) {\r
1777 if (NULL == CurrentClass[Index].DescText) {\r
1778 return ;\r
1779 }\r
1780\r
1781 Index++;\r
1782 }\r
1783 //\r
1784 // A class was found for the I/F code. Assign description, done!\r
1785 //\r
1786 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1787 return ;\r
1788}\r
1789\r
a1d4bfcc 1790/**\r
1791 Print strings that represent PCI device class, subclass and programmed I/F.\r
1792\r
1793 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
e8a57ade 1794 configuration space.\r
a1d4bfcc 1795 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1796**/\r
5d73d92f 1797VOID\r
1798PciPrintClassCode (\r
1799 IN UINT8 *ClassCodePtr,\r
1800 IN BOOLEAN IncludePIF\r
1801 )\r
5d73d92f 1802{\r
1803 UINT32 ClassCode;\r
1804 PCI_CLASS_STRINGS ClassStrings;\r
5d73d92f 1805\r
1806 ClassCode = 0;\r
e8a57ade
JC		 1807 ClassCode |= (UINT32)ClassCodePtr[0];\r
1808 ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r
1809 ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r
5d73d92f 1810\r
1811 //\r
1812 // Get name from class code\r
1813 //\r
1814 PciGetClassStrings (ClassCode, &ClassStrings);\r
1815\r
1816 if (IncludePIF) {\r
1817 //\r
c37e0f16 1818 // Print base class, sub class, and programming inferface name\r
5d73d92f 1819 //\r
c37e0f16 1820 ShellPrintEx (-1, -1, L"%s - %s - %s",\r
5d73d92f 1821 ClassStrings.BaseClass,\r
1822 ClassStrings.SubClass,\r
1823 ClassStrings.PIFClass\r
1824 );\r
1825\r
1826 } else {\r
1827 //\r
c37e0f16 1828 // Only print base class and sub class name\r
5d73d92f 1829 //\r
c37e0f16 1830 ShellPrintEx (-1, -1, L"%s - %s",\r
5d73d92f 1831 ClassStrings.BaseClass,\r
1832 ClassStrings.SubClass\r
c37e0f16 1833 );\r
5d73d92f 1834 }\r
1835}\r
1836\r
a1d4bfcc 1837/**\r
1838 This function finds out the protocol which is in charge of the given\r
1839 segment, and its bus range covers the current bus number. It lookes\r
1840 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1841 criteria is found.\r
1842\r
1843 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1844 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1845 @param[in] Segment Segment number of device we are dealing with.\r
1846 @param[in] Bus Bus number of device we are dealing with.\r
1847 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1848\r
1849 @retval EFI_SUCCESS The command completed successfully.\r
1850 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 1851\r
a1d4bfcc 1852**/\r
5d73d92f 1853EFI_STATUS\r
1854PciFindProtocolInterface (\r
1855 IN EFI_HANDLE *HandleBuf,\r
1856 IN UINTN HandleCount,\r
1857 IN UINT16 Segment,\r
1858 IN UINT16 Bus,\r
1859 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1860 );\r
1861\r
a1d4bfcc 1862/**\r
1863 This function gets the protocol interface from the given handle, and\r
1864 obtains its address space descriptors.\r
1865\r
1866 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1867 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1868 @param[out] Descriptors Points to the address space descriptors.\r
1869\r
1870 @retval EFI_SUCCESS The command completed successfully\r
1871**/\r
5d73d92f 1872EFI_STATUS\r
1873PciGetProtocolAndResource (\r
1874 IN EFI_HANDLE Handle,\r
1875 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1876 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1877 );\r
1878\r
a1d4bfcc 1879/**\r
1880 This function get the next bus range of given address space descriptors.\r
1881 It also moves the pointer backward a node, to get prepared to be called\r
1882 again.\r
1883\r
4ff7e37b
ED		 1884 @param[in, out] Descriptors Points to current position of a serial of address space\r
1885 descriptors.\r
1886 @param[out] MinBus The lower range of bus number.\r
1887 @param[out] MaxBus The upper range of bus number.\r
1888 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 1889\r
1890 @retval EFI_SUCCESS The command completed successfully.\r
1891**/\r
5d73d92f 1892EFI_STATUS\r
1893PciGetNextBusRange (\r
1894 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1895 OUT UINT16 *MinBus,\r
1896 OUT UINT16 *MaxBus,\r
1897 OUT BOOLEAN *IsEnd\r
1898 );\r
1899\r
a1d4bfcc 1900/**\r
1901 Explain the data in PCI configuration space. The part which is common for\r
1902 PCI device and bridge is interpreted in this function. It calls other\r
1903 functions to interpret data unique for device or bridge.\r
1904\r
1905 @param[in] ConfigSpace Data in PCI configuration space.\r
1906 @param[in] Address Address used to access configuration space of this PCI device.\r
1907 @param[in] IoDev Handle used to access configuration space of PCI device.\r
f614ce7e 1908 @param[in] EnhancedDump The print format for the dump data.\r
a1d4bfcc 1909\r
1910 @retval EFI_SUCCESS The command completed successfully.\r
1911**/\r
5d73d92f 1912EFI_STATUS\r
1913PciExplainData (\r
1914 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1915 IN UINT64 Address,\r
705bffb5
JC		 1916 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1917 IN CONST UINT16 EnhancedDump\r
5d73d92f 1918 );\r
1919\r
a1d4bfcc 1920/**\r
1921 Explain the device specific part of data in PCI configuration space.\r
1922\r
1923 @param[in] Device Data in PCI configuration space.\r
1924 @param[in] Address Address used to access configuration space of this PCI device.\r
1925 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1926\r
1927 @retval EFI_SUCCESS The command completed successfully.\r
1928**/\r
5d73d92f 1929EFI_STATUS\r
1930PciExplainDeviceData (\r
1931 IN PCI_DEVICE_HEADER *Device,\r
1932 IN UINT64 Address,\r
1933 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1934 );\r
1935\r
a1d4bfcc 1936/**\r
1937 Explain the bridge specific part of data in PCI configuration space.\r
1938\r
1939 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1940 @param[in] Address Address used to access configuration space of this PCI device.\r
1941 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1942\r
1943 @retval EFI_SUCCESS The command completed successfully.\r
1944**/\r
5d73d92f 1945EFI_STATUS\r
1946PciExplainBridgeData (\r
a1d4bfcc 1947 IN PCI_BRIDGE_HEADER *Bridge,\r
1948 IN UINT64 Address,\r
1949 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
5d73d92f 1950 );\r
1951\r
a1d4bfcc 1952/**\r
1953 Explain the Base Address Register(Bar) in PCI configuration space.\r
1954\r
4ff7e37b
ED		 1955 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1956 @param[in] Command Points to the register Command.\r
1957 @param[in] Address Address used to access configuration space of this PCI device.\r
1958 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1959 @param[in, out] Index The Index.\r
a1d4bfcc 1960\r
1961 @retval EFI_SUCCESS The command completed successfully.\r
1962**/\r
5d73d92f 1963EFI_STATUS\r
1964PciExplainBar (\r
1965 IN UINT32 *Bar,\r
1966 IN UINT16 *Command,\r
1967 IN UINT64 Address,\r
1968 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1969 IN OUT UINTN *Index\r
1970 );\r
1971\r
a1d4bfcc 1972/**\r
1973 Explain the cardbus specific part of data in PCI configuration space.\r
1974\r
1975 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1976 @param[in] Address Address used to access configuration space of this PCI device.\r
1977 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1978\r
1979 @retval EFI_SUCCESS The command completed successfully.\r
1980**/\r
5d73d92f 1981EFI_STATUS\r
1982PciExplainCardBusData (\r
1983 IN PCI_CARDBUS_HEADER *CardBus,\r
1984 IN UINT64 Address,\r
1985 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1986 );\r
1987\r
a1d4bfcc 1988/**\r
1989 Explain each meaningful bit of register Status. The definition of Status is\r
1990 slightly different depending on the PCI header type.\r
1991\r
1992 @param[in] Status Points to the content of register Status.\r
1993 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1994 status).\r
1995 @param[in] HeaderType Header type of this PCI device.\r
1996\r
1997 @retval EFI_SUCCESS The command completed successfully.\r
1998**/\r
5d73d92f 1999EFI_STATUS\r
2000PciExplainStatus (\r
2001 IN UINT16 *Status,\r
2002 IN BOOLEAN MainStatus,\r
2003 IN PCI_HEADER_TYPE HeaderType\r
2004 );\r
2005\r
a1d4bfcc 2006/**\r
2007 Explain each meaningful bit of register Command.\r
2008\r
2009 @param[in] Command Points to the content of register Command.\r
2010\r
2011 @retval EFI_SUCCESS The command completed successfully.\r
2012**/\r
5d73d92f 2013EFI_STATUS\r
2014PciExplainCommand (\r
2015 IN UINT16 *Command\r
2016 );\r
2017\r
a1d4bfcc 2018/**\r
2019 Explain each meaningful bit of register Bridge Control.\r
2020\r
2021 @param[in] BridgeControl Points to the content of register Bridge Control.\r
2022 @param[in] HeaderType The headertype.\r
2023\r
2024 @retval EFI_SUCCESS The command completed successfully.\r
2025**/\r
5d73d92f 2026EFI_STATUS\r
2027PciExplainBridgeControl (\r
2028 IN UINT16 *BridgeControl,\r
2029 IN PCI_HEADER_TYPE HeaderType\r
2030 );\r
2031\r
a1d4bfcc 2032/**\r
2033 Print each capability structure.\r
2034\r
f614ce7e
SQ		 2035 @param[in] IoDev The pointer to the deivce.\r
2036 @param[in] Address The address to start at.\r
2037 @param[in] CapPtr The offset from the address.\r
2038 @param[in] EnhancedDump The print format for the dump data.\r
a1d4bfcc 2039\r
f614ce7e 2040 @retval EFI_SUCCESS The operation was successful.\r
a1d4bfcc 2041**/\r
5d73d92f 2042EFI_STATUS\r
2043PciExplainCapabilityStruct (\r
2044 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
2045 IN UINT64 Address,\r
705bffb5
JC		 2046 IN UINT8 CapPtr,\r
2047 IN CONST UINT16 EnhancedDump\r
5d73d92f 2048 );\r
2049\r
a1d4bfcc 2050/**\r
2051 Display Pcie device structure.\r
2052\r
f614ce7e
SQ		 2053 @param[in] IoDev The pointer to the root pci protocol.\r
2054 @param[in] Address The Address to start at.\r
2055 @param[in] CapabilityPtr The offset from the address to start.\r
2056 @param[in] EnhancedDump The print format for the dump data.\r
2057 \r
2058 @retval EFI_SUCCESS The command completed successfully.\r
2059 @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted. \r
a1d4bfcc 2060**/\r
5d73d92f 2061EFI_STATUS\r
2062PciExplainPciExpress (\r
2063 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
2064 IN UINT64 Address,\r
705bffb5
JC		 2065 IN UINT8 CapabilityPtr,\r
2066 IN CONST UINT16 EnhancedDump\r
5d73d92f 2067 );\r
2068\r
a1d4bfcc 2069/**\r
2070 Print out information of the capability information.\r
2071\r
2072 @param[in] PciExpressCap The pointer to the structure about the device.\r
2073\r
2074 @retval EFI_SUCCESS The operation was successful.\r
2075**/\r
5d73d92f 2076EFI_STATUS\r
2077ExplainPcieCapReg (\r
2412c297 2078 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2079 );\r
2080\r
2081/**\r
2082 Print out information of the device capability information.\r
2083\r
2084 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2085\r
a1d4bfcc 2086 @retval EFI_SUCCESS The operation was successful.\r
2087**/\r
5d73d92f 2088EFI_STATUS\r
2089ExplainPcieDeviceCap (\r
2412c297 2090 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2091 );\r
2092\r
2093/**\r
2094 Print out information of the device control information.\r
5d73d92f 2095\r
a1d4bfcc 2096 @param[in] PciExpressCap The pointer to the structure about the device.\r
2097\r
2098 @retval EFI_SUCCESS The operation was successful.\r
2099**/\r
5d73d92f 2100EFI_STATUS\r
2101ExplainPcieDeviceControl (\r
2412c297 2102 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2103 );\r
5d73d92f 2104\r
a1d4bfcc 2105/**\r
2106 Print out information of the device status information.\r
2107\r
2108 @param[in] PciExpressCap The pointer to the structure about the device.\r
2109\r
2110 @retval EFI_SUCCESS The operation was successful.\r
2111**/\r
5d73d92f 2112EFI_STATUS\r
2113ExplainPcieDeviceStatus (\r
2412c297 2114 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2115 );\r
2116\r
2117/**\r
2118 Print out information of the device link information.\r
2119\r
2120 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2121\r
a1d4bfcc 2122 @retval EFI_SUCCESS The operation was successful.\r
2123**/\r
5d73d92f 2124EFI_STATUS\r
2125ExplainPcieLinkCap (\r
2412c297 2126 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2127 );\r
2128\r
2129/**\r
2130 Print out information of the device link control information.\r
5d73d92f 2131\r
a1d4bfcc 2132 @param[in] PciExpressCap The pointer to the structure about the device.\r
2133\r
2134 @retval EFI_SUCCESS The operation was successful.\r
2135**/\r
5d73d92f 2136EFI_STATUS\r
2137ExplainPcieLinkControl (\r
2412c297 2138 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2139 );\r
5d73d92f 2140\r
a1d4bfcc 2141/**\r
2142 Print out information of the device link status information.\r
2143\r
2144 @param[in] PciExpressCap The pointer to the structure about the device.\r
2145\r
2146 @retval EFI_SUCCESS The operation was successful.\r
2147**/\r
5d73d92f 2148EFI_STATUS\r
2149ExplainPcieLinkStatus (\r
2412c297 2150 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2151 );\r
2152\r
2153/**\r
2154 Print out information of the device slot information.\r
2155\r
2156 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2157\r
a1d4bfcc 2158 @retval EFI_SUCCESS The operation was successful.\r
2159**/\r
5d73d92f 2160EFI_STATUS\r
2161ExplainPcieSlotCap (\r
2412c297 2162 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2163 );\r
2164\r
2165/**\r
2166 Print out information of the device slot control information.\r
5d73d92f 2167\r
a1d4bfcc 2168 @param[in] PciExpressCap The pointer to the structure about the device.\r
2169\r
2170 @retval EFI_SUCCESS The operation was successful.\r
2171**/\r
5d73d92f 2172EFI_STATUS\r
2173ExplainPcieSlotControl (\r
2412c297 2174 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2175 );\r
5d73d92f 2176\r
a1d4bfcc 2177/**\r
2178 Print out information of the device slot status information.\r
2179\r
2180 @param[in] PciExpressCap The pointer to the structure about the device.\r
2181\r
2182 @retval EFI_SUCCESS The operation was successful.\r
2183**/\r
5d73d92f 2184EFI_STATUS\r
2185ExplainPcieSlotStatus (\r
2412c297 2186 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2187 );\r
2188\r
2189/**\r
2190 Print out information of the device root information.\r
2191\r
2192 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 2193\r
a1d4bfcc 2194 @retval EFI_SUCCESS The operation was successful.\r
2195**/\r
5d73d92f 2196EFI_STATUS\r
2197ExplainPcieRootControl (\r
2412c297 2198 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2199 );\r
2200\r
2201/**\r
2202 Print out information of the device root capability information.\r
5d73d92f 2203\r
a1d4bfcc 2204 @param[in] PciExpressCap The pointer to the structure about the device.\r
2205\r
2206 @retval EFI_SUCCESS The operation was successful.\r
2207**/\r
5d73d92f 2208EFI_STATUS\r
2209ExplainPcieRootCap (\r
2412c297 2210 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2211 );\r
5d73d92f 2212\r
a1d4bfcc 2213/**\r
2214 Print out information of the device root status information.\r
2215\r
2216 @param[in] PciExpressCap The pointer to the structure about the device.\r
2217\r
2218 @retval EFI_SUCCESS The operation was successful.\r
2219**/\r
5d73d92f 2220EFI_STATUS\r
2221ExplainPcieRootStatus (\r
2412c297 2222 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 2223 );\r
5d73d92f 2224\r
2412c297 2225typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STRUCTURE *PciExpressCap);\r
5d73d92f 2226\r
2227typedef enum {\r
2228 FieldWidthUINT8,\r
2229 FieldWidthUINT16,\r
2230 FieldWidthUINT32\r
2231} PCIE_CAPREG_FIELD_WIDTH;\r
2232\r
2233typedef enum {\r
2234 PcieExplainTypeCommon,\r
2235 PcieExplainTypeDevice,\r
2236 PcieExplainTypeLink,\r
2237 PcieExplainTypeSlot,\r
2238 PcieExplainTypeRoot,\r
2239 PcieExplainTypeMax\r
2240} PCIE_EXPLAIN_TYPE;\r
2241\r
2242typedef struct\r
2243{\r
2244 UINT16 Token;\r
2245 UINTN Offset;\r
2246 PCIE_CAPREG_FIELD_WIDTH Width;\r
2247 PCIE_EXPLAIN_FUNCTION Func;\r
2248 PCIE_EXPLAIN_TYPE Type;\r
2249} PCIE_EXPLAIN_STRUCT;\r
2250\r
2251PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
2252 {\r
2253 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
2254 0x00,\r
2255 FieldWidthUINT8,\r
2256 NULL,\r
2257 PcieExplainTypeCommon\r
2258 },\r
2259 {\r
2260 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
2261 0x01,\r
2262 FieldWidthUINT8,\r
2263 NULL,\r
2264 PcieExplainTypeCommon\r
2265 },\r
2266 {\r
2267 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
2268 0x02,\r
2269 FieldWidthUINT16,\r
2270 ExplainPcieCapReg,\r
2271 PcieExplainTypeCommon\r
2272 },\r
2273 {\r
2274 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
2275 0x04,\r
2276 FieldWidthUINT32,\r
2277 ExplainPcieDeviceCap,\r
2278 PcieExplainTypeDevice\r
2279 },\r
2280 {\r
2281 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
2282 0x08,\r
2283 FieldWidthUINT16,\r
2284 ExplainPcieDeviceControl,\r
2285 PcieExplainTypeDevice\r
2286 },\r
2287 {\r
2288 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
2289 0x0a,\r
2290 FieldWidthUINT16,\r
2291 ExplainPcieDeviceStatus,\r
2292 PcieExplainTypeDevice\r
2293 },\r
2294 {\r
2295 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
2296 0x0c,\r
2297 FieldWidthUINT32,\r
2298 ExplainPcieLinkCap,\r
2299 PcieExplainTypeLink\r
2300 },\r
2301 {\r
2302 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
2303 0x10,\r
2304 FieldWidthUINT16,\r
2305 ExplainPcieLinkControl,\r
2306 PcieExplainTypeLink\r
2307 },\r
2308 {\r
2309 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
2310 0x12,\r
2311 FieldWidthUINT16,\r
2312 ExplainPcieLinkStatus,\r
2313 PcieExplainTypeLink\r
2314 },\r
2315 {\r
2316 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
2317 0x14,\r
2318 FieldWidthUINT32,\r
2319 ExplainPcieSlotCap,\r
2320 PcieExplainTypeSlot\r
2321 },\r
2322 {\r
2323 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
2324 0x18,\r
2325 FieldWidthUINT16,\r
2326 ExplainPcieSlotControl,\r
2327 PcieExplainTypeSlot\r
2328 },\r
2329 {\r
2330 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
2331 0x1a,\r
2332 FieldWidthUINT16,\r
2333 ExplainPcieSlotStatus,\r
2334 PcieExplainTypeSlot\r
2335 },\r
2336 {\r
2337 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
2338 0x1c,\r
2339 FieldWidthUINT16,\r
2340 ExplainPcieRootControl,\r
2341 PcieExplainTypeRoot\r
2342 },\r
2343 {\r
2344 STRING_TOKEN (STR_PCIEX_RSVDP),\r
2345 0x1e,\r
2346 FieldWidthUINT16,\r
2347 ExplainPcieRootCap,\r
2348 PcieExplainTypeRoot\r
2349 },\r
2350 {\r
2351 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
2352 0x20,\r
2353 FieldWidthUINT32,\r
2354 ExplainPcieRootStatus,\r
2355 PcieExplainTypeRoot\r
2356 },\r
2357 {\r
2358 0,\r
2359 0,\r
2360 (PCIE_CAPREG_FIELD_WIDTH)0,\r
2361 NULL,\r
2362 PcieExplainTypeMax\r
2363 }\r
2364};\r
2365\r
2366//\r
2367// Global Variables\r
2368//\r
2369PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
2370STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
2371 {L"-s", TypeValue},\r
2372 {L"-i", TypeFlag},\r
2373 {NULL, TypeMax}\r
2374 };\r
2375\r
2376CHAR16 *DevicePortTypeTable[] = {\r
2377 L"PCI Express Endpoint",\r
2378 L"Legacy PCI Express Endpoint",\r
2379 L"Unknown Type",\r
2380 L"Unknonw Type",\r
2381 L"Root Port of PCI Express Root Complex",\r
2382 L"Upstream Port of PCI Express Switch",\r
2383 L"Downstream Port of PCI Express Switch",\r
2384 L"PCI Express to PCI/PCI-X Bridge",\r
2385 L"PCI/PCI-X to PCI Express Bridge",\r
2386 L"Root Complex Integrated Endpoint",\r
2387 L"Root Complex Event Collector"\r
2388};\r
2389\r
2390CHAR16 *L0sLatencyStrTable[] = {\r
2391 L"Less than 64ns",\r
2392 L"64ns to less than 128ns",\r
2393 L"128ns to less than 256ns",\r
2394 L"256ns to less than 512ns",\r
2395 L"512ns to less than 1us",\r
2396 L"1us to less than 2us",\r
2397 L"2us-4us",\r
2398 L"More than 4us"\r
2399};\r
2400\r
2401CHAR16 *L1LatencyStrTable[] = {\r
2402 L"Less than 1us",\r
2403 L"1us to less than 2us",\r
2404 L"2us to less than 4us",\r
2405 L"4us to less than 8us",\r
2406 L"8us to less than 16us",\r
2407 L"16us to less than 32us",\r
2408 L"32us-64us",\r
2409 L"More than 64us"\r
2410};\r
2411\r
2412CHAR16 *ASPMCtrlStrTable[] = {\r
2413 L"Disabled",\r
2414 L"L0s Entry Enabled",\r
2415 L"L1 Entry Enabled",\r
2416 L"L0s and L1 Entry Enabled"\r
2417};\r
2418\r
2419CHAR16 *SlotPwrLmtScaleTable[] = {\r
2420 L"1.0x",\r
2421 L"0.1x",\r
2422 L"0.01x",\r
2423 L"0.001x"\r
2424};\r
2425\r
2426CHAR16 *IndicatorTable[] = {\r
2427 L"Reserved",\r
2428 L"On",\r
2429 L"Blink",\r
2430 L"Off"\r
2431};\r
2432\r
2433\r
a1d4bfcc 2434/**\r
2435 Function for 'pci' command.\r
2436\r
2437 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2438 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2439**/\r
5d73d92f 2440SHELL_STATUS\r
2441EFIAPI\r
2442ShellCommandRunPci (\r
2443 IN EFI_HANDLE ImageHandle,\r
2444 IN EFI_SYSTEM_TABLE *SystemTable\r
2445 )\r
2446{\r
2447 UINT16 Segment;\r
2448 UINT16 Bus;\r
2449 UINT16 Device;\r
2450 UINT16 Func;\r
2451 UINT64 Address;\r
2452 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2453 EFI_STATUS Status;\r
2454 PCI_COMMON_HEADER PciHeader;\r
2455 PCI_CONFIG_SPACE ConfigSpace;\r
2456 UINTN ScreenCount;\r
2457 UINTN TempColumn;\r
2458 UINTN ScreenSize;\r
2459 BOOLEAN ExplainData;\r
2460 UINTN Index;\r
2461 UINTN SizeOfHeader;\r
2462 BOOLEAN PrintTitle;\r
2463 UINTN HandleBufSize;\r
2464 EFI_HANDLE *HandleBuf;\r
2465 UINTN HandleCount;\r
2466 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2467 UINT16 MinBus;\r
2468 UINT16 MaxBus;\r
2469 BOOLEAN IsEnd;\r
2470 LIST_ENTRY *Package;\r
2471 CHAR16 *ProblemParam;\r
2472 SHELL_STATUS ShellStatus;\r
5d73d92f 2473 CONST CHAR16 *Temp;\r
6855763e 2474 UINT64 RetVal;\r
705bffb5 2475 UINT16 EnhancedDump;\r
5d73d92f 2476\r
2477 ShellStatus = SHELL_SUCCESS;\r
2478 Status = EFI_SUCCESS;\r
2479 Address = 0;\r
5d73d92f 2480 IoDev = NULL;\r
2481 HandleBuf = NULL;\r
2482 Package = NULL;\r
2483\r
2484 //\r
2485 // initialize the shell lib (we must be in non-auto-init...)\r
2486 //\r
2487 Status = ShellInitialize();\r
2488 ASSERT_EFI_ERROR(Status);\r
2489\r
2490 Status = CommandInit();\r
2491 ASSERT_EFI_ERROR(Status);\r
2492\r
2493 //\r
2494 // parse the command line\r
2495 //\r
2496 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2497 if (EFI_ERROR(Status)) {\r
2498 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
4092a8f6 2499 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam); \r
5d73d92f 2500 FreePool(ProblemParam);\r
2501 ShellStatus = SHELL_INVALID_PARAMETER;\r
2502 } else {\r
2503 ASSERT(FALSE);\r
2504 }\r
2505 } else {\r
2506\r
3737ac2b 2507 if (ShellCommandLineGetCount(Package) == 2) {\r
4092a8f6 2508 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci"); \r
3737ac2b 2509 ShellStatus = SHELL_INVALID_PARAMETER;\r
2510 goto Done;\r
2511 }\r
5d73d92f 2512\r
3737ac2b 2513 if (ShellCommandLineGetCount(Package) > 4) {\r
4092a8f6 2514 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci"); \r
3737ac2b 2515 ShellStatus = SHELL_INVALID_PARAMETER;\r
2516 goto Done;\r
2517 }\r
2518 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
4092a8f6 2519 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s"); \r
3737ac2b 2520 ShellStatus = SHELL_INVALID_PARAMETER;\r
2521 goto Done;\r
2522 }\r
5d73d92f 2523 //\r
2524 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2525 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2526 // space for handles and call it again.\r
2527 //\r
2528 HandleBufSize = sizeof (EFI_HANDLE);\r
3737ac2b 2529 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
5d73d92f 2530 if (HandleBuf == NULL) {\r
4092a8f6 2531 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2532 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2533 goto Done;\r
2534 }\r
2535\r
2536 Status = gBS->LocateHandle (\r
2537 ByProtocol,\r
2538 &gEfiPciRootBridgeIoProtocolGuid,\r
2539 NULL,\r
2540 &HandleBufSize,\r
2541 HandleBuf\r
2542 );\r
2543\r
2544 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2545 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2546 if (HandleBuf == NULL) {\r
4092a8f6 2547 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2548 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2549 goto Done;\r
2550 }\r
2551\r
2552 Status = gBS->LocateHandle (\r
2553 ByProtocol,\r
2554 &gEfiPciRootBridgeIoProtocolGuid,\r
2555 NULL,\r
2556 &HandleBufSize,\r
2557 HandleBuf\r
2558 );\r
2559 }\r
2560\r
2561 if (EFI_ERROR (Status)) {\r
4092a8f6 2562 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2563 ShellStatus = SHELL_NOT_FOUND;\r
2564 goto Done;\r
2565 }\r
2566\r
2567 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2568 //\r
2569 // Argument Count == 1(no other argument): enumerate all pci functions\r
2570 //\r
3737ac2b 2571 if (ShellCommandLineGetCount(Package) == 1) {\r
5d73d92f 2572 gST->ConOut->QueryMode (\r
2573 gST->ConOut,\r
2574 gST->ConOut->Mode->Mode,\r
2575 &TempColumn,\r
2576 &ScreenSize\r
2577 );\r
2578\r
2579 ScreenCount = 0;\r
2580 ScreenSize -= 4;\r
2581 if ((ScreenSize & 1) == 1) {\r
2582 ScreenSize -= 1;\r
2583 }\r
2584\r
2585 PrintTitle = TRUE;\r
2586\r
2587 //\r
2588 // For each handle, which decides a segment and a bus number range,\r
2589 // enumerate all devices on it.\r
2590 //\r
2591 for (Index = 0; Index < HandleCount; Index++) {\r
2592 Status = PciGetProtocolAndResource (\r
2593 HandleBuf[Index],\r
2594 &IoDev,\r
2595 &Descriptors\r
2596 );\r
2597 if (EFI_ERROR (Status)) {\r
4092a8f6 2598 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2599 ShellStatus = SHELL_NOT_FOUND;\r
2600 goto Done;\r
2601 }\r
2602 //\r
2603 // No document say it's impossible for a RootBridgeIo protocol handle\r
2604 // to have more than one address space descriptors, so find out every\r
2605 // bus range and for each of them do device enumeration.\r
2606 //\r
2607 while (TRUE) {\r
2608 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2609\r
2610 if (EFI_ERROR (Status)) {\r
4092a8f6 2611 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2612 ShellStatus = SHELL_NOT_FOUND;\r
2613 goto Done;\r
2614 }\r
2615\r
2616 if (IsEnd) {\r
2617 break;\r
2618 }\r
2619\r
2620 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2621 //\r
2622 // For each devices, enumerate all functions it contains\r
2623 //\r
2624 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2625 //\r
2626 // For each function, read its configuration space and print summary\r
2627 //\r
2628 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2629 if (ShellGetExecutionBreakFlag ()) {\r
2630 ShellStatus = SHELL_ABORTED;\r
2631 goto Done;\r
2632 }\r
2633 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2634 IoDev->Pci.Read (\r
2635 IoDev,\r
2636 EfiPciWidthUint16,\r
2637 Address,\r
2638 1,\r
2639 &PciHeader.VendorId\r
2640 );\r
2641\r
2642 //\r
2643 // If VendorId = 0xffff, there does not exist a device at this\r
2644 // location. For each device, if there is any function on it,\r
2645 // there must be 1 function at Function 0. So if Func = 0, there\r
2646 // will be no more functions in the same device, so we can break\r
2647 // loop to deal with the next device.\r
2648 //\r
2649 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2650 break;\r
2651 }\r
2652\r
2653 if (PciHeader.VendorId != 0xffff) {\r
2654\r
2655 if (PrintTitle) {\r
2656 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2657 PrintTitle = FALSE;\r
2658 }\r
2659\r
2660 IoDev->Pci.Read (\r
2661 IoDev,\r
2662 EfiPciWidthUint32,\r
2663 Address,\r
2664 sizeof (PciHeader) / sizeof (UINT32),\r
2665 &PciHeader\r
2666 );\r
2667\r
2668 ShellPrintHiiEx(\r
2669 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2670 IoDev->SegmentNumber,\r
2671 Bus,\r
2672 Device,\r
2673 Func\r
2674 );\r
2675\r
2676 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2677 ShellPrintHiiEx(\r
2678 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2679 PciHeader.VendorId,\r
2680 PciHeader.DeviceId,\r
2681 PciHeader.ClassCode[0]\r
2682 );\r
2683\r
2684 ScreenCount += 2;\r
2685 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2686 //\r
2687 // If ScreenSize == 0 we have the console redirected so don't\r
2688 // block updates\r
2689 //\r
2690 ScreenCount = 0;\r
2691 }\r
2692 //\r
2693 // If this is not a multi-function device, we can leave the loop\r
2694 // to deal with the next device.\r
2695 //\r
2696 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2697 break;\r
2698 }\r
2699 }\r
2700 }\r
2701 }\r
2702 }\r
2703 //\r
2704 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2705 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2706 // devices on all bus, we can leave loop.\r
2707 //\r
2708 if (Descriptors == NULL) {\r
2709 break;\r
2710 }\r
2711 }\r
2712 }\r
2713\r
2714 Status = EFI_SUCCESS;\r
2715 goto Done;\r
2716 }\r
2717\r
5d73d92f 2718 ExplainData = FALSE;\r
2719 Segment = 0;\r
2720 Bus = 0;\r
2721 Device = 0;\r
2722 Func = 0;\r
2723 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2724 ExplainData = TRUE;\r
2725 }\r
2726\r
2727 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2728 if (Temp != NULL) {\r
6855763e
CP		 2729 //\r
2730 // Input converted to hexadecimal number.\r
2731 //\r
2732 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2733 Segment = (UINT16) RetVal;\r
2734 } else {\r
4092a8f6 2735 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2736 ShellStatus = SHELL_INVALID_PARAMETER;\r
2737 goto Done;\r
2738 }\r
5d73d92f 2739 }\r
2740\r
2741 //\r
2742 // The first Argument(except "-i") is assumed to be Bus number, second\r
2743 // to be Device number, and third to be Func number.\r
2744 //\r
2745 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2746 if (Temp != NULL) {\r
6855763e
CP		 2747 //\r
2748 // Input converted to hexadecimal number.\r
2749 //\r
2750 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2751 Bus = (UINT16) RetVal;\r
2752 } else {\r
4092a8f6 2753 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2754 ShellStatus = SHELL_INVALID_PARAMETER;\r
2755 goto Done;\r
2756 }\r
2757\r
5d73d92f 2758 if (Bus > MAX_BUS_NUMBER) {\r
4092a8f6 2759 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
5d73d92f 2760 ShellStatus = SHELL_INVALID_PARAMETER;\r
2761 goto Done;\r
2762 }\r
2763 }\r
2764 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2765 if (Temp != NULL) {\r
6855763e
CP		 2766 //\r
2767 // Input converted to hexadecimal number.\r
2768 //\r
2769 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2770 Device = (UINT16) RetVal;\r
2771 } else {\r
4092a8f6 2772 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2773 ShellStatus = SHELL_INVALID_PARAMETER;\r
2774 goto Done;\r
2775 }\r
2776\r
5d73d92f 2777 if (Device > MAX_DEVICE_NUMBER){\r
4092a8f6 2778 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
5d73d92f 2779 ShellStatus = SHELL_INVALID_PARAMETER;\r
2780 goto Done;\r
2781 }\r
2782 }\r
2783\r
2784 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2785 if (Temp != NULL) {\r
6855763e
CP		 2786 //\r
2787 // Input converted to hexadecimal number.\r
2788 //\r
2789 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2790 Func = (UINT16) RetVal;\r
2791 } else {\r
4092a8f6 2792 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
6855763e
CP		 2793 ShellStatus = SHELL_INVALID_PARAMETER;\r
2794 goto Done;\r
2795 }\r
2796\r
5d73d92f 2797 if (Func > MAX_FUNCTION_NUMBER){\r
4092a8f6 2798 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
5d73d92f 2799 ShellStatus = SHELL_INVALID_PARAMETER;\r
2800 goto Done;\r
2801 }\r
2802 }\r
2803\r
2804 //\r
2805 // Find the protocol interface who's in charge of current segment, and its\r
2806 // bus range covers the current bus\r
2807 //\r
2808 Status = PciFindProtocolInterface (\r
2809 HandleBuf,\r
2810 HandleCount,\r
2811 Segment,\r
2812 Bus,\r
2813 &IoDev\r
2814 );\r
2815\r
2816 if (EFI_ERROR (Status)) {\r
2817 ShellPrintHiiEx(\r
4092a8f6 2818 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci", \r
5d73d92f 2819 Segment,\r
2820 Bus\r
2821 );\r
2822 ShellStatus = SHELL_NOT_FOUND;\r
2823 goto Done;\r
2824 }\r
2825\r
2826 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2827 Status = IoDev->Pci.Read (\r
2828 IoDev,\r
2829 EfiPciWidthUint8,\r
2830 Address,\r
2831 sizeof (ConfigSpace),\r
2832 &ConfigSpace\r
2833 );\r
2834\r
2835 if (EFI_ERROR (Status)) {\r
4092a8f6 2836 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci"); \r
5d73d92f 2837 ShellStatus = SHELL_ACCESS_DENIED;\r
2838 goto Done;\r
2839 }\r
2840\r
2841 mConfigSpace = &ConfigSpace;\r
2842 ShellPrintHiiEx(\r
2843 -1,\r
2844 -1,\r
2845 NULL,\r
2846 STRING_TOKEN (STR_PCI_INFO),\r
2847 gShellDebug1HiiHandle,\r
2848 Segment,\r
2849 Bus,\r
2850 Device,\r
2851 Func,\r
2852 Segment,\r
2853 Bus,\r
2854 Device,\r
2855 Func\r
2856 );\r
2857\r
2858 //\r
2859 // Dump standard header of configuration space\r
2860 //\r
2861 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2862\r
a1d4bfcc 2863 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
5d73d92f 2864 ShellPrintEx(-1,-1, L"\r\n");\r
2865\r
2866 //\r
2867 // Dump device dependent Part of configuration space\r
2868 //\r
a1d4bfcc 2869 DumpHex (\r
5d73d92f 2870 2,\r
2871 SizeOfHeader,\r
2872 sizeof (ConfigSpace) - SizeOfHeader,\r
2873 ConfigSpace.Data\r
2874 );\r
2875\r
2876 //\r
2877 // If "-i" appears in command line, interpret data in configuration space\r
2878 //\r
2879 if (ExplainData) {\r
705bffb5
JC		 2880 EnhancedDump = 0;\r
2881 if (ShellCommandLineGetFlag(Package, L"-_e")) {\r
2882 EnhancedDump = 0xFFFF;\r
2883 Temp = ShellCommandLineGetValue(Package, L"-_e");\r
2884 if (Temp != NULL) {\r
2885 EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r
2886 }\r
2887 }\r
2888 Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r
5d73d92f 2889 }\r
2890 }\r
2891Done:\r
2892 if (HandleBuf != NULL) {\r
2893 FreePool (HandleBuf);\r
2894 }\r
2895 if (Package != NULL) {\r
2896 ShellCommandLineFreeVarList (Package);\r
2897 }\r
2898 mConfigSpace = NULL;\r
2899 return ShellStatus;\r
2900}\r
2901\r
a1d4bfcc 2902/**\r
5d73d92f 2903 This function finds out the protocol which is in charge of the given\r
2904 segment, and its bus range covers the current bus number. It lookes\r
2905 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2906 criteria is found.\r
2907\r
a1d4bfcc 2908 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2909 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2910 @param[in] Segment Segment number of device we are dealing with.\r
2911 @param[in] Bus Bus number of device we are dealing with.\r
2912 @param[out] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2913\r
a1d4bfcc 2914 @retval EFI_SUCCESS The command completed successfully.\r
2915 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 2916\r
2917**/\r
a1d4bfcc 2918EFI_STATUS\r
2919PciFindProtocolInterface (\r
2920 IN EFI_HANDLE *HandleBuf,\r
2921 IN UINTN HandleCount,\r
2922 IN UINT16 Segment,\r
2923 IN UINT16 Bus,\r
2924 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2925 )\r
5d73d92f 2926{\r
2927 UINTN Index;\r
2928 EFI_STATUS Status;\r
5d73d92f 2929 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2930 UINT16 MinBus;\r
2931 UINT16 MaxBus;\r
2932 BOOLEAN IsEnd;\r
2933\r
5d73d92f 2934 //\r
2935 // Go through all handles, until the one meets the criteria is found\r
2936 //\r
2937 for (Index = 0; Index < HandleCount; Index++) {\r
2938 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2939 if (EFI_ERROR (Status)) {\r
2940 return Status;\r
2941 }\r
2942 //\r
2943 // When Descriptors == NULL, the Configuration() is not implemented,\r
2944 // so we only check the Segment number\r
2945 //\r
2946 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2947 return EFI_SUCCESS;\r
2948 }\r
2949\r
2950 if ((*IoDev)->SegmentNumber != Segment) {\r
2951 continue;\r
2952 }\r
2953\r
2954 while (TRUE) {\r
2955 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2956 if (EFI_ERROR (Status)) {\r
2957 return Status;\r
2958 }\r
2959\r
2960 if (IsEnd) {\r
2961 break;\r
2962 }\r
2963\r
2964 if (MinBus <= Bus && MaxBus >= Bus) {\r
2c46dd23 2965 return EFI_SUCCESS;\r
5d73d92f 2966 }\r
2967 }\r
2968 }\r
2969\r
2c46dd23 2970 return EFI_NOT_FOUND;\r
5d73d92f 2971}\r
2972\r
a1d4bfcc 2973/**\r
2974 This function gets the protocol interface from the given handle, and\r
2975 obtains its address space descriptors.\r
2976\r
2977 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
2978 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2979 @param[out] Descriptors Points to the address space descriptors.\r
2980\r
2981 @retval EFI_SUCCESS The command completed successfully\r
2982**/\r
5d73d92f 2983EFI_STATUS\r
2984PciGetProtocolAndResource (\r
2985 IN EFI_HANDLE Handle,\r
2986 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2987 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2988 )\r
5d73d92f 2989{\r
2990 EFI_STATUS Status;\r
2991\r
2992 //\r
2993 // Get inferface from protocol\r
2994 //\r
2995 Status = gBS->HandleProtocol (\r
2996 Handle,\r
2997 &gEfiPciRootBridgeIoProtocolGuid,\r
2998 (VOID**)IoDev\r
2999 );\r
3000\r
3001 if (EFI_ERROR (Status)) {\r
3002 return Status;\r
3003 }\r
3004 //\r
3005 // Call Configuration() to get address space descriptors\r
3006 //\r
3007 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
3008 if (Status == EFI_UNSUPPORTED) {\r
3009 *Descriptors = NULL;\r
3010 return EFI_SUCCESS;\r
3011\r
3012 } else {\r
3013 return Status;\r
3014 }\r
3015}\r
3016\r
a1d4bfcc 3017/**\r
3018 This function get the next bus range of given address space descriptors.\r
3019 It also moves the pointer backward a node, to get prepared to be called\r
3020 again.\r
3021\r
4ff7e37b
ED		 3022 @param[in, out] Descriptors Points to current position of a serial of address space\r
3023 descriptors.\r
3024 @param[out] MinBus The lower range of bus number.\r
3025 @param[out] MaxBus The upper range of bus number.\r
3026 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 3027\r
3028 @retval EFI_SUCCESS The command completed successfully.\r
3029**/\r
5d73d92f 3030EFI_STATUS\r
3031PciGetNextBusRange (\r
3032 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
3033 OUT UINT16 *MinBus,\r
3034 OUT UINT16 *MaxBus,\r
3035 OUT BOOLEAN *IsEnd\r
3036 )\r
5d73d92f 3037{\r
3038 *IsEnd = FALSE;\r
3039\r
3040 //\r
3041 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
3042 // range is 0~PCI_MAX_BUS\r
3043 //\r
3044 if ((*Descriptors) == NULL) {\r
3045 *MinBus = 0;\r
3046 *MaxBus = PCI_MAX_BUS;\r
3047 return EFI_SUCCESS;\r
3048 }\r
3049 //\r
3050 // *Descriptors points to one or more address space descriptors, which\r
3051 // ends with a end tagged descriptor. Examine each of the descriptors,\r
3052 // if a bus typed one is found and its bus range covers bus, this handle\r
3053 // is the handle we are looking for.\r
3054 //\r
5d73d92f 3055\r
3056 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
3057 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
3058 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
3059 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
3060 (*Descriptors)++;\r
3737ac2b 3061 return (EFI_SUCCESS);\r
5d73d92f 3062 }\r
3063\r
3064 (*Descriptors)++;\r
3065 }\r
3066\r
3737ac2b 3067 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
3068 *IsEnd = TRUE;\r
3069 }\r
3070\r
5d73d92f 3071 return EFI_SUCCESS;\r
3072}\r
3073\r
a1d4bfcc 3074/**\r
5d73d92f 3075 Explain the data in PCI configuration space. The part which is common for\r
3076 PCI device and bridge is interpreted in this function. It calls other\r
3077 functions to interpret data unique for device or bridge.\r
3078\r
a1d4bfcc 3079 @param[in] ConfigSpace Data in PCI configuration space.\r
3080 @param[in] Address Address used to access configuration space of this PCI device.\r
3081 @param[in] IoDev Handle used to access configuration space of PCI device.\r
f614ce7e 3082 @param[in] EnhancedDump The print format for the dump data.\r
5d73d92f 3083\r
a1d4bfcc 3084 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 3085**/\r
a1d4bfcc 3086EFI_STATUS\r
3087PciExplainData (\r
3088 IN PCI_CONFIG_SPACE *ConfigSpace,\r
3089 IN UINT64 Address,\r
705bffb5
JC		 3090 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3091 IN CONST UINT16 EnhancedDump\r
a1d4bfcc 3092 )\r
5d73d92f 3093{\r
3094 PCI_COMMON_HEADER *Common;\r
3095 PCI_HEADER_TYPE HeaderType;\r
3096 EFI_STATUS Status;\r
3097 UINT8 CapPtr;\r
3098\r
3099 Common = &(ConfigSpace->Common);\r
3100\r
c37e0f16 3101 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 3102\r
3103 //\r
3104 // Print Vendor Id and Device Id\r
3105 //\r
3106 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
3107 INDEX_OF (&(Common->VendorId)),\r
3108 Common->VendorId,\r
3109 INDEX_OF (&(Common->DeviceId)),\r
3110 Common->DeviceId\r
3111 );\r
3112\r
3113 //\r
3114 // Print register Command\r
3115 //\r
3116 PciExplainCommand (&(Common->Command));\r
3117\r
3118 //\r
3119 // Print register Status\r
3120 //\r
3121 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
3122\r
3123 //\r
3124 // Print register Revision ID\r
3125 //\r
14b5e3fd 3126 ShellPrintEx(-1, -1, L"\r\n");\r
5d73d92f 3127 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
3128 INDEX_OF (&(Common->RevisionId)),\r
3129 Common->RevisionId\r
3130 );\r
3131\r
3132 //\r
3133 // Print register BIST\r
3134 //\r
a1d4bfcc 3135 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
3136 if ((Common->Bist & PCI_BIT_7) != 0) {\r
3137 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
5d73d92f 3138 } else {\r
3139 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
3140 }\r
3141 //\r
3142 // Print register Cache Line Size\r
3143 //\r
3144 ShellPrintHiiEx(-1, -1, NULL,\r
3145 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
3146 gShellDebug1HiiHandle,\r
3147 INDEX_OF (&(Common->CacheLineSize)),\r
3148 Common->CacheLineSize\r
3149 );\r
3150\r
3151 //\r
3152 // Print register Latency Timer\r
3153 //\r
3154 ShellPrintHiiEx(-1, -1, NULL,\r
3155 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
3156 gShellDebug1HiiHandle,\r
3157 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
3158 Common->PrimaryLatencyTimer\r
3159 );\r
3160\r
3161 //\r
3162 // Print register Header Type\r
3163 //\r
3164 ShellPrintHiiEx(-1, -1, NULL,\r
3165 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
3166 gShellDebug1HiiHandle,\r
3167 INDEX_OF (&(Common->HeaderType)),\r
3168 Common->HeaderType\r
3169 );\r
3170\r
3171 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
3172 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
3173\r
3174 } else {\r
3175 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
3176 }\r
3177\r
3178 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
3179 switch (HeaderType) {\r
3180 case PciDevice:\r
3181 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
3182 break;\r
3183\r
3184 case PciP2pBridge:\r
3185 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
3186 break;\r
3187\r
3188 case PciCardBusBridge:\r
3189 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
3190 break;\r
3191\r
3192 default:\r
3193 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
3194 HeaderType = PciUndefined;\r
3195 }\r
3196\r
3197 //\r
3198 // Print register Class Code\r
3199 //\r
3200 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
3201 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
c37e0f16 3202 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 3203\r
3204 if (ShellGetExecutionBreakFlag()) {\r
3205 return EFI_SUCCESS;\r
3206 }\r
3207\r
3208 //\r
3209 // Interpret remaining part of PCI configuration header depending on\r
3210 // HeaderType\r
3211 //\r
3212 CapPtr = 0;\r
3213 Status = EFI_SUCCESS;\r
3214 switch (HeaderType) {\r
3215 case PciDevice:\r
3216 Status = PciExplainDeviceData (\r
3217 &(ConfigSpace->NonCommon.Device),\r
3218 Address,\r
3219 IoDev\r
3220 );\r
3221 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
3222 break;\r
3223\r
3224 case PciP2pBridge:\r
3225 Status = PciExplainBridgeData (\r
3226 &(ConfigSpace->NonCommon.Bridge),\r
3227 Address,\r
3228 IoDev\r
3229 );\r
3230 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
3231 break;\r
3232\r
3233 case PciCardBusBridge:\r
3234 Status = PciExplainCardBusData (\r
3235 &(ConfigSpace->NonCommon.CardBus),\r
3236 Address,\r
3237 IoDev\r
3238 );\r
3239 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
3240 break;\r
d8f8021c 3241 case PciUndefined:\r
3242 default:\r
3243 break;\r
5d73d92f 3244 }\r
3245 //\r
3246 // If Status bit4 is 1, dump or explain capability structure\r
3247 //\r
3248 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
705bffb5 3249 PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r
5d73d92f 3250 }\r
3251\r
3252 return Status;\r
3253}\r
3254\r
a1d4bfcc 3255/**\r
3256 Explain the device specific part of data in PCI configuration space.\r
3257\r
3258 @param[in] Device Data in PCI configuration space.\r
3259 @param[in] Address Address used to access configuration space of this PCI device.\r
3260 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3261\r
3262 @retval EFI_SUCCESS The command completed successfully.\r
3263**/\r
5d73d92f 3264EFI_STATUS\r
3265PciExplainDeviceData (\r
3266 IN PCI_DEVICE_HEADER *Device,\r
3267 IN UINT64 Address,\r
3268 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3269 )\r
5d73d92f 3270{\r
3271 UINTN Index;\r
3272 BOOLEAN BarExist;\r
3273 EFI_STATUS Status;\r
3274 UINTN BarCount;\r
3275\r
3276 //\r
3277 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
3278 // exist. If these no Bar for this function, print "none", otherwise\r
3279 // list detail information about this Bar.\r
3280 //\r
3281 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
3282\r
3283 BarExist = FALSE;\r
3284 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
3285 for (Index = 0; Index < BarCount; Index++) {\r
3286 if (Device->Bar[Index] == 0) {\r
3287 continue;\r
3288 }\r
3289\r
3290 if (!BarExist) {\r
3291 BarExist = TRUE;\r
3292 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 3293 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 3294 }\r
3295\r
3296 Status = PciExplainBar (\r
3297 &(Device->Bar[Index]),\r
3298 &(mConfigSpace->Common.Command),\r
3299 Address,\r
3300 IoDev,\r
3301 &Index\r
3302 );\r
3303\r
3304 if (EFI_ERROR (Status)) {\r
3305 break;\r
3306 }\r
3307 }\r
3308\r
3309 if (!BarExist) {\r
3310 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3311\r
3312 } else {\r
c37e0f16 3313 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 3314 }\r
3315\r
3316 //\r
3317 // Print register Expansion ROM Base Address\r
3318 //\r
3319 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
3320 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
3321\r
3322 } else {\r
3323 ShellPrintHiiEx(-1, -1, NULL,\r
3324 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
3325 gShellDebug1HiiHandle,\r
3326 INDEX_OF (&(Device->ROMBar)),\r
3327 Device->ROMBar\r
3328 );\r
3329 }\r
3330 //\r
3331 // Print register Cardbus CIS ptr\r
3332 //\r
3333 ShellPrintHiiEx(-1, -1, NULL,\r
3334 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
3335 gShellDebug1HiiHandle,\r
3336 INDEX_OF (&(Device->CardBusCISPtr)),\r
3337 Device->CardBusCISPtr\r
3338 );\r
3339\r
3340 //\r
3341 // Print register Sub-vendor ID and subsystem ID\r
3342 //\r
3343 ShellPrintHiiEx(-1, -1, NULL,\r
3344 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
3345 gShellDebug1HiiHandle,\r
3346 INDEX_OF (&(Device->SubVendorId)),\r
3347 Device->SubVendorId\r
3348 );\r
3349\r
3350 ShellPrintHiiEx(-1, -1, NULL,\r
3351 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
3352 gShellDebug1HiiHandle,\r
3353 INDEX_OF (&(Device->SubSystemId)),\r
3354 Device->SubSystemId\r
3355 );\r
3356\r
3357 //\r
3358 // Print register Capabilities Ptr\r
3359 //\r
3360 ShellPrintHiiEx(-1, -1, NULL,\r
3361 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
3362 gShellDebug1HiiHandle,\r
3363 INDEX_OF (&(Device->CapabilitiesPtr)),\r
3364 Device->CapabilitiesPtr\r
3365 );\r
3366\r
3367 //\r
3368 // Print register Interrupt Line and interrupt pin\r
3369 //\r
3370 ShellPrintHiiEx(-1, -1, NULL,\r
3371 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
3372 gShellDebug1HiiHandle,\r
3373 INDEX_OF (&(Device->InterruptLine)),\r
3374 Device->InterruptLine\r
3375 );\r
3376\r
3377 ShellPrintHiiEx(-1, -1, NULL,\r
3378 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3379 gShellDebug1HiiHandle,\r
3380 INDEX_OF (&(Device->InterruptPin)),\r
3381 Device->InterruptPin\r
3382 );\r
3383\r
3384 //\r
3385 // Print register Min_Gnt and Max_Lat\r
3386 //\r
3387 ShellPrintHiiEx(-1, -1, NULL,\r
3388 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
3389 gShellDebug1HiiHandle,\r
3390 INDEX_OF (&(Device->MinGnt)),\r
3391 Device->MinGnt\r
3392 );\r
3393\r
3394 ShellPrintHiiEx(-1, -1, NULL,\r
3395 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
3396 gShellDebug1HiiHandle,\r
3397 INDEX_OF (&(Device->MaxLat)),\r
3398 Device->MaxLat\r
3399 );\r
3400\r
3401 return EFI_SUCCESS;\r
3402}\r
3403\r
a1d4bfcc 3404/**\r
3405 Explain the bridge specific part of data in PCI configuration space.\r
3406\r
3407 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
3408 @param[in] Address Address used to access configuration space of this PCI device.\r
3409 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3410\r
3411 @retval EFI_SUCCESS The command completed successfully.\r
3412**/\r
5d73d92f 3413EFI_STATUS\r
3414PciExplainBridgeData (\r
3415 IN PCI_BRIDGE_HEADER *Bridge,\r
3416 IN UINT64 Address,\r
3417 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3418 )\r
5d73d92f 3419{\r
3420 UINTN Index;\r
3421 BOOLEAN BarExist;\r
3422 UINTN BarCount;\r
3423 UINT32 IoAddress32;\r
3424 EFI_STATUS Status;\r
3425\r
3426 //\r
3427 // Print Base Address Registers. When Bar = 0, this Bar does not\r
3428 // exist. If these no Bar for this function, print "none", otherwise\r
3429 // list detail information about this Bar.\r
3430 //\r
3431 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
3432\r
3433 BarExist = FALSE;\r
3434 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
3435\r
3436 for (Index = 0; Index < BarCount; Index++) {\r
3437 if (Bridge->Bar[Index] == 0) {\r
3438 continue;\r
3439 }\r
3440\r
3441 if (!BarExist) {\r
3442 BarExist = TRUE;\r
3443 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 3444 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 3445 }\r
3446\r
3447 Status = PciExplainBar (\r
3448 &(Bridge->Bar[Index]),\r
3449 &(mConfigSpace->Common.Command),\r
3450 Address,\r
3451 IoDev,\r
3452 &Index\r
3453 );\r
3454\r
3455 if (EFI_ERROR (Status)) {\r
3456 break;\r
3457 }\r
3458 }\r
3459\r
3460 if (!BarExist) {\r
3461 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3462 } else {\r
c37e0f16 3463 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 3464 }\r
3465\r
3466 //\r
3467 // Expansion register ROM Base Address\r
3468 //\r
3469 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
3470 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
3471\r
3472 } else {\r
3473 ShellPrintHiiEx(-1, -1, NULL,\r
3474 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3475 gShellDebug1HiiHandle,\r
3476 INDEX_OF (&(Bridge->ROMBar)),\r
3477 Bridge->ROMBar\r
3478 );\r
3479 }\r
3480 //\r
3481 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3482 //\r
3483 ShellPrintHiiEx(-1, -1, NULL,\r
3484 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3485 gShellDebug1HiiHandle,\r
3486 INDEX_OF (&(Bridge->PrimaryBus)),\r
3487 INDEX_OF (&(Bridge->SecondaryBus)),\r
3488 INDEX_OF (&(Bridge->SubordinateBus))\r
3489 );\r
3490\r
c37e0f16 3491 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3492\r
3493 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3494 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3495 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3496\r
3497 //\r
3498 // Print register Secondary Latency Timer\r
3499 //\r
3500 ShellPrintHiiEx(-1, -1, NULL,\r
3501 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3502 gShellDebug1HiiHandle,\r
3503 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3504 Bridge->SecondaryLatencyTimer\r
3505 );\r
3506\r
3507 //\r
3508 // Print register Secondary Status\r
3509 //\r
3510 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3511\r
3512 //\r
3513 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3514 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3515 // base and limit address are listed.\r
3516 //\r
3517 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 3518 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3519\r
3520 //\r
3521 // IO Base & Limit\r
3522 //\r
3523 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
3524 IoAddress32 &= 0xfffff000;\r
3525 ShellPrintHiiEx(-1, -1, NULL,\r
3526 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3527 gShellDebug1HiiHandle,\r
3528 INDEX_OF (&(Bridge->IoBase)),\r
3529 IoAddress32\r
3530 );\r
3531\r
3532 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
3533 IoAddress32 |= 0x00000fff;\r
3534 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3535\r
3536 //\r
3537 // Memory Base & Limit\r
3538 //\r
3539 ShellPrintHiiEx(-1, -1, NULL,\r
3540 STRING_TOKEN (STR_PCI2_MEMORY),\r
3541 gShellDebug1HiiHandle,\r
3542 INDEX_OF (&(Bridge->MemoryBase)),\r
3543 (Bridge->MemoryBase << 16) & 0xfff00000\r
3544 );\r
3545\r
3546 ShellPrintHiiEx(-1, -1, NULL,\r
3547 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3548 gShellDebug1HiiHandle,\r
3549 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3550 );\r
3551\r
3552 //\r
3553 // Pre-fetch-able Memory Base & Limit\r
3554 //\r
3555 ShellPrintHiiEx(-1, -1, NULL,\r
3556 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3557 gShellDebug1HiiHandle,\r
3558 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
3559 Bridge->PrefetchableBaseUpper,\r
3560 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
3561 );\r
3562\r
3563 ShellPrintHiiEx(-1, -1, NULL,\r
3564 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3565 gShellDebug1HiiHandle,\r
3566 Bridge->PrefetchableLimitUpper,\r
3567 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3568 );\r
3569\r
3570 //\r
3571 // Print register Capabilities Pointer\r
3572 //\r
3573 ShellPrintHiiEx(-1, -1, NULL,\r
3574 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3575 gShellDebug1HiiHandle,\r
3576 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3577 Bridge->CapabilitiesPtr\r
3578 );\r
3579\r
3580 //\r
3581 // Print register Bridge Control\r
3582 //\r
3583 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3584\r
3585 //\r
3586 // Print register Interrupt Line & PIN\r
3587 //\r
3588 ShellPrintHiiEx(-1, -1, NULL,\r
3589 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3590 gShellDebug1HiiHandle,\r
3591 INDEX_OF (&(Bridge->InterruptLine)),\r
3592 Bridge->InterruptLine\r
3593 );\r
3594\r
3595 ShellPrintHiiEx(-1, -1, NULL,\r
3596 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3597 gShellDebug1HiiHandle,\r
3598 INDEX_OF (&(Bridge->InterruptPin)),\r
3599 Bridge->InterruptPin\r
3600 );\r
3601\r
3602 return EFI_SUCCESS;\r
3603}\r
3604\r
a1d4bfcc 3605/**\r
3606 Explain the Base Address Register(Bar) in PCI configuration space.\r
3607\r
4ff7e37b
ED		 3608 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3609 @param[in] Command Points to the register Command.\r
3610 @param[in] Address Address used to access configuration space of this PCI device.\r
3611 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3612 @param[in, out] Index The Index.\r
a1d4bfcc 3613\r
3614 @retval EFI_SUCCESS The command completed successfully.\r
3615**/\r
5d73d92f 3616EFI_STATUS\r
3617PciExplainBar (\r
3618 IN UINT32 *Bar,\r
3619 IN UINT16 *Command,\r
3620 IN UINT64 Address,\r
3621 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3622 IN OUT UINTN *Index\r
3623 )\r
5d73d92f 3624{\r
3625 UINT16 OldCommand;\r
3626 UINT16 NewCommand;\r
3627 UINT64 Bar64;\r
3628 UINT32 OldBar32;\r
3629 UINT32 NewBar32;\r
3630 UINT64 OldBar64;\r
3631 UINT64 NewBar64;\r
3632 BOOLEAN IsMem;\r
3633 BOOLEAN IsBar32;\r
3634 UINT64 RegAddress;\r
3635\r
3636 IsBar32 = TRUE;\r
3637 Bar64 = 0;\r
3638 NewBar32 = 0;\r
3639 NewBar64 = 0;\r
3640\r
3641 //\r
3642 // According the bar type, list detail about this bar, for example: 32 or\r
3643 // 64 bits; pre-fetchable or not.\r
3644 //\r
3645 if ((*Bar & PCI_BIT_0) == 0) {\r
3646 //\r
3647 // This bar is of memory type\r
3648 //\r
3649 IsMem = TRUE;\r
3650\r
3651 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3652 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3653 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3654 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3655\r
3656 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3657 Bar64 = 0x0;\r
3658 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
46cb4043 3659 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
2b578de0 3660 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
5d73d92f 3661 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3662 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3663 IsBar32 = FALSE;\r
3664 *Index += 1;\r
3665\r
3666 } else {\r
3667 //\r
3668 // Reserved\r
3669 //\r
3670 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3671 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3672 }\r
3673\r
3674 if ((*Bar & PCI_BIT_3) == 0) {\r
3675 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3676\r
3677 } else {\r
3678 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3679 }\r
3680\r
3681 } else {\r
3682 //\r
3683 // This bar is of io type\r
3684 //\r
3685 IsMem = FALSE;\r
3686 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
c37e0f16 3687 ShellPrintEx (-1, -1, L"I/O ");\r
5d73d92f 3688 }\r
3689\r
3690 //\r
3691 // Get BAR length(or the amount of resource this bar demands for). To get\r
3692 // Bar length, first we should temporarily disable I/O and memory access\r
3693 // of this function(by set bits in the register Command), then write all\r
3694 // "1"s to this bar. The bar value read back is the amount of resource\r
3695 // this bar demands for.\r
3696 //\r
3697 //\r
3698 // Disable io & mem access\r
3699 //\r
3700 OldCommand = *Command;\r
3701 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3702 RegAddress = Address | INDEX_OF (Command);\r
3703 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3704\r
3705 RegAddress = Address | INDEX_OF (Bar);\r
3706\r
3707 //\r
3708 // Read after write the BAR to get the size\r
3709 //\r
3710 if (IsBar32) {\r
3711 OldBar32 = *Bar;\r
3712 NewBar32 = 0xffffffff;\r
3713\r
3714 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3715 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3716 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3717\r
3718 if (IsMem) {\r
3719 NewBar32 = NewBar32 & 0xfffffff0;\r
3720 NewBar32 = (~NewBar32) + 1;\r
3721\r
3722 } else {\r
3723 NewBar32 = NewBar32 & 0xfffffffc;\r
3724 NewBar32 = (~NewBar32) + 1;\r
3725 NewBar32 = NewBar32 & 0x0000ffff;\r
3726 }\r
3727 } else {\r
3728\r
3729 OldBar64 = 0x0;\r
3730 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
2b578de0 3731 NewBar64 = 0xffffffffffffffffULL;\r
5d73d92f 3732\r
3733 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3734 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3735 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3736\r
3737 if (IsMem) {\r
2b578de0 3738 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
5d73d92f 3739 NewBar64 = (~NewBar64) + 1;\r
3740\r
3741 } else {\r
2b578de0 3742 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
5d73d92f 3743 NewBar64 = (~NewBar64) + 1;\r
3744 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3745 }\r
3746 }\r
3747 //\r
3748 // Enable io & mem access\r
3749 //\r
3750 RegAddress = Address | INDEX_OF (Command);\r
3751 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3752\r
3753 if (IsMem) {\r
3754 if (IsBar32) {\r
3755 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3756 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3757\r
3758 } else {\r
46cb4043 3759 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
5d73d92f 3760 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
c37e0f16 3761 ShellPrintEx (-1, -1, L" ");\r
5d73d92f 3762 ShellPrintHiiEx(-1, -1, NULL,\r
3763 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3764 gShellDebug1HiiHandle,\r
46cb4043 3765 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
5d73d92f 3766 );\r
2b578de0 3767 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
5d73d92f 3768\r
3769 }\r
3770 } else {\r
3771 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3772 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3773 }\r
3774\r
3775 return EFI_SUCCESS;\r
3776}\r
3777\r
a1d4bfcc 3778/**\r
3779 Explain the cardbus specific part of data in PCI configuration space.\r
3780\r
3781 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3782 @param[in] Address Address used to access configuration space of this PCI device.\r
3783 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3784\r
3785 @retval EFI_SUCCESS The command completed successfully.\r
3786**/\r
5d73d92f 3787EFI_STATUS\r
3788PciExplainCardBusData (\r
3789 IN PCI_CARDBUS_HEADER *CardBus,\r
3790 IN UINT64 Address,\r
3791 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3792 )\r
5d73d92f 3793{\r
3794 BOOLEAN Io32Bit;\r
3795 PCI_CARDBUS_DATA *CardBusData;\r
3796\r
3797 ShellPrintHiiEx(-1, -1, NULL,\r
3798 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3799 gShellDebug1HiiHandle,\r
3800 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3801 CardBus->CardBusSocketReg\r
3802 );\r
3803\r
3804 //\r
3805 // Print Secondary Status\r
3806 //\r
3807 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3808\r
3809 //\r
3810 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3811 // Subordinate bus number\r
3812 //\r
3813 ShellPrintHiiEx(-1, -1, NULL,\r
3814 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3815 gShellDebug1HiiHandle,\r
3816 INDEX_OF (&(CardBus->PciBusNumber)),\r
3817 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3818 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3819 );\r
3820\r
c37e0f16 3821 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3822\r
3823 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3824 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3825 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3826\r
3827 //\r
3828 // Print CardBus Latency Timer\r
3829 //\r
3830 ShellPrintHiiEx(-1, -1, NULL,\r
3831 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3832 gShellDebug1HiiHandle,\r
3833 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3834 CardBus->CardBusLatencyTimer\r
3835 );\r
3836\r
3837 //\r
3838 // Print Memory/Io ranges this cardbus bridge forwards\r
3839 //\r
3840 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 3841 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3842\r
3843 ShellPrintHiiEx(-1, -1, NULL,\r
3844 STRING_TOKEN (STR_PCI2_MEM_3),\r
3845 gShellDebug1HiiHandle,\r
3846 INDEX_OF (&(CardBus->MemoryBase0)),\r
3847 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3848 CardBus->MemoryBase0 & 0xfffff000,\r
3849 CardBus->MemoryLimit0 | 0x00000fff\r
3850 );\r
3851\r
3852 ShellPrintHiiEx(-1, -1, NULL,\r
3853 STRING_TOKEN (STR_PCI2_MEM_3),\r
3854 gShellDebug1HiiHandle,\r
3855 INDEX_OF (&(CardBus->MemoryBase1)),\r
3856 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3857 CardBus->MemoryBase1 & 0xfffff000,\r
3858 CardBus->MemoryLimit1 | 0x00000fff\r
3859 );\r
3860\r
3861 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3862 ShellPrintHiiEx(-1, -1, NULL,\r
3863 STRING_TOKEN (STR_PCI2_IO_2),\r
3864 gShellDebug1HiiHandle,\r
3865 INDEX_OF (&(CardBus->IoBase0)),\r
3866 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3867 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3868 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3869 );\r
3870\r
3871 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3872 ShellPrintHiiEx(-1, -1, NULL,\r
3873 STRING_TOKEN (STR_PCI2_IO_2),\r
3874 gShellDebug1HiiHandle,\r
3875 INDEX_OF (&(CardBus->IoBase1)),\r
3876 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3877 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3878 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3879 );\r
3880\r
3881 //\r
3882 // Print register Interrupt Line & PIN\r
3883 //\r
3884 ShellPrintHiiEx(-1, -1, NULL,\r
3885 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3886 gShellDebug1HiiHandle,\r
3887 INDEX_OF (&(CardBus->InterruptLine)),\r
3888 CardBus->InterruptLine,\r
3889 INDEX_OF (&(CardBus->InterruptPin)),\r
3890 CardBus->InterruptPin\r
3891 );\r
3892\r
3893 //\r
3894 // Print register Bridge Control\r
3895 //\r
3896 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3897\r
3898 //\r
3899 // Print some registers in data region of PCI configuration space for cardbus\r
3900 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3901 // Address.\r
3902 //\r
3903 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3904\r
3905 ShellPrintHiiEx(-1, -1, NULL,\r
3906 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3907 gShellDebug1HiiHandle,\r
3908 INDEX_OF (&(CardBusData->SubVendorId)),\r
3909 CardBusData->SubVendorId,\r
3910 INDEX_OF (&(CardBusData->SubSystemId)),\r
3911 CardBusData->SubSystemId\r
3912 );\r
3913\r
3914 ShellPrintHiiEx(-1, -1, NULL,\r
3915 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3916 gShellDebug1HiiHandle,\r
3917 INDEX_OF (&(CardBusData->LegacyBase)),\r
3918 CardBusData->LegacyBase\r
3919 );\r
3920\r
3921 return EFI_SUCCESS;\r
3922}\r
3923\r
a1d4bfcc 3924/**\r
3925 Explain each meaningful bit of register Status. The definition of Status is\r
3926 slightly different depending on the PCI header type.\r
3927\r
3928 @param[in] Status Points to the content of register Status.\r
3929 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3930 status).\r
3931 @param[in] HeaderType Header type of this PCI device.\r
3932\r
3933 @retval EFI_SUCCESS The command completed successfully.\r
3934**/\r
5d73d92f 3935EFI_STATUS\r
3936PciExplainStatus (\r
3937 IN UINT16 *Status,\r
3938 IN BOOLEAN MainStatus,\r
3939 IN PCI_HEADER_TYPE HeaderType\r
3940 )\r
5d73d92f 3941{\r
3942 if (MainStatus) {\r
3943 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3944\r
3945 } else {\r
3946 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3947 }\r
3948\r
3949 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3950\r
3951 //\r
3952 // Bit 5 is meaningless for CardBus Bridge\r
3953 //\r
3954 if (HeaderType == PciCardBusBridge) {\r
3955 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3956\r
3957 } else {\r
3958 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3959 }\r
3960\r
3961 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3962\r
3963 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3964 //\r
3965 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3966 //\r
3967 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3968 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3969 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3970\r
3971 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3972 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3973\r
3974 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3975 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3976\r
3977 } else {\r
3978 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3979 }\r
3980\r
3981 ShellPrintHiiEx(-1, -1, NULL,\r
3982 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3983 gShellDebug1HiiHandle,\r
3984 (*Status & PCI_BIT_11) != 0\r
3985 );\r
3986\r
3987 ShellPrintHiiEx(-1, -1, NULL,\r
3988 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3989 gShellDebug1HiiHandle,\r
3990 (*Status & PCI_BIT_12) != 0\r
3991 );\r
3992\r
3993 ShellPrintHiiEx(-1, -1, NULL,\r
3994 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3995 gShellDebug1HiiHandle,\r
3996 (*Status & PCI_BIT_13) != 0\r
3997 );\r
3998\r
3999 if (MainStatus) {\r
4000 ShellPrintHiiEx(-1, -1, NULL,\r
4001 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
4002 gShellDebug1HiiHandle,\r
4003 (*Status & PCI_BIT_14) != 0\r
4004 );\r
4005\r
4006 } else {\r
4007 ShellPrintHiiEx(-1, -1, NULL,\r
4008 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
4009 gShellDebug1HiiHandle,\r
4010 (*Status & PCI_BIT_14) != 0\r
4011 );\r
4012 }\r
4013\r
4014 ShellPrintHiiEx(-1, -1, NULL,\r
4015 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
4016 gShellDebug1HiiHandle,\r
4017 (*Status & PCI_BIT_15) != 0\r
4018 );\r
4019\r
4020 return EFI_SUCCESS;\r
4021}\r
4022\r
a1d4bfcc 4023/**\r
5d73d92f 4024 Explain each meaningful bit of register Command.\r
4025\r
a1d4bfcc 4026 @param[in] Command Points to the content of register Command.\r
5d73d92f 4027\r
a1d4bfcc 4028 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 4029**/\r
a1d4bfcc 4030EFI_STATUS\r
4031PciExplainCommand (\r
4032 IN UINT16 *Command\r
4033 )\r
5d73d92f 4034{\r
4035 //\r
4036 // Print the binary value of register Command\r
4037 //\r
4038 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
4039\r
4040 //\r
4041 // Explain register Command bit by bit\r
4042 //\r
4043 ShellPrintHiiEx(-1, -1, NULL,\r
4044 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
4045 gShellDebug1HiiHandle,\r
4046 (*Command & PCI_BIT_0) != 0\r
4047 );\r
4048\r
4049 ShellPrintHiiEx(-1, -1, NULL,\r
4050 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
4051 gShellDebug1HiiHandle,\r
4052 (*Command & PCI_BIT_1) != 0\r
4053 );\r
4054\r
4055 ShellPrintHiiEx(-1, -1, NULL,\r
4056 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
4057 gShellDebug1HiiHandle,\r
4058 (*Command & PCI_BIT_2) != 0\r
4059 );\r
4060\r
4061 ShellPrintHiiEx(-1, -1, NULL,\r
4062 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
4063 gShellDebug1HiiHandle,\r
4064 (*Command & PCI_BIT_3) != 0\r
4065 );\r
4066\r
4067 ShellPrintHiiEx(-1, -1, NULL,\r
4068 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
4069 gShellDebug1HiiHandle,\r
4070 (*Command & PCI_BIT_4) != 0\r
4071 );\r
4072\r
4073 ShellPrintHiiEx(-1, -1, NULL,\r
4074 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
4075 gShellDebug1HiiHandle,\r
4076 (*Command & PCI_BIT_5) != 0\r
4077 );\r
4078\r
4079 ShellPrintHiiEx(-1, -1, NULL,\r
4080 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
4081 gShellDebug1HiiHandle,\r
4082 (*Command & PCI_BIT_6) != 0\r
4083 );\r
4084\r
4085 ShellPrintHiiEx(-1, -1, NULL,\r
4086 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
4087 gShellDebug1HiiHandle,\r
4088 (*Command & PCI_BIT_7) != 0\r
4089 );\r
4090\r
4091 ShellPrintHiiEx(-1, -1, NULL,\r
4092 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
4093 gShellDebug1HiiHandle,\r
4094 (*Command & PCI_BIT_8) != 0\r
4095 );\r
4096\r
4097 ShellPrintHiiEx(-1, -1, NULL,\r
4098 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
4099 gShellDebug1HiiHandle,\r
4100 (*Command & PCI_BIT_9) != 0\r
4101 );\r
4102\r
4103 return EFI_SUCCESS;\r
4104}\r
4105\r
a1d4bfcc 4106/**\r
4107 Explain each meaningful bit of register Bridge Control.\r
4108\r
4109 @param[in] BridgeControl Points to the content of register Bridge Control.\r
4110 @param[in] HeaderType The headertype.\r
4111\r
4112 @retval EFI_SUCCESS The command completed successfully.\r
4113**/\r
5d73d92f 4114EFI_STATUS\r
4115PciExplainBridgeControl (\r
4116 IN UINT16 *BridgeControl,\r
4117 IN PCI_HEADER_TYPE HeaderType\r
4118 )\r
5d73d92f 4119{\r
4120 ShellPrintHiiEx(-1, -1, NULL,\r
4121 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
4122 gShellDebug1HiiHandle,\r
4123 INDEX_OF (BridgeControl),\r
4124 *BridgeControl\r
4125 );\r
4126\r
4127 ShellPrintHiiEx(-1, -1, NULL,\r
4128 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
4129 gShellDebug1HiiHandle,\r
4130 (*BridgeControl & PCI_BIT_0) != 0\r
4131 );\r
4132 ShellPrintHiiEx(-1, -1, NULL,\r
4133 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
4134 gShellDebug1HiiHandle,\r
4135 (*BridgeControl & PCI_BIT_1) != 0\r
4136 );\r
4137 ShellPrintHiiEx(-1, -1, NULL,\r
4138 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
4139 gShellDebug1HiiHandle,\r
4140 (*BridgeControl & PCI_BIT_2) != 0\r
4141 );\r
4142 ShellPrintHiiEx(-1, -1, NULL,\r
4143 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
4144 gShellDebug1HiiHandle,\r
4145 (*BridgeControl & PCI_BIT_3) != 0\r
4146 );\r
4147 ShellPrintHiiEx(-1, -1, NULL,\r
4148 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
4149 gShellDebug1HiiHandle,\r
4150 (*BridgeControl & PCI_BIT_5) != 0\r
4151 );\r
4152\r
4153 //\r
4154 // Register Bridge Control has some slight differences between P2P bridge\r
4155 // and Cardbus bridge from bit 6 to bit 11.\r
4156 //\r
4157 if (HeaderType == PciP2pBridge) {\r
4158 ShellPrintHiiEx(-1, -1, NULL,\r
4159 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
4160 gShellDebug1HiiHandle,\r
4161 (*BridgeControl & PCI_BIT_6) != 0\r
4162 );\r
4163 ShellPrintHiiEx(-1, -1, NULL,\r
4164 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
4165 gShellDebug1HiiHandle,\r
4166 (*BridgeControl & PCI_BIT_7) != 0\r
4167 );\r
4168 ShellPrintHiiEx(-1, -1, NULL,\r
4169 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
4170 gShellDebug1HiiHandle,\r
4171 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
4172 );\r
4173 ShellPrintHiiEx(-1, -1, NULL,\r
4174 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
4175 gShellDebug1HiiHandle,\r
4176 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
4177 );\r
4178 ShellPrintHiiEx(-1, -1, NULL,\r
4179 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
4180 gShellDebug1HiiHandle,\r
4181 (*BridgeControl & PCI_BIT_10) != 0\r
4182 );\r
4183 ShellPrintHiiEx(-1, -1, NULL,\r
4184 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
4185 gShellDebug1HiiHandle,\r
4186 (*BridgeControl & PCI_BIT_11) != 0\r
4187 );\r
4188\r
4189 } else {\r
4190 ShellPrintHiiEx(-1, -1, NULL,\r
4191 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
4192 gShellDebug1HiiHandle,\r
4193 (*BridgeControl & PCI_BIT_6) != 0\r
4194 );\r
4195 ShellPrintHiiEx(-1, -1, NULL,\r
4196 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
4197 gShellDebug1HiiHandle,\r
4198 (*BridgeControl & PCI_BIT_7) != 0\r
4199 );\r
4200 ShellPrintHiiEx(-1, -1, NULL,\r
4201 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
4202 gShellDebug1HiiHandle,\r
4203 (*BridgeControl & PCI_BIT_10) != 0\r
4204 );\r
4205 }\r
4206\r
4207 return EFI_SUCCESS;\r
4208}\r
4209\r
a1d4bfcc 4210/**\r
4211 Print each capability structure.\r
4212\r
f614ce7e
SQ		 4213 @param[in] IoDev The pointer to the deivce.\r
4214 @param[in] Address The address to start at.\r
4215 @param[in] CapPtr The offset from the address.\r
4216 @param[in] EnhancedDump The print format for the dump data.\r
a1d4bfcc 4217\r
4218 @retval EFI_SUCCESS The operation was successful.\r
4219**/\r
5d73d92f 4220EFI_STATUS\r
4221PciExplainCapabilityStruct (\r
4222 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
4223 IN UINT64 Address,\r
705bffb5
JC		 4224 IN UINT8 CapPtr,\r
4225 IN CONST UINT16 EnhancedDump\r
5d73d92f 4226 )\r
4227{\r
4228 UINT8 CapabilityPtr;\r
4229 UINT16 CapabilityEntry;\r
4230 UINT8 CapabilityID;\r
4231 UINT64 RegAddress;\r
4232\r
4233 CapabilityPtr = CapPtr;\r
4234\r
4235 //\r
4236 // Go through the Capability list\r
4237 //\r
4238 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
4239 RegAddress = Address + CapabilityPtr;\r
4240 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
4241\r
4242 CapabilityID = (UINT8) CapabilityEntry;\r
4243\r
4244 //\r
4245 // Explain PciExpress data\r
4246 //\r
4247 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
705bffb5 4248 PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r
5d73d92f 4249 return EFI_SUCCESS;\r
4250 }\r
4251 //\r
4252 // Explain other capabilities here\r
4253 //\r
4254 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
4255 }\r
4256\r
4257 return EFI_SUCCESS;\r
4258}\r
4259\r
a1d4bfcc 4260/**\r
4261 Print out information of the capability information.\r
4262\r
4263 @param[in] PciExpressCap The pointer to the structure about the device.\r
4264\r
4265 @retval EFI_SUCCESS The operation was successful.\r
4266**/\r
5d73d92f 4267EFI_STATUS\r
4268ExplainPcieCapReg (\r
2412c297 4269 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4270 )\r
5d73d92f 4271{\r
4272 UINT16 PcieCapReg;\r
4273 CHAR16 *DevicePortType;\r
4274\r
4275 PcieCapReg = PciExpressCap->PcieCapReg;\r
c37e0f16
CP		 4276 ShellPrintEx (-1, -1,\r
4277 L" Capability Version(3:0): %E0x%04x%N\r\n",\r
5d73d92f 4278 PCIE_CAP_VERSION (PcieCapReg)\r
4279 );\r
4280 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
4281 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
4282 } else {\r
4283 DevicePortType = L"Unknown Type";\r
4284 }\r
c37e0f16
CP		 4285 ShellPrintEx (-1, -1,\r
4286 L" Device/PortType(7:4): %E%s%N\r\n",\r
5d73d92f 4287 DevicePortType\r
4288 );\r
4289 //\r
4290 // 'Slot Implemented' is only valid for:\r
4291 // a) Root Port of PCI Express Root Complex, or\r
4292 // b) Downstream Port of PCI Express Switch\r
4293 //\r
4294 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
4295 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
c37e0f16
CP		 4296 ShellPrintEx (-1, -1,\r
4297 L" Slot Implemented(8): %E%d%N\r\n",\r
5d73d92f 4298 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
4299 );\r
4300 }\r
c37e0f16
CP		 4301 ShellPrintEx (-1, -1,\r
4302 L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
5d73d92f 4303 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
4304 );\r
4305 return EFI_SUCCESS;\r
4306}\r
4307\r
a1d4bfcc 4308/**\r
4309 Print out information of the device capability information.\r
4310\r
4311 @param[in] PciExpressCap The pointer to the structure about the device.\r
4312\r
4313 @retval EFI_SUCCESS The operation was successful.\r
4314**/\r
5d73d92f 4315EFI_STATUS\r
4316ExplainPcieDeviceCap (\r
2412c297 4317 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4318 )\r
5d73d92f 4319{\r
4320 UINT16 PcieCapReg;\r
4321 UINT32 PcieDeviceCap;\r
4322 UINT8 DevicePortType;\r
4323 UINT8 L0sLatency;\r
4324 UINT8 L1Latency;\r
4325\r
4326 PcieCapReg = PciExpressCap->PcieCapReg;\r
4327 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
4328 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
c37e0f16 4329 ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
5d73d92f 4330 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
c37e0f16 4331 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
5d73d92f 4332 } else {\r
c37e0f16 4333 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4334 }\r
c37e0f16
CP		 4335 ShellPrintEx (-1, -1,\r
4336 L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
5d73d92f 4337 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
4338 );\r
c37e0f16
CP		 4339 ShellPrintEx (-1, -1,\r
4340 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
5d73d92f 4341 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
4342 );\r
4343 //\r
4344 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
4345 //\r
4346 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
a1d4bfcc 4347 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
4348 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
c37e0f16 4349 ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
5d73d92f 4350 if (L0sLatency < 4) {\r
c37e0f16 4351 ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
5d73d92f 4352 } else {\r
4353 if (L0sLatency < 7) {\r
c37e0f16 4354 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
5d73d92f 4355 } else {\r
c37e0f16 4356 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 4357 }\r
4358 }\r
c37e0f16 4359 ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
5d73d92f 4360 if (L1Latency < 7) {\r
c37e0f16 4361 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
5d73d92f 4362 } else {\r
c37e0f16 4363 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 4364 }\r
4365 }\r
c37e0f16
CP		 4366 ShellPrintEx (-1, -1,\r
4367 L" Role-based Error Reporting(15): %E%d%N\r\n",\r
5d73d92f 4368 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
4369 );\r
4370 //\r
4371 // Only valid for Upstream Port:\r
4372 // a) Captured Slot Power Limit Value\r
4373 // b) Captured Slot Power Scale\r
4374 //\r
4375 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
c37e0f16
CP		 4376 ShellPrintEx (-1, -1,\r
4377 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
5d73d92f 4378 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
4379 );\r
c37e0f16
CP		 4380 ShellPrintEx (-1, -1,\r
4381 L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
5d73d92f 4382 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
4383 );\r
4384 }\r
4385 //\r
4386 // Function Level Reset Capability is only valid for Endpoint\r
4387 //\r
4388 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
c37e0f16
CP		 4389 ShellPrintEx (-1, -1,\r
4390 L" Function Level Reset Capability(28): %E%d%N\r\n",\r
5d73d92f 4391 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
4392 );\r
4393 }\r
4394 return EFI_SUCCESS;\r
4395}\r
4396\r
a1d4bfcc 4397/**\r
4398 Print out information of the device control information.\r
4399\r
4400 @param[in] PciExpressCap The pointer to the structure about the device.\r
4401\r
4402 @retval EFI_SUCCESS The operation was successful.\r
4403**/\r
5d73d92f 4404EFI_STATUS\r
4405ExplainPcieDeviceControl (\r
2412c297 4406 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4407 )\r
5d73d92f 4408{\r
4409 UINT16 PcieCapReg;\r
4410 UINT16 PcieDeviceControl;\r
4411\r
4412 PcieCapReg = PciExpressCap->PcieCapReg;\r
4413 PcieDeviceControl = PciExpressCap->DeviceControl;\r
c37e0f16
CP		 4414 ShellPrintEx (-1, -1,\r
4415 L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
5d73d92f 4416 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4417 );\r
c37e0f16
CP		 4418 ShellPrintEx (-1, -1,\r
4419 L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
5d73d92f 4420 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4421 );\r
c37e0f16
CP		 4422 ShellPrintEx (-1, -1,\r
4423 L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
5d73d92f 4424 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4425 );\r
c37e0f16
CP		 4426 ShellPrintEx (-1, -1,\r
4427 L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
5d73d92f 4428 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
4429 );\r
c37e0f16
CP		 4430 ShellPrintEx (-1, -1,\r
4431 L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
5d73d92f 4432 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
4433 );\r
c37e0f16 4434 ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
5d73d92f 4435 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
c37e0f16 4436 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
5d73d92f 4437 } else {\r
c37e0f16 4438 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4439 }\r
c37e0f16
CP		 4440 ShellPrintEx (-1, -1,\r
4441 L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
5d73d92f 4442 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
4443 );\r
c37e0f16
CP		 4444 ShellPrintEx (-1, -1,\r
4445 L" Phantom Functions Enable(9): %E%d%N\r\n",\r
5d73d92f 4446 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
4447 );\r
c37e0f16
CP		 4448 ShellPrintEx (-1, -1,\r
4449 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
5d73d92f 4450 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
4451 );\r
c37e0f16
CP		 4452 ShellPrintEx (-1, -1,\r
4453 L" Enable No Snoop(11): %E%d%N\r\n",\r
5d73d92f 4454 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
4455 );\r
c37e0f16 4456 ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
5d73d92f 4457 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
c37e0f16 4458 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
5d73d92f 4459 } else {\r
c37e0f16 4460 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4461 }\r
4462 //\r
4463 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
4464 //\r
4465 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
c37e0f16
CP		 4466 ShellPrintEx (-1, -1,\r
4467 L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
5d73d92f 4468 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
4469 );\r
4470 }\r
4471 return EFI_SUCCESS;\r
4472}\r
4473\r
a1d4bfcc 4474/**\r
4475 Print out information of the device status information.\r
4476\r
4477 @param[in] PciExpressCap The pointer to the structure about the device.\r
4478\r
4479 @retval EFI_SUCCESS The operation was successful.\r
4480**/\r
5d73d92f 4481EFI_STATUS\r
4482ExplainPcieDeviceStatus (\r
2412c297 4483 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4484 )\r
5d73d92f 4485{\r
4486 UINT16 PcieDeviceStatus;\r
4487\r
4488 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
c37e0f16
CP		 4489 ShellPrintEx (-1, -1,\r
4490 L" Correctable Error Detected(0): %E%d%N\r\n",\r
5d73d92f 4491 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
4492 );\r
c37e0f16
CP		 4493 ShellPrintEx (-1, -1,\r
4494 L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
5d73d92f 4495 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
4496 );\r
c37e0f16
CP		 4497 ShellPrintEx (-1, -1,\r
4498 L" Fatal Error Detected(2): %E%d%N\r\n",\r
5d73d92f 4499 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
4500 );\r
c37e0f16
CP		 4501 ShellPrintEx (-1, -1,\r
4502 L" Unsupported Request Detected(3): %E%d%N\r\n",\r
5d73d92f 4503 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
4504 );\r
c37e0f16
CP		 4505 ShellPrintEx (-1, -1,\r
4506 L" AUX Power Detected(4): %E%d%N\r\n",\r
5d73d92f 4507 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
4508 );\r
c37e0f16
CP		 4509 ShellPrintEx (-1, -1,\r
4510 L" Transactions Pending(5): %E%d%N\r\n",\r
5d73d92f 4511 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
4512 );\r
4513 return EFI_SUCCESS;\r
4514}\r
4515\r
a1d4bfcc 4516/**\r
4517 Print out information of the device link information.\r
4518\r
4519 @param[in] PciExpressCap The pointer to the structure about the device.\r
4520\r
4521 @retval EFI_SUCCESS The operation was successful.\r
4522**/\r
5d73d92f 4523EFI_STATUS\r
4524ExplainPcieLinkCap (\r
2412c297 4525 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4526 )\r
5d73d92f 4527{\r
4528 UINT32 PcieLinkCap;\r
541ddf44 4529 CHAR16 *MaxLinkSpeed;\r
a1d4bfcc 4530 CHAR16 *AspmValue;\r
5d73d92f 4531\r
4532 PcieLinkCap = PciExpressCap->LinkCap;\r
541ddf44 4533 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
5d73d92f 4534 case 1:\r
541ddf44 4535 MaxLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4536 break;\r
4537 case 2:\r
541ddf44
CP		 4538 MaxLinkSpeed = L"5.0 GT/s";\r
4539 break;\r
4540 case 3:\r
4541 MaxLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4542 break;\r
4543 default:\r
541ddf44 4544 MaxLinkSpeed = L"Unknown";\r
5d73d92f 4545 break;\r
4546 }\r
c37e0f16 4547 ShellPrintEx (-1, -1,\r
541ddf44
CP		 4548 L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
4549 MaxLinkSpeed\r
5d73d92f 4550 );\r
c37e0f16
CP		 4551 ShellPrintEx (-1, -1,\r
4552 L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
5d73d92f 4553 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
4554 );\r
4555 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
541ddf44
CP		 4556 case 0:\r
4557 AspmValue = L"Not";\r
4558 break;\r
5d73d92f 4559 case 1:\r
541ddf44
CP		 4560 AspmValue = L"L0s";\r
4561 break;\r
4562 case 2:\r
4563 AspmValue = L"L1";\r
5d73d92f 4564 break;\r
4565 case 3:\r
a1d4bfcc 4566 AspmValue = L"L0s and L1";\r
5d73d92f 4567 break;\r
4568 default:\r
a1d4bfcc 4569 AspmValue = L"Reserved";\r
5d73d92f 4570 break;\r
4571 }\r
c37e0f16
CP		 4572 ShellPrintEx (-1, -1,\r
4573 L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
a1d4bfcc 4574 AspmValue\r
5d73d92f 4575 );\r
c37e0f16
CP		 4576 ShellPrintEx (-1, -1,\r
4577 L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
a1d4bfcc 4578 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4579 );\r
c37e0f16
CP		 4580 ShellPrintEx (-1, -1,\r
4581 L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
a1d4bfcc 4582 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4583 );\r
c37e0f16
CP		 4584 ShellPrintEx (-1, -1,\r
4585 L" Clock Power Management(18): %E%d%N\r\n",\r
5d73d92f 4586 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4587 );\r
c37e0f16
CP		 4588 ShellPrintEx (-1, -1,\r
4589 L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
5d73d92f 4590 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4591 );\r
c37e0f16
CP		 4592 ShellPrintEx (-1, -1,\r
4593 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
5d73d92f 4594 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4595 );\r
c37e0f16
CP		 4596 ShellPrintEx (-1, -1,\r
4597 L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
5d73d92f 4598 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4599 );\r
c37e0f16
CP		 4600 ShellPrintEx (-1, -1,\r
4601 L" Port Number(31:24): %E0x%02x%N\r\n",\r
5d73d92f 4602 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4603 );\r
4604 return EFI_SUCCESS;\r
4605}\r
4606\r
a1d4bfcc 4607/**\r
4608 Print out information of the device link control information.\r
4609\r
4610 @param[in] PciExpressCap The pointer to the structure about the device.\r
4611\r
4612 @retval EFI_SUCCESS The operation was successful.\r
4613**/\r
5d73d92f 4614EFI_STATUS\r
4615ExplainPcieLinkControl (\r
2412c297 4616 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4617 )\r
5d73d92f 4618{\r
4619 UINT16 PcieLinkControl;\r
4620 UINT8 DevicePortType;\r
4621\r
4622 PcieLinkControl = PciExpressCap->LinkControl;\r
4623 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
c37e0f16
CP		 4624 ShellPrintEx (-1, -1,\r
4625 L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
5d73d92f 4626 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4627 );\r
4628 //\r
4629 // RCB is not applicable to switches\r
4630 //\r
4631 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
c37e0f16
CP		 4632 ShellPrintEx (-1, -1,\r
4633 L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
5d73d92f 4634 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4635 );\r
4636 }\r
4637 //\r
4638 // Link Disable is reserved on\r
4639 // a) Endpoints\r
4640 // b) PCI Express to PCI/PCI-X bridges\r
4641 // c) Upstream Ports of Switches\r
4642 //\r
4643 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4644 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4645 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
c37e0f16
CP		 4646 ShellPrintEx (-1, -1,\r
4647 L" Link Disable(4): %E%d%N\r\n",\r
5d73d92f 4648 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4649 );\r
4650 }\r
c37e0f16
CP		 4651 ShellPrintEx (-1, -1,\r
4652 L" Common Clock Configuration(6): %E%d%N\r\n",\r
5d73d92f 4653 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4654 );\r
c37e0f16
CP		 4655 ShellPrintEx (-1, -1,\r
4656 L" Extended Synch(7): %E%d%N\r\n",\r
5d73d92f 4657 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4658 );\r
c37e0f16
CP		 4659 ShellPrintEx (-1, -1,\r
4660 L" Enable Clock Power Management(8): %E%d%N\r\n",\r
5d73d92f 4661 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4662 );\r
c37e0f16
CP		 4663 ShellPrintEx (-1, -1,\r
4664 L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
5d73d92f 4665 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4666 );\r
c37e0f16
CP		 4667 ShellPrintEx (-1, -1,\r
4668 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
5d73d92f 4669 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4670 );\r
c37e0f16
CP		 4671 ShellPrintEx (-1, -1,\r
4672 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
5d73d92f 4673 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4674 );\r
4675 return EFI_SUCCESS;\r
4676}\r
4677\r
a1d4bfcc 4678/**\r
4679 Print out information of the device link status information.\r
4680\r
4681 @param[in] PciExpressCap The pointer to the structure about the device.\r
4682\r
4683 @retval EFI_SUCCESS The operation was successful.\r
4684**/\r
5d73d92f 4685EFI_STATUS\r
4686ExplainPcieLinkStatus (\r
2412c297 4687 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4688 )\r
5d73d92f 4689{\r
4690 UINT16 PcieLinkStatus;\r
541ddf44 4691 CHAR16 *CurLinkSpeed;\r
5d73d92f 4692\r
4693 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4694 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4695 case 1:\r
541ddf44 4696 CurLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4697 break;\r
4698 case 2:\r
541ddf44
CP		 4699 CurLinkSpeed = L"5.0 GT/s";\r
4700 break;\r
4701 case 3:\r
4702 CurLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4703 break;\r
4704 default:\r
541ddf44 4705 CurLinkSpeed = L"Reserved";\r
5d73d92f 4706 break;\r
4707 }\r
c37e0f16
CP		 4708 ShellPrintEx (-1, -1,\r
4709 L" Current Link Speed(3:0): %E%s%N\r\n",\r
541ddf44 4710 CurLinkSpeed\r
5d73d92f 4711 );\r
c37e0f16
CP		 4712 ShellPrintEx (-1, -1,\r
4713 L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
5d73d92f 4714 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4715 );\r
c37e0f16
CP		 4716 ShellPrintEx (-1, -1,\r
4717 L" Link Training(11): %E%d%N\r\n",\r
5d73d92f 4718 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4719 );\r
c37e0f16
CP		 4720 ShellPrintEx (-1, -1,\r
4721 L" Slot Clock Configuration(12): %E%d%N\r\n",\r
5d73d92f 4722 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4723 );\r
c37e0f16
CP		 4724 ShellPrintEx (-1, -1,\r
4725 L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
5d73d92f 4726 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4727 );\r
c37e0f16
CP		 4728 ShellPrintEx (-1, -1,\r
4729 L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
5d73d92f 4730 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4731 );\r
c37e0f16
CP		 4732 ShellPrintEx (-1, -1,\r
4733 L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
5d73d92f 4734 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4735 );\r
4736 return EFI_SUCCESS;\r
4737}\r
4738\r
a1d4bfcc 4739/**\r
4740 Print out information of the device slot information.\r
4741\r
4742 @param[in] PciExpressCap The pointer to the structure about the device.\r
4743\r
4744 @retval EFI_SUCCESS The operation was successful.\r
4745**/\r
5d73d92f 4746EFI_STATUS\r
4747ExplainPcieSlotCap (\r
2412c297 4748 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4749 )\r
5d73d92f 4750{\r
4751 UINT32 PcieSlotCap;\r
4752\r
4753 PcieSlotCap = PciExpressCap->SlotCap;\r
4754\r
c37e0f16
CP		 4755 ShellPrintEx (-1, -1,\r
4756 L" Attention Button Present(0): %E%d%N\r\n",\r
5d73d92f 4757 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4758 );\r
c37e0f16
CP		 4759 ShellPrintEx (-1, -1,\r
4760 L" Power Controller Present(1): %E%d%N\r\n",\r
5d73d92f 4761 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4762 );\r
c37e0f16
CP		 4763 ShellPrintEx (-1, -1,\r
4764 L" MRL Sensor Present(2): %E%d%N\r\n",\r
5d73d92f 4765 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4766 );\r
c37e0f16
CP		 4767 ShellPrintEx (-1, -1,\r
4768 L" Attention Indicator Present(3): %E%d%N\r\n",\r
5d73d92f 4769 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4770 );\r
c37e0f16
CP		 4771 ShellPrintEx (-1, -1,\r
4772 L" Power Indicator Present(4): %E%d%N\r\n",\r
5d73d92f 4773 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4774 );\r
c37e0f16
CP		 4775 ShellPrintEx (-1, -1,\r
4776 L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
5d73d92f 4777 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4778 );\r
c37e0f16
CP		 4779 ShellPrintEx (-1, -1,\r
4780 L" Hot-Plug Capable(6): %E%d%N\r\n",\r
5d73d92f 4781 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4782 );\r
c37e0f16
CP		 4783 ShellPrintEx (-1, -1,\r
4784 L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
5d73d92f 4785 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4786 );\r
c37e0f16
CP		 4787 ShellPrintEx (-1, -1,\r
4788 L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
5d73d92f 4789 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4790 );\r
c37e0f16
CP		 4791 ShellPrintEx (-1, -1,\r
4792 L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
5d73d92f 4793 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4794 );\r
c37e0f16
CP		 4795 ShellPrintEx (-1, -1,\r
4796 L" No Command Completed Support(18): %E%d%N\r\n",\r
5d73d92f 4797 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4798 );\r
c37e0f16
CP		 4799 ShellPrintEx (-1, -1,\r
4800 L" Physical Slot Number(31:19): %E%d%N\r\n",\r
5d73d92f 4801 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4802 );\r
4803\r
4804 return EFI_SUCCESS;\r
4805}\r
4806\r
a1d4bfcc 4807/**\r
4808 Print out information of the device slot control information.\r
4809\r
4810 @param[in] PciExpressCap The pointer to the structure about the device.\r
4811\r
4812 @retval EFI_SUCCESS The operation was successful.\r
4813**/\r
5d73d92f 4814EFI_STATUS\r
4815ExplainPcieSlotControl (\r
2412c297 4816 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4817 )\r
5d73d92f 4818{\r
4819 UINT16 PcieSlotControl;\r
4820\r
4821 PcieSlotControl = PciExpressCap->SlotControl;\r
c37e0f16
CP		 4822 ShellPrintEx (-1, -1,\r
4823 L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
5d73d92f 4824 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4825 );\r
c37e0f16
CP		 4826 ShellPrintEx (-1, -1,\r
4827 L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
5d73d92f 4828 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4829 );\r
c37e0f16
CP		 4830 ShellPrintEx (-1, -1,\r
4831 L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
5d73d92f 4832 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4833 );\r
c37e0f16
CP		 4834 ShellPrintEx (-1, -1,\r
4835 L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
5d73d92f 4836 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4837 );\r
c37e0f16
CP		 4838 ShellPrintEx (-1, -1,\r
4839 L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
5d73d92f 4840 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4841 );\r
c37e0f16
CP		 4842 ShellPrintEx (-1, -1,\r
4843 L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
5d73d92f 4844 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4845 );\r
c37e0f16
CP		 4846 ShellPrintEx (-1, -1,\r
4847 L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
5d73d92f 4848 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4849 );\r
c37e0f16
CP		 4850 ShellPrintEx (-1, -1,\r
4851 L" Power Indicator Control(9:8): %E%s%N\r\n",\r
5d73d92f 4852 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4853 );\r
c37e0f16 4854 ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
5d73d92f 4855 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
c37e0f16 4856 ShellPrintEx (-1, -1, L"Off%N\r\n");\r
5d73d92f 4857 } else {\r
c37e0f16 4858 ShellPrintEx (-1, -1, L"On%N\r\n");\r
5d73d92f 4859 }\r
c37e0f16
CP		 4860 ShellPrintEx (-1, -1,\r
4861 L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
5d73d92f 4862 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4863 );\r
c37e0f16
CP		 4864 ShellPrintEx (-1, -1,\r
4865 L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
5d73d92f 4866 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4867 );\r
4868 return EFI_SUCCESS;\r
4869}\r
4870\r
a1d4bfcc 4871/**\r
4872 Print out information of the device slot status information.\r
4873\r
4874 @param[in] PciExpressCap The pointer to the structure about the device.\r
4875\r
4876 @retval EFI_SUCCESS The operation was successful.\r
4877**/\r
5d73d92f 4878EFI_STATUS\r
4879ExplainPcieSlotStatus (\r
2412c297 4880 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4881 )\r
5d73d92f 4882{\r
4883 UINT16 PcieSlotStatus;\r
4884\r
4885 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4886\r
c37e0f16
CP		 4887 ShellPrintEx (-1, -1,\r
4888 L" Attention Button Pressed(0): %E%d%N\r\n",\r
5d73d92f 4889 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4890 );\r
c37e0f16
CP		 4891 ShellPrintEx (-1, -1,\r
4892 L" Power Fault Detected(1): %E%d%N\r\n",\r
5d73d92f 4893 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4894 );\r
c37e0f16
CP		 4895 ShellPrintEx (-1, -1,\r
4896 L" MRL Sensor Changed(2): %E%d%N\r\n",\r
5d73d92f 4897 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4898 );\r
c37e0f16
CP		 4899 ShellPrintEx (-1, -1,\r
4900 L" Presence Detect Changed(3): %E%d%N\r\n",\r
5d73d92f 4901 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4902 );\r
c37e0f16
CP		 4903 ShellPrintEx (-1, -1,\r
4904 L" Command Completed(4): %E%d%N\r\n",\r
5d73d92f 4905 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4906 );\r
c37e0f16 4907 ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
5d73d92f 4908 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
c37e0f16 4909 ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
5d73d92f 4910 } else {\r
c37e0f16 4911 ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
5d73d92f 4912 }\r
c37e0f16 4913 ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
5d73d92f 4914 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
c37e0f16 4915 ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
5d73d92f 4916 } else {\r
c37e0f16 4917 ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
5d73d92f 4918 }\r
c37e0f16 4919 ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
5d73d92f 4920 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
c37e0f16 4921 ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
5d73d92f 4922 } else {\r
c37e0f16 4923 ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
5d73d92f 4924 }\r
c37e0f16
CP		 4925 ShellPrintEx (-1, -1,\r
4926 L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
5d73d92f 4927 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4928 );\r
4929 return EFI_SUCCESS;\r
4930}\r
4931\r
a1d4bfcc 4932/**\r
4933 Print out information of the device root information.\r
4934\r
4935 @param[in] PciExpressCap The pointer to the structure about the device.\r
4936\r
4937 @retval EFI_SUCCESS The operation was successful.\r
4938**/\r
5d73d92f 4939EFI_STATUS\r
4940ExplainPcieRootControl (\r
2412c297 4941 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4942 )\r
5d73d92f 4943{\r
4944 UINT16 PcieRootControl;\r
4945\r
4946 PcieRootControl = PciExpressCap->RootControl;\r
4947\r
c37e0f16
CP		 4948 ShellPrintEx (-1, -1,\r
4949 L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
5d73d92f 4950 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4951 );\r
c37e0f16
CP		 4952 ShellPrintEx (-1, -1,\r
4953 L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
5d73d92f 4954 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4955 );\r
c37e0f16
CP		 4956 ShellPrintEx (-1, -1,\r
4957 L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
5d73d92f 4958 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4959 );\r
c37e0f16
CP		 4960 ShellPrintEx (-1, -1,\r
4961 L" PME Interrupt Enable(3): %E%d%N\r\n",\r
5d73d92f 4962 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4963 );\r
c37e0f16
CP		 4964 ShellPrintEx (-1, -1,\r
4965 L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
5d73d92f 4966 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4967 );\r
4968\r
4969 return EFI_SUCCESS;\r
4970}\r
4971\r
a1d4bfcc 4972/**\r
4973 Print out information of the device root capability information.\r
4974\r
4975 @param[in] PciExpressCap The pointer to the structure about the device.\r
4976\r
4977 @retval EFI_SUCCESS The operation was successful.\r
4978**/\r
5d73d92f 4979EFI_STATUS\r
4980ExplainPcieRootCap (\r
2412c297 4981 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 4982 )\r
5d73d92f 4983{\r
4984 UINT16 PcieRootCap;\r
4985\r
4986 PcieRootCap = PciExpressCap->RsvdP;\r
4987\r
c37e0f16
CP		 4988 ShellPrintEx (-1, -1,\r
4989 L" CRS Software Visibility(0): %E%d%N\r\n",\r
5d73d92f 4990 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4991 );\r
4992\r
4993 return EFI_SUCCESS;\r
4994}\r
4995\r
a1d4bfcc 4996/**\r
4997 Print out information of the device root status information.\r
4998\r
4999 @param[in] PciExpressCap The pointer to the structure about the device.\r
5000\r
5001 @retval EFI_SUCCESS The operation was successful.\r
5002**/\r
5d73d92f 5003EFI_STATUS\r
5004ExplainPcieRootStatus (\r
2412c297 5005 IN PCIE_CAP_STRUCTURE *PciExpressCap\r
a1d4bfcc 5006 )\r
5d73d92f 5007{\r
5008 UINT32 PcieRootStatus;\r
5009\r
5010 PcieRootStatus = PciExpressCap->RootStatus;\r
5011\r
c37e0f16
CP		 5012 ShellPrintEx (-1, -1,\r
5013 L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
5d73d92f 5014 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
5015 );\r
c37e0f16
CP		 5016 ShellPrintEx (-1, -1,\r
5017 L" PME Status(16): %E%d%N\r\n",\r
5d73d92f 5018 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
5019 );\r
c37e0f16
CP		 5020 ShellPrintEx (-1, -1,\r
5021 L" PME Pending(17): %E%d%N\r\n",\r
5d73d92f 5022 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
5023 );\r
5024 return EFI_SUCCESS;\r
5025}\r
5026\r
705bffb5
JC		 5027/**\r
5028 Function to interpret and print out the link control structure\r
5029\r
5030 @param[in] HeaderAddress The Address of this capability header.\r
5031 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5032**/\r
5033EFI_STATUS\r
5034EFIAPI\r
5035PrintInterpretedExtendedCompatibilityLinkControl (\r
5036 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5037 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5038 )\r
5039{\r
5040 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
5041 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
5042\r
5043 ShellPrintHiiEx(\r
5044 -1, -1, NULL, \r
5045 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
5046 gShellDebug1HiiHandle, \r
5047 Header->RootComplexLinkCapabilities,\r
5048 Header->RootComplexLinkControl,\r
5049 Header->RootComplexLinkStatus\r
5050 ); \r
5051 DumpHex (\r
5052 4,\r
5053 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5054 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
5055 (VOID *) (HeaderAddress)\r
5056 );\r
5057 return (EFI_SUCCESS);\r
5058}\r
5059\r
5060/**\r
5061 Function to interpret and print out the power budgeting structure\r
5062\r
5063 @param[in] HeaderAddress The Address of this capability header.\r
5064 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5065**/\r
5066EFI_STATUS\r
5067EFIAPI\r
5068PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
5069 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5070 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5071 )\r
5072{\r
5073 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
5074 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
5075\r
5076 ShellPrintHiiEx(\r
5077 -1, -1, NULL, \r
5078 STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
5079 gShellDebug1HiiHandle, \r
5080 Header->DataSelect,\r
5081 Header->Data,\r
5082 Header->PowerBudgetCapability\r
5083 ); \r
5084 DumpHex (\r
5085 4,\r
5086 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5087 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
5088 (VOID *) (HeaderAddress)\r
5089 );\r
5090 return (EFI_SUCCESS);\r
5091}\r
5092\r
5093/**\r
5094 Function to interpret and print out the ACS structure\r
5095\r
5096 @param[in] HeaderAddress The Address of this capability header.\r
5097 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5098**/\r
5099EFI_STATUS\r
5100EFIAPI\r
5101PrintInterpretedExtendedCompatibilityAcs (\r
5102 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5103 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5104 )\r
5105{\r
5106 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r
5107 UINT16 VectorSize;\r
5108 UINT16 LoopCounter;\r
5109\r
5110 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r
5111 VectorSize = 0;\r
5112\r
5113 ShellPrintHiiEx(\r
5114 -1, -1, NULL, \r
5115 STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
5116 gShellDebug1HiiHandle, \r
5117 Header->AcsCapability,\r
5118 Header->AcsControl\r
5119 ); \r
5120 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
5121 VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
5122 if (VectorSize == 0) {\r
5123 VectorSize = 256;\r
5124 }\r
5125 for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
5126 ShellPrintHiiEx(\r
5127 -1, -1, NULL, \r
5128 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
5129 gShellDebug1HiiHandle, \r
5130 LoopCounter + 1,\r
5131 Header->EgressControlVectorArray[LoopCounter]\r
5132 ); \r
5133 }\r
5134 }\r
5135 DumpHex (\r
5136 4,\r
5137 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5138 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
5139 (VOID *) (HeaderAddress)\r
5140 );\r
5141 return (EFI_SUCCESS);\r
5142}\r
5143\r
5144/**\r
5145 Function to interpret and print out the latency tolerance reporting structure\r
5146\r
5147 @param[in] HeaderAddress The Address of this capability header.\r
5148 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5149**/\r
5150EFI_STATUS\r
5151EFIAPI\r
5152PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
5153 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5154 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5155 )\r
5156{\r
5157 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
5158 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
5159\r
5160 ShellPrintHiiEx(\r
5161 -1, -1, NULL, \r
5162 STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
5163 gShellDebug1HiiHandle, \r
5164 Header->MaxSnoopLatency,\r
5165 Header->MaxNoSnoopLatency\r
5166 ); \r
5167 DumpHex (\r
5168 4,\r
5169 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5170 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
5171 (VOID *) (HeaderAddress)\r
5172 );\r
5173 return (EFI_SUCCESS);\r
5174}\r
5175\r
5176/**\r
5177 Function to interpret and print out the serial number structure\r
5178\r
5179 @param[in] HeaderAddress The Address of this capability header.\r
5180 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5181**/\r
5182EFI_STATUS\r
5183EFIAPI\r
5184PrintInterpretedExtendedCompatibilitySerialNumber (\r
5185 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5186 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5187 )\r
5188{\r
5189 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
5190 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
5191\r
5192 ShellPrintHiiEx(\r
5193 -1, -1, NULL, \r
5194 STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
5195 gShellDebug1HiiHandle, \r
5196 Header->SerialNumber\r
5197 ); \r
5198 DumpHex (\r
5199 4,\r
5200 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5201 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
5202 (VOID *) (HeaderAddress)\r
5203 );\r
5204 return (EFI_SUCCESS);\r
5205}\r
5206\r
5207/**\r
5208 Function to interpret and print out the RCRB structure\r
5209\r
5210 @param[in] HeaderAddress The Address of this capability header.\r
5211 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5212**/\r
5213EFI_STATUS\r
5214EFIAPI\r
5215PrintInterpretedExtendedCompatibilityRcrb (\r
5216 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5217 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5218 )\r
5219{\r
5220 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
5221 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
5222\r
5223 ShellPrintHiiEx(\r
5224 -1, -1, NULL, \r
5225 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
5226 gShellDebug1HiiHandle, \r
5227 Header->VendorId,\r
5228 Header->DeviceId,\r
5229 Header->RcrbCapabilities,\r
5230 Header->RcrbControl\r
5231 ); \r
5232 DumpHex (\r
5233 4,\r
5234 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5235 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
5236 (VOID *) (HeaderAddress)\r
5237 );\r
5238 return (EFI_SUCCESS);\r
5239}\r
5240\r
5241/**\r
5242 Function to interpret and print out the vendor specific structure\r
5243\r
5244 @param[in] HeaderAddress The Address of this capability header.\r
5245 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5246**/\r
5247EFI_STATUS\r
5248EFIAPI\r
5249PrintInterpretedExtendedCompatibilityVendorSpecific (\r
5250 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5251 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5252 )\r
5253{\r
5254 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
5255 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
5256\r
5257 ShellPrintHiiEx(\r
5258 -1, -1, NULL, \r
5259 STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
5260 gShellDebug1HiiHandle, \r
5261 Header->VendorSpecificHeader\r
5262 ); \r
5263 DumpHex (\r
5264 4,\r
5265 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5266 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r
5267 (VOID *) (HeaderAddress)\r
5268 );\r
5269 return (EFI_SUCCESS);\r
5270}\r
5271\r
5272/**\r
5273 Function to interpret and print out the Event Collector Endpoint Association structure\r
5274\r
5275 @param[in] HeaderAddress The Address of this capability header.\r
5276 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5277**/\r
5278EFI_STATUS\r
5279EFIAPI\r
5280PrintInterpretedExtendedCompatibilityECEA (\r
5281 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5282 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5283 )\r
5284{\r
5285 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
5286 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
5287\r
5288 ShellPrintHiiEx(\r
5289 -1, -1, NULL, \r
5290 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
5291 gShellDebug1HiiHandle, \r
5292 Header->AssociationBitmap\r
5293 ); \r
5294 DumpHex (\r
5295 4,\r
5296 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5297 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
5298 (VOID *) (HeaderAddress)\r
5299 );\r
5300 return (EFI_SUCCESS);\r
5301}\r
5302\r
5303/**\r
5304 Function to interpret and print out the ARI structure\r
5305\r
5306 @param[in] HeaderAddress The Address of this capability header.\r
5307 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5308**/\r
5309EFI_STATUS\r
5310EFIAPI\r
5311PrintInterpretedExtendedCompatibilityAri (\r
5312 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5313 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5314 )\r
5315{\r
5316 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
5317 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
5318\r
5319 ShellPrintHiiEx(\r
5320 -1, -1, NULL, \r
5321 STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
5322 gShellDebug1HiiHandle, \r
5323 Header->AriCapability,\r
5324 Header->AriControl\r
5325 ); \r
5326 DumpHex (\r
5327 4,\r
5328 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5329 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
5330 (VOID *) (HeaderAddress)\r
5331 );\r
5332 return (EFI_SUCCESS);\r
5333}\r
5334\r
5335/**\r
5336 Function to interpret and print out the DPA structure\r
5337\r
5338 @param[in] HeaderAddress The Address of this capability header.\r
5339 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5340**/\r
5341EFI_STATUS\r
5342EFIAPI\r
5343PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
5344 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5345 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5346 )\r
5347{\r
5348 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
5349 UINT8 LinkCount;\r
5350 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
5351\r
5352 ShellPrintHiiEx(\r
5353 -1, -1, NULL, \r
5354 STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
5355 gShellDebug1HiiHandle, \r
5356 Header->DpaCapability,\r
5357 Header->DpaLatencyIndicator,\r
5358 Header->DpaStatus,\r
5359 Header->DpaControl\r
5360 ); \r
5361 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
5362 ShellPrintHiiEx(\r
5363 -1, -1, NULL, \r
5364 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
5365 gShellDebug1HiiHandle, \r
5366 LinkCount+1,\r
5367 Header->DpaPowerAllocationArray[LinkCount]\r
5368 );\r
5369 }\r
5370 DumpHex (\r
5371 4,\r
5372 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5373 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r
5374 (VOID *) (HeaderAddress)\r
5375 );\r
5376 return (EFI_SUCCESS);\r
5377}\r
5378\r
5379/**\r
5380 Function to interpret and print out the link declaration structure\r
5381\r
5382 @param[in] HeaderAddress The Address of this capability header.\r
5383 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5384**/\r
5385EFI_STATUS\r
5386EFIAPI\r
5387PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
5388 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5389 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5390 )\r
5391{\r
5392 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r
5393 UINT8 LinkCount;\r
5394 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
5395\r
5396 ShellPrintHiiEx(\r
5397 -1, -1, NULL, \r
5398 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
5399 gShellDebug1HiiHandle, \r
5400 Header->ElementSelfDescription\r
5401 );\r
5402\r
5403 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
5404 ShellPrintHiiEx(\r
5405 -1, -1, NULL, \r
5406 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
5407 gShellDebug1HiiHandle, \r
5408 LinkCount+1,\r
5409 Header->LinkEntry[LinkCount]\r
5410 );\r
5411 }\r
5412 DumpHex (\r
5413 4,\r
5414 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5415 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r
5416 (VOID *) (HeaderAddress)\r
5417 );\r
5418 return (EFI_SUCCESS);\r
5419}\r
5420\r
5421/**\r
5422 Function to interpret and print out the Advanced Error Reporting structure\r
5423\r
5424 @param[in] HeaderAddress The Address of this capability header.\r
5425 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5426**/\r
5427EFI_STATUS\r
5428EFIAPI\r
5429PrintInterpretedExtendedCompatibilityAer (\r
5430 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5431 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5432 )\r
5433{\r
5434 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
5435 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
5436\r
5437 ShellPrintHiiEx(\r
5438 -1, -1, NULL, \r
5439 STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
5440 gShellDebug1HiiHandle, \r
5441 Header->UncorrectableErrorStatus,\r
5442 Header->UncorrectableErrorMask,\r
5443 Header->UncorrectableErrorSeverity,\r
5444 Header->CorrectableErrorStatus,\r
5445 Header->CorrectableErrorMask,\r
5446 Header->AdvancedErrorCapabilitiesAndControl,\r
231ad7d8
QS		 5447 Header->HeaderLog[0],\r
5448 Header->HeaderLog[1],\r
5449 Header->HeaderLog[2],\r
5450 Header->HeaderLog[3],\r
705bffb5
JC		 5451 Header->RootErrorCommand,\r
5452 Header->RootErrorStatus,\r
5453 Header->ErrorSourceIdentification,\r
5454 Header->CorrectableErrorSourceIdentification,\r
5455 Header->TlpPrefixLog[0],\r
5456 Header->TlpPrefixLog[1],\r
5457 Header->TlpPrefixLog[2],\r
5458 Header->TlpPrefixLog[3]\r
5459 );\r
5460 DumpHex (\r
5461 4,\r
5462 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5463 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
5464 (VOID *) (HeaderAddress)\r
5465 );\r
5466 return (EFI_SUCCESS);\r
5467}\r
5468\r
9f7f0697
JC		 5469/**\r
5470 Function to interpret and print out the multicast structure\r
5471\r
5472 @param[in] HeaderAddress The Address of this capability header.\r
5473 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5474 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5475**/\r
5476EFI_STATUS\r
5477EFIAPI\r
5478PrintInterpretedExtendedCompatibilityMulticast (\r
5479 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5480 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
2412c297 5481 IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
9f7f0697
JC		 5482 )\r
5483{\r
5484 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
5485 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
5486\r
5487 ShellPrintHiiEx(\r
5488 -1, -1, NULL, \r
5489 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
5490 gShellDebug1HiiHandle, \r
5491 Header->MultiCastCapability,\r
5492 Header->MulticastControl,\r
5493 Header->McBaseAddress,\r
5494 Header->McReceiveAddress,\r
5495 Header->McBlockAll,\r
5496 Header->McBlockUntranslated,\r
5497 Header->McOverlayBar\r
5498 );\r
5499\r
5500 DumpHex (\r
5501 4,\r
5502 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5503 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
5504 (VOID *) (HeaderAddress)\r
5505 );\r
5506\r
5507 return (EFI_SUCCESS);\r
5508}\r
5509\r
5510/**\r
5511 Function to interpret and print out the virtual channel and multi virtual channel structure\r
5512\r
5513 @param[in] HeaderAddress The Address of this capability header.\r
5514 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5515**/\r
5516EFI_STATUS\r
5517EFIAPI\r
5518PrintInterpretedExtendedCompatibilityVirtualChannel (\r
5519 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5520 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5521 )\r
5522{\r
5523 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
5524 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
5525 UINT32 ItemCount;\r
5526 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
5527\r
5528 ShellPrintHiiEx(\r
5529 -1, -1, NULL, \r
5530 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
5531 gShellDebug1HiiHandle, \r
5532 Header->ExtendedVcCount,\r
5533 Header->PortVcCapability1,\r
5534 Header->PortVcCapability2,\r
5535 Header->VcArbTableOffset,\r
5536 Header->PortVcControl,\r
5537 Header->PortVcStatus\r
5538 );\r
5539 for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
5540 CapabilityItem = &Header->Capability[ItemCount];\r
5541 ShellPrintHiiEx(\r
5542 -1, -1, NULL, \r
5543 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
5544 gShellDebug1HiiHandle, \r
5545 ItemCount+1,\r
5546 CapabilityItem->VcResourceCapability,\r
5547 CapabilityItem->PortArbTableOffset,\r
5548 CapabilityItem->VcResourceControl,\r
5549 CapabilityItem->VcResourceStatus\r
5550 );\r
5551 }\r
5552\r
5553 DumpHex (\r
5554 4,\r
5555 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5556 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r
5557 (VOID *) (HeaderAddress)\r
5558 );\r
5559\r
5560 return (EFI_SUCCESS);\r
5561}\r
5562\r
5563/**\r
5564 Function to interpret and print out the resizeable bar structure\r
5565\r
5566 @param[in] HeaderAddress The Address of this capability header.\r
5567 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5568**/\r
5569EFI_STATUS\r
5570EFIAPI\r
5571PrintInterpretedExtendedCompatibilityResizeableBar (\r
5572 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5573 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5574 )\r
5575{\r
5576 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
5577 UINT32 ItemCount;\r
5578 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
5579\r
5580 for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
5581 ShellPrintHiiEx(\r
5582 -1, -1, NULL, \r
5583 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
5584 gShellDebug1HiiHandle, \r
5585 ItemCount+1,\r
5586 Header->Capability[ItemCount].ResizableBarCapability,\r
5587 Header->Capability[ItemCount].ResizableBarControl\r
5588 );\r
5589 }\r
5590\r
5591 DumpHex (\r
5592 4,\r
5593 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5594 (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
5595 (VOID *) (HeaderAddress)\r
5596 );\r
5597\r
5598 return (EFI_SUCCESS);\r
5599}\r
5600\r
5601/**\r
5602 Function to interpret and print out the TPH structure\r
5603\r
5604 @param[in] HeaderAddress The Address of this capability header.\r
5605 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5606**/\r
5607EFI_STATUS\r
5608EFIAPI\r
5609PrintInterpretedExtendedCompatibilityTph (\r
5610 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5611 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5612 )\r
5613{\r
5614 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
5615 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
5616\r
5617 ShellPrintHiiEx(\r
5618 -1, -1, NULL, \r
5619 STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
5620 gShellDebug1HiiHandle, \r
5621 Header->TphRequesterCapability,\r
5622 Header->TphRequesterControl\r
5623 );\r
5624 DumpHex (\r
5625 8,\r
5626 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
5627 GET_TPH_TABLE_SIZE(Header),\r
5628 (VOID *)Header->TphStTable\r
5629 );\r
5630\r
5631 DumpHex (\r
5632 4,\r
5633 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5634 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
5635 (VOID *) (HeaderAddress)\r
5636 );\r
5637\r
5638 return (EFI_SUCCESS);\r
5639}\r
5640\r
5641/**\r
5642 Function to interpret and print out the secondary PCIe capability structure\r
5643\r
5644 @param[in] HeaderAddress The Address of this capability header.\r
5645 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5646 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5647**/\r
5648EFI_STATUS\r
5649EFIAPI\r
5650PrintInterpretedExtendedCompatibilitySecondary (\r
5651 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5652 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
2412c297 5653 IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
9f7f0697
JC		 5654 )\r
5655{\r
5656 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
5657 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
5658\r
5659 ShellPrintHiiEx(\r
5660 -1, -1, NULL, \r
5661 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
5662 gShellDebug1HiiHandle, \r
5663 Header->LinkControl3,\r
5664 Header->LaneErrorStatus\r
5665 );\r
5666 DumpHex (\r
5667 8,\r
5668 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
5669 PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
5670 (VOID *)Header->EqualizationControl\r
5671 );\r
5672\r
5673 DumpHex (\r
5674 4,\r
5675 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5676 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
5677 (VOID *) (HeaderAddress)\r
5678 );\r
5679\r
5680 return (EFI_SUCCESS);\r
5681}\r
5682\r
705bffb5
JC		 5683/**\r
5684 Display Pcie extended capability details\r
5685\r
5686 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5687 @param[in] HeaderAddress The address of this capability header.\r
5688 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5689**/\r
5690EFI_STATUS\r
5691EFIAPI\r
5692PrintPciExtendedCapabilityDetails(\r
5693 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
5694 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
2412c297 5695 IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
705bffb5
JC		 5696 )\r
5697{\r
5698 switch (HeaderAddress->CapabilityId){\r
5699 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
5700 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5701 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
5702 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5703 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
5704 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5705 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
5706 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5707 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
5708 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5709 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
5710 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5711 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
5712 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5713 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
5714 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5715 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
5716 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5717 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
5718 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5719 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
5720 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5721 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
5722 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5723 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
5724 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
9f7f0697 5725 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
705bffb5 5726 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
9f7f0697
JC		 5727 //\r
5728 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
5729 //\r
5730 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
705bffb5 5731 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
9f7f0697 5732 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
705bffb5 5733 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
9f7f0697 5734 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
705bffb5 5735 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
9f7f0697 5736 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
705bffb5
JC		 5737 default:\r
5738 ShellPrintEx (-1, -1,\r
5739 L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
5740 HeaderAddress->CapabilityId\r
5741 );\r
5742 return EFI_SUCCESS;\r
705bffb5
JC		 5743 };\r
5744\r
5745}\r
5746\r
a1d4bfcc 5747/**\r
5748 Display Pcie device structure.\r
5749\r
5750 @param[in] IoDev The pointer to the root pci protocol.\r
5751 @param[in] Address The Address to start at.\r
5752 @param[in] CapabilityPtr The offset from the address to start.\r
f614ce7e
SQ		 5753 @param[in] EnhancedDump The print format for the dump data.\r
5754 \r
a1d4bfcc 5755**/\r
5d73d92f 5756EFI_STATUS\r
5757PciExplainPciExpress (\r
5758 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
5759 IN UINT64 Address,\r
705bffb5
JC		 5760 IN UINT8 CapabilityPtr,\r
5761 IN CONST UINT16 EnhancedDump\r
5d73d92f 5762 )\r
5763{\r
5764\r
2412c297 5765 PCIE_CAP_STRUCTURE PciExpressCap;\r
5d73d92f 5766 EFI_STATUS Status;\r
5767 UINT64 CapRegAddress;\r
5768 UINT8 Bus;\r
5769 UINT8 Dev;\r
5770 UINT8 Func;\r
5771 UINT8 *ExRegBuffer;\r
5772 UINTN ExtendRegSize;\r
5773 UINT64 Pciex_Address;\r
5774 UINT8 DevicePortType;\r
5775 UINTN Index;\r
5776 UINT8 *RegAddr;\r
5777 UINTN RegValue;\r
705bffb5 5778 PCI_EXP_EXT_HDR *ExtHdr;\r
5d73d92f 5779\r
5780 CapRegAddress = Address + CapabilityPtr;\r
5781 IoDev->Pci.Read (\r
5782 IoDev,\r
5783 EfiPciWidthUint32,\r
5784 CapRegAddress,\r
5785 sizeof (PciExpressCap) / sizeof (UINT32),\r
5786 &PciExpressCap\r
5787 );\r
5788\r
5789 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
5790\r
c37e0f16 5791 ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
5d73d92f 5792\r
5793 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
5794 if (ShellGetExecutionBreakFlag()) {\r
5795 goto Done;\r
5796 }\r
5797 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
5798 switch (PcieExplainList[Index].Width) {\r
5799 case FieldWidthUINT8:\r
5800 RegValue = *(UINT8 *) RegAddr;\r
5801 break;\r
5802 case FieldWidthUINT16:\r
5803 RegValue = *(UINT16 *) RegAddr;\r
5804 break;\r
5805 case FieldWidthUINT32:\r
5806 RegValue = *(UINT32 *) RegAddr;\r
5807 break;\r
5808 default:\r
5809 RegValue = 0;\r
5810 break;\r
5811 }\r
5812 ShellPrintHiiEx(-1, -1, NULL,\r
5813 PcieExplainList[Index].Token,\r
5814 gShellDebug1HiiHandle,\r
5815 PcieExplainList[Index].Offset,\r
5816 RegValue\r
5817 );\r
5818 if (PcieExplainList[Index].Func == NULL) {\r
5819 continue;\r
5820 }\r
5821 switch (PcieExplainList[Index].Type) {\r
5822 case PcieExplainTypeLink:\r
5823 //\r
5824 // Link registers should not be used by\r
5825 // a) Root Complex Integrated Endpoint\r
5826 // b) Root Complex Event Collector\r
5827 //\r
5828 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
5829 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
5830 continue;\r
5831 }\r
5832 break;\r
5833 case PcieExplainTypeSlot:\r
5834 //\r
5835 // Slot registers are only valid for\r
5836 // a) Root Port of PCI Express Root Complex\r
5837 // b) Downstream Port of PCI Express Switch\r
5838 // and when SlotImplemented bit is set in PCIE cap register.\r
5839 //\r
5840 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
5841 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
5842 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
5843 continue;\r
5844 }\r
5845 break;\r
5846 case PcieExplainTypeRoot:\r
5847 //\r
5848 // Root registers are only valid for\r
5849 // Root Port of PCI Express Root Complex\r
5850 //\r
5851 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
5852 continue;\r
5853 }\r
5854 break;\r
5855 default:\r
5856 break;\r
5857 }\r
5858 PcieExplainList[Index].Func (&PciExpressCap);\r
5859 }\r
5860\r
5861 Bus = (UINT8) (RShiftU64 (Address, 24));\r
5862 Dev = (UINT8) (RShiftU64 (Address, 16));\r
5863 Func = (UINT8) (RShiftU64 (Address, 8));\r
5864\r
705bffb5 5865 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
5d73d92f 5866\r
705bffb5 5867 ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
5d73d92f 5868\r
3737ac2b 5869 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
5d73d92f 5870\r
5871 //\r
5872 // PciRootBridgeIo protocol should support pci express extend space IO\r
705bffb5 5873 // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r
5d73d92f 5874 //\r
5875 Status = IoDev->Pci.Read (\r
5876 IoDev,\r
5877 EfiPciWidthUint32,\r
5878 Pciex_Address,\r
5879 (ExtendRegSize) / sizeof (UINT32),\r
5880 (VOID *) (ExRegBuffer)\r
5881 );\r
705bffb5
JC		 5882 if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r
5883 SHELL_FREE_NON_NULL(ExRegBuffer);\r
5d73d92f 5884 return EFI_UNSUPPORTED;\r
5885 }\r
5d73d92f 5886\r
705bffb5
JC		 5887 if (EnhancedDump == 0) {\r
5888 //\r
5889 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
5890 //\r
5891 ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
5892\r
d8f8021c 5893 DumpHex (\r
5894 2,\r
705bffb5 5895 EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
d8f8021c 5896 ExtendRegSize,\r
5897 (VOID *) (ExRegBuffer)\r
705bffb5
JC		 5898 );\r
5899 } else {\r
5900 ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r
5901 while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
5902 //\r
5903 // Process this item\r
5904 //\r
5905 if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r
5906 //\r
5907 // Print this item\r
5908 //\r
5909 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r
5910 }\r
5d73d92f 5911\r
705bffb5
JC		 5912 //\r
5913 // Advance to the next item if it exists\r
5914 //\r
5915 if (ExtHdr->NextCapabilityOffset != 0) {\r
5916 ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset);\r
5917 } else {\r
5918 break;\r
5919 }\r
5920 }\r
d8f8021c 5921 }\r
705bffb5 5922 SHELL_FREE_NON_NULL(ExRegBuffer);\r
5d73d92f 5923\r
5924Done:\r
5925 return EFI_SUCCESS;\r
5926}\r
EFI Development Kit II mirror for PVE