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Old driver sample code does not return an EFI_UNSUPPORTED status code if a callback...
[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c
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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
3737ac2b 4 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
5d73d92f 5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "UefiShellDebug1CommandsLib.h"\r
16#include <Protocol/PciRootBridgeIo.h>\r
17#include <Library/ShellLib.h>\r
18#include <IndustryStandard/Pci.h>\r
19#include <IndustryStandard/Acpi.h>\r
20#include "Pci.h"\r
21\r
22#define PCI_CLASS_STRING_LIMIT 54\r
23//\r
24// Printable strings for Pci class code\r
25//\r
26typedef struct {\r
27 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
28 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
29 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
30} PCI_CLASS_STRINGS;\r
31\r
32//\r
33// a structure holding a single entry, which also points to its lower level\r
34// class\r
35//\r
36typedef struct PCI_CLASS_ENTRY_TAG {\r
37 UINT8 Code; // Class, subclass or I/F code\r
38 CHAR16 *DescText; // Description string\r
39 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
40} PCI_CLASS_ENTRY;\r
41\r
42//\r
43// Declarations of entries which contain printable strings for class codes\r
44// in PCI configuration space\r
45//\r
46PCI_CLASS_ENTRY PCIBlankEntry[];\r
47PCI_CLASS_ENTRY PCISubClass_00[];\r
48PCI_CLASS_ENTRY PCISubClass_01[];\r
49PCI_CLASS_ENTRY PCISubClass_02[];\r
50PCI_CLASS_ENTRY PCISubClass_03[];\r
51PCI_CLASS_ENTRY PCISubClass_04[];\r
52PCI_CLASS_ENTRY PCISubClass_05[];\r
53PCI_CLASS_ENTRY PCISubClass_06[];\r
54PCI_CLASS_ENTRY PCISubClass_07[];\r
55PCI_CLASS_ENTRY PCISubClass_08[];\r
56PCI_CLASS_ENTRY PCISubClass_09[];\r
57PCI_CLASS_ENTRY PCISubClass_0a[];\r
58PCI_CLASS_ENTRY PCISubClass_0b[];\r
59PCI_CLASS_ENTRY PCISubClass_0c[];\r
60PCI_CLASS_ENTRY PCISubClass_0d[];\r
61PCI_CLASS_ENTRY PCISubClass_0e[];\r
62PCI_CLASS_ENTRY PCISubClass_0f[];\r
63PCI_CLASS_ENTRY PCISubClass_10[];\r
64PCI_CLASS_ENTRY PCISubClass_11[];\r
65PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
79\r
80//\r
81// Base class strings entries\r
82//\r
83PCI_CLASS_ENTRY gClassStringList[] = {\r
84 {\r
85 0x00,\r
86 L"Pre 2.0 device",\r
87 PCISubClass_00\r
88 },\r
89 {\r
90 0x01,\r
91 L"Mass Storage Controller",\r
92 PCISubClass_01\r
93 },\r
94 {\r
95 0x02,\r
96 L"Network Controller",\r
97 PCISubClass_02\r
98 },\r
99 {\r
100 0x03,\r
101 L"Display Controller",\r
102 PCISubClass_03\r
103 },\r
104 {\r
105 0x04,\r
106 L"Multimedia Device",\r
107 PCISubClass_04\r
108 },\r
109 {\r
110 0x05,\r
111 L"Memory Controller",\r
112 PCISubClass_05\r
113 },\r
114 {\r
115 0x06,\r
116 L"Bridge Device",\r
117 PCISubClass_06\r
118 },\r
119 {\r
120 0x07,\r
121 L"Simple Communications Controllers",\r
122 PCISubClass_07\r
123 },\r
124 {\r
125 0x08,\r
126 L"Base System Peripherals",\r
127 PCISubClass_08\r
128 },\r
129 {\r
130 0x09,\r
131 L"Input Devices",\r
132 PCISubClass_09\r
133 },\r
134 {\r
135 0x0a,\r
136 L"Docking Stations",\r
137 PCISubClass_0a\r
138 },\r
139 {\r
140 0x0b,\r
141 L"Processors",\r
142 PCISubClass_0b\r
143 },\r
144 {\r
145 0x0c,\r
146 L"Serial Bus Controllers",\r
147 PCISubClass_0c\r
148 },\r
149 {\r
150 0x0d,\r
151 L"Wireless Controllers",\r
152 PCISubClass_0d\r
153 },\r
154 {\r
155 0x0e,\r
156 L"Intelligent IO Controllers",\r
157 PCISubClass_0e\r
158 },\r
159 {\r
160 0x0f,\r
161 L"Satellite Communications Controllers",\r
162 PCISubClass_0f\r
163 },\r
164 {\r
165 0x10,\r
166 L"Encryption/Decryption Controllers",\r
167 PCISubClass_10\r
168 },\r
169 {\r
170 0x11,\r
171 L"Data Acquisition & Signal Processing Controllers",\r
172 PCISubClass_11\r
173 },\r
174 {\r
175 0xff,\r
176 L"Device does not fit in any defined classes",\r
177 PCIBlankEntry\r
178 },\r
179 {\r
180 0x00,\r
181 NULL,\r
182 /* null string ends the list */NULL\r
183 }\r
184};\r
185\r
186//\r
187// Subclass strings entries\r
188//\r
189PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
190 {\r
191 0x00,\r
192 L"",\r
193 PCIBlankEntry\r
194 },\r
195 {\r
196 0x00,\r
197 NULL,\r
198 /* null string ends the list */NULL\r
199 }\r
200};\r
201\r
202PCI_CLASS_ENTRY PCISubClass_00[] = {\r
203 {\r
204 0x00,\r
205 L"All devices other than VGA",\r
206 PCIBlankEntry\r
207 },\r
208 {\r
209 0x01,\r
210 L"VGA-compatible devices",\r
211 PCIBlankEntry\r
212 },\r
213 {\r
214 0x00,\r
215 NULL,\r
216 /* null string ends the list */NULL\r
217 }\r
218};\r
219\r
220PCI_CLASS_ENTRY PCISubClass_01[] = {\r
221 {\r
222 0x00,\r
223 L"SCSI controller",\r
224 PCIBlankEntry\r
225 },\r
226 {\r
227 0x01,\r
228 L"IDE controller",\r
229 PCIPIFClass_0101\r
230 },\r
231 {\r
232 0x02,\r
233 L"Floppy disk controller",\r
234 PCIBlankEntry\r
235 },\r
236 {\r
237 0x03,\r
238 L"IPI controller",\r
239 PCIBlankEntry\r
240 },\r
241 {\r
242 0x04,\r
243 L"RAID controller",\r
244 PCIBlankEntry\r
245 },\r
246 {\r
247 0x80,\r
248 L"Other mass storage controller",\r
249 PCIBlankEntry\r
250 },\r
251 {\r
252 0x00,\r
253 NULL,\r
254 /* null string ends the list */NULL\r
255 }\r
256};\r
257\r
258PCI_CLASS_ENTRY PCISubClass_02[] = {\r
259 {\r
260 0x00,\r
261 L"Ethernet controller",\r
262 PCIBlankEntry\r
263 },\r
264 {\r
265 0x01,\r
266 L"Token ring controller",\r
267 PCIBlankEntry\r
268 },\r
269 {\r
270 0x02,\r
271 L"FDDI controller",\r
272 PCIBlankEntry\r
273 },\r
274 {\r
275 0x03,\r
276 L"ATM controller",\r
277 PCIBlankEntry\r
278 },\r
279 {\r
280 0x04,\r
281 L"ISDN controller",\r
282 PCIBlankEntry\r
283 },\r
284 {\r
285 0x80,\r
286 L"Other network controller",\r
287 PCIBlankEntry\r
288 },\r
289 {\r
290 0x00,\r
291 NULL,\r
292 /* null string ends the list */NULL\r
293 }\r
294};\r
295\r
296PCI_CLASS_ENTRY PCISubClass_03[] = {\r
297 {\r
298 0x00,\r
299 L"VGA/8514 controller",\r
300 PCIPIFClass_0300\r
301 },\r
302 {\r
303 0x01,\r
304 L"XGA controller",\r
305 PCIBlankEntry\r
306 },\r
307 {\r
308 0x02,\r
309 L"3D controller",\r
310 PCIBlankEntry\r
311 },\r
312 {\r
313 0x80,\r
314 L"Other display controller",\r
315 PCIBlankEntry\r
316 },\r
317 {\r
318 0x00,\r
319 NULL,\r
320 /* null string ends the list */PCIBlankEntry\r
321 }\r
322};\r
323\r
324PCI_CLASS_ENTRY PCISubClass_04[] = {\r
325 {\r
326 0x00,\r
327 L"Video device",\r
328 PCIBlankEntry\r
329 },\r
330 {\r
331 0x01,\r
332 L"Audio device",\r
333 PCIBlankEntry\r
334 },\r
335 {\r
336 0x02,\r
337 L"Computer Telephony device",\r
338 PCIBlankEntry\r
339 },\r
340 {\r
341 0x80,\r
342 L"Other multimedia device",\r
343 PCIBlankEntry\r
344 },\r
345 {\r
346 0x00,\r
347 NULL,\r
348 /* null string ends the list */NULL\r
349 }\r
350};\r
351\r
352PCI_CLASS_ENTRY PCISubClass_05[] = {\r
353 {\r
354 0x00,\r
355 L"RAM memory controller",\r
356 PCIBlankEntry\r
357 },\r
358 {\r
359 0x01,\r
360 L"Flash memory controller",\r
361 PCIBlankEntry\r
362 },\r
363 {\r
364 0x80,\r
365 L"Other memory controller",\r
366 PCIBlankEntry\r
367 },\r
368 {\r
369 0x00,\r
370 NULL,\r
371 /* null string ends the list */NULL\r
372 }\r
373};\r
374\r
375PCI_CLASS_ENTRY PCISubClass_06[] = {\r
376 {\r
377 0x00,\r
378 L"Host/PCI bridge",\r
379 PCIBlankEntry\r
380 },\r
381 {\r
382 0x01,\r
383 L"PCI/ISA bridge",\r
384 PCIBlankEntry\r
385 },\r
386 {\r
387 0x02,\r
388 L"PCI/EISA bridge",\r
389 PCIBlankEntry\r
390 },\r
391 {\r
392 0x03,\r
393 L"PCI/Micro Channel bridge",\r
394 PCIBlankEntry\r
395 },\r
396 {\r
397 0x04,\r
398 L"PCI/PCI bridge",\r
399 PCIPIFClass_0604\r
400 },\r
401 {\r
402 0x05,\r
403 L"PCI/PCMCIA bridge",\r
404 PCIBlankEntry\r
405 },\r
406 {\r
407 0x06,\r
408 L"NuBus bridge",\r
409 PCIBlankEntry\r
410 },\r
411 {\r
412 0x07,\r
413 L"CardBus bridge",\r
414 PCIBlankEntry\r
415 },\r
416 {\r
417 0x08,\r
418 L"RACEway bridge",\r
419 PCIBlankEntry\r
420 },\r
421 {\r
422 0x80,\r
423 L"Other bridge type",\r
424 PCIBlankEntry\r
425 },\r
426 {\r
427 0x00,\r
428 NULL,\r
429 /* null string ends the list */NULL\r
430 }\r
431};\r
432\r
433PCI_CLASS_ENTRY PCISubClass_07[] = {\r
434 {\r
435 0x00,\r
436 L"Serial controller",\r
437 PCIPIFClass_0700\r
438 },\r
439 {\r
440 0x01,\r
441 L"Parallel port",\r
442 PCIPIFClass_0701\r
443 },\r
444 {\r
445 0x02,\r
446 L"Multiport serial controller",\r
447 PCIBlankEntry\r
448 },\r
449 {\r
450 0x03,\r
451 L"Modem",\r
452 PCIPIFClass_0703\r
453 },\r
454 {\r
455 0x80,\r
456 L"Other communication device",\r
457 PCIBlankEntry\r
458 },\r
459 {\r
460 0x00,\r
461 NULL,\r
462 /* null string ends the list */NULL\r
463 }\r
464};\r
465\r
466PCI_CLASS_ENTRY PCISubClass_08[] = {\r
467 {\r
468 0x00,\r
469 L"PIC",\r
470 PCIPIFClass_0800\r
471 },\r
472 {\r
473 0x01,\r
474 L"DMA controller",\r
475 PCIPIFClass_0801\r
476 },\r
477 {\r
478 0x02,\r
479 L"System timer",\r
480 PCIPIFClass_0802\r
481 },\r
482 {\r
483 0x03,\r
484 L"RTC controller",\r
485 PCIPIFClass_0803\r
486 },\r
487 {\r
488 0x04,\r
489 L"Generic PCI Hot-Plug controller",\r
490 PCIBlankEntry\r
491 },\r
492 {\r
493 0x80,\r
494 L"Other system peripheral",\r
495 PCIBlankEntry\r
496 },\r
497 {\r
498 0x00,\r
499 NULL,\r
500 /* null string ends the list */NULL\r
501 }\r
502};\r
503\r
504PCI_CLASS_ENTRY PCISubClass_09[] = {\r
505 {\r
506 0x00,\r
507 L"Keyboard controller",\r
508 PCIBlankEntry\r
509 },\r
510 {\r
511 0x01,\r
512 L"Digitizer (pen)",\r
513 PCIBlankEntry\r
514 },\r
515 {\r
516 0x02,\r
517 L"Mouse controller",\r
518 PCIBlankEntry\r
519 },\r
520 {\r
521 0x03,\r
522 L"Scanner controller",\r
523 PCIBlankEntry\r
524 },\r
525 {\r
526 0x04,\r
527 L"Gameport controller",\r
528 PCIPIFClass_0904\r
529 },\r
530 {\r
531 0x80,\r
532 L"Other input controller",\r
533 PCIBlankEntry\r
534 },\r
535 {\r
536 0x00,\r
537 NULL,\r
538 /* null string ends the list */NULL\r
539 }\r
540};\r
541\r
542PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
543 {\r
544 0x00,\r
545 L"Generic docking station",\r
546 PCIBlankEntry\r
547 },\r
548 {\r
549 0x80,\r
550 L"Other type of docking station",\r
551 PCIBlankEntry\r
552 },\r
553 {\r
554 0x00,\r
555 NULL,\r
556 /* null string ends the list */NULL\r
557 }\r
558};\r
559\r
560PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
561 {\r
562 0x00,\r
563 L"386",\r
564 PCIBlankEntry\r
565 },\r
566 {\r
567 0x01,\r
568 L"486",\r
569 PCIBlankEntry\r
570 },\r
571 {\r
572 0x02,\r
573 L"Pentium",\r
574 PCIBlankEntry\r
575 },\r
576 {\r
577 0x10,\r
578 L"Alpha",\r
579 PCIBlankEntry\r
580 },\r
581 {\r
582 0x20,\r
583 L"PowerPC",\r
584 PCIBlankEntry\r
585 },\r
586 {\r
587 0x30,\r
588 L"MIPS",\r
589 PCIBlankEntry\r
590 },\r
591 {\r
592 0x40,\r
593 L"Co-processor",\r
594 PCIBlankEntry\r
595 },\r
596 {\r
597 0x80,\r
598 L"Other processor",\r
599 PCIBlankEntry\r
600 },\r
601 {\r
602 0x00,\r
603 NULL,\r
604 /* null string ends the list */NULL\r
605 }\r
606};\r
607\r
608PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
609 {\r
610 0x00,\r
611 L"Firewire(IEEE 1394)",\r
612 PCIPIFClass_0c03\r
613 },\r
614 {\r
615 0x01,\r
616 L"ACCESS.bus",\r
617 PCIBlankEntry\r
618 },\r
619 {\r
620 0x02,\r
621 L"SSA",\r
622 PCIBlankEntry\r
623 },\r
624 {\r
625 0x03,\r
626 L"USB",\r
627 PCIPIFClass_0c00\r
628 },\r
629 {\r
630 0x04,\r
631 L"Fibre Channel",\r
632 PCIBlankEntry\r
633 },\r
634 {\r
635 0x05,\r
636 L"System Management Bus",\r
637 PCIBlankEntry\r
638 },\r
639 {\r
640 0x80,\r
641 L"Other bus type",\r
642 PCIBlankEntry\r
643 },\r
644 {\r
645 0x00,\r
646 NULL,\r
647 /* null string ends the list */NULL\r
648 }\r
649};\r
650\r
651PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
652 {\r
653 0x00,\r
654 L"iRDA compatible controller",\r
655 PCIBlankEntry\r
656 },\r
657 {\r
658 0x01,\r
659 L"Consumer IR controller",\r
660 PCIBlankEntry\r
661 },\r
662 {\r
663 0x10,\r
664 L"RF controller",\r
665 PCIBlankEntry\r
666 },\r
667 {\r
668 0x80,\r
669 L"Other type of wireless controller",\r
670 PCIBlankEntry\r
671 },\r
672 {\r
673 0x00,\r
674 NULL,\r
675 /* null string ends the list */NULL\r
676 }\r
677};\r
678\r
679PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
680 {\r
681 0x00,\r
682 L"I2O Architecture",\r
683 PCIPIFClass_0e00\r
684 },\r
685 {\r
686 0x00,\r
687 NULL,\r
688 /* null string ends the list */NULL\r
689 }\r
690};\r
691\r
692PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
693 {\r
694 0x00,\r
695 L"TV",\r
696 PCIBlankEntry\r
697 },\r
698 {\r
699 0x01,\r
700 L"Audio",\r
701 PCIBlankEntry\r
702 },\r
703 {\r
704 0x02,\r
705 L"Voice",\r
706 PCIBlankEntry\r
707 },\r
708 {\r
709 0x03,\r
710 L"Data",\r
711 PCIBlankEntry\r
712 },\r
713 {\r
714 0x00,\r
715 NULL,\r
716 /* null string ends the list */NULL\r
717 }\r
718};\r
719\r
720PCI_CLASS_ENTRY PCISubClass_10[] = {\r
721 {\r
722 0x00,\r
723 L"Network & computing Encrypt/Decrypt",\r
724 PCIBlankEntry\r
725 },\r
726 {\r
727 0x01,\r
728 L"Entertainment Encrypt/Decrypt",\r
729 PCIBlankEntry\r
730 },\r
731 {\r
732 0x80,\r
733 L"Other Encrypt/Decrypt",\r
734 PCIBlankEntry\r
735 },\r
736 {\r
737 0x00,\r
738 NULL,\r
739 /* null string ends the list */NULL\r
740 }\r
741};\r
742\r
743PCI_CLASS_ENTRY PCISubClass_11[] = {\r
744 {\r
745 0x00,\r
746 L"DPIO modules",\r
747 PCIBlankEntry\r
748 },\r
749 {\r
750 0x80,\r
751 L"Other DAQ & SP controllers",\r
752 PCIBlankEntry\r
753 },\r
754 {\r
755 0x00,\r
756 NULL,\r
757 /* null string ends the list */NULL\r
758 }\r
759};\r
760\r
761//\r
762// Programming Interface entries\r
763//\r
764PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
765 {\r
766 0x00,\r
767 L"",\r
768 PCIBlankEntry\r
769 },\r
770 {\r
771 0x01,\r
772 L"OM-primary",\r
773 PCIBlankEntry\r
774 },\r
775 {\r
776 0x02,\r
777 L"PI-primary",\r
778 PCIBlankEntry\r
779 },\r
780 {\r
781 0x03,\r
782 L"OM/PI-primary",\r
783 PCIBlankEntry\r
784 },\r
785 {\r
786 0x04,\r
787 L"OM-secondary",\r
788 PCIBlankEntry\r
789 },\r
790 {\r
791 0x05,\r
792 L"OM-primary, OM-secondary",\r
793 PCIBlankEntry\r
794 },\r
795 {\r
796 0x06,\r
797 L"PI-primary, OM-secondary",\r
798 PCIBlankEntry\r
799 },\r
800 {\r
801 0x07,\r
802 L"OM/PI-primary, OM-secondary",\r
803 PCIBlankEntry\r
804 },\r
805 {\r
806 0x08,\r
807 L"OM-secondary",\r
808 PCIBlankEntry\r
809 },\r
810 {\r
811 0x09,\r
812 L"OM-primary, PI-secondary",\r
813 PCIBlankEntry\r
814 },\r
815 {\r
816 0x0a,\r
817 L"PI-primary, PI-secondary",\r
818 PCIBlankEntry\r
819 },\r
820 {\r
821 0x0b,\r
822 L"OM/PI-primary, PI-secondary",\r
823 PCIBlankEntry\r
824 },\r
825 {\r
826 0x0c,\r
827 L"OM-secondary",\r
828 PCIBlankEntry\r
829 },\r
830 {\r
831 0x0d,\r
832 L"OM-primary, OM/PI-secondary",\r
833 PCIBlankEntry\r
834 },\r
835 {\r
836 0x0e,\r
837 L"PI-primary, OM/PI-secondary",\r
838 PCIBlankEntry\r
839 },\r
840 {\r
841 0x0f,\r
842 L"OM/PI-primary, OM/PI-secondary",\r
843 PCIBlankEntry\r
844 },\r
845 {\r
846 0x80,\r
847 L"Master",\r
848 PCIBlankEntry\r
849 },\r
850 {\r
851 0x81,\r
852 L"Master, OM-primary",\r
853 PCIBlankEntry\r
854 },\r
855 {\r
856 0x82,\r
857 L"Master, PI-primary",\r
858 PCIBlankEntry\r
859 },\r
860 {\r
861 0x83,\r
862 L"Master, OM/PI-primary",\r
863 PCIBlankEntry\r
864 },\r
865 {\r
866 0x84,\r
867 L"Master, OM-secondary",\r
868 PCIBlankEntry\r
869 },\r
870 {\r
871 0x85,\r
872 L"Master, OM-primary, OM-secondary",\r
873 PCIBlankEntry\r
874 },\r
875 {\r
876 0x86,\r
877 L"Master, PI-primary, OM-secondary",\r
878 PCIBlankEntry\r
879 },\r
880 {\r
881 0x87,\r
882 L"Master, OM/PI-primary, OM-secondary",\r
883 PCIBlankEntry\r
884 },\r
885 {\r
886 0x88,\r
887 L"Master, OM-secondary",\r
888 PCIBlankEntry\r
889 },\r
890 {\r
891 0x89,\r
892 L"Master, OM-primary, PI-secondary",\r
893 PCIBlankEntry\r
894 },\r
895 {\r
896 0x8a,\r
897 L"Master, PI-primary, PI-secondary",\r
898 PCIBlankEntry\r
899 },\r
900 {\r
901 0x8b,\r
902 L"Master, OM/PI-primary, PI-secondary",\r
903 PCIBlankEntry\r
904 },\r
905 {\r
906 0x8c,\r
907 L"Master, OM-secondary",\r
908 PCIBlankEntry\r
909 },\r
910 {\r
911 0x8d,\r
912 L"Master, OM-primary, OM/PI-secondary",\r
913 PCIBlankEntry\r
914 },\r
915 {\r
916 0x8e,\r
917 L"Master, PI-primary, OM/PI-secondary",\r
918 PCIBlankEntry\r
919 },\r
920 {\r
921 0x8f,\r
922 L"Master, OM/PI-primary, OM/PI-secondary",\r
923 PCIBlankEntry\r
924 },\r
925 {\r
926 0x00,\r
927 NULL,\r
928 /* null string ends the list */NULL\r
929 }\r
930};\r
931\r
932PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
933 {\r
934 0x00,\r
935 L"VGA compatible",\r
936 PCIBlankEntry\r
937 },\r
938 {\r
939 0x01,\r
940 L"8514 compatible",\r
941 PCIBlankEntry\r
942 },\r
943 {\r
944 0x00,\r
945 NULL,\r
946 /* null string ends the list */NULL\r
947 }\r
948};\r
949\r
950PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
951 {\r
952 0x00,\r
953 L"",\r
954 PCIBlankEntry\r
955 },\r
956 {\r
957 0x01,\r
958 L"Subtractive decode",\r
959 PCIBlankEntry\r
960 },\r
961 {\r
962 0x00,\r
963 NULL,\r
964 /* null string ends the list */NULL\r
965 }\r
966};\r
967\r
968PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
969 {\r
970 0x00,\r
971 L"Generic XT-compatible",\r
972 PCIBlankEntry\r
973 },\r
974 {\r
975 0x01,\r
976 L"16450-compatible",\r
977 PCIBlankEntry\r
978 },\r
979 {\r
980 0x02,\r
981 L"16550-compatible",\r
982 PCIBlankEntry\r
983 },\r
984 {\r
985 0x03,\r
986 L"16650-compatible",\r
987 PCIBlankEntry\r
988 },\r
989 {\r
990 0x04,\r
991 L"16750-compatible",\r
992 PCIBlankEntry\r
993 },\r
994 {\r
995 0x05,\r
996 L"16850-compatible",\r
997 PCIBlankEntry\r
998 },\r
999 {\r
1000 0x06,\r
1001 L"16950-compatible",\r
1002 PCIBlankEntry\r
1003 },\r
1004 {\r
1005 0x00,\r
1006 NULL,\r
1007 /* null string ends the list */NULL\r
1008 }\r
1009};\r
1010\r
1011PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1012 {\r
1013 0x00,\r
1014 L"",\r
1015 PCIBlankEntry\r
1016 },\r
1017 {\r
1018 0x01,\r
1019 L"Bi-directional",\r
1020 PCIBlankEntry\r
1021 },\r
1022 {\r
1023 0x02,\r
1024 L"ECP 1.X-compliant",\r
1025 PCIBlankEntry\r
1026 },\r
1027 {\r
1028 0x03,\r
1029 L"IEEE 1284",\r
1030 PCIBlankEntry\r
1031 },\r
1032 {\r
1033 0xfe,\r
1034 L"IEEE 1284 target (not a controller)",\r
1035 PCIBlankEntry\r
1036 },\r
1037 {\r
1038 0x00,\r
1039 NULL,\r
1040 /* null string ends the list */NULL\r
1041 }\r
1042};\r
1043\r
1044PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1045 {\r
1046 0x00,\r
1047 L"Generic",\r
1048 PCIBlankEntry\r
1049 },\r
1050 {\r
1051 0x01,\r
1052 L"Hayes-compatible 16450",\r
1053 PCIBlankEntry\r
1054 },\r
1055 {\r
1056 0x02,\r
1057 L"Hayes-compatible 16550",\r
1058 PCIBlankEntry\r
1059 },\r
1060 {\r
1061 0x03,\r
1062 L"Hayes-compatible 16650",\r
1063 PCIBlankEntry\r
1064 },\r
1065 {\r
1066 0x04,\r
1067 L"Hayes-compatible 16750",\r
1068 PCIBlankEntry\r
1069 },\r
1070 {\r
1071 0x00,\r
1072 NULL,\r
1073 /* null string ends the list */NULL\r
1074 }\r
1075};\r
1076\r
1077PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1078 {\r
1079 0x00,\r
1080 L"Generic 8259",\r
1081 PCIBlankEntry\r
1082 },\r
1083 {\r
1084 0x01,\r
1085 L"ISA",\r
1086 PCIBlankEntry\r
1087 },\r
1088 {\r
1089 0x02,\r
1090 L"EISA",\r
1091 PCIBlankEntry\r
1092 },\r
1093 {\r
1094 0x10,\r
1095 L"IO APIC",\r
1096 PCIBlankEntry\r
1097 },\r
1098 {\r
1099 0x20,\r
1100 L"IO(x) APIC interrupt controller",\r
1101 PCIBlankEntry\r
1102 },\r
1103 {\r
1104 0x00,\r
1105 NULL,\r
1106 /* null string ends the list */NULL\r
1107 }\r
1108};\r
1109\r
1110PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1111 {\r
1112 0x00,\r
1113 L"Generic 8237",\r
1114 PCIBlankEntry\r
1115 },\r
1116 {\r
1117 0x01,\r
1118 L"ISA",\r
1119 PCIBlankEntry\r
1120 },\r
1121 {\r
1122 0x02,\r
1123 L"EISA",\r
1124 PCIBlankEntry\r
1125 },\r
1126 {\r
1127 0x00,\r
1128 NULL,\r
1129 /* null string ends the list */NULL\r
1130 }\r
1131};\r
1132\r
1133PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1134 {\r
1135 0x00,\r
1136 L"Generic 8254",\r
1137 PCIBlankEntry\r
1138 },\r
1139 {\r
1140 0x01,\r
1141 L"ISA",\r
1142 PCIBlankEntry\r
1143 },\r
1144 {\r
1145 0x02,\r
1146 L"EISA",\r
1147 PCIBlankEntry\r
1148 },\r
1149 {\r
1150 0x00,\r
1151 NULL,\r
1152 /* null string ends the list */NULL\r
1153 }\r
1154};\r
1155\r
1156PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1157 {\r
1158 0x00,\r
1159 L"Generic",\r
1160 PCIBlankEntry\r
1161 },\r
1162 {\r
1163 0x01,\r
1164 L"ISA",\r
1165 PCIBlankEntry\r
1166 },\r
1167 {\r
1168 0x02,\r
1169 L"EISA",\r
1170 PCIBlankEntry\r
1171 },\r
1172 {\r
1173 0x00,\r
1174 NULL,\r
1175 /* null string ends the list */NULL\r
1176 }\r
1177};\r
1178\r
1179PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1180 {\r
1181 0x00,\r
1182 L"Generic",\r
1183 PCIBlankEntry\r
1184 },\r
1185 {\r
1186 0x10,\r
1187 L"",\r
1188 PCIBlankEntry\r
1189 },\r
1190 {\r
1191 0x00,\r
1192 NULL,\r
1193 /* null string ends the list */NULL\r
1194 }\r
1195};\r
1196\r
1197PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1198 {\r
1199 0x00,\r
1200 L"Universal Host Controller spec",\r
1201 PCIBlankEntry\r
1202 },\r
1203 {\r
1204 0x10,\r
1205 L"Open Host Controller spec",\r
1206 PCIBlankEntry\r
1207 },\r
1208 {\r
1209 0x80,\r
1210 L"No specific programming interface",\r
1211 PCIBlankEntry\r
1212 },\r
1213 {\r
1214 0xfe,\r
1215 L"(Not Host Controller)",\r
1216 PCIBlankEntry\r
1217 },\r
1218 {\r
1219 0x00,\r
1220 NULL,\r
1221 /* null string ends the list */NULL\r
1222 }\r
1223};\r
1224\r
1225PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1226 {\r
1227 0x00,\r
1228 L"",\r
1229 PCIBlankEntry\r
1230 },\r
1231 {\r
1232 0x10,\r
1233 L"Using 1394 OpenHCI spec",\r
1234 PCIBlankEntry\r
1235 },\r
1236 {\r
1237 0x00,\r
1238 NULL,\r
1239 /* null string ends the list */NULL\r
1240 }\r
1241};\r
1242\r
1243PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1244 {\r
1245 0x00,\r
1246 L"Message FIFO at offset 40h",\r
1247 PCIBlankEntry\r
1248 },\r
1249 {\r
1250 0x01,\r
1251 L"",\r
1252 PCIBlankEntry\r
1253 },\r
1254 {\r
1255 0x00,\r
1256 NULL,\r
1257 /* null string ends the list */NULL\r
1258 }\r
1259};\r
1260\r
5d73d92f 1261\r
a1d4bfcc 1262/**\r
5d73d92f 1263 Generates printable Unicode strings that represent PCI device class,\r
1264 subclass and programmed I/F based on a value passed to the function.\r
1265\r
a1d4bfcc 1266 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
5d73d92f 1267 PCI device. The encodings are:\r
1268 bits 23:16 - Base Class Code\r
1269 bits 15:8 - Sub-Class Code\r
1270 bits 7:0 - Programming Interface\r
a1d4bfcc 1271 @param[in,out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
5d73d92f 1272 printable class strings corresponding to ClassCode. The\r
1273 caller must not modify the strings that are pointed by\r
1274 the fields in ClassStrings.\r
5d73d92f 1275**/\r
a1d4bfcc 1276VOID\r
1277PciGetClassStrings (\r
1278 IN UINT32 ClassCode,\r
1279 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1280 )\r
5d73d92f 1281{\r
1282 INTN Index;\r
1283 UINT8 Code;\r
1284 PCI_CLASS_ENTRY *CurrentClass;\r
1285\r
1286 //\r
1287 // Assume no strings found\r
1288 //\r
1289 ClassStrings->BaseClass = L"UNDEFINED";\r
1290 ClassStrings->SubClass = L"UNDEFINED";\r
1291 ClassStrings->PIFClass = L"UNDEFINED";\r
1292\r
1293 CurrentClass = gClassStringList;\r
1294 Code = (UINT8) (ClassCode >> 16);\r
1295 Index = 0;\r
1296\r
1297 //\r
1298 // Go through all entries of the base class, until the entry with a matching\r
1299 // base class code is found. If reaches an entry with a null description\r
1300 // text, the last entry is met, which means no text for the base class was\r
1301 // found, so no more action is needed.\r
1302 //\r
1303 while (Code != CurrentClass[Index].Code) {\r
1304 if (NULL == CurrentClass[Index].DescText) {\r
1305 return ;\r
1306 }\r
1307\r
1308 Index++;\r
1309 }\r
1310 //\r
1311 // A base class was found. Assign description, and check if this class has\r
1312 // sub-class defined. If sub-class defined, no more action is needed,\r
1313 // otherwise, continue to find description for the sub-class code.\r
1314 //\r
1315 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1316 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1317 return ;\r
1318 }\r
1319 //\r
1320 // find Subclass entry\r
1321 //\r
1322 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1323 Code = (UINT8) (ClassCode >> 8);\r
1324 Index = 0;\r
1325\r
1326 //\r
1327 // Go through all entries of the sub-class, until the entry with a matching\r
1328 // sub-class code is found. If reaches an entry with a null description\r
1329 // text, the last entry is met, which means no text for the sub-class was\r
1330 // found, so no more action is needed.\r
1331 //\r
1332 while (Code != CurrentClass[Index].Code) {\r
1333 if (NULL == CurrentClass[Index].DescText) {\r
1334 return ;\r
1335 }\r
1336\r
1337 Index++;\r
1338 }\r
1339 //\r
1340 // A class was found for the sub-class code. Assign description, and check if\r
1341 // this sub-class has programming interface defined. If no, no more action is\r
1342 // needed, otherwise, continue to find description for the programming\r
1343 // interface.\r
1344 //\r
1345 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1346 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1347 return ;\r
1348 }\r
1349 //\r
1350 // Find programming interface entry\r
1351 //\r
1352 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1353 Code = (UINT8) ClassCode;\r
1354 Index = 0;\r
1355\r
1356 //\r
1357 // Go through all entries of the I/F entries, until the entry with a\r
1358 // matching I/F code is found. If reaches an entry with a null description\r
1359 // text, the last entry is met, which means no text was found, so no more\r
1360 // action is needed.\r
1361 //\r
1362 while (Code != CurrentClass[Index].Code) {\r
1363 if (NULL == CurrentClass[Index].DescText) {\r
1364 return ;\r
1365 }\r
1366\r
1367 Index++;\r
1368 }\r
1369 //\r
1370 // A class was found for the I/F code. Assign description, done!\r
1371 //\r
1372 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1373 return ;\r
1374}\r
1375\r
a1d4bfcc 1376/**\r
1377 Print strings that represent PCI device class, subclass and programmed I/F.\r
1378\r
1379 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1380 configuation space.\r
1381 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1382**/\r
5d73d92f 1383VOID\r
1384PciPrintClassCode (\r
1385 IN UINT8 *ClassCodePtr,\r
1386 IN BOOLEAN IncludePIF\r
1387 )\r
5d73d92f 1388{\r
1389 UINT32 ClassCode;\r
1390 PCI_CLASS_STRINGS ClassStrings;\r
1391 CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];\r
1392\r
1393 ClassCode = 0;\r
1394 ClassCode |= ClassCodePtr[0];\r
1395 ClassCode |= (ClassCodePtr[1] << 8);\r
1396 ClassCode |= (ClassCodePtr[2] << 16);\r
1397\r
1398 //\r
1399 // Get name from class code\r
1400 //\r
1401 PciGetClassStrings (ClassCode, &ClassStrings);\r
1402\r
1403 if (IncludePIF) {\r
1404 //\r
1405 // Only print base class and sub class name\r
1406 //\r
1407 ShellPrintEx(-1,-1, L"%s - %s - %s",\r
1408 ClassStrings.BaseClass,\r
1409 ClassStrings.SubClass,\r
1410 ClassStrings.PIFClass\r
1411 );\r
1412\r
1413 } else {\r
1414 //\r
1415 // Print base class, sub class, and programming inferface name\r
1416 //\r
1417 UnicodeSPrint (\r
1418 OutputString,\r
1419 PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),\r
1420 L"%s - %s",\r
1421 ClassStrings.BaseClass,\r
1422 ClassStrings.SubClass\r
1423 );\r
1424\r
1425 OutputString[PCI_CLASS_STRING_LIMIT] = 0;\r
1426 ShellPrintEx(-1,-1, L"%s", OutputString);\r
1427 }\r
1428}\r
1429\r
a1d4bfcc 1430/**\r
1431 This function finds out the protocol which is in charge of the given\r
1432 segment, and its bus range covers the current bus number. It lookes\r
1433 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1434 criteria is found.\r
1435\r
1436 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1437 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1438 @param[in] Segment Segment number of device we are dealing with.\r
1439 @param[in] Bus Bus number of device we are dealing with.\r
1440 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1441\r
1442 @retval EFI_SUCCESS The command completed successfully.\r
1443 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 1444\r
a1d4bfcc 1445**/\r
5d73d92f 1446EFI_STATUS\r
1447PciFindProtocolInterface (\r
1448 IN EFI_HANDLE *HandleBuf,\r
1449 IN UINTN HandleCount,\r
1450 IN UINT16 Segment,\r
1451 IN UINT16 Bus,\r
1452 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1453 );\r
1454\r
a1d4bfcc 1455/**\r
1456 This function gets the protocol interface from the given handle, and\r
1457 obtains its address space descriptors.\r
1458\r
1459 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1460 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1461 @param[out] Descriptors Points to the address space descriptors.\r
1462\r
1463 @retval EFI_SUCCESS The command completed successfully\r
1464**/\r
5d73d92f 1465EFI_STATUS\r
1466PciGetProtocolAndResource (\r
1467 IN EFI_HANDLE Handle,\r
1468 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1469 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1470 );\r
1471\r
a1d4bfcc 1472/**\r
1473 This function get the next bus range of given address space descriptors.\r
1474 It also moves the pointer backward a node, to get prepared to be called\r
1475 again.\r
1476\r
1477 @param[in,out] Descriptors Points to current position of a serial of address space\r
1478 descriptors.\r
1479 @param[out] MinBus The lower range of bus number.\r
1480 @param[out] ManBus The upper range of bus number.\r
1481 @param[out] IsEnd Meet end of the serial of descriptors.\r
1482\r
1483 @retval EFI_SUCCESS The command completed successfully.\r
1484**/\r
5d73d92f 1485EFI_STATUS\r
1486PciGetNextBusRange (\r
1487 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1488 OUT UINT16 *MinBus,\r
1489 OUT UINT16 *MaxBus,\r
1490 OUT BOOLEAN *IsEnd\r
1491 );\r
1492\r
a1d4bfcc 1493/**\r
1494 Explain the data in PCI configuration space. The part which is common for\r
1495 PCI device and bridge is interpreted in this function. It calls other\r
1496 functions to interpret data unique for device or bridge.\r
1497\r
1498 @param[in] ConfigSpace Data in PCI configuration space.\r
1499 @param[in] Address Address used to access configuration space of this PCI device.\r
1500 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1501\r
1502 @retval EFI_SUCCESS The command completed successfully.\r
1503**/\r
5d73d92f 1504EFI_STATUS\r
1505PciExplainData (\r
1506 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1507 IN UINT64 Address,\r
1508 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1509 );\r
1510\r
a1d4bfcc 1511/**\r
1512 Explain the device specific part of data in PCI configuration space.\r
1513\r
1514 @param[in] Device Data in PCI configuration space.\r
1515 @param[in] Address Address used to access configuration space of this PCI device.\r
1516 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1517\r
1518 @retval EFI_SUCCESS The command completed successfully.\r
1519**/\r
5d73d92f 1520EFI_STATUS\r
1521PciExplainDeviceData (\r
1522 IN PCI_DEVICE_HEADER *Device,\r
1523 IN UINT64 Address,\r
1524 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1525 );\r
1526\r
a1d4bfcc 1527/**\r
1528 Explain the bridge specific part of data in PCI configuration space.\r
1529\r
1530 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1531 @param[in] Address Address used to access configuration space of this PCI device.\r
1532 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1533\r
1534 @retval EFI_SUCCESS The command completed successfully.\r
1535**/\r
5d73d92f 1536EFI_STATUS\r
1537PciExplainBridgeData (\r
a1d4bfcc 1538 IN PCI_BRIDGE_HEADER *Bridge,\r
1539 IN UINT64 Address,\r
1540 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
5d73d92f 1541 );\r
1542\r
a1d4bfcc 1543/**\r
1544 Explain the Base Address Register(Bar) in PCI configuration space.\r
1545\r
1546 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1547 @param[in] Command Points to the register Command.\r
1548 @param[in] Address Address used to access configuration space of this PCI device.\r
1549 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1550 @param[in,out] Index The Index.\r
1551\r
1552 @retval EFI_SUCCESS The command completed successfully.\r
1553**/\r
5d73d92f 1554EFI_STATUS\r
1555PciExplainBar (\r
1556 IN UINT32 *Bar,\r
1557 IN UINT16 *Command,\r
1558 IN UINT64 Address,\r
1559 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1560 IN OUT UINTN *Index\r
1561 );\r
1562\r
a1d4bfcc 1563/**\r
1564 Explain the cardbus specific part of data in PCI configuration space.\r
1565\r
1566 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1567 @param[in] Address Address used to access configuration space of this PCI device.\r
1568 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1569\r
1570 @retval EFI_SUCCESS The command completed successfully.\r
1571**/\r
5d73d92f 1572EFI_STATUS\r
1573PciExplainCardBusData (\r
1574 IN PCI_CARDBUS_HEADER *CardBus,\r
1575 IN UINT64 Address,\r
1576 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1577 );\r
1578\r
a1d4bfcc 1579/**\r
1580 Explain each meaningful bit of register Status. The definition of Status is\r
1581 slightly different depending on the PCI header type.\r
1582\r
1583 @param[in] Status Points to the content of register Status.\r
1584 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1585 status).\r
1586 @param[in] HeaderType Header type of this PCI device.\r
1587\r
1588 @retval EFI_SUCCESS The command completed successfully.\r
1589**/\r
5d73d92f 1590EFI_STATUS\r
1591PciExplainStatus (\r
1592 IN UINT16 *Status,\r
1593 IN BOOLEAN MainStatus,\r
1594 IN PCI_HEADER_TYPE HeaderType\r
1595 );\r
1596\r
a1d4bfcc 1597/**\r
1598 Explain each meaningful bit of register Command.\r
1599\r
1600 @param[in] Command Points to the content of register Command.\r
1601\r
1602 @retval EFI_SUCCESS The command completed successfully.\r
1603**/\r
5d73d92f 1604EFI_STATUS\r
1605PciExplainCommand (\r
1606 IN UINT16 *Command\r
1607 );\r
1608\r
a1d4bfcc 1609/**\r
1610 Explain each meaningful bit of register Bridge Control.\r
1611\r
1612 @param[in] BridgeControl Points to the content of register Bridge Control.\r
1613 @param[in] HeaderType The headertype.\r
1614\r
1615 @retval EFI_SUCCESS The command completed successfully.\r
1616**/\r
5d73d92f 1617EFI_STATUS\r
1618PciExplainBridgeControl (\r
1619 IN UINT16 *BridgeControl,\r
1620 IN PCI_HEADER_TYPE HeaderType\r
1621 );\r
1622\r
a1d4bfcc 1623/**\r
1624 Print each capability structure.\r
1625\r
1626 @param[in] IoDev The pointer to the deivce.\r
1627 @param[in] Address The address to start at.\r
1628 @param[in] CapPtr The offset from the address.\r
1629\r
1630 @retval EFI_SUCCESS The operation was successful.\r
1631**/\r
5d73d92f 1632EFI_STATUS\r
1633PciExplainCapabilityStruct (\r
1634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1635 IN UINT64 Address,\r
1636 IN UINT8 CapPtr\r
1637 );\r
1638\r
a1d4bfcc 1639/**\r
1640 Display Pcie device structure.\r
1641\r
1642 @param[in] IoDev The pointer to the root pci protocol.\r
1643 @param[in] Address The Address to start at.\r
1644 @param[in] CapabilityPtr The offset from the address to start.\r
1645**/\r
5d73d92f 1646EFI_STATUS\r
1647PciExplainPciExpress (\r
1648 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1649 IN UINT64 Address,\r
1650 IN UINT8 CapabilityPtr\r
1651 );\r
1652\r
a1d4bfcc 1653/**\r
1654 Print out information of the capability information.\r
1655\r
1656 @param[in] PciExpressCap The pointer to the structure about the device.\r
1657\r
1658 @retval EFI_SUCCESS The operation was successful.\r
1659**/\r
5d73d92f 1660EFI_STATUS\r
1661ExplainPcieCapReg (\r
1662 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1663 );\r
1664\r
1665/**\r
1666 Print out information of the device capability information.\r
1667\r
1668 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1669\r
a1d4bfcc 1670 @retval EFI_SUCCESS The operation was successful.\r
1671**/\r
5d73d92f 1672EFI_STATUS\r
1673ExplainPcieDeviceCap (\r
1674 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1675 );\r
1676\r
1677/**\r
1678 Print out information of the device control information.\r
5d73d92f 1679\r
a1d4bfcc 1680 @param[in] PciExpressCap The pointer to the structure about the device.\r
1681\r
1682 @retval EFI_SUCCESS The operation was successful.\r
1683**/\r
5d73d92f 1684EFI_STATUS\r
1685ExplainPcieDeviceControl (\r
1686 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1687 );\r
5d73d92f 1688\r
a1d4bfcc 1689/**\r
1690 Print out information of the device status information.\r
1691\r
1692 @param[in] PciExpressCap The pointer to the structure about the device.\r
1693\r
1694 @retval EFI_SUCCESS The operation was successful.\r
1695**/\r
5d73d92f 1696EFI_STATUS\r
1697ExplainPcieDeviceStatus (\r
1698 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1699 );\r
1700\r
1701/**\r
1702 Print out information of the device link information.\r
1703\r
1704 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1705\r
a1d4bfcc 1706 @retval EFI_SUCCESS The operation was successful.\r
1707**/\r
5d73d92f 1708EFI_STATUS\r
1709ExplainPcieLinkCap (\r
1710 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1711 );\r
1712\r
1713/**\r
1714 Print out information of the device link control information.\r
5d73d92f 1715\r
a1d4bfcc 1716 @param[in] PciExpressCap The pointer to the structure about the device.\r
1717\r
1718 @retval EFI_SUCCESS The operation was successful.\r
1719**/\r
5d73d92f 1720EFI_STATUS\r
1721ExplainPcieLinkControl (\r
1722 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1723 );\r
5d73d92f 1724\r
a1d4bfcc 1725/**\r
1726 Print out information of the device link status information.\r
1727\r
1728 @param[in] PciExpressCap The pointer to the structure about the device.\r
1729\r
1730 @retval EFI_SUCCESS The operation was successful.\r
1731**/\r
5d73d92f 1732EFI_STATUS\r
1733ExplainPcieLinkStatus (\r
1734 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1735 );\r
1736\r
1737/**\r
1738 Print out information of the device slot information.\r
1739\r
1740 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1741\r
a1d4bfcc 1742 @retval EFI_SUCCESS The operation was successful.\r
1743**/\r
5d73d92f 1744EFI_STATUS\r
1745ExplainPcieSlotCap (\r
1746 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1747 );\r
1748\r
1749/**\r
1750 Print out information of the device slot control information.\r
5d73d92f 1751\r
a1d4bfcc 1752 @param[in] PciExpressCap The pointer to the structure about the device.\r
1753\r
1754 @retval EFI_SUCCESS The operation was successful.\r
1755**/\r
5d73d92f 1756EFI_STATUS\r
1757ExplainPcieSlotControl (\r
1758 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1759 );\r
5d73d92f 1760\r
a1d4bfcc 1761/**\r
1762 Print out information of the device slot status information.\r
1763\r
1764 @param[in] PciExpressCap The pointer to the structure about the device.\r
1765\r
1766 @retval EFI_SUCCESS The operation was successful.\r
1767**/\r
5d73d92f 1768EFI_STATUS\r
1769ExplainPcieSlotStatus (\r
1770 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1771 );\r
1772\r
1773/**\r
1774 Print out information of the device root information.\r
1775\r
1776 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1777\r
a1d4bfcc 1778 @retval EFI_SUCCESS The operation was successful.\r
1779**/\r
5d73d92f 1780EFI_STATUS\r
1781ExplainPcieRootControl (\r
1782 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1783 );\r
1784\r
1785/**\r
1786 Print out information of the device root capability information.\r
5d73d92f 1787\r
a1d4bfcc 1788 @param[in] PciExpressCap The pointer to the structure about the device.\r
1789\r
1790 @retval EFI_SUCCESS The operation was successful.\r
1791**/\r
5d73d92f 1792EFI_STATUS\r
1793ExplainPcieRootCap (\r
1794 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1795 );\r
5d73d92f 1796\r
a1d4bfcc 1797/**\r
1798 Print out information of the device root status information.\r
1799\r
1800 @param[in] PciExpressCap The pointer to the structure about the device.\r
1801\r
1802 @retval EFI_SUCCESS The operation was successful.\r
1803**/\r
5d73d92f 1804EFI_STATUS\r
1805ExplainPcieRootStatus (\r
1806 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1807 );\r
5d73d92f 1808\r
1809typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1810\r
1811typedef enum {\r
1812 FieldWidthUINT8,\r
1813 FieldWidthUINT16,\r
1814 FieldWidthUINT32\r
1815} PCIE_CAPREG_FIELD_WIDTH;\r
1816\r
1817typedef enum {\r
1818 PcieExplainTypeCommon,\r
1819 PcieExplainTypeDevice,\r
1820 PcieExplainTypeLink,\r
1821 PcieExplainTypeSlot,\r
1822 PcieExplainTypeRoot,\r
1823 PcieExplainTypeMax\r
1824} PCIE_EXPLAIN_TYPE;\r
1825\r
1826typedef struct\r
1827{\r
1828 UINT16 Token;\r
1829 UINTN Offset;\r
1830 PCIE_CAPREG_FIELD_WIDTH Width;\r
1831 PCIE_EXPLAIN_FUNCTION Func;\r
1832 PCIE_EXPLAIN_TYPE Type;\r
1833} PCIE_EXPLAIN_STRUCT;\r
1834\r
1835PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1836 {\r
1837 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1838 0x00,\r
1839 FieldWidthUINT8,\r
1840 NULL,\r
1841 PcieExplainTypeCommon\r
1842 },\r
1843 {\r
1844 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1845 0x01,\r
1846 FieldWidthUINT8,\r
1847 NULL,\r
1848 PcieExplainTypeCommon\r
1849 },\r
1850 {\r
1851 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1852 0x02,\r
1853 FieldWidthUINT16,\r
1854 ExplainPcieCapReg,\r
1855 PcieExplainTypeCommon\r
1856 },\r
1857 {\r
1858 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1859 0x04,\r
1860 FieldWidthUINT32,\r
1861 ExplainPcieDeviceCap,\r
1862 PcieExplainTypeDevice\r
1863 },\r
1864 {\r
1865 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1866 0x08,\r
1867 FieldWidthUINT16,\r
1868 ExplainPcieDeviceControl,\r
1869 PcieExplainTypeDevice\r
1870 },\r
1871 {\r
1872 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1873 0x0a,\r
1874 FieldWidthUINT16,\r
1875 ExplainPcieDeviceStatus,\r
1876 PcieExplainTypeDevice\r
1877 },\r
1878 {\r
1879 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1880 0x0c,\r
1881 FieldWidthUINT32,\r
1882 ExplainPcieLinkCap,\r
1883 PcieExplainTypeLink\r
1884 },\r
1885 {\r
1886 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1887 0x10,\r
1888 FieldWidthUINT16,\r
1889 ExplainPcieLinkControl,\r
1890 PcieExplainTypeLink\r
1891 },\r
1892 {\r
1893 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1894 0x12,\r
1895 FieldWidthUINT16,\r
1896 ExplainPcieLinkStatus,\r
1897 PcieExplainTypeLink\r
1898 },\r
1899 {\r
1900 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1901 0x14,\r
1902 FieldWidthUINT32,\r
1903 ExplainPcieSlotCap,\r
1904 PcieExplainTypeSlot\r
1905 },\r
1906 {\r
1907 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1908 0x18,\r
1909 FieldWidthUINT16,\r
1910 ExplainPcieSlotControl,\r
1911 PcieExplainTypeSlot\r
1912 },\r
1913 {\r
1914 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1915 0x1a,\r
1916 FieldWidthUINT16,\r
1917 ExplainPcieSlotStatus,\r
1918 PcieExplainTypeSlot\r
1919 },\r
1920 {\r
1921 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1922 0x1c,\r
1923 FieldWidthUINT16,\r
1924 ExplainPcieRootControl,\r
1925 PcieExplainTypeRoot\r
1926 },\r
1927 {\r
1928 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1929 0x1e,\r
1930 FieldWidthUINT16,\r
1931 ExplainPcieRootCap,\r
1932 PcieExplainTypeRoot\r
1933 },\r
1934 {\r
1935 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1936 0x20,\r
1937 FieldWidthUINT32,\r
1938 ExplainPcieRootStatus,\r
1939 PcieExplainTypeRoot\r
1940 },\r
1941 {\r
1942 0,\r
1943 0,\r
1944 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1945 NULL,\r
1946 PcieExplainTypeMax\r
1947 }\r
1948};\r
1949\r
1950//\r
1951// Global Variables\r
1952//\r
1953PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1954STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1955 {L"-s", TypeValue},\r
1956 {L"-i", TypeFlag},\r
1957 {NULL, TypeMax}\r
1958 };\r
1959\r
1960CHAR16 *DevicePortTypeTable[] = {\r
1961 L"PCI Express Endpoint",\r
1962 L"Legacy PCI Express Endpoint",\r
1963 L"Unknown Type",\r
1964 L"Unknonw Type",\r
1965 L"Root Port of PCI Express Root Complex",\r
1966 L"Upstream Port of PCI Express Switch",\r
1967 L"Downstream Port of PCI Express Switch",\r
1968 L"PCI Express to PCI/PCI-X Bridge",\r
1969 L"PCI/PCI-X to PCI Express Bridge",\r
1970 L"Root Complex Integrated Endpoint",\r
1971 L"Root Complex Event Collector"\r
1972};\r
1973\r
1974CHAR16 *L0sLatencyStrTable[] = {\r
1975 L"Less than 64ns",\r
1976 L"64ns to less than 128ns",\r
1977 L"128ns to less than 256ns",\r
1978 L"256ns to less than 512ns",\r
1979 L"512ns to less than 1us",\r
1980 L"1us to less than 2us",\r
1981 L"2us-4us",\r
1982 L"More than 4us"\r
1983};\r
1984\r
1985CHAR16 *L1LatencyStrTable[] = {\r
1986 L"Less than 1us",\r
1987 L"1us to less than 2us",\r
1988 L"2us to less than 4us",\r
1989 L"4us to less than 8us",\r
1990 L"8us to less than 16us",\r
1991 L"16us to less than 32us",\r
1992 L"32us-64us",\r
1993 L"More than 64us"\r
1994};\r
1995\r
1996CHAR16 *ASPMCtrlStrTable[] = {\r
1997 L"Disabled",\r
1998 L"L0s Entry Enabled",\r
1999 L"L1 Entry Enabled",\r
2000 L"L0s and L1 Entry Enabled"\r
2001};\r
2002\r
2003CHAR16 *SlotPwrLmtScaleTable[] = {\r
2004 L"1.0x",\r
2005 L"0.1x",\r
2006 L"0.01x",\r
2007 L"0.001x"\r
2008};\r
2009\r
2010CHAR16 *IndicatorTable[] = {\r
2011 L"Reserved",\r
2012 L"On",\r
2013 L"Blink",\r
2014 L"Off"\r
2015};\r
2016\r
2017\r
a1d4bfcc 2018/**\r
2019 Function for 'pci' command.\r
2020\r
2021 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2022 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2023**/\r
5d73d92f 2024SHELL_STATUS\r
2025EFIAPI\r
2026ShellCommandRunPci (\r
2027 IN EFI_HANDLE ImageHandle,\r
2028 IN EFI_SYSTEM_TABLE *SystemTable\r
2029 )\r
2030{\r
2031 UINT16 Segment;\r
2032 UINT16 Bus;\r
2033 UINT16 Device;\r
2034 UINT16 Func;\r
2035 UINT64 Address;\r
2036 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2037 EFI_STATUS Status;\r
2038 PCI_COMMON_HEADER PciHeader;\r
2039 PCI_CONFIG_SPACE ConfigSpace;\r
2040 UINTN ScreenCount;\r
2041 UINTN TempColumn;\r
2042 UINTN ScreenSize;\r
2043 BOOLEAN ExplainData;\r
2044 UINTN Index;\r
2045 UINTN SizeOfHeader;\r
2046 BOOLEAN PrintTitle;\r
2047 UINTN HandleBufSize;\r
2048 EFI_HANDLE *HandleBuf;\r
2049 UINTN HandleCount;\r
2050 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2051 UINT16 MinBus;\r
2052 UINT16 MaxBus;\r
2053 BOOLEAN IsEnd;\r
2054 LIST_ENTRY *Package;\r
2055 CHAR16 *ProblemParam;\r
2056 SHELL_STATUS ShellStatus;\r
2057 UINTN Size;\r
2058 CONST CHAR16 *Temp;\r
2059\r
2060 ShellStatus = SHELL_SUCCESS;\r
2061 Status = EFI_SUCCESS;\r
2062 Address = 0;\r
2063 Size = 0;\r
2064 IoDev = NULL;\r
2065 HandleBuf = NULL;\r
2066 Package = NULL;\r
2067\r
2068 //\r
2069 // initialize the shell lib (we must be in non-auto-init...)\r
2070 //\r
2071 Status = ShellInitialize();\r
2072 ASSERT_EFI_ERROR(Status);\r
2073\r
2074 Status = CommandInit();\r
2075 ASSERT_EFI_ERROR(Status);\r
2076\r
2077 //\r
2078 // parse the command line\r
2079 //\r
2080 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2081 if (EFI_ERROR(Status)) {\r
2082 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
2083 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
2084 FreePool(ProblemParam);\r
2085 ShellStatus = SHELL_INVALID_PARAMETER;\r
2086 } else {\r
2087 ASSERT(FALSE);\r
2088 }\r
2089 } else {\r
2090\r
3737ac2b 2091 if (ShellCommandLineGetCount(Package) == 2) {\r
2092 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
2093 ShellStatus = SHELL_INVALID_PARAMETER;\r
2094 goto Done;\r
2095 }\r
5d73d92f 2096\r
3737ac2b 2097 if (ShellCommandLineGetCount(Package) > 4) {\r
2098 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
2099 ShellStatus = SHELL_INVALID_PARAMETER;\r
2100 goto Done;\r
2101 }\r
2102 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
2103 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
2104 ShellStatus = SHELL_INVALID_PARAMETER;\r
2105 goto Done;\r
2106 }\r
5d73d92f 2107 //\r
2108 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2109 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2110 // space for handles and call it again.\r
2111 //\r
2112 HandleBufSize = sizeof (EFI_HANDLE);\r
3737ac2b 2113 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
5d73d92f 2114 if (HandleBuf == NULL) {\r
2115 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2116 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2117 goto Done;\r
2118 }\r
2119\r
2120 Status = gBS->LocateHandle (\r
2121 ByProtocol,\r
2122 &gEfiPciRootBridgeIoProtocolGuid,\r
2123 NULL,\r
2124 &HandleBufSize,\r
2125 HandleBuf\r
2126 );\r
2127\r
2128 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2129 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2130 if (HandleBuf == NULL) {\r
2131 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2132 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2133 goto Done;\r
2134 }\r
2135\r
2136 Status = gBS->LocateHandle (\r
2137 ByProtocol,\r
2138 &gEfiPciRootBridgeIoProtocolGuid,\r
2139 NULL,\r
2140 &HandleBufSize,\r
2141 HandleBuf\r
2142 );\r
2143 }\r
2144\r
2145 if (EFI_ERROR (Status)) {\r
2146 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
2147 ShellStatus = SHELL_NOT_FOUND;\r
2148 goto Done;\r
2149 }\r
2150\r
2151 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2152 //\r
2153 // Argument Count == 1(no other argument): enumerate all pci functions\r
2154 //\r
3737ac2b 2155 if (ShellCommandLineGetCount(Package) == 1) {\r
5d73d92f 2156 gST->ConOut->QueryMode (\r
2157 gST->ConOut,\r
2158 gST->ConOut->Mode->Mode,\r
2159 &TempColumn,\r
2160 &ScreenSize\r
2161 );\r
2162\r
2163 ScreenCount = 0;\r
2164 ScreenSize -= 4;\r
2165 if ((ScreenSize & 1) == 1) {\r
2166 ScreenSize -= 1;\r
2167 }\r
2168\r
2169 PrintTitle = TRUE;\r
2170\r
2171 //\r
2172 // For each handle, which decides a segment and a bus number range,\r
2173 // enumerate all devices on it.\r
2174 //\r
2175 for (Index = 0; Index < HandleCount; Index++) {\r
2176 Status = PciGetProtocolAndResource (\r
2177 HandleBuf[Index],\r
2178 &IoDev,\r
2179 &Descriptors\r
2180 );\r
2181 if (EFI_ERROR (Status)) {\r
2182 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2183 ShellStatus = SHELL_NOT_FOUND;\r
2184 goto Done;\r
2185 }\r
2186 //\r
2187 // No document say it's impossible for a RootBridgeIo protocol handle\r
2188 // to have more than one address space descriptors, so find out every\r
2189 // bus range and for each of them do device enumeration.\r
2190 //\r
2191 while (TRUE) {\r
2192 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2193\r
2194 if (EFI_ERROR (Status)) {\r
2195 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2196 ShellStatus = SHELL_NOT_FOUND;\r
2197 goto Done;\r
2198 }\r
2199\r
2200 if (IsEnd) {\r
2201 break;\r
2202 }\r
2203\r
2204 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2205 //\r
2206 // For each devices, enumerate all functions it contains\r
2207 //\r
2208 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2209 //\r
2210 // For each function, read its configuration space and print summary\r
2211 //\r
2212 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2213 if (ShellGetExecutionBreakFlag ()) {\r
2214 ShellStatus = SHELL_ABORTED;\r
2215 goto Done;\r
2216 }\r
2217 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2218 IoDev->Pci.Read (\r
2219 IoDev,\r
2220 EfiPciWidthUint16,\r
2221 Address,\r
2222 1,\r
2223 &PciHeader.VendorId\r
2224 );\r
2225\r
2226 //\r
2227 // If VendorId = 0xffff, there does not exist a device at this\r
2228 // location. For each device, if there is any function on it,\r
2229 // there must be 1 function at Function 0. So if Func = 0, there\r
2230 // will be no more functions in the same device, so we can break\r
2231 // loop to deal with the next device.\r
2232 //\r
2233 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2234 break;\r
2235 }\r
2236\r
2237 if (PciHeader.VendorId != 0xffff) {\r
2238\r
2239 if (PrintTitle) {\r
2240 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2241 PrintTitle = FALSE;\r
2242 }\r
2243\r
2244 IoDev->Pci.Read (\r
2245 IoDev,\r
2246 EfiPciWidthUint32,\r
2247 Address,\r
2248 sizeof (PciHeader) / sizeof (UINT32),\r
2249 &PciHeader\r
2250 );\r
2251\r
2252 ShellPrintHiiEx(\r
2253 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2254 IoDev->SegmentNumber,\r
2255 Bus,\r
2256 Device,\r
2257 Func\r
2258 );\r
2259\r
2260 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2261 ShellPrintHiiEx(\r
2262 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2263 PciHeader.VendorId,\r
2264 PciHeader.DeviceId,\r
2265 PciHeader.ClassCode[0]\r
2266 );\r
2267\r
2268 ScreenCount += 2;\r
2269 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2270 //\r
2271 // If ScreenSize == 0 we have the console redirected so don't\r
2272 // block updates\r
2273 //\r
2274 ScreenCount = 0;\r
2275 }\r
2276 //\r
2277 // If this is not a multi-function device, we can leave the loop\r
2278 // to deal with the next device.\r
2279 //\r
2280 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2281 break;\r
2282 }\r
2283 }\r
2284 }\r
2285 }\r
2286 }\r
2287 //\r
2288 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2289 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2290 // devices on all bus, we can leave loop.\r
2291 //\r
2292 if (Descriptors == NULL) {\r
2293 break;\r
2294 }\r
2295 }\r
2296 }\r
2297\r
2298 Status = EFI_SUCCESS;\r
2299 goto Done;\r
2300 }\r
2301\r
5d73d92f 2302 ExplainData = FALSE;\r
2303 Segment = 0;\r
2304 Bus = 0;\r
2305 Device = 0;\r
2306 Func = 0;\r
2307 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2308 ExplainData = TRUE;\r
2309 }\r
2310\r
2311 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2312 if (Temp != NULL) {\r
3737ac2b 2313 Segment = (UINT16) ShellStrToUintn (Temp);\r
5d73d92f 2314 }\r
2315\r
2316 //\r
2317 // The first Argument(except "-i") is assumed to be Bus number, second\r
2318 // to be Device number, and third to be Func number.\r
2319 //\r
2320 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2321 if (Temp != NULL) {\r
3737ac2b 2322 Bus = (UINT16)ShellStrToUintn(Temp);\r
5d73d92f 2323 if (Bus > MAX_BUS_NUMBER) {\r
2324 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2325 ShellStatus = SHELL_INVALID_PARAMETER;\r
2326 goto Done;\r
2327 }\r
2328 }\r
2329 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2330 if (Temp != NULL) {\r
3737ac2b 2331 Device = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2332 if (Device > MAX_DEVICE_NUMBER){\r
2333 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2334 ShellStatus = SHELL_INVALID_PARAMETER;\r
2335 goto Done;\r
2336 }\r
2337 }\r
2338\r
2339 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2340 if (Temp != NULL) {\r
3737ac2b 2341 Func = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2342 if (Func > MAX_FUNCTION_NUMBER){\r
2343 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2344 ShellStatus = SHELL_INVALID_PARAMETER;\r
2345 goto Done;\r
2346 }\r
2347 }\r
2348\r
2349 //\r
2350 // Find the protocol interface who's in charge of current segment, and its\r
2351 // bus range covers the current bus\r
2352 //\r
2353 Status = PciFindProtocolInterface (\r
2354 HandleBuf,\r
2355 HandleCount,\r
2356 Segment,\r
2357 Bus,\r
2358 &IoDev\r
2359 );\r
2360\r
2361 if (EFI_ERROR (Status)) {\r
2362 ShellPrintHiiEx(\r
2363 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
2364 gShellDebug1HiiHandle,\r
2365 Segment,\r
2366 Bus\r
2367 );\r
2368 ShellStatus = SHELL_NOT_FOUND;\r
2369 goto Done;\r
2370 }\r
2371\r
2372 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2373 Status = IoDev->Pci.Read (\r
2374 IoDev,\r
2375 EfiPciWidthUint8,\r
2376 Address,\r
2377 sizeof (ConfigSpace),\r
2378 &ConfigSpace\r
2379 );\r
2380\r
2381 if (EFI_ERROR (Status)) {\r
2382 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2383 ShellStatus = SHELL_ACCESS_DENIED;\r
2384 goto Done;\r
2385 }\r
2386\r
2387 mConfigSpace = &ConfigSpace;\r
2388 ShellPrintHiiEx(\r
2389 -1,\r
2390 -1,\r
2391 NULL,\r
2392 STRING_TOKEN (STR_PCI_INFO),\r
2393 gShellDebug1HiiHandle,\r
2394 Segment,\r
2395 Bus,\r
2396 Device,\r
2397 Func,\r
2398 Segment,\r
2399 Bus,\r
2400 Device,\r
2401 Func\r
2402 );\r
2403\r
2404 //\r
2405 // Dump standard header of configuration space\r
2406 //\r
2407 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2408\r
a1d4bfcc 2409 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
5d73d92f 2410 ShellPrintEx(-1,-1, L"\r\n");\r
2411\r
2412 //\r
2413 // Dump device dependent Part of configuration space\r
2414 //\r
a1d4bfcc 2415 DumpHex (\r
5d73d92f 2416 2,\r
2417 SizeOfHeader,\r
2418 sizeof (ConfigSpace) - SizeOfHeader,\r
2419 ConfigSpace.Data\r
2420 );\r
2421\r
2422 //\r
2423 // If "-i" appears in command line, interpret data in configuration space\r
2424 //\r
2425 if (ExplainData) {\r
2426 Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
2427 }\r
2428 }\r
2429Done:\r
2430 if (HandleBuf != NULL) {\r
2431 FreePool (HandleBuf);\r
2432 }\r
2433 if (Package != NULL) {\r
2434 ShellCommandLineFreeVarList (Package);\r
2435 }\r
2436 mConfigSpace = NULL;\r
2437 return ShellStatus;\r
2438}\r
2439\r
a1d4bfcc 2440/**\r
5d73d92f 2441 This function finds out the protocol which is in charge of the given\r
2442 segment, and its bus range covers the current bus number. It lookes\r
2443 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2444 criteria is found.\r
2445\r
a1d4bfcc 2446 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2447 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2448 @param[in] Segment Segment number of device we are dealing with.\r
2449 @param[in] Bus Bus number of device we are dealing with.\r
2450 @param[out] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2451\r
a1d4bfcc 2452 @retval EFI_SUCCESS The command completed successfully.\r
2453 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 2454\r
2455**/\r
a1d4bfcc 2456EFI_STATUS\r
2457PciFindProtocolInterface (\r
2458 IN EFI_HANDLE *HandleBuf,\r
2459 IN UINTN HandleCount,\r
2460 IN UINT16 Segment,\r
2461 IN UINT16 Bus,\r
2462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2463 )\r
5d73d92f 2464{\r
2465 UINTN Index;\r
2466 EFI_STATUS Status;\r
2467 BOOLEAN FoundInterface;\r
2468 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2469 UINT16 MinBus;\r
2470 UINT16 MaxBus;\r
2471 BOOLEAN IsEnd;\r
2472\r
2473 FoundInterface = FALSE;\r
2474 //\r
2475 // Go through all handles, until the one meets the criteria is found\r
2476 //\r
2477 for (Index = 0; Index < HandleCount; Index++) {\r
2478 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2479 if (EFI_ERROR (Status)) {\r
2480 return Status;\r
2481 }\r
2482 //\r
2483 // When Descriptors == NULL, the Configuration() is not implemented,\r
2484 // so we only check the Segment number\r
2485 //\r
2486 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2487 return EFI_SUCCESS;\r
2488 }\r
2489\r
2490 if ((*IoDev)->SegmentNumber != Segment) {\r
2491 continue;\r
2492 }\r
2493\r
2494 while (TRUE) {\r
2495 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2496 if (EFI_ERROR (Status)) {\r
2497 return Status;\r
2498 }\r
2499\r
2500 if (IsEnd) {\r
2501 break;\r
2502 }\r
2503\r
2504 if (MinBus <= Bus && MaxBus >= Bus) {\r
2505 FoundInterface = TRUE;\r
2506 break;\r
2507 }\r
2508 }\r
2509 }\r
2510\r
2511 if (FoundInterface) {\r
2512 return EFI_SUCCESS;\r
2513 } else {\r
2514 return EFI_INVALID_PARAMETER;\r
2515 }\r
2516}\r
2517\r
a1d4bfcc 2518/**\r
2519 This function gets the protocol interface from the given handle, and\r
2520 obtains its address space descriptors.\r
2521\r
2522 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
2523 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2524 @param[out] Descriptors Points to the address space descriptors.\r
2525\r
2526 @retval EFI_SUCCESS The command completed successfully\r
2527**/\r
5d73d92f 2528EFI_STATUS\r
2529PciGetProtocolAndResource (\r
2530 IN EFI_HANDLE Handle,\r
2531 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2532 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2533 )\r
5d73d92f 2534{\r
2535 EFI_STATUS Status;\r
2536\r
2537 //\r
2538 // Get inferface from protocol\r
2539 //\r
2540 Status = gBS->HandleProtocol (\r
2541 Handle,\r
2542 &gEfiPciRootBridgeIoProtocolGuid,\r
2543 (VOID**)IoDev\r
2544 );\r
2545\r
2546 if (EFI_ERROR (Status)) {\r
2547 return Status;\r
2548 }\r
2549 //\r
2550 // Call Configuration() to get address space descriptors\r
2551 //\r
2552 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2553 if (Status == EFI_UNSUPPORTED) {\r
2554 *Descriptors = NULL;\r
2555 return EFI_SUCCESS;\r
2556\r
2557 } else {\r
2558 return Status;\r
2559 }\r
2560}\r
2561\r
a1d4bfcc 2562/**\r
2563 This function get the next bus range of given address space descriptors.\r
2564 It also moves the pointer backward a node, to get prepared to be called\r
2565 again.\r
2566\r
2567 @param[in,out] Descriptors Points to current position of a serial of address space\r
2568 descriptors.\r
2569 @param[out] MinBus The lower range of bus number.\r
2570 @param[out] ManBus The upper range of bus number.\r
2571 @param[out] IsEnd Meet end of the serial of descriptors.\r
2572\r
2573 @retval EFI_SUCCESS The command completed successfully.\r
2574**/\r
5d73d92f 2575EFI_STATUS\r
2576PciGetNextBusRange (\r
2577 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2578 OUT UINT16 *MinBus,\r
2579 OUT UINT16 *MaxBus,\r
2580 OUT BOOLEAN *IsEnd\r
2581 )\r
5d73d92f 2582{\r
2583 *IsEnd = FALSE;\r
2584\r
2585 //\r
2586 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2587 // range is 0~PCI_MAX_BUS\r
2588 //\r
2589 if ((*Descriptors) == NULL) {\r
2590 *MinBus = 0;\r
2591 *MaxBus = PCI_MAX_BUS;\r
2592 return EFI_SUCCESS;\r
2593 }\r
2594 //\r
2595 // *Descriptors points to one or more address space descriptors, which\r
2596 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2597 // if a bus typed one is found and its bus range covers bus, this handle\r
2598 // is the handle we are looking for.\r
2599 //\r
5d73d92f 2600\r
2601 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2602 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2603 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2604 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2605 (*Descriptors)++;\r
3737ac2b 2606 return (EFI_SUCCESS);\r
5d73d92f 2607 }\r
2608\r
2609 (*Descriptors)++;\r
2610 }\r
2611\r
3737ac2b 2612 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2613 *IsEnd = TRUE;\r
2614 }\r
2615\r
5d73d92f 2616 return EFI_SUCCESS;\r
2617}\r
2618\r
a1d4bfcc 2619/**\r
5d73d92f 2620 Explain the data in PCI configuration space. The part which is common for\r
2621 PCI device and bridge is interpreted in this function. It calls other\r
2622 functions to interpret data unique for device or bridge.\r
2623\r
a1d4bfcc 2624 @param[in] ConfigSpace Data in PCI configuration space.\r
2625 @param[in] Address Address used to access configuration space of this PCI device.\r
2626 @param[in] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2627\r
a1d4bfcc 2628 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 2629**/\r
a1d4bfcc 2630EFI_STATUS\r
2631PciExplainData (\r
2632 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2633 IN UINT64 Address,\r
2634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2635 )\r
5d73d92f 2636{\r
2637 PCI_COMMON_HEADER *Common;\r
2638 PCI_HEADER_TYPE HeaderType;\r
2639 EFI_STATUS Status;\r
2640 UINT8 CapPtr;\r
2641\r
2642 Common = &(ConfigSpace->Common);\r
2643\r
2644 Print (L"\n");\r
2645\r
2646 //\r
2647 // Print Vendor Id and Device Id\r
2648 //\r
2649 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2650 INDEX_OF (&(Common->VendorId)),\r
2651 Common->VendorId,\r
2652 INDEX_OF (&(Common->DeviceId)),\r
2653 Common->DeviceId\r
2654 );\r
2655\r
2656 //\r
2657 // Print register Command\r
2658 //\r
2659 PciExplainCommand (&(Common->Command));\r
2660\r
2661 //\r
2662 // Print register Status\r
2663 //\r
2664 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2665\r
2666 //\r
2667 // Print register Revision ID\r
2668 //\r
2669 ShellPrintEx(-1, -1, L"/r/n");\r
2670 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2671 INDEX_OF (&(Common->RevisionId)),\r
2672 Common->RevisionId\r
2673 );\r
2674\r
2675 //\r
2676 // Print register BIST\r
2677 //\r
a1d4bfcc 2678 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
2679 if ((Common->Bist & PCI_BIT_7) != 0) {\r
2680 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
5d73d92f 2681 } else {\r
2682 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2683 }\r
2684 //\r
2685 // Print register Cache Line Size\r
2686 //\r
2687 ShellPrintHiiEx(-1, -1, NULL,\r
2688 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2689 gShellDebug1HiiHandle,\r
2690 INDEX_OF (&(Common->CacheLineSize)),\r
2691 Common->CacheLineSize\r
2692 );\r
2693\r
2694 //\r
2695 // Print register Latency Timer\r
2696 //\r
2697 ShellPrintHiiEx(-1, -1, NULL,\r
2698 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2699 gShellDebug1HiiHandle,\r
2700 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2701 Common->PrimaryLatencyTimer\r
2702 );\r
2703\r
2704 //\r
2705 // Print register Header Type\r
2706 //\r
2707 ShellPrintHiiEx(-1, -1, NULL,\r
2708 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2709 gShellDebug1HiiHandle,\r
2710 INDEX_OF (&(Common->HeaderType)),\r
2711 Common->HeaderType\r
2712 );\r
2713\r
2714 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2715 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2716\r
2717 } else {\r
2718 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2719 }\r
2720\r
2721 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2722 switch (HeaderType) {\r
2723 case PciDevice:\r
2724 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2725 break;\r
2726\r
2727 case PciP2pBridge:\r
2728 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2729 break;\r
2730\r
2731 case PciCardBusBridge:\r
2732 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2733 break;\r
2734\r
2735 default:\r
2736 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2737 HeaderType = PciUndefined;\r
2738 }\r
2739\r
2740 //\r
2741 // Print register Class Code\r
2742 //\r
2743 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2744 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
2745 Print (L"\n");\r
2746\r
2747 if (ShellGetExecutionBreakFlag()) {\r
2748 return EFI_SUCCESS;\r
2749 }\r
2750\r
2751 //\r
2752 // Interpret remaining part of PCI configuration header depending on\r
2753 // HeaderType\r
2754 //\r
2755 CapPtr = 0;\r
2756 Status = EFI_SUCCESS;\r
2757 switch (HeaderType) {\r
2758 case PciDevice:\r
2759 Status = PciExplainDeviceData (\r
2760 &(ConfigSpace->NonCommon.Device),\r
2761 Address,\r
2762 IoDev\r
2763 );\r
2764 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2765 break;\r
2766\r
2767 case PciP2pBridge:\r
2768 Status = PciExplainBridgeData (\r
2769 &(ConfigSpace->NonCommon.Bridge),\r
2770 Address,\r
2771 IoDev\r
2772 );\r
2773 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2774 break;\r
2775\r
2776 case PciCardBusBridge:\r
2777 Status = PciExplainCardBusData (\r
2778 &(ConfigSpace->NonCommon.CardBus),\r
2779 Address,\r
2780 IoDev\r
2781 );\r
2782 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2783 break;\r
d8f8021c 2784 case PciUndefined:\r
2785 default:\r
2786 break;\r
5d73d92f 2787 }\r
2788 //\r
2789 // If Status bit4 is 1, dump or explain capability structure\r
2790 //\r
2791 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
2792 PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
2793 }\r
2794\r
2795 return Status;\r
2796}\r
2797\r
a1d4bfcc 2798/**\r
2799 Explain the device specific part of data in PCI configuration space.\r
2800\r
2801 @param[in] Device Data in PCI configuration space.\r
2802 @param[in] Address Address used to access configuration space of this PCI device.\r
2803 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2804\r
2805 @retval EFI_SUCCESS The command completed successfully.\r
2806**/\r
5d73d92f 2807EFI_STATUS\r
2808PciExplainDeviceData (\r
2809 IN PCI_DEVICE_HEADER *Device,\r
2810 IN UINT64 Address,\r
2811 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2812 )\r
5d73d92f 2813{\r
2814 UINTN Index;\r
2815 BOOLEAN BarExist;\r
2816 EFI_STATUS Status;\r
2817 UINTN BarCount;\r
2818\r
2819 //\r
2820 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2821 // exist. If these no Bar for this function, print "none", otherwise\r
2822 // list detail information about this Bar.\r
2823 //\r
2824 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2825\r
2826 BarExist = FALSE;\r
2827 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2828 for (Index = 0; Index < BarCount; Index++) {\r
2829 if (Device->Bar[Index] == 0) {\r
2830 continue;\r
2831 }\r
2832\r
2833 if (!BarExist) {\r
2834 BarExist = TRUE;\r
2835 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
2836 Print (L" --------------------------------------------------------------------------");\r
2837 }\r
2838\r
2839 Status = PciExplainBar (\r
2840 &(Device->Bar[Index]),\r
2841 &(mConfigSpace->Common.Command),\r
2842 Address,\r
2843 IoDev,\r
2844 &Index\r
2845 );\r
2846\r
2847 if (EFI_ERROR (Status)) {\r
2848 break;\r
2849 }\r
2850 }\r
2851\r
2852 if (!BarExist) {\r
2853 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2854\r
2855 } else {\r
2856 Print (L"\n --------------------------------------------------------------------------");\r
2857 }\r
2858\r
2859 //\r
2860 // Print register Expansion ROM Base Address\r
2861 //\r
2862 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2863 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2864\r
2865 } else {\r
2866 ShellPrintHiiEx(-1, -1, NULL,\r
2867 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2868 gShellDebug1HiiHandle,\r
2869 INDEX_OF (&(Device->ROMBar)),\r
2870 Device->ROMBar\r
2871 );\r
2872 }\r
2873 //\r
2874 // Print register Cardbus CIS ptr\r
2875 //\r
2876 ShellPrintHiiEx(-1, -1, NULL,\r
2877 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2878 gShellDebug1HiiHandle,\r
2879 INDEX_OF (&(Device->CardBusCISPtr)),\r
2880 Device->CardBusCISPtr\r
2881 );\r
2882\r
2883 //\r
2884 // Print register Sub-vendor ID and subsystem ID\r
2885 //\r
2886 ShellPrintHiiEx(-1, -1, NULL,\r
2887 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2888 gShellDebug1HiiHandle,\r
2889 INDEX_OF (&(Device->SubVendorId)),\r
2890 Device->SubVendorId\r
2891 );\r
2892\r
2893 ShellPrintHiiEx(-1, -1, NULL,\r
2894 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2895 gShellDebug1HiiHandle,\r
2896 INDEX_OF (&(Device->SubSystemId)),\r
2897 Device->SubSystemId\r
2898 );\r
2899\r
2900 //\r
2901 // Print register Capabilities Ptr\r
2902 //\r
2903 ShellPrintHiiEx(-1, -1, NULL,\r
2904 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2905 gShellDebug1HiiHandle,\r
2906 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2907 Device->CapabilitiesPtr\r
2908 );\r
2909\r
2910 //\r
2911 // Print register Interrupt Line and interrupt pin\r
2912 //\r
2913 ShellPrintHiiEx(-1, -1, NULL,\r
2914 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2915 gShellDebug1HiiHandle,\r
2916 INDEX_OF (&(Device->InterruptLine)),\r
2917 Device->InterruptLine\r
2918 );\r
2919\r
2920 ShellPrintHiiEx(-1, -1, NULL,\r
2921 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2922 gShellDebug1HiiHandle,\r
2923 INDEX_OF (&(Device->InterruptPin)),\r
2924 Device->InterruptPin\r
2925 );\r
2926\r
2927 //\r
2928 // Print register Min_Gnt and Max_Lat\r
2929 //\r
2930 ShellPrintHiiEx(-1, -1, NULL,\r
2931 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2932 gShellDebug1HiiHandle,\r
2933 INDEX_OF (&(Device->MinGnt)),\r
2934 Device->MinGnt\r
2935 );\r
2936\r
2937 ShellPrintHiiEx(-1, -1, NULL,\r
2938 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2939 gShellDebug1HiiHandle,\r
2940 INDEX_OF (&(Device->MaxLat)),\r
2941 Device->MaxLat\r
2942 );\r
2943\r
2944 return EFI_SUCCESS;\r
2945}\r
2946\r
a1d4bfcc 2947/**\r
2948 Explain the bridge specific part of data in PCI configuration space.\r
2949\r
2950 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
2951 @param[in] Address Address used to access configuration space of this PCI device.\r
2952 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2953\r
2954 @retval EFI_SUCCESS The command completed successfully.\r
2955**/\r
5d73d92f 2956EFI_STATUS\r
2957PciExplainBridgeData (\r
2958 IN PCI_BRIDGE_HEADER *Bridge,\r
2959 IN UINT64 Address,\r
2960 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2961 )\r
5d73d92f 2962{\r
2963 UINTN Index;\r
2964 BOOLEAN BarExist;\r
2965 UINTN BarCount;\r
2966 UINT32 IoAddress32;\r
2967 EFI_STATUS Status;\r
2968\r
2969 //\r
2970 // Print Base Address Registers. When Bar = 0, this Bar does not\r
2971 // exist. If these no Bar for this function, print "none", otherwise\r
2972 // list detail information about this Bar.\r
2973 //\r
2974 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
2975\r
2976 BarExist = FALSE;\r
2977 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
2978\r
2979 for (Index = 0; Index < BarCount; Index++) {\r
2980 if (Bridge->Bar[Index] == 0) {\r
2981 continue;\r
2982 }\r
2983\r
2984 if (!BarExist) {\r
2985 BarExist = TRUE;\r
2986 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
2987 Print (L" --------------------------------------------------------------------------");\r
2988 }\r
2989\r
2990 Status = PciExplainBar (\r
2991 &(Bridge->Bar[Index]),\r
2992 &(mConfigSpace->Common.Command),\r
2993 Address,\r
2994 IoDev,\r
2995 &Index\r
2996 );\r
2997\r
2998 if (EFI_ERROR (Status)) {\r
2999 break;\r
3000 }\r
3001 }\r
3002\r
3003 if (!BarExist) {\r
3004 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3005 } else {\r
3006 Print (L"\n --------------------------------------------------------------------------");\r
3007 }\r
3008\r
3009 //\r
3010 // Expansion register ROM Base Address\r
3011 //\r
3012 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
3013 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
3014\r
3015 } else {\r
3016 ShellPrintHiiEx(-1, -1, NULL,\r
3017 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3018 gShellDebug1HiiHandle,\r
3019 INDEX_OF (&(Bridge->ROMBar)),\r
3020 Bridge->ROMBar\r
3021 );\r
3022 }\r
3023 //\r
3024 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3025 //\r
3026 ShellPrintHiiEx(-1, -1, NULL,\r
3027 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3028 gShellDebug1HiiHandle,\r
3029 INDEX_OF (&(Bridge->PrimaryBus)),\r
3030 INDEX_OF (&(Bridge->SecondaryBus)),\r
3031 INDEX_OF (&(Bridge->SubordinateBus))\r
3032 );\r
3033\r
3034 Print (L" ------------------------------------------------------\n");\r
3035\r
3036 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3037 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3038 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3039\r
3040 //\r
3041 // Print register Secondary Latency Timer\r
3042 //\r
3043 ShellPrintHiiEx(-1, -1, NULL,\r
3044 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3045 gShellDebug1HiiHandle,\r
3046 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3047 Bridge->SecondaryLatencyTimer\r
3048 );\r
3049\r
3050 //\r
3051 // Print register Secondary Status\r
3052 //\r
3053 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3054\r
3055 //\r
3056 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3057 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3058 // base and limit address are listed.\r
3059 //\r
3060 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
3061 Print (L"----------------------------------------------------------------------\n");\r
3062\r
3063 //\r
3064 // IO Base & Limit\r
3065 //\r
3066 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
3067 IoAddress32 &= 0xfffff000;\r
3068 ShellPrintHiiEx(-1, -1, NULL,\r
3069 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3070 gShellDebug1HiiHandle,\r
3071 INDEX_OF (&(Bridge->IoBase)),\r
3072 IoAddress32\r
3073 );\r
3074\r
3075 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
3076 IoAddress32 |= 0x00000fff;\r
3077 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3078\r
3079 //\r
3080 // Memory Base & Limit\r
3081 //\r
3082 ShellPrintHiiEx(-1, -1, NULL,\r
3083 STRING_TOKEN (STR_PCI2_MEMORY),\r
3084 gShellDebug1HiiHandle,\r
3085 INDEX_OF (&(Bridge->MemoryBase)),\r
3086 (Bridge->MemoryBase << 16) & 0xfff00000\r
3087 );\r
3088\r
3089 ShellPrintHiiEx(-1, -1, NULL,\r
3090 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3091 gShellDebug1HiiHandle,\r
3092 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3093 );\r
3094\r
3095 //\r
3096 // Pre-fetch-able Memory Base & Limit\r
3097 //\r
3098 ShellPrintHiiEx(-1, -1, NULL,\r
3099 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3100 gShellDebug1HiiHandle,\r
3101 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
3102 Bridge->PrefetchableBaseUpper,\r
3103 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
3104 );\r
3105\r
3106 ShellPrintHiiEx(-1, -1, NULL,\r
3107 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3108 gShellDebug1HiiHandle,\r
3109 Bridge->PrefetchableLimitUpper,\r
3110 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3111 );\r
3112\r
3113 //\r
3114 // Print register Capabilities Pointer\r
3115 //\r
3116 ShellPrintHiiEx(-1, -1, NULL,\r
3117 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3118 gShellDebug1HiiHandle,\r
3119 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3120 Bridge->CapabilitiesPtr\r
3121 );\r
3122\r
3123 //\r
3124 // Print register Bridge Control\r
3125 //\r
3126 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3127\r
3128 //\r
3129 // Print register Interrupt Line & PIN\r
3130 //\r
3131 ShellPrintHiiEx(-1, -1, NULL,\r
3132 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3133 gShellDebug1HiiHandle,\r
3134 INDEX_OF (&(Bridge->InterruptLine)),\r
3135 Bridge->InterruptLine\r
3136 );\r
3137\r
3138 ShellPrintHiiEx(-1, -1, NULL,\r
3139 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3140 gShellDebug1HiiHandle,\r
3141 INDEX_OF (&(Bridge->InterruptPin)),\r
3142 Bridge->InterruptPin\r
3143 );\r
3144\r
3145 return EFI_SUCCESS;\r
3146}\r
3147\r
a1d4bfcc 3148/**\r
3149 Explain the Base Address Register(Bar) in PCI configuration space.\r
3150\r
3151 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3152 @param[in] Command Points to the register Command.\r
3153 @param[in] Address Address used to access configuration space of this PCI device.\r
3154 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3155 @param[in,out] Index The Index.\r
3156\r
3157 @retval EFI_SUCCESS The command completed successfully.\r
3158**/\r
5d73d92f 3159EFI_STATUS\r
3160PciExplainBar (\r
3161 IN UINT32 *Bar,\r
3162 IN UINT16 *Command,\r
3163 IN UINT64 Address,\r
3164 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3165 IN OUT UINTN *Index\r
3166 )\r
5d73d92f 3167{\r
3168 UINT16 OldCommand;\r
3169 UINT16 NewCommand;\r
3170 UINT64 Bar64;\r
3171 UINT32 OldBar32;\r
3172 UINT32 NewBar32;\r
3173 UINT64 OldBar64;\r
3174 UINT64 NewBar64;\r
3175 BOOLEAN IsMem;\r
3176 BOOLEAN IsBar32;\r
3177 UINT64 RegAddress;\r
3178\r
3179 IsBar32 = TRUE;\r
3180 Bar64 = 0;\r
3181 NewBar32 = 0;\r
3182 NewBar64 = 0;\r
3183\r
3184 //\r
3185 // According the bar type, list detail about this bar, for example: 32 or\r
3186 // 64 bits; pre-fetchable or not.\r
3187 //\r
3188 if ((*Bar & PCI_BIT_0) == 0) {\r
3189 //\r
3190 // This bar is of memory type\r
3191 //\r
3192 IsMem = TRUE;\r
3193\r
3194 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3195 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3196 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3197 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3198\r
3199 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3200 Bar64 = 0x0;\r
3201 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
3202 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0), 32));\r
3203 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0));\r
3204 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3205 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3206 IsBar32 = FALSE;\r
3207 *Index += 1;\r
3208\r
3209 } else {\r
3210 //\r
3211 // Reserved\r
3212 //\r
3213 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3214 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3215 }\r
3216\r
3217 if ((*Bar & PCI_BIT_3) == 0) {\r
3218 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3219\r
3220 } else {\r
3221 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3222 }\r
3223\r
3224 } else {\r
3225 //\r
3226 // This bar is of io type\r
3227 //\r
3228 IsMem = FALSE;\r
3229 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
3230 Print (L"I/O ");\r
3231 }\r
3232\r
3233 //\r
3234 // Get BAR length(or the amount of resource this bar demands for). To get\r
3235 // Bar length, first we should temporarily disable I/O and memory access\r
3236 // of this function(by set bits in the register Command), then write all\r
3237 // "1"s to this bar. The bar value read back is the amount of resource\r
3238 // this bar demands for.\r
3239 //\r
3240 //\r
3241 // Disable io & mem access\r
3242 //\r
3243 OldCommand = *Command;\r
3244 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3245 RegAddress = Address | INDEX_OF (Command);\r
3246 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3247\r
3248 RegAddress = Address | INDEX_OF (Bar);\r
3249\r
3250 //\r
3251 // Read after write the BAR to get the size\r
3252 //\r
3253 if (IsBar32) {\r
3254 OldBar32 = *Bar;\r
3255 NewBar32 = 0xffffffff;\r
3256\r
3257 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3258 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3259 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3260\r
3261 if (IsMem) {\r
3262 NewBar32 = NewBar32 & 0xfffffff0;\r
3263 NewBar32 = (~NewBar32) + 1;\r
3264\r
3265 } else {\r
3266 NewBar32 = NewBar32 & 0xfffffffc;\r
3267 NewBar32 = (~NewBar32) + 1;\r
3268 NewBar32 = NewBar32 & 0x0000ffff;\r
3269 }\r
3270 } else {\r
3271\r
3272 OldBar64 = 0x0;\r
3273 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
3274 NewBar64 = 0xffffffffffffffff;\r
3275\r
3276 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3277 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3278 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3279\r
3280 if (IsMem) {\r
3281 NewBar64 = NewBar64 & 0xfffffffffffffff0;\r
3282 NewBar64 = (~NewBar64) + 1;\r
3283\r
3284 } else {\r
3285 NewBar64 = NewBar64 & 0xfffffffffffffffc;\r
3286 NewBar64 = (~NewBar64) + 1;\r
3287 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3288 }\r
3289 }\r
3290 //\r
3291 // Enable io & mem access\r
3292 //\r
3293 RegAddress = Address | INDEX_OF (Command);\r
3294 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3295\r
3296 if (IsMem) {\r
3297 if (IsBar32) {\r
3298 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3299 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3300\r
3301 } else {\r
3302 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));\r
3303 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
3304 Print (L" ");\r
3305 ShellPrintHiiEx(-1, -1, NULL,\r
3306 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3307 gShellDebug1HiiHandle,\r
3308 RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1), 32)\r
3309 );\r
3310 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1));\r
3311\r
3312 }\r
3313 } else {\r
3314 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3315 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3316 }\r
3317\r
3318 return EFI_SUCCESS;\r
3319}\r
3320\r
a1d4bfcc 3321/**\r
3322 Explain the cardbus specific part of data in PCI configuration space.\r
3323\r
3324 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3325 @param[in] Address Address used to access configuration space of this PCI device.\r
3326 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3327\r
3328 @retval EFI_SUCCESS The command completed successfully.\r
3329**/\r
5d73d92f 3330EFI_STATUS\r
3331PciExplainCardBusData (\r
3332 IN PCI_CARDBUS_HEADER *CardBus,\r
3333 IN UINT64 Address,\r
3334 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3335 )\r
5d73d92f 3336{\r
3337 BOOLEAN Io32Bit;\r
3338 PCI_CARDBUS_DATA *CardBusData;\r
3339\r
3340 ShellPrintHiiEx(-1, -1, NULL,\r
3341 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3342 gShellDebug1HiiHandle,\r
3343 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3344 CardBus->CardBusSocketReg\r
3345 );\r
3346\r
3347 //\r
3348 // Print Secondary Status\r
3349 //\r
3350 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3351\r
3352 //\r
3353 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3354 // Subordinate bus number\r
3355 //\r
3356 ShellPrintHiiEx(-1, -1, NULL,\r
3357 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3358 gShellDebug1HiiHandle,\r
3359 INDEX_OF (&(CardBus->PciBusNumber)),\r
3360 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3361 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3362 );\r
3363\r
3364 Print (L" ------------------------------------------------------\n");\r
3365\r
3366 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3367 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3368 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3369\r
3370 //\r
3371 // Print CardBus Latency Timer\r
3372 //\r
3373 ShellPrintHiiEx(-1, -1, NULL,\r
3374 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3375 gShellDebug1HiiHandle,\r
3376 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3377 CardBus->CardBusLatencyTimer\r
3378 );\r
3379\r
3380 //\r
3381 // Print Memory/Io ranges this cardbus bridge forwards\r
3382 //\r
3383 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
3384 Print (L"----------------------------------------------------------------------\n");\r
3385\r
3386 ShellPrintHiiEx(-1, -1, NULL,\r
3387 STRING_TOKEN (STR_PCI2_MEM_3),\r
3388 gShellDebug1HiiHandle,\r
3389 INDEX_OF (&(CardBus->MemoryBase0)),\r
3390 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3391 CardBus->MemoryBase0 & 0xfffff000,\r
3392 CardBus->MemoryLimit0 | 0x00000fff\r
3393 );\r
3394\r
3395 ShellPrintHiiEx(-1, -1, NULL,\r
3396 STRING_TOKEN (STR_PCI2_MEM_3),\r
3397 gShellDebug1HiiHandle,\r
3398 INDEX_OF (&(CardBus->MemoryBase1)),\r
3399 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3400 CardBus->MemoryBase1 & 0xfffff000,\r
3401 CardBus->MemoryLimit1 | 0x00000fff\r
3402 );\r
3403\r
3404 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3405 ShellPrintHiiEx(-1, -1, NULL,\r
3406 STRING_TOKEN (STR_PCI2_IO_2),\r
3407 gShellDebug1HiiHandle,\r
3408 INDEX_OF (&(CardBus->IoBase0)),\r
3409 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3410 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3411 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3412 );\r
3413\r
3414 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3415 ShellPrintHiiEx(-1, -1, NULL,\r
3416 STRING_TOKEN (STR_PCI2_IO_2),\r
3417 gShellDebug1HiiHandle,\r
3418 INDEX_OF (&(CardBus->IoBase1)),\r
3419 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3420 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3421 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3422 );\r
3423\r
3424 //\r
3425 // Print register Interrupt Line & PIN\r
3426 //\r
3427 ShellPrintHiiEx(-1, -1, NULL,\r
3428 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3429 gShellDebug1HiiHandle,\r
3430 INDEX_OF (&(CardBus->InterruptLine)),\r
3431 CardBus->InterruptLine,\r
3432 INDEX_OF (&(CardBus->InterruptPin)),\r
3433 CardBus->InterruptPin\r
3434 );\r
3435\r
3436 //\r
3437 // Print register Bridge Control\r
3438 //\r
3439 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3440\r
3441 //\r
3442 // Print some registers in data region of PCI configuration space for cardbus\r
3443 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3444 // Address.\r
3445 //\r
3446 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3447\r
3448 ShellPrintHiiEx(-1, -1, NULL,\r
3449 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3450 gShellDebug1HiiHandle,\r
3451 INDEX_OF (&(CardBusData->SubVendorId)),\r
3452 CardBusData->SubVendorId,\r
3453 INDEX_OF (&(CardBusData->SubSystemId)),\r
3454 CardBusData->SubSystemId\r
3455 );\r
3456\r
3457 ShellPrintHiiEx(-1, -1, NULL,\r
3458 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3459 gShellDebug1HiiHandle,\r
3460 INDEX_OF (&(CardBusData->LegacyBase)),\r
3461 CardBusData->LegacyBase\r
3462 );\r
3463\r
3464 return EFI_SUCCESS;\r
3465}\r
3466\r
a1d4bfcc 3467/**\r
3468 Explain each meaningful bit of register Status. The definition of Status is\r
3469 slightly different depending on the PCI header type.\r
3470\r
3471 @param[in] Status Points to the content of register Status.\r
3472 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3473 status).\r
3474 @param[in] HeaderType Header type of this PCI device.\r
3475\r
3476 @retval EFI_SUCCESS The command completed successfully.\r
3477**/\r
5d73d92f 3478EFI_STATUS\r
3479PciExplainStatus (\r
3480 IN UINT16 *Status,\r
3481 IN BOOLEAN MainStatus,\r
3482 IN PCI_HEADER_TYPE HeaderType\r
3483 )\r
5d73d92f 3484{\r
3485 if (MainStatus) {\r
3486 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3487\r
3488 } else {\r
3489 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3490 }\r
3491\r
3492 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3493\r
3494 //\r
3495 // Bit 5 is meaningless for CardBus Bridge\r
3496 //\r
3497 if (HeaderType == PciCardBusBridge) {\r
3498 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3499\r
3500 } else {\r
3501 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3502 }\r
3503\r
3504 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3505\r
3506 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3507 //\r
3508 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3509 //\r
3510 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3511 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3512 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3513\r
3514 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3515 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3516\r
3517 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3518 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3519\r
3520 } else {\r
3521 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3522 }\r
3523\r
3524 ShellPrintHiiEx(-1, -1, NULL,\r
3525 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3526 gShellDebug1HiiHandle,\r
3527 (*Status & PCI_BIT_11) != 0\r
3528 );\r
3529\r
3530 ShellPrintHiiEx(-1, -1, NULL,\r
3531 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3532 gShellDebug1HiiHandle,\r
3533 (*Status & PCI_BIT_12) != 0\r
3534 );\r
3535\r
3536 ShellPrintHiiEx(-1, -1, NULL,\r
3537 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3538 gShellDebug1HiiHandle,\r
3539 (*Status & PCI_BIT_13) != 0\r
3540 );\r
3541\r
3542 if (MainStatus) {\r
3543 ShellPrintHiiEx(-1, -1, NULL,\r
3544 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3545 gShellDebug1HiiHandle,\r
3546 (*Status & PCI_BIT_14) != 0\r
3547 );\r
3548\r
3549 } else {\r
3550 ShellPrintHiiEx(-1, -1, NULL,\r
3551 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3552 gShellDebug1HiiHandle,\r
3553 (*Status & PCI_BIT_14) != 0\r
3554 );\r
3555 }\r
3556\r
3557 ShellPrintHiiEx(-1, -1, NULL,\r
3558 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3559 gShellDebug1HiiHandle,\r
3560 (*Status & PCI_BIT_15) != 0\r
3561 );\r
3562\r
3563 return EFI_SUCCESS;\r
3564}\r
3565\r
a1d4bfcc 3566/**\r
5d73d92f 3567 Explain each meaningful bit of register Command.\r
3568\r
a1d4bfcc 3569 @param[in] Command Points to the content of register Command.\r
5d73d92f 3570\r
a1d4bfcc 3571 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 3572**/\r
a1d4bfcc 3573EFI_STATUS\r
3574PciExplainCommand (\r
3575 IN UINT16 *Command\r
3576 )\r
5d73d92f 3577{\r
3578 //\r
3579 // Print the binary value of register Command\r
3580 //\r
3581 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3582\r
3583 //\r
3584 // Explain register Command bit by bit\r
3585 //\r
3586 ShellPrintHiiEx(-1, -1, NULL,\r
3587 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3588 gShellDebug1HiiHandle,\r
3589 (*Command & PCI_BIT_0) != 0\r
3590 );\r
3591\r
3592 ShellPrintHiiEx(-1, -1, NULL,\r
3593 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3594 gShellDebug1HiiHandle,\r
3595 (*Command & PCI_BIT_1) != 0\r
3596 );\r
3597\r
3598 ShellPrintHiiEx(-1, -1, NULL,\r
3599 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3600 gShellDebug1HiiHandle,\r
3601 (*Command & PCI_BIT_2) != 0\r
3602 );\r
3603\r
3604 ShellPrintHiiEx(-1, -1, NULL,\r
3605 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3606 gShellDebug1HiiHandle,\r
3607 (*Command & PCI_BIT_3) != 0\r
3608 );\r
3609\r
3610 ShellPrintHiiEx(-1, -1, NULL,\r
3611 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3612 gShellDebug1HiiHandle,\r
3613 (*Command & PCI_BIT_4) != 0\r
3614 );\r
3615\r
3616 ShellPrintHiiEx(-1, -1, NULL,\r
3617 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3618 gShellDebug1HiiHandle,\r
3619 (*Command & PCI_BIT_5) != 0\r
3620 );\r
3621\r
3622 ShellPrintHiiEx(-1, -1, NULL,\r
3623 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3624 gShellDebug1HiiHandle,\r
3625 (*Command & PCI_BIT_6) != 0\r
3626 );\r
3627\r
3628 ShellPrintHiiEx(-1, -1, NULL,\r
3629 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3630 gShellDebug1HiiHandle,\r
3631 (*Command & PCI_BIT_7) != 0\r
3632 );\r
3633\r
3634 ShellPrintHiiEx(-1, -1, NULL,\r
3635 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3636 gShellDebug1HiiHandle,\r
3637 (*Command & PCI_BIT_8) != 0\r
3638 );\r
3639\r
3640 ShellPrintHiiEx(-1, -1, NULL,\r
3641 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3642 gShellDebug1HiiHandle,\r
3643 (*Command & PCI_BIT_9) != 0\r
3644 );\r
3645\r
3646 return EFI_SUCCESS;\r
3647}\r
3648\r
a1d4bfcc 3649/**\r
3650 Explain each meaningful bit of register Bridge Control.\r
3651\r
3652 @param[in] BridgeControl Points to the content of register Bridge Control.\r
3653 @param[in] HeaderType The headertype.\r
3654\r
3655 @retval EFI_SUCCESS The command completed successfully.\r
3656**/\r
5d73d92f 3657EFI_STATUS\r
3658PciExplainBridgeControl (\r
3659 IN UINT16 *BridgeControl,\r
3660 IN PCI_HEADER_TYPE HeaderType\r
3661 )\r
5d73d92f 3662{\r
3663 ShellPrintHiiEx(-1, -1, NULL,\r
3664 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3665 gShellDebug1HiiHandle,\r
3666 INDEX_OF (BridgeControl),\r
3667 *BridgeControl\r
3668 );\r
3669\r
3670 ShellPrintHiiEx(-1, -1, NULL,\r
3671 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3672 gShellDebug1HiiHandle,\r
3673 (*BridgeControl & PCI_BIT_0) != 0\r
3674 );\r
3675 ShellPrintHiiEx(-1, -1, NULL,\r
3676 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3677 gShellDebug1HiiHandle,\r
3678 (*BridgeControl & PCI_BIT_1) != 0\r
3679 );\r
3680 ShellPrintHiiEx(-1, -1, NULL,\r
3681 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3682 gShellDebug1HiiHandle,\r
3683 (*BridgeControl & PCI_BIT_2) != 0\r
3684 );\r
3685 ShellPrintHiiEx(-1, -1, NULL,\r
3686 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3687 gShellDebug1HiiHandle,\r
3688 (*BridgeControl & PCI_BIT_3) != 0\r
3689 );\r
3690 ShellPrintHiiEx(-1, -1, NULL,\r
3691 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3692 gShellDebug1HiiHandle,\r
3693 (*BridgeControl & PCI_BIT_5) != 0\r
3694 );\r
3695\r
3696 //\r
3697 // Register Bridge Control has some slight differences between P2P bridge\r
3698 // and Cardbus bridge from bit 6 to bit 11.\r
3699 //\r
3700 if (HeaderType == PciP2pBridge) {\r
3701 ShellPrintHiiEx(-1, -1, NULL,\r
3702 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3703 gShellDebug1HiiHandle,\r
3704 (*BridgeControl & PCI_BIT_6) != 0\r
3705 );\r
3706 ShellPrintHiiEx(-1, -1, NULL,\r
3707 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3708 gShellDebug1HiiHandle,\r
3709 (*BridgeControl & PCI_BIT_7) != 0\r
3710 );\r
3711 ShellPrintHiiEx(-1, -1, NULL,\r
3712 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3713 gShellDebug1HiiHandle,\r
3714 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3715 );\r
3716 ShellPrintHiiEx(-1, -1, NULL,\r
3717 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3718 gShellDebug1HiiHandle,\r
3719 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3720 );\r
3721 ShellPrintHiiEx(-1, -1, NULL,\r
3722 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3723 gShellDebug1HiiHandle,\r
3724 (*BridgeControl & PCI_BIT_10) != 0\r
3725 );\r
3726 ShellPrintHiiEx(-1, -1, NULL,\r
3727 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3728 gShellDebug1HiiHandle,\r
3729 (*BridgeControl & PCI_BIT_11) != 0\r
3730 );\r
3731\r
3732 } else {\r
3733 ShellPrintHiiEx(-1, -1, NULL,\r
3734 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3735 gShellDebug1HiiHandle,\r
3736 (*BridgeControl & PCI_BIT_6) != 0\r
3737 );\r
3738 ShellPrintHiiEx(-1, -1, NULL,\r
3739 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3740 gShellDebug1HiiHandle,\r
3741 (*BridgeControl & PCI_BIT_7) != 0\r
3742 );\r
3743 ShellPrintHiiEx(-1, -1, NULL,\r
3744 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3745 gShellDebug1HiiHandle,\r
3746 (*BridgeControl & PCI_BIT_10) != 0\r
3747 );\r
3748 }\r
3749\r
3750 return EFI_SUCCESS;\r
3751}\r
3752\r
a1d4bfcc 3753/**\r
3754 Print each capability structure.\r
3755\r
3756 @param[in] IoDev The pointer to the deivce.\r
3757 @param[in] Address The address to start at.\r
3758 @param[in] CapPtr The offset from the address.\r
3759\r
3760 @retval EFI_SUCCESS The operation was successful.\r
3761**/\r
5d73d92f 3762EFI_STATUS\r
3763PciExplainCapabilityStruct (\r
3764 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3765 IN UINT64 Address,\r
3766 IN UINT8 CapPtr\r
3767 )\r
3768{\r
3769 UINT8 CapabilityPtr;\r
3770 UINT16 CapabilityEntry;\r
3771 UINT8 CapabilityID;\r
3772 UINT64 RegAddress;\r
3773\r
3774 CapabilityPtr = CapPtr;\r
3775\r
3776 //\r
3777 // Go through the Capability list\r
3778 //\r
3779 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3780 RegAddress = Address + CapabilityPtr;\r
3781 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3782\r
3783 CapabilityID = (UINT8) CapabilityEntry;\r
3784\r
3785 //\r
3786 // Explain PciExpress data\r
3787 //\r
3788 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
3789 PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
3790 return EFI_SUCCESS;\r
3791 }\r
3792 //\r
3793 // Explain other capabilities here\r
3794 //\r
3795 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3796 }\r
3797\r
3798 return EFI_SUCCESS;\r
3799}\r
3800\r
a1d4bfcc 3801/**\r
3802 Print out information of the capability information.\r
3803\r
3804 @param[in] PciExpressCap The pointer to the structure about the device.\r
3805\r
3806 @retval EFI_SUCCESS The operation was successful.\r
3807**/\r
5d73d92f 3808EFI_STATUS\r
3809ExplainPcieCapReg (\r
3810 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3811 )\r
5d73d92f 3812{\r
3813 UINT16 PcieCapReg;\r
3814 CHAR16 *DevicePortType;\r
3815\r
3816 PcieCapReg = PciExpressCap->PcieCapReg;\r
3817 Print (\r
3818 L" Capability Version(3:0): %E0x%04x%N\n",\r
3819 PCIE_CAP_VERSION (PcieCapReg)\r
3820 );\r
3821 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3822 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3823 } else {\r
3824 DevicePortType = L"Unknown Type";\r
3825 }\r
3826 Print (\r
3827 L" Device/PortType(7:4): %E%s%N\n",\r
3828 DevicePortType\r
3829 );\r
3830 //\r
3831 // 'Slot Implemented' is only valid for:\r
3832 // a) Root Port of PCI Express Root Complex, or\r
3833 // b) Downstream Port of PCI Express Switch\r
3834 //\r
3835 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3836 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
3837 Print (\r
3838 L" Slot Implemented(8): %E%d%N\n",\r
3839 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3840 );\r
3841 }\r
3842 Print (\r
3843 L" Interrupt Message Number(13:9): %E0x%05x%N\n",\r
3844 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3845 );\r
3846 return EFI_SUCCESS;\r
3847}\r
3848\r
a1d4bfcc 3849/**\r
3850 Print out information of the device capability information.\r
3851\r
3852 @param[in] PciExpressCap The pointer to the structure about the device.\r
3853\r
3854 @retval EFI_SUCCESS The operation was successful.\r
3855**/\r
5d73d92f 3856EFI_STATUS\r
3857ExplainPcieDeviceCap (\r
3858 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3859 )\r
5d73d92f 3860{\r
3861 UINT16 PcieCapReg;\r
3862 UINT32 PcieDeviceCap;\r
3863 UINT8 DevicePortType;\r
3864 UINT8 L0sLatency;\r
3865 UINT8 L1Latency;\r
3866\r
3867 PcieCapReg = PciExpressCap->PcieCapReg;\r
3868 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3869 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
3870 Print (L" Max_Payload_Size Supported(2:0): ");\r
3871 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
3872 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
3873 } else {\r
3874 Print (L"%EUnknown%N\n");\r
3875 }\r
3876 Print (\r
3877 L" Phantom Functions Supported(4:3): %E%d%N\n",\r
3878 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3879 );\r
3880 Print (\r
3881 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",\r
3882 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3883 );\r
3884 //\r
3885 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3886 //\r
3887 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
a1d4bfcc 3888 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
3889 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
5d73d92f 3890 Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
3891 if (L0sLatency < 4) {\r
3892 Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
3893 } else {\r
3894 if (L0sLatency < 7) {\r
3895 Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));\r
3896 } else {\r
3897 Print (L"%ENo limit%N\n");\r
3898 }\r
3899 }\r
3900 Print (L" Endpoint L1 Acceptable Latency(11:9): ");\r
3901 if (L1Latency < 7) {\r
3902 Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));\r
3903 } else {\r
3904 Print (L"%ENo limit%N\n");\r
3905 }\r
3906 }\r
3907 Print (\r
3908 L" Role-based Error Reporting(15): %E%d%N\n",\r
3909 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3910 );\r
3911 //\r
3912 // Only valid for Upstream Port:\r
3913 // a) Captured Slot Power Limit Value\r
3914 // b) Captured Slot Power Scale\r
3915 //\r
3916 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
3917 Print (\r
3918 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",\r
3919 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3920 );\r
3921 Print (\r
3922 L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",\r
3923 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3924 );\r
3925 }\r
3926 //\r
3927 // Function Level Reset Capability is only valid for Endpoint\r
3928 //\r
3929 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3930 Print (\r
3931 L" Function Level Reset Capability(28): %E%d%N\n",\r
3932 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3933 );\r
3934 }\r
3935 return EFI_SUCCESS;\r
3936}\r
3937\r
a1d4bfcc 3938/**\r
3939 Print out information of the device control information.\r
3940\r
3941 @param[in] PciExpressCap The pointer to the structure about the device.\r
3942\r
3943 @retval EFI_SUCCESS The operation was successful.\r
3944**/\r
5d73d92f 3945EFI_STATUS\r
3946ExplainPcieDeviceControl (\r
3947 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3948 )\r
5d73d92f 3949{\r
3950 UINT16 PcieCapReg;\r
3951 UINT16 PcieDeviceControl;\r
3952\r
3953 PcieCapReg = PciExpressCap->PcieCapReg;\r
3954 PcieDeviceControl = PciExpressCap->DeviceControl;\r
3955 Print (\r
3956 L" Correctable Error Reporting Enable(0): %E%d%N\n",\r
3957 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3958 );\r
3959 Print (\r
3960 L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",\r
3961 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3962 );\r
3963 Print (\r
3964 L" Fatal Error Reporting Enable(2): %E%d%N\n",\r
3965 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3966 );\r
3967 Print (\r
3968 L" Unsupported Request Reporting Enable(3): %E%d%N\n",\r
3969 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
3970 );\r
3971 Print (\r
3972 L" Enable Relaxed Ordering(4): %E%d%N\n",\r
3973 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
3974 );\r
3975 Print (L" Max_Payload_Size(7:5): ");\r
3976 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
3977 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
3978 } else {\r
3979 Print (L"%EUnknown%N\n");\r
3980 }\r
3981 Print (\r
3982 L" Extended Tag Field Enable(8): %E%d%N\n",\r
3983 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
3984 );\r
3985 Print (\r
3986 L" Phantom Functions Enable(9): %E%d%N\n",\r
3987 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
3988 );\r
3989 Print (\r
3990 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",\r
3991 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
3992 );\r
3993 Print (\r
3994 L" Enable No Snoop(11): %E%d%N\n",\r
3995 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
3996 );\r
3997 Print (L" Max_Read_Request_Size(14:12): ");\r
3998 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
3999 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
4000 } else {\r
4001 Print (L"%EUnknown%N\n");\r
4002 }\r
4003 //\r
4004 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
4005 //\r
4006 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4007 Print (\r
4008 L" Bridge Configuration Retry Enable(15): %E%d%N\n",\r
4009 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
4010 );\r
4011 }\r
4012 return EFI_SUCCESS;\r
4013}\r
4014\r
a1d4bfcc 4015/**\r
4016 Print out information of the device status information.\r
4017\r
4018 @param[in] PciExpressCap The pointer to the structure about the device.\r
4019\r
4020 @retval EFI_SUCCESS The operation was successful.\r
4021**/\r
5d73d92f 4022EFI_STATUS\r
4023ExplainPcieDeviceStatus (\r
4024 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4025 )\r
5d73d92f 4026{\r
4027 UINT16 PcieDeviceStatus;\r
4028\r
4029 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
4030 Print (\r
4031 L" Correctable Error Detected(0): %E%d%N\n",\r
4032 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
4033 );\r
4034 Print (\r
4035 L" Non-Fatal Error Detected(1): %E%d%N\n",\r
4036 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
4037 );\r
4038 Print (\r
4039 L" Fatal Error Detected(2): %E%d%N\n",\r
4040 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
4041 );\r
4042 Print (\r
4043 L" Unsupported Request Detected(3): %E%d%N\n",\r
4044 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
4045 );\r
4046 Print (\r
4047 L" AUX Power Detected(4): %E%d%N\n",\r
4048 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
4049 );\r
4050 Print (\r
4051 L" Transactions Pending(5): %E%d%N\n",\r
4052 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
4053 );\r
4054 return EFI_SUCCESS;\r
4055}\r
4056\r
a1d4bfcc 4057/**\r
4058 Print out information of the device link information.\r
4059\r
4060 @param[in] PciExpressCap The pointer to the structure about the device.\r
4061\r
4062 @retval EFI_SUCCESS The operation was successful.\r
4063**/\r
5d73d92f 4064EFI_STATUS\r
4065ExplainPcieLinkCap (\r
4066 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4067 )\r
5d73d92f 4068{\r
4069 UINT32 PcieLinkCap;\r
4070 CHAR16 *SupLinkSpeeds;\r
a1d4bfcc 4071 CHAR16 *AspmValue;\r
5d73d92f 4072\r
4073 PcieLinkCap = PciExpressCap->LinkCap;\r
4074 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
4075 case 1:\r
4076 SupLinkSpeeds = L"2.5 GT/s";\r
4077 break;\r
4078 case 2:\r
4079 SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
4080 break;\r
4081 default:\r
4082 SupLinkSpeeds = L"Unknown";\r
4083 break;\r
4084 }\r
4085 Print (\r
4086 L" Supported Link Speeds(3:0): %E%s supported%N\n",\r
4087 SupLinkSpeeds\r
4088 );\r
4089 Print (\r
4090 L" Maximum Link Width(9:4): %Ex%d%N\n",\r
4091 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
4092 );\r
4093 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
4094 case 1:\r
a1d4bfcc 4095 AspmValue = L"L0s Entry";\r
5d73d92f 4096 break;\r
4097 case 3:\r
a1d4bfcc 4098 AspmValue = L"L0s and L1";\r
5d73d92f 4099 break;\r
4100 default:\r
a1d4bfcc 4101 AspmValue = L"Reserved";\r
5d73d92f 4102 break;\r
4103 }\r
4104 Print (\r
4105 L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
a1d4bfcc 4106 AspmValue\r
5d73d92f 4107 );\r
4108 Print (\r
4109 L" L0s Exit Latency(14:12): %E%s%N\n",\r
a1d4bfcc 4110 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4111 );\r
4112 Print (\r
4113 L" L1 Exit Latency(17:15): %E%s%N\n",\r
a1d4bfcc 4114 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4115 );\r
4116 Print (\r
4117 L" Clock Power Management(18): %E%d%N\n",\r
4118 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4119 );\r
4120 Print (\r
4121 L" Surprise Down Error Reporting Capable(19): %E%d%N\n",\r
4122 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4123 );\r
4124 Print (\r
4125 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",\r
4126 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4127 );\r
4128 Print (\r
4129 L" Link Bandwidth Notification Capability(21): %E%d%N\n",\r
4130 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4131 );\r
4132 Print (\r
4133 L" Port Number(31:24): %E0x%02x%N\n",\r
4134 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4135 );\r
4136 return EFI_SUCCESS;\r
4137}\r
4138\r
a1d4bfcc 4139/**\r
4140 Print out information of the device link control information.\r
4141\r
4142 @param[in] PciExpressCap The pointer to the structure about the device.\r
4143\r
4144 @retval EFI_SUCCESS The operation was successful.\r
4145**/\r
5d73d92f 4146EFI_STATUS\r
4147ExplainPcieLinkControl (\r
4148 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4149 )\r
5d73d92f 4150{\r
4151 UINT16 PcieLinkControl;\r
4152 UINT8 DevicePortType;\r
4153\r
4154 PcieLinkControl = PciExpressCap->LinkControl;\r
4155 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
4156 Print (\r
4157 L" Active State Power Management Control(1:0): %E%s%N\n",\r
4158 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4159 );\r
4160 //\r
4161 // RCB is not applicable to switches\r
4162 //\r
4163 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
4164 Print (\r
4165 L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",\r
4166 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4167 );\r
4168 }\r
4169 //\r
4170 // Link Disable is reserved on\r
4171 // a) Endpoints\r
4172 // b) PCI Express to PCI/PCI-X bridges\r
4173 // c) Upstream Ports of Switches\r
4174 //\r
4175 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4176 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4177 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4178 Print (\r
4179 L" Link Disable(4): %E%d%N\n",\r
4180 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4181 );\r
4182 }\r
4183 Print (\r
4184 L" Common Clock Configuration(6): %E%d%N\n",\r
4185 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4186 );\r
4187 Print (\r
4188 L" Extended Synch(7): %E%d%N\n",\r
4189 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4190 );\r
4191 Print (\r
4192 L" Enable Clock Power Management(8): %E%d%N\n",\r
4193 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4194 );\r
4195 Print (\r
4196 L" Hardware Autonomous Width Disable(9): %E%d%N\n",\r
4197 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4198 );\r
4199 Print (\r
4200 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",\r
4201 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4202 );\r
4203 Print (\r
4204 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",\r
4205 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4206 );\r
4207 return EFI_SUCCESS;\r
4208}\r
4209\r
a1d4bfcc 4210/**\r
4211 Print out information of the device link status information.\r
4212\r
4213 @param[in] PciExpressCap The pointer to the structure about the device.\r
4214\r
4215 @retval EFI_SUCCESS The operation was successful.\r
4216**/\r
5d73d92f 4217EFI_STATUS\r
4218ExplainPcieLinkStatus (\r
4219 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4220 )\r
5d73d92f 4221{\r
4222 UINT16 PcieLinkStatus;\r
4223 CHAR16 *SupLinkSpeeds;\r
4224\r
4225 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4226 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4227 case 1:\r
4228 SupLinkSpeeds = L"2.5 GT/s";\r
4229 break;\r
4230 case 2:\r
4231 SupLinkSpeeds = L"5.0 GT/s";\r
4232 break;\r
4233 default:\r
4234 SupLinkSpeeds = L"Reserved";\r
4235 break;\r
4236 }\r
4237 Print (\r
4238 L" Current Link Speed(3:0): %E%s%N\n",\r
4239 SupLinkSpeeds\r
4240 );\r
4241 Print (\r
4242 L" Negotiated Link Width(9:4): %Ex%d%N\n",\r
4243 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4244 );\r
4245 Print (\r
4246 L" Link Training(11): %E%d%N\n",\r
4247 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4248 );\r
4249 Print (\r
4250 L" Slot Clock Configuration(12): %E%d%N\n",\r
4251 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4252 );\r
4253 Print (\r
4254 L" Data Link Layer Link Active(13): %E%d%N\n",\r
4255 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4256 );\r
4257 Print (\r
4258 L" Link Bandwidth Management Status(14): %E%d%N\n",\r
4259 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4260 );\r
4261 Print (\r
4262 L" Link Autonomous Bandwidth Status(15): %E%d%N\n",\r
4263 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4264 );\r
4265 return EFI_SUCCESS;\r
4266}\r
4267\r
a1d4bfcc 4268/**\r
4269 Print out information of the device slot information.\r
4270\r
4271 @param[in] PciExpressCap The pointer to the structure about the device.\r
4272\r
4273 @retval EFI_SUCCESS The operation was successful.\r
4274**/\r
5d73d92f 4275EFI_STATUS\r
4276ExplainPcieSlotCap (\r
4277 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4278 )\r
5d73d92f 4279{\r
4280 UINT32 PcieSlotCap;\r
4281\r
4282 PcieSlotCap = PciExpressCap->SlotCap;\r
4283\r
4284 Print (\r
4285 L" Attention Button Present(0): %E%d%N\n",\r
4286 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4287 );\r
4288 Print (\r
4289 L" Power Controller Present(1): %E%d%N\n",\r
4290 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4291 );\r
4292 Print (\r
4293 L" MRL Sensor Present(2): %E%d%N\n",\r
4294 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4295 );\r
4296 Print (\r
4297 L" Attention Indicator Present(3): %E%d%N\n",\r
4298 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4299 );\r
4300 Print (\r
4301 L" Power Indicator Present(4): %E%d%N\n",\r
4302 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4303 );\r
4304 Print (\r
4305 L" Hot-Plug Surprise(5): %E%d%N\n",\r
4306 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4307 );\r
4308 Print (\r
4309 L" Hot-Plug Capable(6): %E%d%N\n",\r
4310 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4311 );\r
4312 Print (\r
4313 L" Slot Power Limit Value(14:7): %E0x%02x%N\n",\r
4314 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4315 );\r
4316 Print (\r
4317 L" Slot Power Limit Scale(16:15): %E%s%N\n",\r
4318 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4319 );\r
4320 Print (\r
4321 L" Electromechanical Interlock Present(17): %E%d%N\n",\r
4322 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4323 );\r
4324 Print (\r
4325 L" No Command Completed Support(18): %E%d%N\n",\r
4326 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4327 );\r
4328 Print (\r
4329 L" Physical Slot Number(31:19): %E%d%N\n",\r
4330 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4331 );\r
4332\r
4333 return EFI_SUCCESS;\r
4334}\r
4335\r
a1d4bfcc 4336/**\r
4337 Print out information of the device slot control information.\r
4338\r
4339 @param[in] PciExpressCap The pointer to the structure about the device.\r
4340\r
4341 @retval EFI_SUCCESS The operation was successful.\r
4342**/\r
5d73d92f 4343EFI_STATUS\r
4344ExplainPcieSlotControl (\r
4345 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4346 )\r
5d73d92f 4347{\r
4348 UINT16 PcieSlotControl;\r
4349\r
4350 PcieSlotControl = PciExpressCap->SlotControl;\r
4351 Print (\r
4352 L" Attention Button Pressed Enable(0): %E%d%N\n",\r
4353 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4354 );\r
4355 Print (\r
4356 L" Power Fault Detected Enable(1): %E%d%N\n",\r
4357 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4358 );\r
4359 Print (\r
4360 L" MRL Sensor Changed Enable(2): %E%d%N\n",\r
4361 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4362 );\r
4363 Print (\r
4364 L" Presence Detect Changed Enable(3): %E%d%N\n",\r
4365 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4366 );\r
4367 Print (\r
4368 L" Command Completed Interrupt Enable(4): %E%d%N\n",\r
4369 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4370 );\r
4371 Print (\r
4372 L" Hot-Plug Interrupt Enable(5): %E%d%N\n",\r
4373 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4374 );\r
4375 Print (\r
4376 L" Attention Indicator Control(7:6): %E%s%N\n",\r
4377 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4378 );\r
4379 Print (\r
4380 L" Power Indicator Control(9:8): %E%s%N\n",\r
4381 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4382 );\r
4383 Print (L" Power Controller Control(10): %EPower ");\r
4384 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
4385 Print (L"Off%N\n");\r
4386 } else {\r
4387 Print (L"On%N\n");\r
4388 }\r
4389 Print (\r
4390 L" Electromechanical Interlock Control(11): %E%d%N\n",\r
4391 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4392 );\r
4393 Print (\r
4394 L" Data Link Layer State Changed Enable(12): %E%d%N\n",\r
4395 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4396 );\r
4397 return EFI_SUCCESS;\r
4398}\r
4399\r
a1d4bfcc 4400/**\r
4401 Print out information of the device slot status information.\r
4402\r
4403 @param[in] PciExpressCap The pointer to the structure about the device.\r
4404\r
4405 @retval EFI_SUCCESS The operation was successful.\r
4406**/\r
5d73d92f 4407EFI_STATUS\r
4408ExplainPcieSlotStatus (\r
4409 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4410 )\r
5d73d92f 4411{\r
4412 UINT16 PcieSlotStatus;\r
4413\r
4414 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4415\r
4416 Print (\r
4417 L" Attention Button Pressed(0): %E%d%N\n",\r
4418 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4419 );\r
4420 Print (\r
4421 L" Power Fault Detected(1): %E%d%N\n",\r
4422 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4423 );\r
4424 Print (\r
4425 L" MRL Sensor Changed(2): %E%d%N\n",\r
4426 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4427 );\r
4428 Print (\r
4429 L" Presence Detect Changed(3): %E%d%N\n",\r
4430 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4431 );\r
4432 Print (\r
4433 L" Command Completed(4): %E%d%N\n",\r
4434 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4435 );\r
4436 Print (L" MRL Sensor State(5): %EMRL ");\r
4437 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
4438 Print (L" Opened%N\n");\r
4439 } else {\r
4440 Print (L" Closed%N\n");\r
4441 }\r
4442 Print (L" Presence Detect State(6): ");\r
4443 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
4444 Print (L"%ECard Present in slot%N\n");\r
4445 } else {\r
4446 Print (L"%ESlot Empty%N\n");\r
4447 }\r
4448 Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
4449 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
4450 Print (L"Engaged%N\n");\r
4451 } else {\r
4452 Print (L"Disengaged%N\n");\r
4453 }\r
4454 Print (\r
4455 L" Data Link Layer State Changed(8): %E%d%N\n",\r
4456 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4457 );\r
4458 return EFI_SUCCESS;\r
4459}\r
4460\r
a1d4bfcc 4461/**\r
4462 Print out information of the device root information.\r
4463\r
4464 @param[in] PciExpressCap The pointer to the structure about the device.\r
4465\r
4466 @retval EFI_SUCCESS The operation was successful.\r
4467**/\r
5d73d92f 4468EFI_STATUS\r
4469ExplainPcieRootControl (\r
4470 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4471 )\r
5d73d92f 4472{\r
4473 UINT16 PcieRootControl;\r
4474\r
4475 PcieRootControl = PciExpressCap->RootControl;\r
4476\r
4477 Print (\r
4478 L" System Error on Correctable Error Enable(0): %E%d%N\n",\r
4479 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4480 );\r
4481 Print (\r
4482 L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",\r
4483 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4484 );\r
4485 Print (\r
4486 L" System Error on Fatal Error Enable(2): %E%d%N\n",\r
4487 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4488 );\r
4489 Print (\r
4490 L" PME Interrupt Enable(3): %E%d%N\n",\r
4491 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4492 );\r
4493 Print (\r
4494 L" CRS Software Visibility Enable(4): %E%d%N\n",\r
4495 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4496 );\r
4497\r
4498 return EFI_SUCCESS;\r
4499}\r
4500\r
a1d4bfcc 4501/**\r
4502 Print out information of the device root capability information.\r
4503\r
4504 @param[in] PciExpressCap The pointer to the structure about the device.\r
4505\r
4506 @retval EFI_SUCCESS The operation was successful.\r
4507**/\r
5d73d92f 4508EFI_STATUS\r
4509ExplainPcieRootCap (\r
4510 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4511 )\r
5d73d92f 4512{\r
4513 UINT16 PcieRootCap;\r
4514\r
4515 PcieRootCap = PciExpressCap->RsvdP;\r
4516\r
4517 Print (\r
4518 L" CRS Software Visibility(0): %E%d%N\n",\r
4519 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4520 );\r
4521\r
4522 return EFI_SUCCESS;\r
4523}\r
4524\r
a1d4bfcc 4525/**\r
4526 Print out information of the device root status information.\r
4527\r
4528 @param[in] PciExpressCap The pointer to the structure about the device.\r
4529\r
4530 @retval EFI_SUCCESS The operation was successful.\r
4531**/\r
5d73d92f 4532EFI_STATUS\r
4533ExplainPcieRootStatus (\r
4534 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4535 )\r
5d73d92f 4536{\r
4537 UINT32 PcieRootStatus;\r
4538\r
4539 PcieRootStatus = PciExpressCap->RootStatus;\r
4540\r
4541 Print (\r
4542 L" PME Requester ID(15:0): %E0x%04x%N\n",\r
4543 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4544 );\r
4545 Print (\r
4546 L" PME Status(16): %E%d%N\n",\r
4547 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4548 );\r
4549 Print (\r
4550 L" PME Pending(17): %E%d%N\n",\r
4551 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4552 );\r
4553 return EFI_SUCCESS;\r
4554}\r
4555\r
a1d4bfcc 4556/**\r
4557 Display Pcie device structure.\r
4558\r
4559 @param[in] IoDev The pointer to the root pci protocol.\r
4560 @param[in] Address The Address to start at.\r
4561 @param[in] CapabilityPtr The offset from the address to start.\r
4562**/\r
5d73d92f 4563EFI_STATUS\r
4564PciExplainPciExpress (\r
4565 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
4566 IN UINT64 Address,\r
4567 IN UINT8 CapabilityPtr\r
4568 )\r
4569{\r
4570\r
4571 PCIE_CAP_STURCTURE PciExpressCap;\r
4572 EFI_STATUS Status;\r
4573 UINT64 CapRegAddress;\r
4574 UINT8 Bus;\r
4575 UINT8 Dev;\r
4576 UINT8 Func;\r
4577 UINT8 *ExRegBuffer;\r
4578 UINTN ExtendRegSize;\r
4579 UINT64 Pciex_Address;\r
4580 UINT8 DevicePortType;\r
4581 UINTN Index;\r
4582 UINT8 *RegAddr;\r
4583 UINTN RegValue;\r
4584\r
4585 CapRegAddress = Address + CapabilityPtr;\r
4586 IoDev->Pci.Read (\r
4587 IoDev,\r
4588 EfiPciWidthUint32,\r
4589 CapRegAddress,\r
4590 sizeof (PciExpressCap) / sizeof (UINT32),\r
4591 &PciExpressCap\r
4592 );\r
4593\r
4594 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
4595\r
4596 Print (L"\nPci Express device capability structure:\n");\r
4597\r
4598 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
4599 if (ShellGetExecutionBreakFlag()) {\r
4600 goto Done;\r
4601 }\r
4602 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
4603 switch (PcieExplainList[Index].Width) {\r
4604 case FieldWidthUINT8:\r
4605 RegValue = *(UINT8 *) RegAddr;\r
4606 break;\r
4607 case FieldWidthUINT16:\r
4608 RegValue = *(UINT16 *) RegAddr;\r
4609 break;\r
4610 case FieldWidthUINT32:\r
4611 RegValue = *(UINT32 *) RegAddr;\r
4612 break;\r
4613 default:\r
4614 RegValue = 0;\r
4615 break;\r
4616 }\r
4617 ShellPrintHiiEx(-1, -1, NULL,\r
4618 PcieExplainList[Index].Token,\r
4619 gShellDebug1HiiHandle,\r
4620 PcieExplainList[Index].Offset,\r
4621 RegValue\r
4622 );\r
4623 if (PcieExplainList[Index].Func == NULL) {\r
4624 continue;\r
4625 }\r
4626 switch (PcieExplainList[Index].Type) {\r
4627 case PcieExplainTypeLink:\r
4628 //\r
4629 // Link registers should not be used by\r
4630 // a) Root Complex Integrated Endpoint\r
4631 // b) Root Complex Event Collector\r
4632 //\r
4633 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
4634 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
4635 continue;\r
4636 }\r
4637 break;\r
4638 case PcieExplainTypeSlot:\r
4639 //\r
4640 // Slot registers are only valid for\r
4641 // a) Root Port of PCI Express Root Complex\r
4642 // b) Downstream Port of PCI Express Switch\r
4643 // and when SlotImplemented bit is set in PCIE cap register.\r
4644 //\r
4645 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
4646 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
4647 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
4648 continue;\r
4649 }\r
4650 break;\r
4651 case PcieExplainTypeRoot:\r
4652 //\r
4653 // Root registers are only valid for\r
4654 // Root Port of PCI Express Root Complex\r
4655 //\r
4656 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
4657 continue;\r
4658 }\r
4659 break;\r
4660 default:\r
4661 break;\r
4662 }\r
4663 PcieExplainList[Index].Func (&PciExpressCap);\r
4664 }\r
4665\r
4666 Bus = (UINT8) (RShiftU64 (Address, 24));\r
4667 Dev = (UINT8) (RShiftU64 (Address, 16));\r
4668 Func = (UINT8) (RShiftU64 (Address, 8));\r
4669\r
4670 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
4671\r
4672 ExtendRegSize = 0x1000 - 0x100;\r
4673\r
3737ac2b 4674 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
5d73d92f 4675\r
4676 //\r
4677 // PciRootBridgeIo protocol should support pci express extend space IO\r
4678 // (Begins at offset 0x100)\r
4679 //\r
4680 Status = IoDev->Pci.Read (\r
4681 IoDev,\r
4682 EfiPciWidthUint32,\r
4683 Pciex_Address,\r
4684 (ExtendRegSize) / sizeof (UINT32),\r
4685 (VOID *) (ExRegBuffer)\r
4686 );\r
4687 if (EFI_ERROR (Status)) {\r
4688 FreePool ((VOID *) ExRegBuffer);\r
4689 return EFI_UNSUPPORTED;\r
4690 }\r
4691 //\r
4692 // Start outputing PciEx extend space( 0xFF-0xFFF)\r
4693 //\r
4694 Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
4695\r
d8f8021c 4696 if (ExRegBuffer != NULL) {\r
4697 DumpHex (\r
4698 2,\r
4699 0x100,\r
4700 ExtendRegSize,\r
4701 (VOID *) (ExRegBuffer)\r
4702 );\r
5d73d92f 4703\r
d8f8021c 4704 FreePool ((VOID *) ExRegBuffer);\r
4705 }\r
5d73d92f 4706\r
4707Done:\r
4708 return EFI_SUCCESS;\r
4709}\r
EFI Development Kit II mirror for PVE