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Add "Debug1" profile (all but Edit and HexEdit commands)
[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c
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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
4 Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "UefiShellDebug1CommandsLib.h"\r
16#include <Protocol/PciRootBridgeIo.h>\r
17#include <Library/ShellLib.h>\r
18#include <IndustryStandard/Pci.h>\r
19#include <IndustryStandard/Acpi.h>\r
20#include "Pci.h"\r
21\r
22#define PCI_CLASS_STRING_LIMIT 54\r
23//\r
24// Printable strings for Pci class code\r
25//\r
26typedef struct {\r
27 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
28 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
29 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
30} PCI_CLASS_STRINGS;\r
31\r
32//\r
33// a structure holding a single entry, which also points to its lower level\r
34// class\r
35//\r
36typedef struct PCI_CLASS_ENTRY_TAG {\r
37 UINT8 Code; // Class, subclass or I/F code\r
38 CHAR16 *DescText; // Description string\r
39 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
40} PCI_CLASS_ENTRY;\r
41\r
42//\r
43// Declarations of entries which contain printable strings for class codes\r
44// in PCI configuration space\r
45//\r
46PCI_CLASS_ENTRY PCIBlankEntry[];\r
47PCI_CLASS_ENTRY PCISubClass_00[];\r
48PCI_CLASS_ENTRY PCISubClass_01[];\r
49PCI_CLASS_ENTRY PCISubClass_02[];\r
50PCI_CLASS_ENTRY PCISubClass_03[];\r
51PCI_CLASS_ENTRY PCISubClass_04[];\r
52PCI_CLASS_ENTRY PCISubClass_05[];\r
53PCI_CLASS_ENTRY PCISubClass_06[];\r
54PCI_CLASS_ENTRY PCISubClass_07[];\r
55PCI_CLASS_ENTRY PCISubClass_08[];\r
56PCI_CLASS_ENTRY PCISubClass_09[];\r
57PCI_CLASS_ENTRY PCISubClass_0a[];\r
58PCI_CLASS_ENTRY PCISubClass_0b[];\r
59PCI_CLASS_ENTRY PCISubClass_0c[];\r
60PCI_CLASS_ENTRY PCISubClass_0d[];\r
61PCI_CLASS_ENTRY PCISubClass_0e[];\r
62PCI_CLASS_ENTRY PCISubClass_0f[];\r
63PCI_CLASS_ENTRY PCISubClass_10[];\r
64PCI_CLASS_ENTRY PCISubClass_11[];\r
65PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
79\r
80//\r
81// Base class strings entries\r
82//\r
83PCI_CLASS_ENTRY gClassStringList[] = {\r
84 {\r
85 0x00,\r
86 L"Pre 2.0 device",\r
87 PCISubClass_00\r
88 },\r
89 {\r
90 0x01,\r
91 L"Mass Storage Controller",\r
92 PCISubClass_01\r
93 },\r
94 {\r
95 0x02,\r
96 L"Network Controller",\r
97 PCISubClass_02\r
98 },\r
99 {\r
100 0x03,\r
101 L"Display Controller",\r
102 PCISubClass_03\r
103 },\r
104 {\r
105 0x04,\r
106 L"Multimedia Device",\r
107 PCISubClass_04\r
108 },\r
109 {\r
110 0x05,\r
111 L"Memory Controller",\r
112 PCISubClass_05\r
113 },\r
114 {\r
115 0x06,\r
116 L"Bridge Device",\r
117 PCISubClass_06\r
118 },\r
119 {\r
120 0x07,\r
121 L"Simple Communications Controllers",\r
122 PCISubClass_07\r
123 },\r
124 {\r
125 0x08,\r
126 L"Base System Peripherals",\r
127 PCISubClass_08\r
128 },\r
129 {\r
130 0x09,\r
131 L"Input Devices",\r
132 PCISubClass_09\r
133 },\r
134 {\r
135 0x0a,\r
136 L"Docking Stations",\r
137 PCISubClass_0a\r
138 },\r
139 {\r
140 0x0b,\r
141 L"Processors",\r
142 PCISubClass_0b\r
143 },\r
144 {\r
145 0x0c,\r
146 L"Serial Bus Controllers",\r
147 PCISubClass_0c\r
148 },\r
149 {\r
150 0x0d,\r
151 L"Wireless Controllers",\r
152 PCISubClass_0d\r
153 },\r
154 {\r
155 0x0e,\r
156 L"Intelligent IO Controllers",\r
157 PCISubClass_0e\r
158 },\r
159 {\r
160 0x0f,\r
161 L"Satellite Communications Controllers",\r
162 PCISubClass_0f\r
163 },\r
164 {\r
165 0x10,\r
166 L"Encryption/Decryption Controllers",\r
167 PCISubClass_10\r
168 },\r
169 {\r
170 0x11,\r
171 L"Data Acquisition & Signal Processing Controllers",\r
172 PCISubClass_11\r
173 },\r
174 {\r
175 0xff,\r
176 L"Device does not fit in any defined classes",\r
177 PCIBlankEntry\r
178 },\r
179 {\r
180 0x00,\r
181 NULL,\r
182 /* null string ends the list */NULL\r
183 }\r
184};\r
185\r
186//\r
187// Subclass strings entries\r
188//\r
189PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
190 {\r
191 0x00,\r
192 L"",\r
193 PCIBlankEntry\r
194 },\r
195 {\r
196 0x00,\r
197 NULL,\r
198 /* null string ends the list */NULL\r
199 }\r
200};\r
201\r
202PCI_CLASS_ENTRY PCISubClass_00[] = {\r
203 {\r
204 0x00,\r
205 L"All devices other than VGA",\r
206 PCIBlankEntry\r
207 },\r
208 {\r
209 0x01,\r
210 L"VGA-compatible devices",\r
211 PCIBlankEntry\r
212 },\r
213 {\r
214 0x00,\r
215 NULL,\r
216 /* null string ends the list */NULL\r
217 }\r
218};\r
219\r
220PCI_CLASS_ENTRY PCISubClass_01[] = {\r
221 {\r
222 0x00,\r
223 L"SCSI controller",\r
224 PCIBlankEntry\r
225 },\r
226 {\r
227 0x01,\r
228 L"IDE controller",\r
229 PCIPIFClass_0101\r
230 },\r
231 {\r
232 0x02,\r
233 L"Floppy disk controller",\r
234 PCIBlankEntry\r
235 },\r
236 {\r
237 0x03,\r
238 L"IPI controller",\r
239 PCIBlankEntry\r
240 },\r
241 {\r
242 0x04,\r
243 L"RAID controller",\r
244 PCIBlankEntry\r
245 },\r
246 {\r
247 0x80,\r
248 L"Other mass storage controller",\r
249 PCIBlankEntry\r
250 },\r
251 {\r
252 0x00,\r
253 NULL,\r
254 /* null string ends the list */NULL\r
255 }\r
256};\r
257\r
258PCI_CLASS_ENTRY PCISubClass_02[] = {\r
259 {\r
260 0x00,\r
261 L"Ethernet controller",\r
262 PCIBlankEntry\r
263 },\r
264 {\r
265 0x01,\r
266 L"Token ring controller",\r
267 PCIBlankEntry\r
268 },\r
269 {\r
270 0x02,\r
271 L"FDDI controller",\r
272 PCIBlankEntry\r
273 },\r
274 {\r
275 0x03,\r
276 L"ATM controller",\r
277 PCIBlankEntry\r
278 },\r
279 {\r
280 0x04,\r
281 L"ISDN controller",\r
282 PCIBlankEntry\r
283 },\r
284 {\r
285 0x80,\r
286 L"Other network controller",\r
287 PCIBlankEntry\r
288 },\r
289 {\r
290 0x00,\r
291 NULL,\r
292 /* null string ends the list */NULL\r
293 }\r
294};\r
295\r
296PCI_CLASS_ENTRY PCISubClass_03[] = {\r
297 {\r
298 0x00,\r
299 L"VGA/8514 controller",\r
300 PCIPIFClass_0300\r
301 },\r
302 {\r
303 0x01,\r
304 L"XGA controller",\r
305 PCIBlankEntry\r
306 },\r
307 {\r
308 0x02,\r
309 L"3D controller",\r
310 PCIBlankEntry\r
311 },\r
312 {\r
313 0x80,\r
314 L"Other display controller",\r
315 PCIBlankEntry\r
316 },\r
317 {\r
318 0x00,\r
319 NULL,\r
320 /* null string ends the list */PCIBlankEntry\r
321 }\r
322};\r
323\r
324PCI_CLASS_ENTRY PCISubClass_04[] = {\r
325 {\r
326 0x00,\r
327 L"Video device",\r
328 PCIBlankEntry\r
329 },\r
330 {\r
331 0x01,\r
332 L"Audio device",\r
333 PCIBlankEntry\r
334 },\r
335 {\r
336 0x02,\r
337 L"Computer Telephony device",\r
338 PCIBlankEntry\r
339 },\r
340 {\r
341 0x80,\r
342 L"Other multimedia device",\r
343 PCIBlankEntry\r
344 },\r
345 {\r
346 0x00,\r
347 NULL,\r
348 /* null string ends the list */NULL\r
349 }\r
350};\r
351\r
352PCI_CLASS_ENTRY PCISubClass_05[] = {\r
353 {\r
354 0x00,\r
355 L"RAM memory controller",\r
356 PCIBlankEntry\r
357 },\r
358 {\r
359 0x01,\r
360 L"Flash memory controller",\r
361 PCIBlankEntry\r
362 },\r
363 {\r
364 0x80,\r
365 L"Other memory controller",\r
366 PCIBlankEntry\r
367 },\r
368 {\r
369 0x00,\r
370 NULL,\r
371 /* null string ends the list */NULL\r
372 }\r
373};\r
374\r
375PCI_CLASS_ENTRY PCISubClass_06[] = {\r
376 {\r
377 0x00,\r
378 L"Host/PCI bridge",\r
379 PCIBlankEntry\r
380 },\r
381 {\r
382 0x01,\r
383 L"PCI/ISA bridge",\r
384 PCIBlankEntry\r
385 },\r
386 {\r
387 0x02,\r
388 L"PCI/EISA bridge",\r
389 PCIBlankEntry\r
390 },\r
391 {\r
392 0x03,\r
393 L"PCI/Micro Channel bridge",\r
394 PCIBlankEntry\r
395 },\r
396 {\r
397 0x04,\r
398 L"PCI/PCI bridge",\r
399 PCIPIFClass_0604\r
400 },\r
401 {\r
402 0x05,\r
403 L"PCI/PCMCIA bridge",\r
404 PCIBlankEntry\r
405 },\r
406 {\r
407 0x06,\r
408 L"NuBus bridge",\r
409 PCIBlankEntry\r
410 },\r
411 {\r
412 0x07,\r
413 L"CardBus bridge",\r
414 PCIBlankEntry\r
415 },\r
416 {\r
417 0x08,\r
418 L"RACEway bridge",\r
419 PCIBlankEntry\r
420 },\r
421 {\r
422 0x80,\r
423 L"Other bridge type",\r
424 PCIBlankEntry\r
425 },\r
426 {\r
427 0x00,\r
428 NULL,\r
429 /* null string ends the list */NULL\r
430 }\r
431};\r
432\r
433PCI_CLASS_ENTRY PCISubClass_07[] = {\r
434 {\r
435 0x00,\r
436 L"Serial controller",\r
437 PCIPIFClass_0700\r
438 },\r
439 {\r
440 0x01,\r
441 L"Parallel port",\r
442 PCIPIFClass_0701\r
443 },\r
444 {\r
445 0x02,\r
446 L"Multiport serial controller",\r
447 PCIBlankEntry\r
448 },\r
449 {\r
450 0x03,\r
451 L"Modem",\r
452 PCIPIFClass_0703\r
453 },\r
454 {\r
455 0x80,\r
456 L"Other communication device",\r
457 PCIBlankEntry\r
458 },\r
459 {\r
460 0x00,\r
461 NULL,\r
462 /* null string ends the list */NULL\r
463 }\r
464};\r
465\r
466PCI_CLASS_ENTRY PCISubClass_08[] = {\r
467 {\r
468 0x00,\r
469 L"PIC",\r
470 PCIPIFClass_0800\r
471 },\r
472 {\r
473 0x01,\r
474 L"DMA controller",\r
475 PCIPIFClass_0801\r
476 },\r
477 {\r
478 0x02,\r
479 L"System timer",\r
480 PCIPIFClass_0802\r
481 },\r
482 {\r
483 0x03,\r
484 L"RTC controller",\r
485 PCIPIFClass_0803\r
486 },\r
487 {\r
488 0x04,\r
489 L"Generic PCI Hot-Plug controller",\r
490 PCIBlankEntry\r
491 },\r
492 {\r
493 0x80,\r
494 L"Other system peripheral",\r
495 PCIBlankEntry\r
496 },\r
497 {\r
498 0x00,\r
499 NULL,\r
500 /* null string ends the list */NULL\r
501 }\r
502};\r
503\r
504PCI_CLASS_ENTRY PCISubClass_09[] = {\r
505 {\r
506 0x00,\r
507 L"Keyboard controller",\r
508 PCIBlankEntry\r
509 },\r
510 {\r
511 0x01,\r
512 L"Digitizer (pen)",\r
513 PCIBlankEntry\r
514 },\r
515 {\r
516 0x02,\r
517 L"Mouse controller",\r
518 PCIBlankEntry\r
519 },\r
520 {\r
521 0x03,\r
522 L"Scanner controller",\r
523 PCIBlankEntry\r
524 },\r
525 {\r
526 0x04,\r
527 L"Gameport controller",\r
528 PCIPIFClass_0904\r
529 },\r
530 {\r
531 0x80,\r
532 L"Other input controller",\r
533 PCIBlankEntry\r
534 },\r
535 {\r
536 0x00,\r
537 NULL,\r
538 /* null string ends the list */NULL\r
539 }\r
540};\r
541\r
542PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
543 {\r
544 0x00,\r
545 L"Generic docking station",\r
546 PCIBlankEntry\r
547 },\r
548 {\r
549 0x80,\r
550 L"Other type of docking station",\r
551 PCIBlankEntry\r
552 },\r
553 {\r
554 0x00,\r
555 NULL,\r
556 /* null string ends the list */NULL\r
557 }\r
558};\r
559\r
560PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
561 {\r
562 0x00,\r
563 L"386",\r
564 PCIBlankEntry\r
565 },\r
566 {\r
567 0x01,\r
568 L"486",\r
569 PCIBlankEntry\r
570 },\r
571 {\r
572 0x02,\r
573 L"Pentium",\r
574 PCIBlankEntry\r
575 },\r
576 {\r
577 0x10,\r
578 L"Alpha",\r
579 PCIBlankEntry\r
580 },\r
581 {\r
582 0x20,\r
583 L"PowerPC",\r
584 PCIBlankEntry\r
585 },\r
586 {\r
587 0x30,\r
588 L"MIPS",\r
589 PCIBlankEntry\r
590 },\r
591 {\r
592 0x40,\r
593 L"Co-processor",\r
594 PCIBlankEntry\r
595 },\r
596 {\r
597 0x80,\r
598 L"Other processor",\r
599 PCIBlankEntry\r
600 },\r
601 {\r
602 0x00,\r
603 NULL,\r
604 /* null string ends the list */NULL\r
605 }\r
606};\r
607\r
608PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
609 {\r
610 0x00,\r
611 L"Firewire(IEEE 1394)",\r
612 PCIPIFClass_0c03\r
613 },\r
614 {\r
615 0x01,\r
616 L"ACCESS.bus",\r
617 PCIBlankEntry\r
618 },\r
619 {\r
620 0x02,\r
621 L"SSA",\r
622 PCIBlankEntry\r
623 },\r
624 {\r
625 0x03,\r
626 L"USB",\r
627 PCIPIFClass_0c00\r
628 },\r
629 {\r
630 0x04,\r
631 L"Fibre Channel",\r
632 PCIBlankEntry\r
633 },\r
634 {\r
635 0x05,\r
636 L"System Management Bus",\r
637 PCIBlankEntry\r
638 },\r
639 {\r
640 0x80,\r
641 L"Other bus type",\r
642 PCIBlankEntry\r
643 },\r
644 {\r
645 0x00,\r
646 NULL,\r
647 /* null string ends the list */NULL\r
648 }\r
649};\r
650\r
651PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
652 {\r
653 0x00,\r
654 L"iRDA compatible controller",\r
655 PCIBlankEntry\r
656 },\r
657 {\r
658 0x01,\r
659 L"Consumer IR controller",\r
660 PCIBlankEntry\r
661 },\r
662 {\r
663 0x10,\r
664 L"RF controller",\r
665 PCIBlankEntry\r
666 },\r
667 {\r
668 0x80,\r
669 L"Other type of wireless controller",\r
670 PCIBlankEntry\r
671 },\r
672 {\r
673 0x00,\r
674 NULL,\r
675 /* null string ends the list */NULL\r
676 }\r
677};\r
678\r
679PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
680 {\r
681 0x00,\r
682 L"I2O Architecture",\r
683 PCIPIFClass_0e00\r
684 },\r
685 {\r
686 0x00,\r
687 NULL,\r
688 /* null string ends the list */NULL\r
689 }\r
690};\r
691\r
692PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
693 {\r
694 0x00,\r
695 L"TV",\r
696 PCIBlankEntry\r
697 },\r
698 {\r
699 0x01,\r
700 L"Audio",\r
701 PCIBlankEntry\r
702 },\r
703 {\r
704 0x02,\r
705 L"Voice",\r
706 PCIBlankEntry\r
707 },\r
708 {\r
709 0x03,\r
710 L"Data",\r
711 PCIBlankEntry\r
712 },\r
713 {\r
714 0x00,\r
715 NULL,\r
716 /* null string ends the list */NULL\r
717 }\r
718};\r
719\r
720PCI_CLASS_ENTRY PCISubClass_10[] = {\r
721 {\r
722 0x00,\r
723 L"Network & computing Encrypt/Decrypt",\r
724 PCIBlankEntry\r
725 },\r
726 {\r
727 0x01,\r
728 L"Entertainment Encrypt/Decrypt",\r
729 PCIBlankEntry\r
730 },\r
731 {\r
732 0x80,\r
733 L"Other Encrypt/Decrypt",\r
734 PCIBlankEntry\r
735 },\r
736 {\r
737 0x00,\r
738 NULL,\r
739 /* null string ends the list */NULL\r
740 }\r
741};\r
742\r
743PCI_CLASS_ENTRY PCISubClass_11[] = {\r
744 {\r
745 0x00,\r
746 L"DPIO modules",\r
747 PCIBlankEntry\r
748 },\r
749 {\r
750 0x80,\r
751 L"Other DAQ & SP controllers",\r
752 PCIBlankEntry\r
753 },\r
754 {\r
755 0x00,\r
756 NULL,\r
757 /* null string ends the list */NULL\r
758 }\r
759};\r
760\r
761//\r
762// Programming Interface entries\r
763//\r
764PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
765 {\r
766 0x00,\r
767 L"",\r
768 PCIBlankEntry\r
769 },\r
770 {\r
771 0x01,\r
772 L"OM-primary",\r
773 PCIBlankEntry\r
774 },\r
775 {\r
776 0x02,\r
777 L"PI-primary",\r
778 PCIBlankEntry\r
779 },\r
780 {\r
781 0x03,\r
782 L"OM/PI-primary",\r
783 PCIBlankEntry\r
784 },\r
785 {\r
786 0x04,\r
787 L"OM-secondary",\r
788 PCIBlankEntry\r
789 },\r
790 {\r
791 0x05,\r
792 L"OM-primary, OM-secondary",\r
793 PCIBlankEntry\r
794 },\r
795 {\r
796 0x06,\r
797 L"PI-primary, OM-secondary",\r
798 PCIBlankEntry\r
799 },\r
800 {\r
801 0x07,\r
802 L"OM/PI-primary, OM-secondary",\r
803 PCIBlankEntry\r
804 },\r
805 {\r
806 0x08,\r
807 L"OM-secondary",\r
808 PCIBlankEntry\r
809 },\r
810 {\r
811 0x09,\r
812 L"OM-primary, PI-secondary",\r
813 PCIBlankEntry\r
814 },\r
815 {\r
816 0x0a,\r
817 L"PI-primary, PI-secondary",\r
818 PCIBlankEntry\r
819 },\r
820 {\r
821 0x0b,\r
822 L"OM/PI-primary, PI-secondary",\r
823 PCIBlankEntry\r
824 },\r
825 {\r
826 0x0c,\r
827 L"OM-secondary",\r
828 PCIBlankEntry\r
829 },\r
830 {\r
831 0x0d,\r
832 L"OM-primary, OM/PI-secondary",\r
833 PCIBlankEntry\r
834 },\r
835 {\r
836 0x0e,\r
837 L"PI-primary, OM/PI-secondary",\r
838 PCIBlankEntry\r
839 },\r
840 {\r
841 0x0f,\r
842 L"OM/PI-primary, OM/PI-secondary",\r
843 PCIBlankEntry\r
844 },\r
845 {\r
846 0x80,\r
847 L"Master",\r
848 PCIBlankEntry\r
849 },\r
850 {\r
851 0x81,\r
852 L"Master, OM-primary",\r
853 PCIBlankEntry\r
854 },\r
855 {\r
856 0x82,\r
857 L"Master, PI-primary",\r
858 PCIBlankEntry\r
859 },\r
860 {\r
861 0x83,\r
862 L"Master, OM/PI-primary",\r
863 PCIBlankEntry\r
864 },\r
865 {\r
866 0x84,\r
867 L"Master, OM-secondary",\r
868 PCIBlankEntry\r
869 },\r
870 {\r
871 0x85,\r
872 L"Master, OM-primary, OM-secondary",\r
873 PCIBlankEntry\r
874 },\r
875 {\r
876 0x86,\r
877 L"Master, PI-primary, OM-secondary",\r
878 PCIBlankEntry\r
879 },\r
880 {\r
881 0x87,\r
882 L"Master, OM/PI-primary, OM-secondary",\r
883 PCIBlankEntry\r
884 },\r
885 {\r
886 0x88,\r
887 L"Master, OM-secondary",\r
888 PCIBlankEntry\r
889 },\r
890 {\r
891 0x89,\r
892 L"Master, OM-primary, PI-secondary",\r
893 PCIBlankEntry\r
894 },\r
895 {\r
896 0x8a,\r
897 L"Master, PI-primary, PI-secondary",\r
898 PCIBlankEntry\r
899 },\r
900 {\r
901 0x8b,\r
902 L"Master, OM/PI-primary, PI-secondary",\r
903 PCIBlankEntry\r
904 },\r
905 {\r
906 0x8c,\r
907 L"Master, OM-secondary",\r
908 PCIBlankEntry\r
909 },\r
910 {\r
911 0x8d,\r
912 L"Master, OM-primary, OM/PI-secondary",\r
913 PCIBlankEntry\r
914 },\r
915 {\r
916 0x8e,\r
917 L"Master, PI-primary, OM/PI-secondary",\r
918 PCIBlankEntry\r
919 },\r
920 {\r
921 0x8f,\r
922 L"Master, OM/PI-primary, OM/PI-secondary",\r
923 PCIBlankEntry\r
924 },\r
925 {\r
926 0x00,\r
927 NULL,\r
928 /* null string ends the list */NULL\r
929 }\r
930};\r
931\r
932PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
933 {\r
934 0x00,\r
935 L"VGA compatible",\r
936 PCIBlankEntry\r
937 },\r
938 {\r
939 0x01,\r
940 L"8514 compatible",\r
941 PCIBlankEntry\r
942 },\r
943 {\r
944 0x00,\r
945 NULL,\r
946 /* null string ends the list */NULL\r
947 }\r
948};\r
949\r
950PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
951 {\r
952 0x00,\r
953 L"",\r
954 PCIBlankEntry\r
955 },\r
956 {\r
957 0x01,\r
958 L"Subtractive decode",\r
959 PCIBlankEntry\r
960 },\r
961 {\r
962 0x00,\r
963 NULL,\r
964 /* null string ends the list */NULL\r
965 }\r
966};\r
967\r
968PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
969 {\r
970 0x00,\r
971 L"Generic XT-compatible",\r
972 PCIBlankEntry\r
973 },\r
974 {\r
975 0x01,\r
976 L"16450-compatible",\r
977 PCIBlankEntry\r
978 },\r
979 {\r
980 0x02,\r
981 L"16550-compatible",\r
982 PCIBlankEntry\r
983 },\r
984 {\r
985 0x03,\r
986 L"16650-compatible",\r
987 PCIBlankEntry\r
988 },\r
989 {\r
990 0x04,\r
991 L"16750-compatible",\r
992 PCIBlankEntry\r
993 },\r
994 {\r
995 0x05,\r
996 L"16850-compatible",\r
997 PCIBlankEntry\r
998 },\r
999 {\r
1000 0x06,\r
1001 L"16950-compatible",\r
1002 PCIBlankEntry\r
1003 },\r
1004 {\r
1005 0x00,\r
1006 NULL,\r
1007 /* null string ends the list */NULL\r
1008 }\r
1009};\r
1010\r
1011PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1012 {\r
1013 0x00,\r
1014 L"",\r
1015 PCIBlankEntry\r
1016 },\r
1017 {\r
1018 0x01,\r
1019 L"Bi-directional",\r
1020 PCIBlankEntry\r
1021 },\r
1022 {\r
1023 0x02,\r
1024 L"ECP 1.X-compliant",\r
1025 PCIBlankEntry\r
1026 },\r
1027 {\r
1028 0x03,\r
1029 L"IEEE 1284",\r
1030 PCIBlankEntry\r
1031 },\r
1032 {\r
1033 0xfe,\r
1034 L"IEEE 1284 target (not a controller)",\r
1035 PCIBlankEntry\r
1036 },\r
1037 {\r
1038 0x00,\r
1039 NULL,\r
1040 /* null string ends the list */NULL\r
1041 }\r
1042};\r
1043\r
1044PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1045 {\r
1046 0x00,\r
1047 L"Generic",\r
1048 PCIBlankEntry\r
1049 },\r
1050 {\r
1051 0x01,\r
1052 L"Hayes-compatible 16450",\r
1053 PCIBlankEntry\r
1054 },\r
1055 {\r
1056 0x02,\r
1057 L"Hayes-compatible 16550",\r
1058 PCIBlankEntry\r
1059 },\r
1060 {\r
1061 0x03,\r
1062 L"Hayes-compatible 16650",\r
1063 PCIBlankEntry\r
1064 },\r
1065 {\r
1066 0x04,\r
1067 L"Hayes-compatible 16750",\r
1068 PCIBlankEntry\r
1069 },\r
1070 {\r
1071 0x00,\r
1072 NULL,\r
1073 /* null string ends the list */NULL\r
1074 }\r
1075};\r
1076\r
1077PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1078 {\r
1079 0x00,\r
1080 L"Generic 8259",\r
1081 PCIBlankEntry\r
1082 },\r
1083 {\r
1084 0x01,\r
1085 L"ISA",\r
1086 PCIBlankEntry\r
1087 },\r
1088 {\r
1089 0x02,\r
1090 L"EISA",\r
1091 PCIBlankEntry\r
1092 },\r
1093 {\r
1094 0x10,\r
1095 L"IO APIC",\r
1096 PCIBlankEntry\r
1097 },\r
1098 {\r
1099 0x20,\r
1100 L"IO(x) APIC interrupt controller",\r
1101 PCIBlankEntry\r
1102 },\r
1103 {\r
1104 0x00,\r
1105 NULL,\r
1106 /* null string ends the list */NULL\r
1107 }\r
1108};\r
1109\r
1110PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1111 {\r
1112 0x00,\r
1113 L"Generic 8237",\r
1114 PCIBlankEntry\r
1115 },\r
1116 {\r
1117 0x01,\r
1118 L"ISA",\r
1119 PCIBlankEntry\r
1120 },\r
1121 {\r
1122 0x02,\r
1123 L"EISA",\r
1124 PCIBlankEntry\r
1125 },\r
1126 {\r
1127 0x00,\r
1128 NULL,\r
1129 /* null string ends the list */NULL\r
1130 }\r
1131};\r
1132\r
1133PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1134 {\r
1135 0x00,\r
1136 L"Generic 8254",\r
1137 PCIBlankEntry\r
1138 },\r
1139 {\r
1140 0x01,\r
1141 L"ISA",\r
1142 PCIBlankEntry\r
1143 },\r
1144 {\r
1145 0x02,\r
1146 L"EISA",\r
1147 PCIBlankEntry\r
1148 },\r
1149 {\r
1150 0x00,\r
1151 NULL,\r
1152 /* null string ends the list */NULL\r
1153 }\r
1154};\r
1155\r
1156PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1157 {\r
1158 0x00,\r
1159 L"Generic",\r
1160 PCIBlankEntry\r
1161 },\r
1162 {\r
1163 0x01,\r
1164 L"ISA",\r
1165 PCIBlankEntry\r
1166 },\r
1167 {\r
1168 0x02,\r
1169 L"EISA",\r
1170 PCIBlankEntry\r
1171 },\r
1172 {\r
1173 0x00,\r
1174 NULL,\r
1175 /* null string ends the list */NULL\r
1176 }\r
1177};\r
1178\r
1179PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1180 {\r
1181 0x00,\r
1182 L"Generic",\r
1183 PCIBlankEntry\r
1184 },\r
1185 {\r
1186 0x10,\r
1187 L"",\r
1188 PCIBlankEntry\r
1189 },\r
1190 {\r
1191 0x00,\r
1192 NULL,\r
1193 /* null string ends the list */NULL\r
1194 }\r
1195};\r
1196\r
1197PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1198 {\r
1199 0x00,\r
1200 L"Universal Host Controller spec",\r
1201 PCIBlankEntry\r
1202 },\r
1203 {\r
1204 0x10,\r
1205 L"Open Host Controller spec",\r
1206 PCIBlankEntry\r
1207 },\r
1208 {\r
1209 0x80,\r
1210 L"No specific programming interface",\r
1211 PCIBlankEntry\r
1212 },\r
1213 {\r
1214 0xfe,\r
1215 L"(Not Host Controller)",\r
1216 PCIBlankEntry\r
1217 },\r
1218 {\r
1219 0x00,\r
1220 NULL,\r
1221 /* null string ends the list */NULL\r
1222 }\r
1223};\r
1224\r
1225PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1226 {\r
1227 0x00,\r
1228 L"",\r
1229 PCIBlankEntry\r
1230 },\r
1231 {\r
1232 0x10,\r
1233 L"Using 1394 OpenHCI spec",\r
1234 PCIBlankEntry\r
1235 },\r
1236 {\r
1237 0x00,\r
1238 NULL,\r
1239 /* null string ends the list */NULL\r
1240 }\r
1241};\r
1242\r
1243PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1244 {\r
1245 0x00,\r
1246 L"Message FIFO at offset 40h",\r
1247 PCIBlankEntry\r
1248 },\r
1249 {\r
1250 0x01,\r
1251 L"",\r
1252 PCIBlankEntry\r
1253 },\r
1254 {\r
1255 0x00,\r
1256 NULL,\r
1257 /* null string ends the list */NULL\r
1258 }\r
1259};\r
1260\r
1261#define EFI_HEX_DISP_SIZE 32\r
1262BOOLEAN\r
1263PrivateDumpHex (\r
1264 IN UINTN Indent,\r
1265 IN UINTN Offset,\r
1266 IN UINTN DataSize,\r
1267 IN VOID *UserData\r
1268 )\r
1269/*++\r
1270\r
1271Routine Description:\r
1272\r
1273 Add page break feature to the DumpHex\r
1274\r
1275Arguments:\r
1276 Indent - The indent space\r
1277\r
1278 Offset - The offset\r
1279\r
1280 DataSize - The data size\r
1281\r
1282 UserData - The data\r
1283\r
1284Returns:\r
1285\r
1286 TRUE - The dump is broke\r
1287 FALSE - The dump is completed\r
1288\r
1289**/\r
1290{\r
1291 UINTN DispSize;\r
1292 UINT8 *DispData;\r
1293\r
1294 DispSize = EFI_HEX_DISP_SIZE;\r
1295 DispData = (UINT8 *) UserData;\r
1296\r
1297 while (DataSize!=0) {\r
1298 if (ShellGetExecutionBreakFlag ()) {\r
1299 return TRUE;\r
1300 }\r
1301\r
1302 if (DataSize > EFI_HEX_DISP_SIZE) {\r
1303 DataSize -= EFI_HEX_DISP_SIZE;\r
1304 } else {\r
1305 DispSize = DataSize;\r
1306 DataSize = 0;\r
1307 }\r
1308\r
1309 DumpHex (Indent, Offset + DispData - (UINT8 *) UserData, DispSize, DispData);\r
1310 DispData += DispSize;\r
1311 }\r
1312\r
1313 return FALSE;\r
1314}\r
1315\r
1316//\r
1317// Implemetations\r
1318//\r
1319VOID\r
1320PciGetClassStrings (\r
1321 IN UINT32 ClassCode,\r
1322 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1323 )\r
1324/*++\r
1325Routine Description:\r
1326\r
1327 Generates printable Unicode strings that represent PCI device class,\r
1328 subclass and programmed I/F based on a value passed to the function.\r
1329\r
1330Arguments:\r
1331\r
1332 ClassCode Value representing the PCI "Class Code" register read from a\r
1333 PCI device. The encodings are:\r
1334 bits 23:16 - Base Class Code\r
1335 bits 15:8 - Sub-Class Code\r
1336 bits 7:0 - Programming Interface\r
1337 ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
1338 printable class strings corresponding to ClassCode. The\r
1339 caller must not modify the strings that are pointed by\r
1340 the fields in ClassStrings.\r
1341Returns:\r
1342\r
1343 None\r
1344**/\r
1345{\r
1346 INTN Index;\r
1347 UINT8 Code;\r
1348 PCI_CLASS_ENTRY *CurrentClass;\r
1349\r
1350 //\r
1351 // Assume no strings found\r
1352 //\r
1353 ClassStrings->BaseClass = L"UNDEFINED";\r
1354 ClassStrings->SubClass = L"UNDEFINED";\r
1355 ClassStrings->PIFClass = L"UNDEFINED";\r
1356\r
1357 CurrentClass = gClassStringList;\r
1358 Code = (UINT8) (ClassCode >> 16);\r
1359 Index = 0;\r
1360\r
1361 //\r
1362 // Go through all entries of the base class, until the entry with a matching\r
1363 // base class code is found. If reaches an entry with a null description\r
1364 // text, the last entry is met, which means no text for the base class was\r
1365 // found, so no more action is needed.\r
1366 //\r
1367 while (Code != CurrentClass[Index].Code) {\r
1368 if (NULL == CurrentClass[Index].DescText) {\r
1369 return ;\r
1370 }\r
1371\r
1372 Index++;\r
1373 }\r
1374 //\r
1375 // A base class was found. Assign description, and check if this class has\r
1376 // sub-class defined. If sub-class defined, no more action is needed,\r
1377 // otherwise, continue to find description for the sub-class code.\r
1378 //\r
1379 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1380 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1381 return ;\r
1382 }\r
1383 //\r
1384 // find Subclass entry\r
1385 //\r
1386 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1387 Code = (UINT8) (ClassCode >> 8);\r
1388 Index = 0;\r
1389\r
1390 //\r
1391 // Go through all entries of the sub-class, until the entry with a matching\r
1392 // sub-class code is found. If reaches an entry with a null description\r
1393 // text, the last entry is met, which means no text for the sub-class was\r
1394 // found, so no more action is needed.\r
1395 //\r
1396 while (Code != CurrentClass[Index].Code) {\r
1397 if (NULL == CurrentClass[Index].DescText) {\r
1398 return ;\r
1399 }\r
1400\r
1401 Index++;\r
1402 }\r
1403 //\r
1404 // A class was found for the sub-class code. Assign description, and check if\r
1405 // this sub-class has programming interface defined. If no, no more action is\r
1406 // needed, otherwise, continue to find description for the programming\r
1407 // interface.\r
1408 //\r
1409 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1410 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1411 return ;\r
1412 }\r
1413 //\r
1414 // Find programming interface entry\r
1415 //\r
1416 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1417 Code = (UINT8) ClassCode;\r
1418 Index = 0;\r
1419\r
1420 //\r
1421 // Go through all entries of the I/F entries, until the entry with a\r
1422 // matching I/F code is found. If reaches an entry with a null description\r
1423 // text, the last entry is met, which means no text was found, so no more\r
1424 // action is needed.\r
1425 //\r
1426 while (Code != CurrentClass[Index].Code) {\r
1427 if (NULL == CurrentClass[Index].DescText) {\r
1428 return ;\r
1429 }\r
1430\r
1431 Index++;\r
1432 }\r
1433 //\r
1434 // A class was found for the I/F code. Assign description, done!\r
1435 //\r
1436 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1437 return ;\r
1438}\r
1439\r
1440VOID\r
1441PciPrintClassCode (\r
1442 IN UINT8 *ClassCodePtr,\r
1443 IN BOOLEAN IncludePIF\r
1444 )\r
1445/*++\r
1446Routine Description:\r
1447\r
1448 Print strings that represent PCI device class, subclass and programmed I/F\r
1449\r
1450Arguments:\r
1451\r
1452 ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1453 configuation space.\r
1454 IncludePIF If the printed string should include the programming I/F part\r
1455Returns:\r
1456\r
1457 None\r
1458**/\r
1459{\r
1460 UINT32 ClassCode;\r
1461 PCI_CLASS_STRINGS ClassStrings;\r
1462 CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];\r
1463\r
1464 ClassCode = 0;\r
1465 ClassCode |= ClassCodePtr[0];\r
1466 ClassCode |= (ClassCodePtr[1] << 8);\r
1467 ClassCode |= (ClassCodePtr[2] << 16);\r
1468\r
1469 //\r
1470 // Get name from class code\r
1471 //\r
1472 PciGetClassStrings (ClassCode, &ClassStrings);\r
1473\r
1474 if (IncludePIF) {\r
1475 //\r
1476 // Only print base class and sub class name\r
1477 //\r
1478 ShellPrintEx(-1,-1, L"%s - %s - %s",\r
1479 ClassStrings.BaseClass,\r
1480 ClassStrings.SubClass,\r
1481 ClassStrings.PIFClass\r
1482 );\r
1483\r
1484 } else {\r
1485 //\r
1486 // Print base class, sub class, and programming inferface name\r
1487 //\r
1488 UnicodeSPrint (\r
1489 OutputString,\r
1490 PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),\r
1491 L"%s - %s",\r
1492 ClassStrings.BaseClass,\r
1493 ClassStrings.SubClass\r
1494 );\r
1495\r
1496 OutputString[PCI_CLASS_STRING_LIMIT] = 0;\r
1497 ShellPrintEx(-1,-1, L"%s", OutputString);\r
1498 }\r
1499}\r
1500\r
1501EFI_STATUS\r
1502PciDump (\r
1503 IN EFI_HANDLE ImageHandle,\r
1504 IN EFI_SYSTEM_TABLE *SystemTable\r
1505 );\r
1506\r
1507EFI_STATUS\r
1508PciFindProtocolInterface (\r
1509 IN EFI_HANDLE *HandleBuf,\r
1510 IN UINTN HandleCount,\r
1511 IN UINT16 Segment,\r
1512 IN UINT16 Bus,\r
1513 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1514 );\r
1515\r
1516EFI_STATUS\r
1517PciGetProtocolAndResource (\r
1518 IN EFI_HANDLE Handle,\r
1519 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1520 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1521 );\r
1522\r
1523EFI_STATUS\r
1524PciGetNextBusRange (\r
1525 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1526 OUT UINT16 *MinBus,\r
1527 OUT UINT16 *MaxBus,\r
1528 OUT BOOLEAN *IsEnd\r
1529 );\r
1530\r
1531EFI_STATUS\r
1532PciExplainData (\r
1533 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1534 IN UINT64 Address,\r
1535 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1536 );\r
1537\r
1538EFI_STATUS\r
1539PciExplainDeviceData (\r
1540 IN PCI_DEVICE_HEADER *Device,\r
1541 IN UINT64 Address,\r
1542 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1543 );\r
1544\r
1545EFI_STATUS\r
1546PciExplainBridgeData (\r
1547 IN PCI_BRIDGE_HEADER *Bridge,\r
1548 IN UINT64 Address,\r
1549 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1550 );\r
1551\r
1552EFI_STATUS\r
1553PciExplainBar (\r
1554 IN UINT32 *Bar,\r
1555 IN UINT16 *Command,\r
1556 IN UINT64 Address,\r
1557 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1558 IN OUT UINTN *Index\r
1559 );\r
1560\r
1561EFI_STATUS\r
1562PciExplainCardBusData (\r
1563 IN PCI_CARDBUS_HEADER *CardBus,\r
1564 IN UINT64 Address,\r
1565 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1566 );\r
1567\r
1568EFI_STATUS\r
1569PciExplainStatus (\r
1570 IN UINT16 *Status,\r
1571 IN BOOLEAN MainStatus,\r
1572 IN PCI_HEADER_TYPE HeaderType\r
1573 );\r
1574\r
1575EFI_STATUS\r
1576PciExplainCommand (\r
1577 IN UINT16 *Command\r
1578 );\r
1579\r
1580EFI_STATUS\r
1581PciExplainBridgeControl (\r
1582 IN UINT16 *BridgeControl,\r
1583 IN PCI_HEADER_TYPE HeaderType\r
1584 );\r
1585\r
1586EFI_STATUS\r
1587PciExplainCapabilityStruct (\r
1588 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1589 IN UINT64 Address,\r
1590 IN UINT8 CapPtr\r
1591 );\r
1592\r
1593EFI_STATUS\r
1594PciExplainPciExpress (\r
1595 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1596 IN UINT64 Address,\r
1597 IN UINT8 CapabilityPtr\r
1598 );\r
1599\r
1600EFI_STATUS\r
1601ExplainPcieCapReg (\r
1602 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1603);\r
1604\r
1605EFI_STATUS\r
1606ExplainPcieDeviceCap (\r
1607 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1608);\r
1609\r
1610EFI_STATUS\r
1611ExplainPcieDeviceControl (\r
1612 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1613);\r
1614\r
1615EFI_STATUS\r
1616ExplainPcieDeviceStatus (\r
1617 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1618);\r
1619\r
1620EFI_STATUS\r
1621ExplainPcieLinkCap (\r
1622 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1623);\r
1624\r
1625EFI_STATUS\r
1626ExplainPcieLinkControl (\r
1627 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1628);\r
1629\r
1630EFI_STATUS\r
1631ExplainPcieLinkStatus (\r
1632 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1633);\r
1634\r
1635EFI_STATUS\r
1636ExplainPcieSlotCap (\r
1637 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1638);\r
1639\r
1640EFI_STATUS\r
1641ExplainPcieSlotControl (\r
1642 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1643);\r
1644\r
1645EFI_STATUS\r
1646ExplainPcieSlotStatus (\r
1647 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1648);\r
1649\r
1650EFI_STATUS\r
1651ExplainPcieRootControl (\r
1652 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1653);\r
1654\r
1655EFI_STATUS\r
1656ExplainPcieRootCap (\r
1657 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1658);\r
1659\r
1660EFI_STATUS\r
1661ExplainPcieRootStatus (\r
1662 IN PCIE_CAP_STURCTURE *PciExpressCap\r
1663);\r
1664\r
1665typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1666\r
1667typedef enum {\r
1668 FieldWidthUINT8,\r
1669 FieldWidthUINT16,\r
1670 FieldWidthUINT32\r
1671} PCIE_CAPREG_FIELD_WIDTH;\r
1672\r
1673typedef enum {\r
1674 PcieExplainTypeCommon,\r
1675 PcieExplainTypeDevice,\r
1676 PcieExplainTypeLink,\r
1677 PcieExplainTypeSlot,\r
1678 PcieExplainTypeRoot,\r
1679 PcieExplainTypeMax\r
1680} PCIE_EXPLAIN_TYPE;\r
1681\r
1682typedef struct\r
1683{\r
1684 UINT16 Token;\r
1685 UINTN Offset;\r
1686 PCIE_CAPREG_FIELD_WIDTH Width;\r
1687 PCIE_EXPLAIN_FUNCTION Func;\r
1688 PCIE_EXPLAIN_TYPE Type;\r
1689} PCIE_EXPLAIN_STRUCT;\r
1690\r
1691PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1692 {\r
1693 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1694 0x00,\r
1695 FieldWidthUINT8,\r
1696 NULL,\r
1697 PcieExplainTypeCommon\r
1698 },\r
1699 {\r
1700 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1701 0x01,\r
1702 FieldWidthUINT8,\r
1703 NULL,\r
1704 PcieExplainTypeCommon\r
1705 },\r
1706 {\r
1707 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1708 0x02,\r
1709 FieldWidthUINT16,\r
1710 ExplainPcieCapReg,\r
1711 PcieExplainTypeCommon\r
1712 },\r
1713 {\r
1714 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1715 0x04,\r
1716 FieldWidthUINT32,\r
1717 ExplainPcieDeviceCap,\r
1718 PcieExplainTypeDevice\r
1719 },\r
1720 {\r
1721 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1722 0x08,\r
1723 FieldWidthUINT16,\r
1724 ExplainPcieDeviceControl,\r
1725 PcieExplainTypeDevice\r
1726 },\r
1727 {\r
1728 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1729 0x0a,\r
1730 FieldWidthUINT16,\r
1731 ExplainPcieDeviceStatus,\r
1732 PcieExplainTypeDevice\r
1733 },\r
1734 {\r
1735 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1736 0x0c,\r
1737 FieldWidthUINT32,\r
1738 ExplainPcieLinkCap,\r
1739 PcieExplainTypeLink\r
1740 },\r
1741 {\r
1742 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1743 0x10,\r
1744 FieldWidthUINT16,\r
1745 ExplainPcieLinkControl,\r
1746 PcieExplainTypeLink\r
1747 },\r
1748 {\r
1749 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1750 0x12,\r
1751 FieldWidthUINT16,\r
1752 ExplainPcieLinkStatus,\r
1753 PcieExplainTypeLink\r
1754 },\r
1755 {\r
1756 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1757 0x14,\r
1758 FieldWidthUINT32,\r
1759 ExplainPcieSlotCap,\r
1760 PcieExplainTypeSlot\r
1761 },\r
1762 {\r
1763 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1764 0x18,\r
1765 FieldWidthUINT16,\r
1766 ExplainPcieSlotControl,\r
1767 PcieExplainTypeSlot\r
1768 },\r
1769 {\r
1770 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1771 0x1a,\r
1772 FieldWidthUINT16,\r
1773 ExplainPcieSlotStatus,\r
1774 PcieExplainTypeSlot\r
1775 },\r
1776 {\r
1777 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1778 0x1c,\r
1779 FieldWidthUINT16,\r
1780 ExplainPcieRootControl,\r
1781 PcieExplainTypeRoot\r
1782 },\r
1783 {\r
1784 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1785 0x1e,\r
1786 FieldWidthUINT16,\r
1787 ExplainPcieRootCap,\r
1788 PcieExplainTypeRoot\r
1789 },\r
1790 {\r
1791 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1792 0x20,\r
1793 FieldWidthUINT32,\r
1794 ExplainPcieRootStatus,\r
1795 PcieExplainTypeRoot\r
1796 },\r
1797 {\r
1798 0,\r
1799 0,\r
1800 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1801 NULL,\r
1802 PcieExplainTypeMax\r
1803 }\r
1804};\r
1805\r
1806//\r
1807// Global Variables\r
1808//\r
1809PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1810STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1811 {L"-s", TypeValue},\r
1812 {L"-i", TypeFlag},\r
1813 {NULL, TypeMax}\r
1814 };\r
1815\r
1816CHAR16 *DevicePortTypeTable[] = {\r
1817 L"PCI Express Endpoint",\r
1818 L"Legacy PCI Express Endpoint",\r
1819 L"Unknown Type",\r
1820 L"Unknonw Type",\r
1821 L"Root Port of PCI Express Root Complex",\r
1822 L"Upstream Port of PCI Express Switch",\r
1823 L"Downstream Port of PCI Express Switch",\r
1824 L"PCI Express to PCI/PCI-X Bridge",\r
1825 L"PCI/PCI-X to PCI Express Bridge",\r
1826 L"Root Complex Integrated Endpoint",\r
1827 L"Root Complex Event Collector"\r
1828};\r
1829\r
1830CHAR16 *L0sLatencyStrTable[] = {\r
1831 L"Less than 64ns",\r
1832 L"64ns to less than 128ns",\r
1833 L"128ns to less than 256ns",\r
1834 L"256ns to less than 512ns",\r
1835 L"512ns to less than 1us",\r
1836 L"1us to less than 2us",\r
1837 L"2us-4us",\r
1838 L"More than 4us"\r
1839};\r
1840\r
1841CHAR16 *L1LatencyStrTable[] = {\r
1842 L"Less than 1us",\r
1843 L"1us to less than 2us",\r
1844 L"2us to less than 4us",\r
1845 L"4us to less than 8us",\r
1846 L"8us to less than 16us",\r
1847 L"16us to less than 32us",\r
1848 L"32us-64us",\r
1849 L"More than 64us"\r
1850};\r
1851\r
1852CHAR16 *ASPMCtrlStrTable[] = {\r
1853 L"Disabled",\r
1854 L"L0s Entry Enabled",\r
1855 L"L1 Entry Enabled",\r
1856 L"L0s and L1 Entry Enabled"\r
1857};\r
1858\r
1859CHAR16 *SlotPwrLmtScaleTable[] = {\r
1860 L"1.0x",\r
1861 L"0.1x",\r
1862 L"0.01x",\r
1863 L"0.001x"\r
1864};\r
1865\r
1866CHAR16 *IndicatorTable[] = {\r
1867 L"Reserved",\r
1868 L"On",\r
1869 L"Blink",\r
1870 L"Off"\r
1871};\r
1872\r
1873\r
1874SHELL_STATUS\r
1875EFIAPI\r
1876ShellCommandRunPci (\r
1877 IN EFI_HANDLE ImageHandle,\r
1878 IN EFI_SYSTEM_TABLE *SystemTable\r
1879 )\r
1880{\r
1881 UINT16 Segment;\r
1882 UINT16 Bus;\r
1883 UINT16 Device;\r
1884 UINT16 Func;\r
1885 UINT64 Address;\r
1886 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
1887 EFI_STATUS Status;\r
1888 PCI_COMMON_HEADER PciHeader;\r
1889 PCI_CONFIG_SPACE ConfigSpace;\r
1890 UINTN ScreenCount;\r
1891 UINTN TempColumn;\r
1892 UINTN ScreenSize;\r
1893 BOOLEAN ExplainData;\r
1894 UINTN Index;\r
1895 UINTN SizeOfHeader;\r
1896 BOOLEAN PrintTitle;\r
1897 UINTN HandleBufSize;\r
1898 EFI_HANDLE *HandleBuf;\r
1899 UINTN HandleCount;\r
1900 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
1901 UINT16 MinBus;\r
1902 UINT16 MaxBus;\r
1903 BOOLEAN IsEnd;\r
1904 LIST_ENTRY *Package;\r
1905 CHAR16 *ProblemParam;\r
1906 SHELL_STATUS ShellStatus;\r
1907 UINTN Size;\r
1908 CONST CHAR16 *Temp;\r
1909\r
1910 ShellStatus = SHELL_SUCCESS;\r
1911 Status = EFI_SUCCESS;\r
1912 Address = 0;\r
1913 Size = 0;\r
1914 IoDev = NULL;\r
1915 HandleBuf = NULL;\r
1916 Package = NULL;\r
1917\r
1918 //\r
1919 // initialize the shell lib (we must be in non-auto-init...)\r
1920 //\r
1921 Status = ShellInitialize();\r
1922 ASSERT_EFI_ERROR(Status);\r
1923\r
1924 Status = CommandInit();\r
1925 ASSERT_EFI_ERROR(Status);\r
1926\r
1927 //\r
1928 // parse the command line\r
1929 //\r
1930 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
1931 if (EFI_ERROR(Status)) {\r
1932 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
1933 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
1934 FreePool(ProblemParam);\r
1935 ShellStatus = SHELL_INVALID_PARAMETER;\r
1936 } else {\r
1937 ASSERT(FALSE);\r
1938 }\r
1939 } else {\r
1940\r
1941\r
1942 //\r
1943 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
1944 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
1945 // space for handles and call it again.\r
1946 //\r
1947 HandleBufSize = sizeof (EFI_HANDLE);\r
1948 HandleBuf = (EFI_HANDLE *) AllocatePool (HandleBufSize);\r
1949 if (HandleBuf == NULL) {\r
1950 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
1951 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
1952 goto Done;\r
1953 }\r
1954\r
1955 Status = gBS->LocateHandle (\r
1956 ByProtocol,\r
1957 &gEfiPciRootBridgeIoProtocolGuid,\r
1958 NULL,\r
1959 &HandleBufSize,\r
1960 HandleBuf\r
1961 );\r
1962\r
1963 if (Status == EFI_BUFFER_TOO_SMALL) {\r
1964 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
1965 if (HandleBuf == NULL) {\r
1966 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
1967 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
1968 goto Done;\r
1969 }\r
1970\r
1971 Status = gBS->LocateHandle (\r
1972 ByProtocol,\r
1973 &gEfiPciRootBridgeIoProtocolGuid,\r
1974 NULL,\r
1975 &HandleBufSize,\r
1976 HandleBuf\r
1977 );\r
1978 }\r
1979\r
1980 if (EFI_ERROR (Status)) {\r
1981 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
1982 ShellStatus = SHELL_NOT_FOUND;\r
1983 goto Done;\r
1984 }\r
1985\r
1986 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
1987 //\r
1988 // Argument Count == 1(no other argument): enumerate all pci functions\r
1989 //\r
1990 if (ShellCommandLineGetCount(Package) == 0) {\r
1991 gST->ConOut->QueryMode (\r
1992 gST->ConOut,\r
1993 gST->ConOut->Mode->Mode,\r
1994 &TempColumn,\r
1995 &ScreenSize\r
1996 );\r
1997\r
1998 ScreenCount = 0;\r
1999 ScreenSize -= 4;\r
2000 if ((ScreenSize & 1) == 1) {\r
2001 ScreenSize -= 1;\r
2002 }\r
2003\r
2004 PrintTitle = TRUE;\r
2005\r
2006 //\r
2007 // For each handle, which decides a segment and a bus number range,\r
2008 // enumerate all devices on it.\r
2009 //\r
2010 for (Index = 0; Index < HandleCount; Index++) {\r
2011 Status = PciGetProtocolAndResource (\r
2012 HandleBuf[Index],\r
2013 &IoDev,\r
2014 &Descriptors\r
2015 );\r
2016 if (EFI_ERROR (Status)) {\r
2017 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2018 ShellStatus = SHELL_NOT_FOUND;\r
2019 goto Done;\r
2020 }\r
2021 //\r
2022 // No document say it's impossible for a RootBridgeIo protocol handle\r
2023 // to have more than one address space descriptors, so find out every\r
2024 // bus range and for each of them do device enumeration.\r
2025 //\r
2026 while (TRUE) {\r
2027 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2028\r
2029 if (EFI_ERROR (Status)) {\r
2030 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2031 ShellStatus = SHELL_NOT_FOUND;\r
2032 goto Done;\r
2033 }\r
2034\r
2035 if (IsEnd) {\r
2036 break;\r
2037 }\r
2038\r
2039 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2040 //\r
2041 // For each devices, enumerate all functions it contains\r
2042 //\r
2043 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2044 //\r
2045 // For each function, read its configuration space and print summary\r
2046 //\r
2047 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2048 if (ShellGetExecutionBreakFlag ()) {\r
2049 ShellStatus = SHELL_ABORTED;\r
2050 goto Done;\r
2051 }\r
2052 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2053 IoDev->Pci.Read (\r
2054 IoDev,\r
2055 EfiPciWidthUint16,\r
2056 Address,\r
2057 1,\r
2058 &PciHeader.VendorId\r
2059 );\r
2060\r
2061 //\r
2062 // If VendorId = 0xffff, there does not exist a device at this\r
2063 // location. For each device, if there is any function on it,\r
2064 // there must be 1 function at Function 0. So if Func = 0, there\r
2065 // will be no more functions in the same device, so we can break\r
2066 // loop to deal with the next device.\r
2067 //\r
2068 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2069 break;\r
2070 }\r
2071\r
2072 if (PciHeader.VendorId != 0xffff) {\r
2073\r
2074 if (PrintTitle) {\r
2075 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2076 PrintTitle = FALSE;\r
2077 }\r
2078\r
2079 IoDev->Pci.Read (\r
2080 IoDev,\r
2081 EfiPciWidthUint32,\r
2082 Address,\r
2083 sizeof (PciHeader) / sizeof (UINT32),\r
2084 &PciHeader\r
2085 );\r
2086\r
2087 ShellPrintHiiEx(\r
2088 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2089 IoDev->SegmentNumber,\r
2090 Bus,\r
2091 Device,\r
2092 Func\r
2093 );\r
2094\r
2095 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2096 ShellPrintHiiEx(\r
2097 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2098 PciHeader.VendorId,\r
2099 PciHeader.DeviceId,\r
2100 PciHeader.ClassCode[0]\r
2101 );\r
2102\r
2103 ScreenCount += 2;\r
2104 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2105 //\r
2106 // If ScreenSize == 0 we have the console redirected so don't\r
2107 // block updates\r
2108 //\r
2109 ScreenCount = 0;\r
2110 }\r
2111 //\r
2112 // If this is not a multi-function device, we can leave the loop\r
2113 // to deal with the next device.\r
2114 //\r
2115 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2116 break;\r
2117 }\r
2118 }\r
2119 }\r
2120 }\r
2121 }\r
2122 //\r
2123 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2124 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2125 // devices on all bus, we can leave loop.\r
2126 //\r
2127 if (Descriptors == NULL) {\r
2128 break;\r
2129 }\r
2130 }\r
2131 }\r
2132\r
2133 Status = EFI_SUCCESS;\r
2134 goto Done;\r
2135 }\r
2136\r
2137 if (ShellCommandLineGetCount(Package) == 1) {\r
2138 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
2139 ShellStatus = SHELL_INVALID_PARAMETER;\r
2140 goto Done;\r
2141 }\r
2142 //\r
2143 // Arg count >= 3, dump binary of specified function, interpret if necessary\r
2144 //\r
2145 if (ShellCommandLineGetCount(Package) > 3) {\r
2146 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
2147 ShellStatus = SHELL_INVALID_PARAMETER;\r
2148 goto Done;\r
2149 }\r
2150\r
2151 ExplainData = FALSE;\r
2152 Segment = 0;\r
2153 Bus = 0;\r
2154 Device = 0;\r
2155 Func = 0;\r
2156 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2157 ExplainData = TRUE;\r
2158 }\r
2159\r
2160 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2161 if (Temp != NULL) {\r
2162 Segment = (UINT16) StrHexToUintn (Temp);\r
2163 }\r
2164\r
2165 //\r
2166 // The first Argument(except "-i") is assumed to be Bus number, second\r
2167 // to be Device number, and third to be Func number.\r
2168 //\r
2169 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2170 if (Temp != NULL) {\r
2171 Bus = (UINT16)StrHexToUintn(Temp);\r
2172 if (Bus > MAX_BUS_NUMBER) {\r
2173 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2174 ShellStatus = SHELL_INVALID_PARAMETER;\r
2175 goto Done;\r
2176 }\r
2177 }\r
2178 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2179 if (Temp != NULL) {\r
2180 Device = (UINT16) StrHexToUintn(Temp);\r
2181 if (Device > MAX_DEVICE_NUMBER){\r
2182 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2183 ShellStatus = SHELL_INVALID_PARAMETER;\r
2184 goto Done;\r
2185 }\r
2186 }\r
2187\r
2188 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2189 if (Temp != NULL) {\r
2190 Func = (UINT16) StrHexToUintn(Temp);\r
2191 if (Func > MAX_FUNCTION_NUMBER){\r
2192 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2193 ShellStatus = SHELL_INVALID_PARAMETER;\r
2194 goto Done;\r
2195 }\r
2196 }\r
2197\r
2198 //\r
2199 // Find the protocol interface who's in charge of current segment, and its\r
2200 // bus range covers the current bus\r
2201 //\r
2202 Status = PciFindProtocolInterface (\r
2203 HandleBuf,\r
2204 HandleCount,\r
2205 Segment,\r
2206 Bus,\r
2207 &IoDev\r
2208 );\r
2209\r
2210 if (EFI_ERROR (Status)) {\r
2211 ShellPrintHiiEx(\r
2212 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
2213 gShellDebug1HiiHandle,\r
2214 Segment,\r
2215 Bus\r
2216 );\r
2217 ShellStatus = SHELL_NOT_FOUND;\r
2218 goto Done;\r
2219 }\r
2220\r
2221 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2222 Status = IoDev->Pci.Read (\r
2223 IoDev,\r
2224 EfiPciWidthUint8,\r
2225 Address,\r
2226 sizeof (ConfigSpace),\r
2227 &ConfigSpace\r
2228 );\r
2229\r
2230 if (EFI_ERROR (Status)) {\r
2231 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2232 ShellStatus = SHELL_ACCESS_DENIED;\r
2233 goto Done;\r
2234 }\r
2235\r
2236 mConfigSpace = &ConfigSpace;\r
2237 ShellPrintHiiEx(\r
2238 -1,\r
2239 -1,\r
2240 NULL,\r
2241 STRING_TOKEN (STR_PCI_INFO),\r
2242 gShellDebug1HiiHandle,\r
2243 Segment,\r
2244 Bus,\r
2245 Device,\r
2246 Func,\r
2247 Segment,\r
2248 Bus,\r
2249 Device,\r
2250 Func\r
2251 );\r
2252\r
2253 //\r
2254 // Dump standard header of configuration space\r
2255 //\r
2256 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2257\r
2258 PrivateDumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
2259 ShellPrintEx(-1,-1, L"\r\n");\r
2260\r
2261 //\r
2262 // Dump device dependent Part of configuration space\r
2263 //\r
2264 PrivateDumpHex (\r
2265 2,\r
2266 SizeOfHeader,\r
2267 sizeof (ConfigSpace) - SizeOfHeader,\r
2268 ConfigSpace.Data\r
2269 );\r
2270\r
2271 //\r
2272 // If "-i" appears in command line, interpret data in configuration space\r
2273 //\r
2274 if (ExplainData) {\r
2275 Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
2276 }\r
2277 }\r
2278Done:\r
2279 if (HandleBuf != NULL) {\r
2280 FreePool (HandleBuf);\r
2281 }\r
2282 if (Package != NULL) {\r
2283 ShellCommandLineFreeVarList (Package);\r
2284 }\r
2285 mConfigSpace = NULL;\r
2286 return ShellStatus;\r
2287}\r
2288\r
2289EFI_STATUS\r
2290PciFindProtocolInterface (\r
2291 IN EFI_HANDLE *HandleBuf,\r
2292 IN UINTN HandleCount,\r
2293 IN UINT16 Segment,\r
2294 IN UINT16 Bus,\r
2295 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2296 )\r
2297/*++\r
2298\r
2299Routine Description:\r
2300\r
2301 This function finds out the protocol which is in charge of the given\r
2302 segment, and its bus range covers the current bus number. It lookes\r
2303 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2304 criteria is found.\r
2305\r
2306Arguments:\r
2307\r
2308 HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
2309 HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles\r
2310 Segment Segment number of device we are dealing with\r
2311 Bus Bus number of device we are dealing with\r
2312 IoDev Handle used to access configuration space of PCI device\r
2313\r
2314Returns:\r
2315\r
2316 EFI_SUCCESS - The command completed successfully\r
2317 EFI_INVALID_PARAMETER - Invalid parameter\r
2318\r
2319**/\r
2320{\r
2321 UINTN Index;\r
2322 EFI_STATUS Status;\r
2323 BOOLEAN FoundInterface;\r
2324 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2325 UINT16 MinBus;\r
2326 UINT16 MaxBus;\r
2327 BOOLEAN IsEnd;\r
2328\r
2329 FoundInterface = FALSE;\r
2330 //\r
2331 // Go through all handles, until the one meets the criteria is found\r
2332 //\r
2333 for (Index = 0; Index < HandleCount; Index++) {\r
2334 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2335 if (EFI_ERROR (Status)) {\r
2336 return Status;\r
2337 }\r
2338 //\r
2339 // When Descriptors == NULL, the Configuration() is not implemented,\r
2340 // so we only check the Segment number\r
2341 //\r
2342 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2343 return EFI_SUCCESS;\r
2344 }\r
2345\r
2346 if ((*IoDev)->SegmentNumber != Segment) {\r
2347 continue;\r
2348 }\r
2349\r
2350 while (TRUE) {\r
2351 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2352 if (EFI_ERROR (Status)) {\r
2353 return Status;\r
2354 }\r
2355\r
2356 if (IsEnd) {\r
2357 break;\r
2358 }\r
2359\r
2360 if (MinBus <= Bus && MaxBus >= Bus) {\r
2361 FoundInterface = TRUE;\r
2362 break;\r
2363 }\r
2364 }\r
2365 }\r
2366\r
2367 if (FoundInterface) {\r
2368 return EFI_SUCCESS;\r
2369 } else {\r
2370 return EFI_INVALID_PARAMETER;\r
2371 }\r
2372}\r
2373\r
2374EFI_STATUS\r
2375PciGetProtocolAndResource (\r
2376 IN EFI_HANDLE Handle,\r
2377 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2378 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2379 )\r
2380/*++\r
2381\r
2382Routine Description:\r
2383\r
2384 This function gets the protocol interface from the given handle, and\r
2385 obtains its address space descriptors.\r
2386\r
2387Arguments:\r
2388\r
2389 Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle\r
2390 IoDev Handle used to access configuration space of PCI device\r
2391 Descriptors Points to the address space descriptors\r
2392\r
2393Returns:\r
2394\r
2395 EFI_SUCCESS The command completed successfully\r
2396\r
2397**/\r
2398{\r
2399 EFI_STATUS Status;\r
2400\r
2401 //\r
2402 // Get inferface from protocol\r
2403 //\r
2404 Status = gBS->HandleProtocol (\r
2405 Handle,\r
2406 &gEfiPciRootBridgeIoProtocolGuid,\r
2407 (VOID**)IoDev\r
2408 );\r
2409\r
2410 if (EFI_ERROR (Status)) {\r
2411 return Status;\r
2412 }\r
2413 //\r
2414 // Call Configuration() to get address space descriptors\r
2415 //\r
2416 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2417 if (Status == EFI_UNSUPPORTED) {\r
2418 *Descriptors = NULL;\r
2419 return EFI_SUCCESS;\r
2420\r
2421 } else {\r
2422 return Status;\r
2423 }\r
2424}\r
2425\r
2426EFI_STATUS\r
2427PciGetNextBusRange (\r
2428 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2429 OUT UINT16 *MinBus,\r
2430 OUT UINT16 *MaxBus,\r
2431 OUT BOOLEAN *IsEnd\r
2432 )\r
2433/*++\r
2434\r
2435Routine Description:\r
2436\r
2437 This function get the next bus range of given address space descriptors.\r
2438 It also moves the pointer backward a node, to get prepared to be called\r
2439 again.\r
2440\r
2441Arguments:\r
2442\r
2443 Descriptors points to current position of a serial of address space\r
2444 descriptors\r
2445 MinBus The lower range of bus number\r
2446 ManBus The upper range of bus number\r
2447 IsEnd Meet end of the serial of descriptors\r
2448\r
2449Returns:\r
2450\r
2451 EFI_SUCCESS The command completed successfully\r
2452\r
2453**/\r
2454{\r
2455 *IsEnd = FALSE;\r
2456\r
2457 //\r
2458 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2459 // range is 0~PCI_MAX_BUS\r
2460 //\r
2461 if ((*Descriptors) == NULL) {\r
2462 *MinBus = 0;\r
2463 *MaxBus = PCI_MAX_BUS;\r
2464 return EFI_SUCCESS;\r
2465 }\r
2466 //\r
2467 // *Descriptors points to one or more address space descriptors, which\r
2468 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2469 // if a bus typed one is found and its bus range covers bus, this handle\r
2470 // is the handle we are looking for.\r
2471 //\r
2472 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2473 *IsEnd = TRUE;\r
2474 }\r
2475\r
2476 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2477 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2478 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2479 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2480 (*Descriptors)++;\r
2481 break;\r
2482 }\r
2483\r
2484 (*Descriptors)++;\r
2485 }\r
2486\r
2487 return EFI_SUCCESS;\r
2488}\r
2489\r
2490EFI_STATUS\r
2491PciExplainData (\r
2492 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2493 IN UINT64 Address,\r
2494 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2495 )\r
2496/*++\r
2497\r
2498Routine Description:\r
2499\r
2500 Explain the data in PCI configuration space. The part which is common for\r
2501 PCI device and bridge is interpreted in this function. It calls other\r
2502 functions to interpret data unique for device or bridge.\r
2503\r
2504Arguments:\r
2505\r
2506 ConfigSpace Data in PCI configuration space\r
2507 Address Address used to access configuration space of this PCI device\r
2508 IoDev Handle used to access configuration space of PCI device\r
2509\r
2510Returns:\r
2511\r
2512 EFI_SUCCESS The command completed successfully\r
2513\r
2514**/\r
2515{\r
2516 PCI_COMMON_HEADER *Common;\r
2517 PCI_HEADER_TYPE HeaderType;\r
2518 EFI_STATUS Status;\r
2519 UINT8 CapPtr;\r
2520\r
2521 Common = &(ConfigSpace->Common);\r
2522\r
2523 Print (L"\n");\r
2524\r
2525 //\r
2526 // Print Vendor Id and Device Id\r
2527 //\r
2528 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2529 INDEX_OF (&(Common->VendorId)),\r
2530 Common->VendorId,\r
2531 INDEX_OF (&(Common->DeviceId)),\r
2532 Common->DeviceId\r
2533 );\r
2534\r
2535 //\r
2536 // Print register Command\r
2537 //\r
2538 PciExplainCommand (&(Common->Command));\r
2539\r
2540 //\r
2541 // Print register Status\r
2542 //\r
2543 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2544\r
2545 //\r
2546 // Print register Revision ID\r
2547 //\r
2548 ShellPrintEx(-1, -1, L"/r/n");\r
2549 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2550 INDEX_OF (&(Common->RevisionId)),\r
2551 Common->RevisionId\r
2552 );\r
2553\r
2554 //\r
2555 // Print register BIST\r
2556 //\r
2557 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->BIST)));\r
2558 if ((Common->BIST & PCI_BIT_7) != 0) {\r
2559 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->BIST);\r
2560 } else {\r
2561 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2562 }\r
2563 //\r
2564 // Print register Cache Line Size\r
2565 //\r
2566 ShellPrintHiiEx(-1, -1, NULL,\r
2567 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2568 gShellDebug1HiiHandle,\r
2569 INDEX_OF (&(Common->CacheLineSize)),\r
2570 Common->CacheLineSize\r
2571 );\r
2572\r
2573 //\r
2574 // Print register Latency Timer\r
2575 //\r
2576 ShellPrintHiiEx(-1, -1, NULL,\r
2577 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2578 gShellDebug1HiiHandle,\r
2579 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2580 Common->PrimaryLatencyTimer\r
2581 );\r
2582\r
2583 //\r
2584 // Print register Header Type\r
2585 //\r
2586 ShellPrintHiiEx(-1, -1, NULL,\r
2587 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2588 gShellDebug1HiiHandle,\r
2589 INDEX_OF (&(Common->HeaderType)),\r
2590 Common->HeaderType\r
2591 );\r
2592\r
2593 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2594 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2595\r
2596 } else {\r
2597 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2598 }\r
2599\r
2600 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2601 switch (HeaderType) {\r
2602 case PciDevice:\r
2603 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2604 break;\r
2605\r
2606 case PciP2pBridge:\r
2607 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2608 break;\r
2609\r
2610 case PciCardBusBridge:\r
2611 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2612 break;\r
2613\r
2614 default:\r
2615 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2616 HeaderType = PciUndefined;\r
2617 }\r
2618\r
2619 //\r
2620 // Print register Class Code\r
2621 //\r
2622 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2623 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
2624 Print (L"\n");\r
2625\r
2626 if (ShellGetExecutionBreakFlag()) {\r
2627 return EFI_SUCCESS;\r
2628 }\r
2629\r
2630 //\r
2631 // Interpret remaining part of PCI configuration header depending on\r
2632 // HeaderType\r
2633 //\r
2634 CapPtr = 0;\r
2635 Status = EFI_SUCCESS;\r
2636 switch (HeaderType) {\r
2637 case PciDevice:\r
2638 Status = PciExplainDeviceData (\r
2639 &(ConfigSpace->NonCommon.Device),\r
2640 Address,\r
2641 IoDev\r
2642 );\r
2643 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2644 break;\r
2645\r
2646 case PciP2pBridge:\r
2647 Status = PciExplainBridgeData (\r
2648 &(ConfigSpace->NonCommon.Bridge),\r
2649 Address,\r
2650 IoDev\r
2651 );\r
2652 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2653 break;\r
2654\r
2655 case PciCardBusBridge:\r
2656 Status = PciExplainCardBusData (\r
2657 &(ConfigSpace->NonCommon.CardBus),\r
2658 Address,\r
2659 IoDev\r
2660 );\r
2661 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2662 break;\r
2663 }\r
2664 //\r
2665 // If Status bit4 is 1, dump or explain capability structure\r
2666 //\r
2667 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
2668 PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
2669 }\r
2670\r
2671 return Status;\r
2672}\r
2673\r
2674EFI_STATUS\r
2675PciExplainDeviceData (\r
2676 IN PCI_DEVICE_HEADER *Device,\r
2677 IN UINT64 Address,\r
2678 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2679 )\r
2680/*++\r
2681\r
2682Routine Description:\r
2683\r
2684 Explain the device specific part of data in PCI configuration space.\r
2685\r
2686Arguments:\r
2687\r
2688 Device Data in PCI configuration space\r
2689 Address Address used to access configuration space of this PCI device\r
2690 IoDev Handle used to access configuration space of PCI device\r
2691\r
2692Returns:\r
2693\r
2694 EFI_SUCCESS The command completed successfully\r
2695\r
2696**/\r
2697{\r
2698 UINTN Index;\r
2699 BOOLEAN BarExist;\r
2700 EFI_STATUS Status;\r
2701 UINTN BarCount;\r
2702\r
2703 //\r
2704 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2705 // exist. If these no Bar for this function, print "none", otherwise\r
2706 // list detail information about this Bar.\r
2707 //\r
2708 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2709\r
2710 BarExist = FALSE;\r
2711 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2712 for (Index = 0; Index < BarCount; Index++) {\r
2713 if (Device->Bar[Index] == 0) {\r
2714 continue;\r
2715 }\r
2716\r
2717 if (!BarExist) {\r
2718 BarExist = TRUE;\r
2719 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
2720 Print (L" --------------------------------------------------------------------------");\r
2721 }\r
2722\r
2723 Status = PciExplainBar (\r
2724 &(Device->Bar[Index]),\r
2725 &(mConfigSpace->Common.Command),\r
2726 Address,\r
2727 IoDev,\r
2728 &Index\r
2729 );\r
2730\r
2731 if (EFI_ERROR (Status)) {\r
2732 break;\r
2733 }\r
2734 }\r
2735\r
2736 if (!BarExist) {\r
2737 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2738\r
2739 } else {\r
2740 Print (L"\n --------------------------------------------------------------------------");\r
2741 }\r
2742\r
2743 //\r
2744 // Print register Expansion ROM Base Address\r
2745 //\r
2746 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2747 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2748\r
2749 } else {\r
2750 ShellPrintHiiEx(-1, -1, NULL,\r
2751 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2752 gShellDebug1HiiHandle,\r
2753 INDEX_OF (&(Device->ROMBar)),\r
2754 Device->ROMBar\r
2755 );\r
2756 }\r
2757 //\r
2758 // Print register Cardbus CIS ptr\r
2759 //\r
2760 ShellPrintHiiEx(-1, -1, NULL,\r
2761 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2762 gShellDebug1HiiHandle,\r
2763 INDEX_OF (&(Device->CardBusCISPtr)),\r
2764 Device->CardBusCISPtr\r
2765 );\r
2766\r
2767 //\r
2768 // Print register Sub-vendor ID and subsystem ID\r
2769 //\r
2770 ShellPrintHiiEx(-1, -1, NULL,\r
2771 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2772 gShellDebug1HiiHandle,\r
2773 INDEX_OF (&(Device->SubVendorId)),\r
2774 Device->SubVendorId\r
2775 );\r
2776\r
2777 ShellPrintHiiEx(-1, -1, NULL,\r
2778 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2779 gShellDebug1HiiHandle,\r
2780 INDEX_OF (&(Device->SubSystemId)),\r
2781 Device->SubSystemId\r
2782 );\r
2783\r
2784 //\r
2785 // Print register Capabilities Ptr\r
2786 //\r
2787 ShellPrintHiiEx(-1, -1, NULL,\r
2788 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2789 gShellDebug1HiiHandle,\r
2790 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2791 Device->CapabilitiesPtr\r
2792 );\r
2793\r
2794 //\r
2795 // Print register Interrupt Line and interrupt pin\r
2796 //\r
2797 ShellPrintHiiEx(-1, -1, NULL,\r
2798 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2799 gShellDebug1HiiHandle,\r
2800 INDEX_OF (&(Device->InterruptLine)),\r
2801 Device->InterruptLine\r
2802 );\r
2803\r
2804 ShellPrintHiiEx(-1, -1, NULL,\r
2805 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2806 gShellDebug1HiiHandle,\r
2807 INDEX_OF (&(Device->InterruptPin)),\r
2808 Device->InterruptPin\r
2809 );\r
2810\r
2811 //\r
2812 // Print register Min_Gnt and Max_Lat\r
2813 //\r
2814 ShellPrintHiiEx(-1, -1, NULL,\r
2815 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2816 gShellDebug1HiiHandle,\r
2817 INDEX_OF (&(Device->MinGnt)),\r
2818 Device->MinGnt\r
2819 );\r
2820\r
2821 ShellPrintHiiEx(-1, -1, NULL,\r
2822 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2823 gShellDebug1HiiHandle,\r
2824 INDEX_OF (&(Device->MaxLat)),\r
2825 Device->MaxLat\r
2826 );\r
2827\r
2828 return EFI_SUCCESS;\r
2829}\r
2830\r
2831EFI_STATUS\r
2832PciExplainBridgeData (\r
2833 IN PCI_BRIDGE_HEADER *Bridge,\r
2834 IN UINT64 Address,\r
2835 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2836 )\r
2837/*++\r
2838\r
2839Routine Description:\r
2840\r
2841 Explain the bridge specific part of data in PCI configuration space.\r
2842\r
2843Arguments:\r
2844\r
2845 Bridge Bridge specific data region in PCI configuration space\r
2846 Address Address used to access configuration space of this PCI device\r
2847 IoDev Handle used to access configuration space of PCI device\r
2848\r
2849Returns:\r
2850\r
2851 EFI_SUCCESS The command completed successfully\r
2852\r
2853**/\r
2854{\r
2855 UINTN Index;\r
2856 BOOLEAN BarExist;\r
2857 UINTN BarCount;\r
2858 UINT32 IoAddress32;\r
2859 EFI_STATUS Status;\r
2860\r
2861 //\r
2862 // Print Base Address Registers. When Bar = 0, this Bar does not\r
2863 // exist. If these no Bar for this function, print "none", otherwise\r
2864 // list detail information about this Bar.\r
2865 //\r
2866 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
2867\r
2868 BarExist = FALSE;\r
2869 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
2870\r
2871 for (Index = 0; Index < BarCount; Index++) {\r
2872 if (Bridge->Bar[Index] == 0) {\r
2873 continue;\r
2874 }\r
2875\r
2876 if (!BarExist) {\r
2877 BarExist = TRUE;\r
2878 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
2879 Print (L" --------------------------------------------------------------------------");\r
2880 }\r
2881\r
2882 Status = PciExplainBar (\r
2883 &(Bridge->Bar[Index]),\r
2884 &(mConfigSpace->Common.Command),\r
2885 Address,\r
2886 IoDev,\r
2887 &Index\r
2888 );\r
2889\r
2890 if (EFI_ERROR (Status)) {\r
2891 break;\r
2892 }\r
2893 }\r
2894\r
2895 if (!BarExist) {\r
2896 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2897 } else {\r
2898 Print (L"\n --------------------------------------------------------------------------");\r
2899 }\r
2900\r
2901 //\r
2902 // Expansion register ROM Base Address\r
2903 //\r
2904 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
2905 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
2906\r
2907 } else {\r
2908 ShellPrintHiiEx(-1, -1, NULL,\r
2909 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
2910 gShellDebug1HiiHandle,\r
2911 INDEX_OF (&(Bridge->ROMBar)),\r
2912 Bridge->ROMBar\r
2913 );\r
2914 }\r
2915 //\r
2916 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
2917 //\r
2918 ShellPrintHiiEx(-1, -1, NULL,\r
2919 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
2920 gShellDebug1HiiHandle,\r
2921 INDEX_OF (&(Bridge->PrimaryBus)),\r
2922 INDEX_OF (&(Bridge->SecondaryBus)),\r
2923 INDEX_OF (&(Bridge->SubordinateBus))\r
2924 );\r
2925\r
2926 Print (L" ------------------------------------------------------\n");\r
2927\r
2928 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
2929 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
2930 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
2931\r
2932 //\r
2933 // Print register Secondary Latency Timer\r
2934 //\r
2935 ShellPrintHiiEx(-1, -1, NULL,\r
2936 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
2937 gShellDebug1HiiHandle,\r
2938 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
2939 Bridge->SecondaryLatencyTimer\r
2940 );\r
2941\r
2942 //\r
2943 // Print register Secondary Status\r
2944 //\r
2945 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
2946\r
2947 //\r
2948 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
2949 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
2950 // base and limit address are listed.\r
2951 //\r
2952 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
2953 Print (L"----------------------------------------------------------------------\n");\r
2954\r
2955 //\r
2956 // IO Base & Limit\r
2957 //\r
2958 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
2959 IoAddress32 &= 0xfffff000;\r
2960 ShellPrintHiiEx(-1, -1, NULL,\r
2961 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
2962 gShellDebug1HiiHandle,\r
2963 INDEX_OF (&(Bridge->IoBase)),\r
2964 IoAddress32\r
2965 );\r
2966\r
2967 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
2968 IoAddress32 |= 0x00000fff;\r
2969 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
2970\r
2971 //\r
2972 // Memory Base & Limit\r
2973 //\r
2974 ShellPrintHiiEx(-1, -1, NULL,\r
2975 STRING_TOKEN (STR_PCI2_MEMORY),\r
2976 gShellDebug1HiiHandle,\r
2977 INDEX_OF (&(Bridge->MemoryBase)),\r
2978 (Bridge->MemoryBase << 16) & 0xfff00000\r
2979 );\r
2980\r
2981 ShellPrintHiiEx(-1, -1, NULL,\r
2982 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
2983 gShellDebug1HiiHandle,\r
2984 (Bridge->MemoryLimit << 16) | 0x000fffff\r
2985 );\r
2986\r
2987 //\r
2988 // Pre-fetch-able Memory Base & Limit\r
2989 //\r
2990 ShellPrintHiiEx(-1, -1, NULL,\r
2991 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
2992 gShellDebug1HiiHandle,\r
2993 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
2994 Bridge->PrefetchableBaseUpper,\r
2995 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
2996 );\r
2997\r
2998 ShellPrintHiiEx(-1, -1, NULL,\r
2999 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3000 gShellDebug1HiiHandle,\r
3001 Bridge->PrefetchableLimitUpper,\r
3002 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3003 );\r
3004\r
3005 //\r
3006 // Print register Capabilities Pointer\r
3007 //\r
3008 ShellPrintHiiEx(-1, -1, NULL,\r
3009 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3010 gShellDebug1HiiHandle,\r
3011 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3012 Bridge->CapabilitiesPtr\r
3013 );\r
3014\r
3015 //\r
3016 // Print register Bridge Control\r
3017 //\r
3018 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3019\r
3020 //\r
3021 // Print register Interrupt Line & PIN\r
3022 //\r
3023 ShellPrintHiiEx(-1, -1, NULL,\r
3024 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3025 gShellDebug1HiiHandle,\r
3026 INDEX_OF (&(Bridge->InterruptLine)),\r
3027 Bridge->InterruptLine\r
3028 );\r
3029\r
3030 ShellPrintHiiEx(-1, -1, NULL,\r
3031 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3032 gShellDebug1HiiHandle,\r
3033 INDEX_OF (&(Bridge->InterruptPin)),\r
3034 Bridge->InterruptPin\r
3035 );\r
3036\r
3037 return EFI_SUCCESS;\r
3038}\r
3039\r
3040EFI_STATUS\r
3041PciExplainBar (\r
3042 IN UINT32 *Bar,\r
3043 IN UINT16 *Command,\r
3044 IN UINT64 Address,\r
3045 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3046 IN OUT UINTN *Index\r
3047 )\r
3048/*++\r
3049\r
3050Routine Description:\r
3051\r
3052 Explain the Base Address Register(Bar) in PCI configuration space.\r
3053\r
3054Arguments:\r
3055\r
3056 Bar Points to the Base Address Register intended to interpret\r
3057 Command Points to the register Command\r
3058 Address Address used to access configuration space of this PCI device\r
3059 IoDev Handle used to access configuration space of PCI device\r
3060 Index The Index\r
3061\r
3062Returns:\r
3063\r
3064 EFI_SUCCESS The command completed successfully\r
3065\r
3066**/\r
3067{\r
3068 UINT16 OldCommand;\r
3069 UINT16 NewCommand;\r
3070 UINT64 Bar64;\r
3071 UINT32 OldBar32;\r
3072 UINT32 NewBar32;\r
3073 UINT64 OldBar64;\r
3074 UINT64 NewBar64;\r
3075 BOOLEAN IsMem;\r
3076 BOOLEAN IsBar32;\r
3077 UINT64 RegAddress;\r
3078\r
3079 IsBar32 = TRUE;\r
3080 Bar64 = 0;\r
3081 NewBar32 = 0;\r
3082 NewBar64 = 0;\r
3083\r
3084 //\r
3085 // According the bar type, list detail about this bar, for example: 32 or\r
3086 // 64 bits; pre-fetchable or not.\r
3087 //\r
3088 if ((*Bar & PCI_BIT_0) == 0) {\r
3089 //\r
3090 // This bar is of memory type\r
3091 //\r
3092 IsMem = TRUE;\r
3093\r
3094 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3095 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3096 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3097 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3098\r
3099 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3100 Bar64 = 0x0;\r
3101 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
3102 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0), 32));\r
3103 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0));\r
3104 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3105 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3106 IsBar32 = FALSE;\r
3107 *Index += 1;\r
3108\r
3109 } else {\r
3110 //\r
3111 // Reserved\r
3112 //\r
3113 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3114 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3115 }\r
3116\r
3117 if ((*Bar & PCI_BIT_3) == 0) {\r
3118 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3119\r
3120 } else {\r
3121 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3122 }\r
3123\r
3124 } else {\r
3125 //\r
3126 // This bar is of io type\r
3127 //\r
3128 IsMem = FALSE;\r
3129 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
3130 Print (L"I/O ");\r
3131 }\r
3132\r
3133 //\r
3134 // Get BAR length(or the amount of resource this bar demands for). To get\r
3135 // Bar length, first we should temporarily disable I/O and memory access\r
3136 // of this function(by set bits in the register Command), then write all\r
3137 // "1"s to this bar. The bar value read back is the amount of resource\r
3138 // this bar demands for.\r
3139 //\r
3140 //\r
3141 // Disable io & mem access\r
3142 //\r
3143 OldCommand = *Command;\r
3144 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3145 RegAddress = Address | INDEX_OF (Command);\r
3146 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3147\r
3148 RegAddress = Address | INDEX_OF (Bar);\r
3149\r
3150 //\r
3151 // Read after write the BAR to get the size\r
3152 //\r
3153 if (IsBar32) {\r
3154 OldBar32 = *Bar;\r
3155 NewBar32 = 0xffffffff;\r
3156\r
3157 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3158 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3159 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3160\r
3161 if (IsMem) {\r
3162 NewBar32 = NewBar32 & 0xfffffff0;\r
3163 NewBar32 = (~NewBar32) + 1;\r
3164\r
3165 } else {\r
3166 NewBar32 = NewBar32 & 0xfffffffc;\r
3167 NewBar32 = (~NewBar32) + 1;\r
3168 NewBar32 = NewBar32 & 0x0000ffff;\r
3169 }\r
3170 } else {\r
3171\r
3172 OldBar64 = 0x0;\r
3173 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
3174 NewBar64 = 0xffffffffffffffff;\r
3175\r
3176 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3177 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3178 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3179\r
3180 if (IsMem) {\r
3181 NewBar64 = NewBar64 & 0xfffffffffffffff0;\r
3182 NewBar64 = (~NewBar64) + 1;\r
3183\r
3184 } else {\r
3185 NewBar64 = NewBar64 & 0xfffffffffffffffc;\r
3186 NewBar64 = (~NewBar64) + 1;\r
3187 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3188 }\r
3189 }\r
3190 //\r
3191 // Enable io & mem access\r
3192 //\r
3193 RegAddress = Address | INDEX_OF (Command);\r
3194 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3195\r
3196 if (IsMem) {\r
3197 if (IsBar32) {\r
3198 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3199 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3200\r
3201 } else {\r
3202 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));\r
3203 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
3204 Print (L" ");\r
3205 ShellPrintHiiEx(-1, -1, NULL,\r
3206 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3207 gShellDebug1HiiHandle,\r
3208 RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1), 32)\r
3209 );\r
3210 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0) - 1));\r
3211\r
3212 }\r
3213 } else {\r
3214 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3215 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3216 }\r
3217\r
3218 return EFI_SUCCESS;\r
3219}\r
3220\r
3221EFI_STATUS\r
3222PciExplainCardBusData (\r
3223 IN PCI_CARDBUS_HEADER *CardBus,\r
3224 IN UINT64 Address,\r
3225 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3226 )\r
3227/*++\r
3228\r
3229Routine Description:\r
3230\r
3231 Explain the cardbus specific part of data in PCI configuration space.\r
3232\r
3233Arguments:\r
3234\r
3235 CardBus CardBus specific region of PCI configuration space\r
3236 Address Address used to access configuration space of this PCI device\r
3237 IoDev Handle used to access configuration space of PCI device\r
3238\r
3239Returns:\r
3240\r
3241 EFI_SUCCESS The command completed successfully\r
3242\r
3243**/\r
3244{\r
3245 BOOLEAN Io32Bit;\r
3246 PCI_CARDBUS_DATA *CardBusData;\r
3247\r
3248 ShellPrintHiiEx(-1, -1, NULL,\r
3249 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3250 gShellDebug1HiiHandle,\r
3251 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3252 CardBus->CardBusSocketReg\r
3253 );\r
3254\r
3255 //\r
3256 // Print Secondary Status\r
3257 //\r
3258 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3259\r
3260 //\r
3261 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3262 // Subordinate bus number\r
3263 //\r
3264 ShellPrintHiiEx(-1, -1, NULL,\r
3265 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3266 gShellDebug1HiiHandle,\r
3267 INDEX_OF (&(CardBus->PciBusNumber)),\r
3268 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3269 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3270 );\r
3271\r
3272 Print (L" ------------------------------------------------------\n");\r
3273\r
3274 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3275 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3276 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3277\r
3278 //\r
3279 // Print CardBus Latency Timer\r
3280 //\r
3281 ShellPrintHiiEx(-1, -1, NULL,\r
3282 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3283 gShellDebug1HiiHandle,\r
3284 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3285 CardBus->CardBusLatencyTimer\r
3286 );\r
3287\r
3288 //\r
3289 // Print Memory/Io ranges this cardbus bridge forwards\r
3290 //\r
3291 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
3292 Print (L"----------------------------------------------------------------------\n");\r
3293\r
3294 ShellPrintHiiEx(-1, -1, NULL,\r
3295 STRING_TOKEN (STR_PCI2_MEM_3),\r
3296 gShellDebug1HiiHandle,\r
3297 INDEX_OF (&(CardBus->MemoryBase0)),\r
3298 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3299 CardBus->MemoryBase0 & 0xfffff000,\r
3300 CardBus->MemoryLimit0 | 0x00000fff\r
3301 );\r
3302\r
3303 ShellPrintHiiEx(-1, -1, NULL,\r
3304 STRING_TOKEN (STR_PCI2_MEM_3),\r
3305 gShellDebug1HiiHandle,\r
3306 INDEX_OF (&(CardBus->MemoryBase1)),\r
3307 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3308 CardBus->MemoryBase1 & 0xfffff000,\r
3309 CardBus->MemoryLimit1 | 0x00000fff\r
3310 );\r
3311\r
3312 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3313 ShellPrintHiiEx(-1, -1, NULL,\r
3314 STRING_TOKEN (STR_PCI2_IO_2),\r
3315 gShellDebug1HiiHandle,\r
3316 INDEX_OF (&(CardBus->IoBase0)),\r
3317 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3318 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3319 CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
3320 );\r
3321\r
3322 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3323 ShellPrintHiiEx(-1, -1, NULL,\r
3324 STRING_TOKEN (STR_PCI2_IO_2),\r
3325 gShellDebug1HiiHandle,\r
3326 INDEX_OF (&(CardBus->IoBase1)),\r
3327 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3328 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
3329 CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff) | 0x00000003\r
3330 );\r
3331\r
3332 //\r
3333 // Print register Interrupt Line & PIN\r
3334 //\r
3335 ShellPrintHiiEx(-1, -1, NULL,\r
3336 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3337 gShellDebug1HiiHandle,\r
3338 INDEX_OF (&(CardBus->InterruptLine)),\r
3339 CardBus->InterruptLine,\r
3340 INDEX_OF (&(CardBus->InterruptPin)),\r
3341 CardBus->InterruptPin\r
3342 );\r
3343\r
3344 //\r
3345 // Print register Bridge Control\r
3346 //\r
3347 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3348\r
3349 //\r
3350 // Print some registers in data region of PCI configuration space for cardbus\r
3351 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3352 // Address.\r
3353 //\r
3354 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3355\r
3356 ShellPrintHiiEx(-1, -1, NULL,\r
3357 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3358 gShellDebug1HiiHandle,\r
3359 INDEX_OF (&(CardBusData->SubVendorId)),\r
3360 CardBusData->SubVendorId,\r
3361 INDEX_OF (&(CardBusData->SubSystemId)),\r
3362 CardBusData->SubSystemId\r
3363 );\r
3364\r
3365 ShellPrintHiiEx(-1, -1, NULL,\r
3366 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3367 gShellDebug1HiiHandle,\r
3368 INDEX_OF (&(CardBusData->LegacyBase)),\r
3369 CardBusData->LegacyBase\r
3370 );\r
3371\r
3372 return EFI_SUCCESS;\r
3373}\r
3374\r
3375EFI_STATUS\r
3376PciExplainStatus (\r
3377 IN UINT16 *Status,\r
3378 IN BOOLEAN MainStatus,\r
3379 IN PCI_HEADER_TYPE HeaderType\r
3380 )\r
3381/*++\r
3382\r
3383Routine Description:\r
3384\r
3385 Explain each meaningful bit of register Status. The definition of Status is\r
3386 slightly different depending on the PCI header type.\r
3387\r
3388Arguments:\r
3389\r
3390 Status Points to the content of register Status\r
3391 MainStatus Indicates if this register is main status(not secondary\r
3392 status)\r
3393 HeaderType Header type of this PCI device\r
3394\r
3395Returns:\r
3396\r
3397 EFI_SUCCESS The command completed successfully\r
3398\r
3399**/\r
3400{\r
3401 if (MainStatus) {\r
3402 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3403\r
3404 } else {\r
3405 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3406 }\r
3407\r
3408 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3409\r
3410 //\r
3411 // Bit 5 is meaningless for CardBus Bridge\r
3412 //\r
3413 if (HeaderType == PciCardBusBridge) {\r
3414 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3415\r
3416 } else {\r
3417 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3418 }\r
3419\r
3420 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3421\r
3422 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3423 //\r
3424 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3425 //\r
3426 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3427 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3428 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3429\r
3430 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3431 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3432\r
3433 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3434 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3435\r
3436 } else {\r
3437 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3438 }\r
3439\r
3440 ShellPrintHiiEx(-1, -1, NULL,\r
3441 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3442 gShellDebug1HiiHandle,\r
3443 (*Status & PCI_BIT_11) != 0\r
3444 );\r
3445\r
3446 ShellPrintHiiEx(-1, -1, NULL,\r
3447 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3448 gShellDebug1HiiHandle,\r
3449 (*Status & PCI_BIT_12) != 0\r
3450 );\r
3451\r
3452 ShellPrintHiiEx(-1, -1, NULL,\r
3453 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3454 gShellDebug1HiiHandle,\r
3455 (*Status & PCI_BIT_13) != 0\r
3456 );\r
3457\r
3458 if (MainStatus) {\r
3459 ShellPrintHiiEx(-1, -1, NULL,\r
3460 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3461 gShellDebug1HiiHandle,\r
3462 (*Status & PCI_BIT_14) != 0\r
3463 );\r
3464\r
3465 } else {\r
3466 ShellPrintHiiEx(-1, -1, NULL,\r
3467 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3468 gShellDebug1HiiHandle,\r
3469 (*Status & PCI_BIT_14) != 0\r
3470 );\r
3471 }\r
3472\r
3473 ShellPrintHiiEx(-1, -1, NULL,\r
3474 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3475 gShellDebug1HiiHandle,\r
3476 (*Status & PCI_BIT_15) != 0\r
3477 );\r
3478\r
3479 return EFI_SUCCESS;\r
3480}\r
3481\r
3482EFI_STATUS\r
3483PciExplainCommand (\r
3484 IN UINT16 *Command\r
3485 )\r
3486/*++\r
3487\r
3488Routine Description:\r
3489\r
3490 Explain each meaningful bit of register Command.\r
3491\r
3492Arguments:\r
3493\r
3494 Command Points to the content of register Command\r
3495\r
3496Returns:\r
3497\r
3498 EFI_SUCCESS The command completed successfully\r
3499\r
3500**/\r
3501{\r
3502 //\r
3503 // Print the binary value of register Command\r
3504 //\r
3505 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3506\r
3507 //\r
3508 // Explain register Command bit by bit\r
3509 //\r
3510 ShellPrintHiiEx(-1, -1, NULL,\r
3511 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3512 gShellDebug1HiiHandle,\r
3513 (*Command & PCI_BIT_0) != 0\r
3514 );\r
3515\r
3516 ShellPrintHiiEx(-1, -1, NULL,\r
3517 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3518 gShellDebug1HiiHandle,\r
3519 (*Command & PCI_BIT_1) != 0\r
3520 );\r
3521\r
3522 ShellPrintHiiEx(-1, -1, NULL,\r
3523 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3524 gShellDebug1HiiHandle,\r
3525 (*Command & PCI_BIT_2) != 0\r
3526 );\r
3527\r
3528 ShellPrintHiiEx(-1, -1, NULL,\r
3529 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3530 gShellDebug1HiiHandle,\r
3531 (*Command & PCI_BIT_3) != 0\r
3532 );\r
3533\r
3534 ShellPrintHiiEx(-1, -1, NULL,\r
3535 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3536 gShellDebug1HiiHandle,\r
3537 (*Command & PCI_BIT_4) != 0\r
3538 );\r
3539\r
3540 ShellPrintHiiEx(-1, -1, NULL,\r
3541 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3542 gShellDebug1HiiHandle,\r
3543 (*Command & PCI_BIT_5) != 0\r
3544 );\r
3545\r
3546 ShellPrintHiiEx(-1, -1, NULL,\r
3547 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3548 gShellDebug1HiiHandle,\r
3549 (*Command & PCI_BIT_6) != 0\r
3550 );\r
3551\r
3552 ShellPrintHiiEx(-1, -1, NULL,\r
3553 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3554 gShellDebug1HiiHandle,\r
3555 (*Command & PCI_BIT_7) != 0\r
3556 );\r
3557\r
3558 ShellPrintHiiEx(-1, -1, NULL,\r
3559 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3560 gShellDebug1HiiHandle,\r
3561 (*Command & PCI_BIT_8) != 0\r
3562 );\r
3563\r
3564 ShellPrintHiiEx(-1, -1, NULL,\r
3565 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3566 gShellDebug1HiiHandle,\r
3567 (*Command & PCI_BIT_9) != 0\r
3568 );\r
3569\r
3570 return EFI_SUCCESS;\r
3571}\r
3572\r
3573EFI_STATUS\r
3574PciExplainBridgeControl (\r
3575 IN UINT16 *BridgeControl,\r
3576 IN PCI_HEADER_TYPE HeaderType\r
3577 )\r
3578/*++\r
3579\r
3580Routine Description:\r
3581\r
3582 Explain each meaningful bit of register Bridge Control.\r
3583\r
3584Arguments:\r
3585\r
3586 BridgeControl Points to the content of register Bridge Control\r
3587 HeaderType The headertype\r
3588\r
3589Returns:\r
3590\r
3591 EFI_SUCCESS The command completed successfully\r
3592\r
3593**/\r
3594{\r
3595 ShellPrintHiiEx(-1, -1, NULL,\r
3596 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3597 gShellDebug1HiiHandle,\r
3598 INDEX_OF (BridgeControl),\r
3599 *BridgeControl\r
3600 );\r
3601\r
3602 ShellPrintHiiEx(-1, -1, NULL,\r
3603 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3604 gShellDebug1HiiHandle,\r
3605 (*BridgeControl & PCI_BIT_0) != 0\r
3606 );\r
3607 ShellPrintHiiEx(-1, -1, NULL,\r
3608 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3609 gShellDebug1HiiHandle,\r
3610 (*BridgeControl & PCI_BIT_1) != 0\r
3611 );\r
3612 ShellPrintHiiEx(-1, -1, NULL,\r
3613 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3614 gShellDebug1HiiHandle,\r
3615 (*BridgeControl & PCI_BIT_2) != 0\r
3616 );\r
3617 ShellPrintHiiEx(-1, -1, NULL,\r
3618 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3619 gShellDebug1HiiHandle,\r
3620 (*BridgeControl & PCI_BIT_3) != 0\r
3621 );\r
3622 ShellPrintHiiEx(-1, -1, NULL,\r
3623 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3624 gShellDebug1HiiHandle,\r
3625 (*BridgeControl & PCI_BIT_5) != 0\r
3626 );\r
3627\r
3628 //\r
3629 // Register Bridge Control has some slight differences between P2P bridge\r
3630 // and Cardbus bridge from bit 6 to bit 11.\r
3631 //\r
3632 if (HeaderType == PciP2pBridge) {\r
3633 ShellPrintHiiEx(-1, -1, NULL,\r
3634 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3635 gShellDebug1HiiHandle,\r
3636 (*BridgeControl & PCI_BIT_6) != 0\r
3637 );\r
3638 ShellPrintHiiEx(-1, -1, NULL,\r
3639 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3640 gShellDebug1HiiHandle,\r
3641 (*BridgeControl & PCI_BIT_7) != 0\r
3642 );\r
3643 ShellPrintHiiEx(-1, -1, NULL,\r
3644 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3645 gShellDebug1HiiHandle,\r
3646 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3647 );\r
3648 ShellPrintHiiEx(-1, -1, NULL,\r
3649 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3650 gShellDebug1HiiHandle,\r
3651 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3652 );\r
3653 ShellPrintHiiEx(-1, -1, NULL,\r
3654 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3655 gShellDebug1HiiHandle,\r
3656 (*BridgeControl & PCI_BIT_10) != 0\r
3657 );\r
3658 ShellPrintHiiEx(-1, -1, NULL,\r
3659 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3660 gShellDebug1HiiHandle,\r
3661 (*BridgeControl & PCI_BIT_11) != 0\r
3662 );\r
3663\r
3664 } else {\r
3665 ShellPrintHiiEx(-1, -1, NULL,\r
3666 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3667 gShellDebug1HiiHandle,\r
3668 (*BridgeControl & PCI_BIT_6) != 0\r
3669 );\r
3670 ShellPrintHiiEx(-1, -1, NULL,\r
3671 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3672 gShellDebug1HiiHandle,\r
3673 (*BridgeControl & PCI_BIT_7) != 0\r
3674 );\r
3675 ShellPrintHiiEx(-1, -1, NULL,\r
3676 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3677 gShellDebug1HiiHandle,\r
3678 (*BridgeControl & PCI_BIT_10) != 0\r
3679 );\r
3680 }\r
3681\r
3682 return EFI_SUCCESS;\r
3683}\r
3684\r
3685EFI_STATUS\r
3686PciExplainCapabilityStruct (\r
3687 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3688 IN UINT64 Address,\r
3689 IN UINT8 CapPtr\r
3690 )\r
3691{\r
3692 UINT8 CapabilityPtr;\r
3693 UINT16 CapabilityEntry;\r
3694 UINT8 CapabilityID;\r
3695 UINT64 RegAddress;\r
3696\r
3697 CapabilityPtr = CapPtr;\r
3698\r
3699 //\r
3700 // Go through the Capability list\r
3701 //\r
3702 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3703 RegAddress = Address + CapabilityPtr;\r
3704 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3705\r
3706 CapabilityID = (UINT8) CapabilityEntry;\r
3707\r
3708 //\r
3709 // Explain PciExpress data\r
3710 //\r
3711 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
3712 PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
3713 return EFI_SUCCESS;\r
3714 }\r
3715 //\r
3716 // Explain other capabilities here\r
3717 //\r
3718 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3719 }\r
3720\r
3721 return EFI_SUCCESS;\r
3722}\r
3723\r
3724EFI_STATUS\r
3725ExplainPcieCapReg (\r
3726 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3727)\r
3728{\r
3729 UINT16 PcieCapReg;\r
3730 CHAR16 *DevicePortType;\r
3731\r
3732 PcieCapReg = PciExpressCap->PcieCapReg;\r
3733 Print (\r
3734 L" Capability Version(3:0): %E0x%04x%N\n",\r
3735 PCIE_CAP_VERSION (PcieCapReg)\r
3736 );\r
3737 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3738 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3739 } else {\r
3740 DevicePortType = L"Unknown Type";\r
3741 }\r
3742 Print (\r
3743 L" Device/PortType(7:4): %E%s%N\n",\r
3744 DevicePortType\r
3745 );\r
3746 //\r
3747 // 'Slot Implemented' is only valid for:\r
3748 // a) Root Port of PCI Express Root Complex, or\r
3749 // b) Downstream Port of PCI Express Switch\r
3750 //\r
3751 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3752 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
3753 Print (\r
3754 L" Slot Implemented(8): %E%d%N\n",\r
3755 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3756 );\r
3757 }\r
3758 Print (\r
3759 L" Interrupt Message Number(13:9): %E0x%05x%N\n",\r
3760 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3761 );\r
3762 return EFI_SUCCESS;\r
3763}\r
3764\r
3765EFI_STATUS\r
3766ExplainPcieDeviceCap (\r
3767 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3768)\r
3769{\r
3770 UINT16 PcieCapReg;\r
3771 UINT32 PcieDeviceCap;\r
3772 UINT8 DevicePortType;\r
3773 UINT8 L0sLatency;\r
3774 UINT8 L1Latency;\r
3775\r
3776 PcieCapReg = PciExpressCap->PcieCapReg;\r
3777 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3778 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
3779 Print (L" Max_Payload_Size Supported(2:0): ");\r
3780 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
3781 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
3782 } else {\r
3783 Print (L"%EUnknown%N\n");\r
3784 }\r
3785 Print (\r
3786 L" Phantom Functions Supported(4:3): %E%d%N\n",\r
3787 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3788 );\r
3789 Print (\r
3790 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",\r
3791 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3792 );\r
3793 //\r
3794 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3795 //\r
3796 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3797 L0sLatency = (UINT8) PCIE_CAP_L0sLatency (PcieDeviceCap);\r
3798 L1Latency = (UINT8) PCIE_CAP_L1Latency (PcieDeviceCap);\r
3799 Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
3800 if (L0sLatency < 4) {\r
3801 Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
3802 } else {\r
3803 if (L0sLatency < 7) {\r
3804 Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));\r
3805 } else {\r
3806 Print (L"%ENo limit%N\n");\r
3807 }\r
3808 }\r
3809 Print (L" Endpoint L1 Acceptable Latency(11:9): ");\r
3810 if (L1Latency < 7) {\r
3811 Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));\r
3812 } else {\r
3813 Print (L"%ENo limit%N\n");\r
3814 }\r
3815 }\r
3816 Print (\r
3817 L" Role-based Error Reporting(15): %E%d%N\n",\r
3818 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3819 );\r
3820 //\r
3821 // Only valid for Upstream Port:\r
3822 // a) Captured Slot Power Limit Value\r
3823 // b) Captured Slot Power Scale\r
3824 //\r
3825 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
3826 Print (\r
3827 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",\r
3828 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3829 );\r
3830 Print (\r
3831 L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",\r
3832 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3833 );\r
3834 }\r
3835 //\r
3836 // Function Level Reset Capability is only valid for Endpoint\r
3837 //\r
3838 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3839 Print (\r
3840 L" Function Level Reset Capability(28): %E%d%N\n",\r
3841 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3842 );\r
3843 }\r
3844 return EFI_SUCCESS;\r
3845}\r
3846\r
3847EFI_STATUS\r
3848ExplainPcieDeviceControl (\r
3849 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3850)\r
3851{\r
3852 UINT16 PcieCapReg;\r
3853 UINT16 PcieDeviceControl;\r
3854\r
3855 PcieCapReg = PciExpressCap->PcieCapReg;\r
3856 PcieDeviceControl = PciExpressCap->DeviceControl;\r
3857 Print (\r
3858 L" Correctable Error Reporting Enable(0): %E%d%N\n",\r
3859 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3860 );\r
3861 Print (\r
3862 L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",\r
3863 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3864 );\r
3865 Print (\r
3866 L" Fatal Error Reporting Enable(2): %E%d%N\n",\r
3867 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3868 );\r
3869 Print (\r
3870 L" Unsupported Request Reporting Enable(3): %E%d%N\n",\r
3871 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
3872 );\r
3873 Print (\r
3874 L" Enable Relaxed Ordering(4): %E%d%N\n",\r
3875 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
3876 );\r
3877 Print (L" Max_Payload_Size(7:5): ");\r
3878 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
3879 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
3880 } else {\r
3881 Print (L"%EUnknown%N\n");\r
3882 }\r
3883 Print (\r
3884 L" Extended Tag Field Enable(8): %E%d%N\n",\r
3885 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
3886 );\r
3887 Print (\r
3888 L" Phantom Functions Enable(9): %E%d%N\n",\r
3889 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
3890 );\r
3891 Print (\r
3892 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",\r
3893 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
3894 );\r
3895 Print (\r
3896 L" Enable No Snoop(11): %E%d%N\n",\r
3897 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
3898 );\r
3899 Print (L" Max_Read_Request_Size(14:12): ");\r
3900 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
3901 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
3902 } else {\r
3903 Print (L"%EUnknown%N\n");\r
3904 }\r
3905 //\r
3906 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
3907 //\r
3908 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
3909 Print (\r
3910 L" Bridge Configuration Retry Enable(15): %E%d%N\n",\r
3911 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
3912 );\r
3913 }\r
3914 return EFI_SUCCESS;\r
3915}\r
3916\r
3917EFI_STATUS\r
3918ExplainPcieDeviceStatus (\r
3919 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3920)\r
3921{\r
3922 UINT16 PcieDeviceStatus;\r
3923\r
3924 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
3925 Print (\r
3926 L" Correctable Error Detected(0): %E%d%N\n",\r
3927 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
3928 );\r
3929 Print (\r
3930 L" Non-Fatal Error Detected(1): %E%d%N\n",\r
3931 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
3932 );\r
3933 Print (\r
3934 L" Fatal Error Detected(2): %E%d%N\n",\r
3935 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
3936 );\r
3937 Print (\r
3938 L" Unsupported Request Detected(3): %E%d%N\n",\r
3939 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
3940 );\r
3941 Print (\r
3942 L" AUX Power Detected(4): %E%d%N\n",\r
3943 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
3944 );\r
3945 Print (\r
3946 L" Transactions Pending(5): %E%d%N\n",\r
3947 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
3948 );\r
3949 return EFI_SUCCESS;\r
3950}\r
3951\r
3952EFI_STATUS\r
3953ExplainPcieLinkCap (\r
3954 IN PCIE_CAP_STURCTURE *PciExpressCap\r
3955)\r
3956{\r
3957 UINT32 PcieLinkCap;\r
3958 CHAR16 *SupLinkSpeeds;\r
3959 CHAR16 *ASPM;\r
3960\r
3961 PcieLinkCap = PciExpressCap->LinkCap;\r
3962 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
3963 case 1:\r
3964 SupLinkSpeeds = L"2.5 GT/s";\r
3965 break;\r
3966 case 2:\r
3967 SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
3968 break;\r
3969 default:\r
3970 SupLinkSpeeds = L"Unknown";\r
3971 break;\r
3972 }\r
3973 Print (\r
3974 L" Supported Link Speeds(3:0): %E%s supported%N\n",\r
3975 SupLinkSpeeds\r
3976 );\r
3977 Print (\r
3978 L" Maximum Link Width(9:4): %Ex%d%N\n",\r
3979 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
3980 );\r
3981 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
3982 case 1:\r
3983 ASPM = L"L0s Entry";\r
3984 break;\r
3985 case 3:\r
3986 ASPM = L"L0s and L1";\r
3987 break;\r
3988 default:\r
3989 ASPM = L"Reserved";\r
3990 break;\r
3991 }\r
3992 Print (\r
3993 L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
3994 ASPM\r
3995 );\r
3996 Print (\r
3997 L" L0s Exit Latency(14:12): %E%s%N\n",\r
3998 L0sLatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
3999 );\r
4000 Print (\r
4001 L" L1 Exit Latency(17:15): %E%s%N\n",\r
4002 L1LatencyStrTable[PCIE_CAP_L0s_LATENCY (PcieLinkCap)]\r
4003 );\r
4004 Print (\r
4005 L" Clock Power Management(18): %E%d%N\n",\r
4006 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4007 );\r
4008 Print (\r
4009 L" Surprise Down Error Reporting Capable(19): %E%d%N\n",\r
4010 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4011 );\r
4012 Print (\r
4013 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",\r
4014 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4015 );\r
4016 Print (\r
4017 L" Link Bandwidth Notification Capability(21): %E%d%N\n",\r
4018 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4019 );\r
4020 Print (\r
4021 L" Port Number(31:24): %E0x%02x%N\n",\r
4022 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4023 );\r
4024 return EFI_SUCCESS;\r
4025}\r
4026\r
4027EFI_STATUS\r
4028ExplainPcieLinkControl (\r
4029 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4030)\r
4031{\r
4032 UINT16 PcieLinkControl;\r
4033 UINT8 DevicePortType;\r
4034\r
4035 PcieLinkControl = PciExpressCap->LinkControl;\r
4036 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
4037 Print (\r
4038 L" Active State Power Management Control(1:0): %E%s%N\n",\r
4039 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4040 );\r
4041 //\r
4042 // RCB is not applicable to switches\r
4043 //\r
4044 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
4045 Print (\r
4046 L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",\r
4047 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4048 );\r
4049 }\r
4050 //\r
4051 // Link Disable is reserved on\r
4052 // a) Endpoints\r
4053 // b) PCI Express to PCI/PCI-X bridges\r
4054 // c) Upstream Ports of Switches\r
4055 //\r
4056 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4057 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4058 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4059 Print (\r
4060 L" Link Disable(4): %E%d%N\n",\r
4061 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4062 );\r
4063 }\r
4064 Print (\r
4065 L" Common Clock Configuration(6): %E%d%N\n",\r
4066 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4067 );\r
4068 Print (\r
4069 L" Extended Synch(7): %E%d%N\n",\r
4070 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4071 );\r
4072 Print (\r
4073 L" Enable Clock Power Management(8): %E%d%N\n",\r
4074 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4075 );\r
4076 Print (\r
4077 L" Hardware Autonomous Width Disable(9): %E%d%N\n",\r
4078 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4079 );\r
4080 Print (\r
4081 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",\r
4082 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4083 );\r
4084 Print (\r
4085 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",\r
4086 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4087 );\r
4088 return EFI_SUCCESS;\r
4089}\r
4090\r
4091EFI_STATUS\r
4092ExplainPcieLinkStatus (\r
4093 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4094)\r
4095{\r
4096 UINT16 PcieLinkStatus;\r
4097 CHAR16 *SupLinkSpeeds;\r
4098\r
4099 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4100 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4101 case 1:\r
4102 SupLinkSpeeds = L"2.5 GT/s";\r
4103 break;\r
4104 case 2:\r
4105 SupLinkSpeeds = L"5.0 GT/s";\r
4106 break;\r
4107 default:\r
4108 SupLinkSpeeds = L"Reserved";\r
4109 break;\r
4110 }\r
4111 Print (\r
4112 L" Current Link Speed(3:0): %E%s%N\n",\r
4113 SupLinkSpeeds\r
4114 );\r
4115 Print (\r
4116 L" Negotiated Link Width(9:4): %Ex%d%N\n",\r
4117 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4118 );\r
4119 Print (\r
4120 L" Link Training(11): %E%d%N\n",\r
4121 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4122 );\r
4123 Print (\r
4124 L" Slot Clock Configuration(12): %E%d%N\n",\r
4125 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4126 );\r
4127 Print (\r
4128 L" Data Link Layer Link Active(13): %E%d%N\n",\r
4129 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4130 );\r
4131 Print (\r
4132 L" Link Bandwidth Management Status(14): %E%d%N\n",\r
4133 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4134 );\r
4135 Print (\r
4136 L" Link Autonomous Bandwidth Status(15): %E%d%N\n",\r
4137 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4138 );\r
4139 return EFI_SUCCESS;\r
4140}\r
4141\r
4142EFI_STATUS\r
4143ExplainPcieSlotCap (\r
4144 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4145)\r
4146{\r
4147 UINT32 PcieSlotCap;\r
4148\r
4149 PcieSlotCap = PciExpressCap->SlotCap;\r
4150\r
4151 Print (\r
4152 L" Attention Button Present(0): %E%d%N\n",\r
4153 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4154 );\r
4155 Print (\r
4156 L" Power Controller Present(1): %E%d%N\n",\r
4157 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4158 );\r
4159 Print (\r
4160 L" MRL Sensor Present(2): %E%d%N\n",\r
4161 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4162 );\r
4163 Print (\r
4164 L" Attention Indicator Present(3): %E%d%N\n",\r
4165 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4166 );\r
4167 Print (\r
4168 L" Power Indicator Present(4): %E%d%N\n",\r
4169 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4170 );\r
4171 Print (\r
4172 L" Hot-Plug Surprise(5): %E%d%N\n",\r
4173 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4174 );\r
4175 Print (\r
4176 L" Hot-Plug Capable(6): %E%d%N\n",\r
4177 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4178 );\r
4179 Print (\r
4180 L" Slot Power Limit Value(14:7): %E0x%02x%N\n",\r
4181 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4182 );\r
4183 Print (\r
4184 L" Slot Power Limit Scale(16:15): %E%s%N\n",\r
4185 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4186 );\r
4187 Print (\r
4188 L" Electromechanical Interlock Present(17): %E%d%N\n",\r
4189 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4190 );\r
4191 Print (\r
4192 L" No Command Completed Support(18): %E%d%N\n",\r
4193 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4194 );\r
4195 Print (\r
4196 L" Physical Slot Number(31:19): %E%d%N\n",\r
4197 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4198 );\r
4199\r
4200 return EFI_SUCCESS;\r
4201}\r
4202\r
4203EFI_STATUS\r
4204ExplainPcieSlotControl (\r
4205 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4206)\r
4207{\r
4208 UINT16 PcieSlotControl;\r
4209\r
4210 PcieSlotControl = PciExpressCap->SlotControl;\r
4211 Print (\r
4212 L" Attention Button Pressed Enable(0): %E%d%N\n",\r
4213 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4214 );\r
4215 Print (\r
4216 L" Power Fault Detected Enable(1): %E%d%N\n",\r
4217 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4218 );\r
4219 Print (\r
4220 L" MRL Sensor Changed Enable(2): %E%d%N\n",\r
4221 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4222 );\r
4223 Print (\r
4224 L" Presence Detect Changed Enable(3): %E%d%N\n",\r
4225 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4226 );\r
4227 Print (\r
4228 L" Command Completed Interrupt Enable(4): %E%d%N\n",\r
4229 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4230 );\r
4231 Print (\r
4232 L" Hot-Plug Interrupt Enable(5): %E%d%N\n",\r
4233 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4234 );\r
4235 Print (\r
4236 L" Attention Indicator Control(7:6): %E%s%N\n",\r
4237 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4238 );\r
4239 Print (\r
4240 L" Power Indicator Control(9:8): %E%s%N\n",\r
4241 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4242 );\r
4243 Print (L" Power Controller Control(10): %EPower ");\r
4244 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
4245 Print (L"Off%N\n");\r
4246 } else {\r
4247 Print (L"On%N\n");\r
4248 }\r
4249 Print (\r
4250 L" Electromechanical Interlock Control(11): %E%d%N\n",\r
4251 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4252 );\r
4253 Print (\r
4254 L" Data Link Layer State Changed Enable(12): %E%d%N\n",\r
4255 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4256 );\r
4257 return EFI_SUCCESS;\r
4258}\r
4259\r
4260EFI_STATUS\r
4261ExplainPcieSlotStatus (\r
4262 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4263)\r
4264{\r
4265 UINT16 PcieSlotStatus;\r
4266\r
4267 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4268\r
4269 Print (\r
4270 L" Attention Button Pressed(0): %E%d%N\n",\r
4271 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4272 );\r
4273 Print (\r
4274 L" Power Fault Detected(1): %E%d%N\n",\r
4275 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4276 );\r
4277 Print (\r
4278 L" MRL Sensor Changed(2): %E%d%N\n",\r
4279 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4280 );\r
4281 Print (\r
4282 L" Presence Detect Changed(3): %E%d%N\n",\r
4283 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4284 );\r
4285 Print (\r
4286 L" Command Completed(4): %E%d%N\n",\r
4287 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4288 );\r
4289 Print (L" MRL Sensor State(5): %EMRL ");\r
4290 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
4291 Print (L" Opened%N\n");\r
4292 } else {\r
4293 Print (L" Closed%N\n");\r
4294 }\r
4295 Print (L" Presence Detect State(6): ");\r
4296 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
4297 Print (L"%ECard Present in slot%N\n");\r
4298 } else {\r
4299 Print (L"%ESlot Empty%N\n");\r
4300 }\r
4301 Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
4302 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
4303 Print (L"Engaged%N\n");\r
4304 } else {\r
4305 Print (L"Disengaged%N\n");\r
4306 }\r
4307 Print (\r
4308 L" Data Link Layer State Changed(8): %E%d%N\n",\r
4309 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4310 );\r
4311 return EFI_SUCCESS;\r
4312}\r
4313\r
4314EFI_STATUS\r
4315ExplainPcieRootControl (\r
4316 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4317)\r
4318{\r
4319 UINT16 PcieRootControl;\r
4320\r
4321 PcieRootControl = PciExpressCap->RootControl;\r
4322\r
4323 Print (\r
4324 L" System Error on Correctable Error Enable(0): %E%d%N\n",\r
4325 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4326 );\r
4327 Print (\r
4328 L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",\r
4329 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4330 );\r
4331 Print (\r
4332 L" System Error on Fatal Error Enable(2): %E%d%N\n",\r
4333 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4334 );\r
4335 Print (\r
4336 L" PME Interrupt Enable(3): %E%d%N\n",\r
4337 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4338 );\r
4339 Print (\r
4340 L" CRS Software Visibility Enable(4): %E%d%N\n",\r
4341 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4342 );\r
4343\r
4344 return EFI_SUCCESS;\r
4345}\r
4346\r
4347EFI_STATUS\r
4348ExplainPcieRootCap (\r
4349 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4350)\r
4351{\r
4352 UINT16 PcieRootCap;\r
4353\r
4354 PcieRootCap = PciExpressCap->RsvdP;\r
4355\r
4356 Print (\r
4357 L" CRS Software Visibility(0): %E%d%N\n",\r
4358 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4359 );\r
4360\r
4361 return EFI_SUCCESS;\r
4362}\r
4363\r
4364EFI_STATUS\r
4365ExplainPcieRootStatus (\r
4366 IN PCIE_CAP_STURCTURE *PciExpressCap\r
4367)\r
4368{\r
4369 UINT32 PcieRootStatus;\r
4370\r
4371 PcieRootStatus = PciExpressCap->RootStatus;\r
4372\r
4373 Print (\r
4374 L" PME Requester ID(15:0): %E0x%04x%N\n",\r
4375 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4376 );\r
4377 Print (\r
4378 L" PME Status(16): %E%d%N\n",\r
4379 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4380 );\r
4381 Print (\r
4382 L" PME Pending(17): %E%d%N\n",\r
4383 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4384 );\r
4385 return EFI_SUCCESS;\r
4386}\r
4387\r
4388EFI_STATUS\r
4389PciExplainPciExpress (\r
4390 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
4391 IN UINT64 Address,\r
4392 IN UINT8 CapabilityPtr\r
4393 )\r
4394{\r
4395\r
4396 PCIE_CAP_STURCTURE PciExpressCap;\r
4397 EFI_STATUS Status;\r
4398 UINT64 CapRegAddress;\r
4399 UINT8 Bus;\r
4400 UINT8 Dev;\r
4401 UINT8 Func;\r
4402 UINT8 *ExRegBuffer;\r
4403 UINTN ExtendRegSize;\r
4404 UINT64 Pciex_Address;\r
4405 UINT8 DevicePortType;\r
4406 UINTN Index;\r
4407 UINT8 *RegAddr;\r
4408 UINTN RegValue;\r
4409\r
4410 CapRegAddress = Address + CapabilityPtr;\r
4411 IoDev->Pci.Read (\r
4412 IoDev,\r
4413 EfiPciWidthUint32,\r
4414 CapRegAddress,\r
4415 sizeof (PciExpressCap) / sizeof (UINT32),\r
4416 &PciExpressCap\r
4417 );\r
4418\r
4419 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
4420\r
4421 Print (L"\nPci Express device capability structure:\n");\r
4422\r
4423 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
4424 if (ShellGetExecutionBreakFlag()) {\r
4425 goto Done;\r
4426 }\r
4427 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
4428 switch (PcieExplainList[Index].Width) {\r
4429 case FieldWidthUINT8:\r
4430 RegValue = *(UINT8 *) RegAddr;\r
4431 break;\r
4432 case FieldWidthUINT16:\r
4433 RegValue = *(UINT16 *) RegAddr;\r
4434 break;\r
4435 case FieldWidthUINT32:\r
4436 RegValue = *(UINT32 *) RegAddr;\r
4437 break;\r
4438 default:\r
4439 RegValue = 0;\r
4440 break;\r
4441 }\r
4442 ShellPrintHiiEx(-1, -1, NULL,\r
4443 PcieExplainList[Index].Token,\r
4444 gShellDebug1HiiHandle,\r
4445 PcieExplainList[Index].Offset,\r
4446 RegValue\r
4447 );\r
4448 if (PcieExplainList[Index].Func == NULL) {\r
4449 continue;\r
4450 }\r
4451 switch (PcieExplainList[Index].Type) {\r
4452 case PcieExplainTypeLink:\r
4453 //\r
4454 // Link registers should not be used by\r
4455 // a) Root Complex Integrated Endpoint\r
4456 // b) Root Complex Event Collector\r
4457 //\r
4458 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
4459 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
4460 continue;\r
4461 }\r
4462 break;\r
4463 case PcieExplainTypeSlot:\r
4464 //\r
4465 // Slot registers are only valid for\r
4466 // a) Root Port of PCI Express Root Complex\r
4467 // b) Downstream Port of PCI Express Switch\r
4468 // and when SlotImplemented bit is set in PCIE cap register.\r
4469 //\r
4470 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
4471 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
4472 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
4473 continue;\r
4474 }\r
4475 break;\r
4476 case PcieExplainTypeRoot:\r
4477 //\r
4478 // Root registers are only valid for\r
4479 // Root Port of PCI Express Root Complex\r
4480 //\r
4481 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
4482 continue;\r
4483 }\r
4484 break;\r
4485 default:\r
4486 break;\r
4487 }\r
4488 PcieExplainList[Index].Func (&PciExpressCap);\r
4489 }\r
4490\r
4491 Bus = (UINT8) (RShiftU64 (Address, 24));\r
4492 Dev = (UINT8) (RShiftU64 (Address, 16));\r
4493 Func = (UINT8) (RShiftU64 (Address, 8));\r
4494\r
4495 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
4496\r
4497 ExtendRegSize = 0x1000 - 0x100;\r
4498\r
4499 ExRegBuffer = (UINT8 *) AllocatePool (ExtendRegSize);\r
4500\r
4501 //\r
4502 // PciRootBridgeIo protocol should support pci express extend space IO\r
4503 // (Begins at offset 0x100)\r
4504 //\r
4505 Status = IoDev->Pci.Read (\r
4506 IoDev,\r
4507 EfiPciWidthUint32,\r
4508 Pciex_Address,\r
4509 (ExtendRegSize) / sizeof (UINT32),\r
4510 (VOID *) (ExRegBuffer)\r
4511 );\r
4512 if (EFI_ERROR (Status)) {\r
4513 FreePool ((VOID *) ExRegBuffer);\r
4514 return EFI_UNSUPPORTED;\r
4515 }\r
4516 //\r
4517 // Start outputing PciEx extend space( 0xFF-0xFFF)\r
4518 //\r
4519 Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
4520\r
4521 PrivateDumpHex (\r
4522 2,\r
4523 0x100,\r
4524 ExtendRegSize,\r
4525 (VOID *) (ExRegBuffer)\r
4526 );\r
4527\r
4528 FreePool ((VOID *) ExRegBuffer);\r
4529\r
4530Done:\r
4531 return EFI_SUCCESS;\r
4532}\r
EFI Development Kit II mirror for PVE