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ShellPkg: Add EfiIdeControllerInitProtocol to Shell’s output
[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c
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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
3737ac2b 4 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
5d73d92f 5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "UefiShellDebug1CommandsLib.h"\r
16#include <Protocol/PciRootBridgeIo.h>\r
17#include <Library/ShellLib.h>\r
18#include <IndustryStandard/Pci.h>\r
19#include <IndustryStandard/Acpi.h>\r
20#include "Pci.h"\r
21\r
22#define PCI_CLASS_STRING_LIMIT 54\r
23//\r
24// Printable strings for Pci class code\r
25//\r
26typedef struct {\r
27 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
28 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
29 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
30} PCI_CLASS_STRINGS;\r
31\r
32//\r
33// a structure holding a single entry, which also points to its lower level\r
34// class\r
35//\r
36typedef struct PCI_CLASS_ENTRY_TAG {\r
37 UINT8 Code; // Class, subclass or I/F code\r
38 CHAR16 *DescText; // Description string\r
39 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
40} PCI_CLASS_ENTRY;\r
41\r
42//\r
43// Declarations of entries which contain printable strings for class codes\r
44// in PCI configuration space\r
45//\r
46PCI_CLASS_ENTRY PCIBlankEntry[];\r
47PCI_CLASS_ENTRY PCISubClass_00[];\r
48PCI_CLASS_ENTRY PCISubClass_01[];\r
49PCI_CLASS_ENTRY PCISubClass_02[];\r
50PCI_CLASS_ENTRY PCISubClass_03[];\r
51PCI_CLASS_ENTRY PCISubClass_04[];\r
52PCI_CLASS_ENTRY PCISubClass_05[];\r
53PCI_CLASS_ENTRY PCISubClass_06[];\r
54PCI_CLASS_ENTRY PCISubClass_07[];\r
55PCI_CLASS_ENTRY PCISubClass_08[];\r
56PCI_CLASS_ENTRY PCISubClass_09[];\r
57PCI_CLASS_ENTRY PCISubClass_0a[];\r
58PCI_CLASS_ENTRY PCISubClass_0b[];\r
59PCI_CLASS_ENTRY PCISubClass_0c[];\r
60PCI_CLASS_ENTRY PCISubClass_0d[];\r
61PCI_CLASS_ENTRY PCISubClass_0e[];\r
62PCI_CLASS_ENTRY PCISubClass_0f[];\r
63PCI_CLASS_ENTRY PCISubClass_10[];\r
64PCI_CLASS_ENTRY PCISubClass_11[];\r
65PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
79\r
80//\r
81// Base class strings entries\r
82//\r
83PCI_CLASS_ENTRY gClassStringList[] = {\r
84 {\r
85 0x00,\r
86 L"Pre 2.0 device",\r
87 PCISubClass_00\r
88 },\r
89 {\r
90 0x01,\r
91 L"Mass Storage Controller",\r
92 PCISubClass_01\r
93 },\r
94 {\r
95 0x02,\r
96 L"Network Controller",\r
97 PCISubClass_02\r
98 },\r
99 {\r
100 0x03,\r
101 L"Display Controller",\r
102 PCISubClass_03\r
103 },\r
104 {\r
105 0x04,\r
106 L"Multimedia Device",\r
107 PCISubClass_04\r
108 },\r
109 {\r
110 0x05,\r
111 L"Memory Controller",\r
112 PCISubClass_05\r
113 },\r
114 {\r
115 0x06,\r
116 L"Bridge Device",\r
117 PCISubClass_06\r
118 },\r
119 {\r
120 0x07,\r
121 L"Simple Communications Controllers",\r
122 PCISubClass_07\r
123 },\r
124 {\r
125 0x08,\r
126 L"Base System Peripherals",\r
127 PCISubClass_08\r
128 },\r
129 {\r
130 0x09,\r
131 L"Input Devices",\r
132 PCISubClass_09\r
133 },\r
134 {\r
135 0x0a,\r
136 L"Docking Stations",\r
137 PCISubClass_0a\r
138 },\r
139 {\r
140 0x0b,\r
141 L"Processors",\r
142 PCISubClass_0b\r
143 },\r
144 {\r
145 0x0c,\r
146 L"Serial Bus Controllers",\r
147 PCISubClass_0c\r
148 },\r
149 {\r
150 0x0d,\r
151 L"Wireless Controllers",\r
152 PCISubClass_0d\r
153 },\r
154 {\r
155 0x0e,\r
156 L"Intelligent IO Controllers",\r
157 PCISubClass_0e\r
158 },\r
159 {\r
160 0x0f,\r
161 L"Satellite Communications Controllers",\r
162 PCISubClass_0f\r
163 },\r
164 {\r
165 0x10,\r
166 L"Encryption/Decryption Controllers",\r
167 PCISubClass_10\r
168 },\r
169 {\r
170 0x11,\r
171 L"Data Acquisition & Signal Processing Controllers",\r
172 PCISubClass_11\r
173 },\r
174 {\r
175 0xff,\r
176 L"Device does not fit in any defined classes",\r
177 PCIBlankEntry\r
178 },\r
179 {\r
180 0x00,\r
181 NULL,\r
182 /* null string ends the list */NULL\r
183 }\r
184};\r
185\r
186//\r
187// Subclass strings entries\r
188//\r
189PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
190 {\r
191 0x00,\r
192 L"",\r
193 PCIBlankEntry\r
194 },\r
195 {\r
196 0x00,\r
197 NULL,\r
198 /* null string ends the list */NULL\r
199 }\r
200};\r
201\r
202PCI_CLASS_ENTRY PCISubClass_00[] = {\r
203 {\r
204 0x00,\r
205 L"All devices other than VGA",\r
206 PCIBlankEntry\r
207 },\r
208 {\r
209 0x01,\r
210 L"VGA-compatible devices",\r
211 PCIBlankEntry\r
212 },\r
213 {\r
214 0x00,\r
215 NULL,\r
216 /* null string ends the list */NULL\r
217 }\r
218};\r
219\r
220PCI_CLASS_ENTRY PCISubClass_01[] = {\r
221 {\r
222 0x00,\r
223 L"SCSI controller",\r
224 PCIBlankEntry\r
225 },\r
226 {\r
227 0x01,\r
228 L"IDE controller",\r
229 PCIPIFClass_0101\r
230 },\r
231 {\r
232 0x02,\r
233 L"Floppy disk controller",\r
234 PCIBlankEntry\r
235 },\r
236 {\r
237 0x03,\r
238 L"IPI controller",\r
239 PCIBlankEntry\r
240 },\r
241 {\r
242 0x04,\r
243 L"RAID controller",\r
244 PCIBlankEntry\r
245 },\r
246 {\r
247 0x80,\r
248 L"Other mass storage controller",\r
249 PCIBlankEntry\r
250 },\r
251 {\r
252 0x00,\r
253 NULL,\r
254 /* null string ends the list */NULL\r
255 }\r
256};\r
257\r
258PCI_CLASS_ENTRY PCISubClass_02[] = {\r
259 {\r
260 0x00,\r
261 L"Ethernet controller",\r
262 PCIBlankEntry\r
263 },\r
264 {\r
265 0x01,\r
266 L"Token ring controller",\r
267 PCIBlankEntry\r
268 },\r
269 {\r
270 0x02,\r
271 L"FDDI controller",\r
272 PCIBlankEntry\r
273 },\r
274 {\r
275 0x03,\r
276 L"ATM controller",\r
277 PCIBlankEntry\r
278 },\r
279 {\r
280 0x04,\r
281 L"ISDN controller",\r
282 PCIBlankEntry\r
283 },\r
284 {\r
285 0x80,\r
286 L"Other network controller",\r
287 PCIBlankEntry\r
288 },\r
289 {\r
290 0x00,\r
291 NULL,\r
292 /* null string ends the list */NULL\r
293 }\r
294};\r
295\r
296PCI_CLASS_ENTRY PCISubClass_03[] = {\r
297 {\r
298 0x00,\r
299 L"VGA/8514 controller",\r
300 PCIPIFClass_0300\r
301 },\r
302 {\r
303 0x01,\r
304 L"XGA controller",\r
305 PCIBlankEntry\r
306 },\r
307 {\r
308 0x02,\r
309 L"3D controller",\r
310 PCIBlankEntry\r
311 },\r
312 {\r
313 0x80,\r
314 L"Other display controller",\r
315 PCIBlankEntry\r
316 },\r
317 {\r
318 0x00,\r
319 NULL,\r
320 /* null string ends the list */PCIBlankEntry\r
321 }\r
322};\r
323\r
324PCI_CLASS_ENTRY PCISubClass_04[] = {\r
325 {\r
326 0x00,\r
327 L"Video device",\r
328 PCIBlankEntry\r
329 },\r
330 {\r
331 0x01,\r
332 L"Audio device",\r
333 PCIBlankEntry\r
334 },\r
335 {\r
336 0x02,\r
337 L"Computer Telephony device",\r
338 PCIBlankEntry\r
339 },\r
340 {\r
341 0x80,\r
342 L"Other multimedia device",\r
343 PCIBlankEntry\r
344 },\r
345 {\r
346 0x00,\r
347 NULL,\r
348 /* null string ends the list */NULL\r
349 }\r
350};\r
351\r
352PCI_CLASS_ENTRY PCISubClass_05[] = {\r
353 {\r
354 0x00,\r
355 L"RAM memory controller",\r
356 PCIBlankEntry\r
357 },\r
358 {\r
359 0x01,\r
360 L"Flash memory controller",\r
361 PCIBlankEntry\r
362 },\r
363 {\r
364 0x80,\r
365 L"Other memory controller",\r
366 PCIBlankEntry\r
367 },\r
368 {\r
369 0x00,\r
370 NULL,\r
371 /* null string ends the list */NULL\r
372 }\r
373};\r
374\r
375PCI_CLASS_ENTRY PCISubClass_06[] = {\r
376 {\r
377 0x00,\r
378 L"Host/PCI bridge",\r
379 PCIBlankEntry\r
380 },\r
381 {\r
382 0x01,\r
383 L"PCI/ISA bridge",\r
384 PCIBlankEntry\r
385 },\r
386 {\r
387 0x02,\r
388 L"PCI/EISA bridge",\r
389 PCIBlankEntry\r
390 },\r
391 {\r
392 0x03,\r
393 L"PCI/Micro Channel bridge",\r
394 PCIBlankEntry\r
395 },\r
396 {\r
397 0x04,\r
398 L"PCI/PCI bridge",\r
399 PCIPIFClass_0604\r
400 },\r
401 {\r
402 0x05,\r
403 L"PCI/PCMCIA bridge",\r
404 PCIBlankEntry\r
405 },\r
406 {\r
407 0x06,\r
408 L"NuBus bridge",\r
409 PCIBlankEntry\r
410 },\r
411 {\r
412 0x07,\r
413 L"CardBus bridge",\r
414 PCIBlankEntry\r
415 },\r
416 {\r
417 0x08,\r
418 L"RACEway bridge",\r
419 PCIBlankEntry\r
420 },\r
421 {\r
422 0x80,\r
423 L"Other bridge type",\r
424 PCIBlankEntry\r
425 },\r
426 {\r
427 0x00,\r
428 NULL,\r
429 /* null string ends the list */NULL\r
430 }\r
431};\r
432\r
433PCI_CLASS_ENTRY PCISubClass_07[] = {\r
434 {\r
435 0x00,\r
436 L"Serial controller",\r
437 PCIPIFClass_0700\r
438 },\r
439 {\r
440 0x01,\r
441 L"Parallel port",\r
442 PCIPIFClass_0701\r
443 },\r
444 {\r
445 0x02,\r
446 L"Multiport serial controller",\r
447 PCIBlankEntry\r
448 },\r
449 {\r
450 0x03,\r
451 L"Modem",\r
452 PCIPIFClass_0703\r
453 },\r
454 {\r
455 0x80,\r
456 L"Other communication device",\r
457 PCIBlankEntry\r
458 },\r
459 {\r
460 0x00,\r
461 NULL,\r
462 /* null string ends the list */NULL\r
463 }\r
464};\r
465\r
466PCI_CLASS_ENTRY PCISubClass_08[] = {\r
467 {\r
468 0x00,\r
469 L"PIC",\r
470 PCIPIFClass_0800\r
471 },\r
472 {\r
473 0x01,\r
474 L"DMA controller",\r
475 PCIPIFClass_0801\r
476 },\r
477 {\r
478 0x02,\r
479 L"System timer",\r
480 PCIPIFClass_0802\r
481 },\r
482 {\r
483 0x03,\r
484 L"RTC controller",\r
485 PCIPIFClass_0803\r
486 },\r
487 {\r
488 0x04,\r
489 L"Generic PCI Hot-Plug controller",\r
490 PCIBlankEntry\r
491 },\r
492 {\r
493 0x80,\r
494 L"Other system peripheral",\r
495 PCIBlankEntry\r
496 },\r
497 {\r
498 0x00,\r
499 NULL,\r
500 /* null string ends the list */NULL\r
501 }\r
502};\r
503\r
504PCI_CLASS_ENTRY PCISubClass_09[] = {\r
505 {\r
506 0x00,\r
507 L"Keyboard controller",\r
508 PCIBlankEntry\r
509 },\r
510 {\r
511 0x01,\r
512 L"Digitizer (pen)",\r
513 PCIBlankEntry\r
514 },\r
515 {\r
516 0x02,\r
517 L"Mouse controller",\r
518 PCIBlankEntry\r
519 },\r
520 {\r
521 0x03,\r
522 L"Scanner controller",\r
523 PCIBlankEntry\r
524 },\r
525 {\r
526 0x04,\r
527 L"Gameport controller",\r
528 PCIPIFClass_0904\r
529 },\r
530 {\r
531 0x80,\r
532 L"Other input controller",\r
533 PCIBlankEntry\r
534 },\r
535 {\r
536 0x00,\r
537 NULL,\r
538 /* null string ends the list */NULL\r
539 }\r
540};\r
541\r
542PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
543 {\r
544 0x00,\r
545 L"Generic docking station",\r
546 PCIBlankEntry\r
547 },\r
548 {\r
549 0x80,\r
550 L"Other type of docking station",\r
551 PCIBlankEntry\r
552 },\r
553 {\r
554 0x00,\r
555 NULL,\r
556 /* null string ends the list */NULL\r
557 }\r
558};\r
559\r
560PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
561 {\r
562 0x00,\r
563 L"386",\r
564 PCIBlankEntry\r
565 },\r
566 {\r
567 0x01,\r
568 L"486",\r
569 PCIBlankEntry\r
570 },\r
571 {\r
572 0x02,\r
573 L"Pentium",\r
574 PCIBlankEntry\r
575 },\r
576 {\r
577 0x10,\r
578 L"Alpha",\r
579 PCIBlankEntry\r
580 },\r
581 {\r
582 0x20,\r
583 L"PowerPC",\r
584 PCIBlankEntry\r
585 },\r
586 {\r
587 0x30,\r
588 L"MIPS",\r
589 PCIBlankEntry\r
590 },\r
591 {\r
592 0x40,\r
593 L"Co-processor",\r
594 PCIBlankEntry\r
595 },\r
596 {\r
597 0x80,\r
598 L"Other processor",\r
599 PCIBlankEntry\r
600 },\r
601 {\r
602 0x00,\r
603 NULL,\r
604 /* null string ends the list */NULL\r
605 }\r
606};\r
607\r
608PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
609 {\r
610 0x00,\r
611 L"Firewire(IEEE 1394)",\r
612 PCIPIFClass_0c03\r
613 },\r
614 {\r
615 0x01,\r
616 L"ACCESS.bus",\r
617 PCIBlankEntry\r
618 },\r
619 {\r
620 0x02,\r
621 L"SSA",\r
622 PCIBlankEntry\r
623 },\r
624 {\r
625 0x03,\r
626 L"USB",\r
627 PCIPIFClass_0c00\r
628 },\r
629 {\r
630 0x04,\r
631 L"Fibre Channel",\r
632 PCIBlankEntry\r
633 },\r
634 {\r
635 0x05,\r
636 L"System Management Bus",\r
637 PCIBlankEntry\r
638 },\r
639 {\r
640 0x80,\r
641 L"Other bus type",\r
642 PCIBlankEntry\r
643 },\r
644 {\r
645 0x00,\r
646 NULL,\r
647 /* null string ends the list */NULL\r
648 }\r
649};\r
650\r
651PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
652 {\r
653 0x00,\r
654 L"iRDA compatible controller",\r
655 PCIBlankEntry\r
656 },\r
657 {\r
658 0x01,\r
659 L"Consumer IR controller",\r
660 PCIBlankEntry\r
661 },\r
662 {\r
663 0x10,\r
664 L"RF controller",\r
665 PCIBlankEntry\r
666 },\r
667 {\r
668 0x80,\r
669 L"Other type of wireless controller",\r
670 PCIBlankEntry\r
671 },\r
672 {\r
673 0x00,\r
674 NULL,\r
675 /* null string ends the list */NULL\r
676 }\r
677};\r
678\r
679PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
680 {\r
681 0x00,\r
682 L"I2O Architecture",\r
683 PCIPIFClass_0e00\r
684 },\r
685 {\r
686 0x00,\r
687 NULL,\r
688 /* null string ends the list */NULL\r
689 }\r
690};\r
691\r
692PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
693 {\r
694 0x00,\r
695 L"TV",\r
696 PCIBlankEntry\r
697 },\r
698 {\r
699 0x01,\r
700 L"Audio",\r
701 PCIBlankEntry\r
702 },\r
703 {\r
704 0x02,\r
705 L"Voice",\r
706 PCIBlankEntry\r
707 },\r
708 {\r
709 0x03,\r
710 L"Data",\r
711 PCIBlankEntry\r
712 },\r
713 {\r
714 0x00,\r
715 NULL,\r
716 /* null string ends the list */NULL\r
717 }\r
718};\r
719\r
720PCI_CLASS_ENTRY PCISubClass_10[] = {\r
721 {\r
722 0x00,\r
723 L"Network & computing Encrypt/Decrypt",\r
724 PCIBlankEntry\r
725 },\r
726 {\r
727 0x01,\r
728 L"Entertainment Encrypt/Decrypt",\r
729 PCIBlankEntry\r
730 },\r
731 {\r
732 0x80,\r
733 L"Other Encrypt/Decrypt",\r
734 PCIBlankEntry\r
735 },\r
736 {\r
737 0x00,\r
738 NULL,\r
739 /* null string ends the list */NULL\r
740 }\r
741};\r
742\r
743PCI_CLASS_ENTRY PCISubClass_11[] = {\r
744 {\r
745 0x00,\r
746 L"DPIO modules",\r
747 PCIBlankEntry\r
748 },\r
749 {\r
750 0x80,\r
751 L"Other DAQ & SP controllers",\r
752 PCIBlankEntry\r
753 },\r
754 {\r
755 0x00,\r
756 NULL,\r
757 /* null string ends the list */NULL\r
758 }\r
759};\r
760\r
761//\r
762// Programming Interface entries\r
763//\r
764PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
765 {\r
766 0x00,\r
767 L"",\r
768 PCIBlankEntry\r
769 },\r
770 {\r
771 0x01,\r
772 L"OM-primary",\r
773 PCIBlankEntry\r
774 },\r
775 {\r
776 0x02,\r
777 L"PI-primary",\r
778 PCIBlankEntry\r
779 },\r
780 {\r
781 0x03,\r
782 L"OM/PI-primary",\r
783 PCIBlankEntry\r
784 },\r
785 {\r
786 0x04,\r
787 L"OM-secondary",\r
788 PCIBlankEntry\r
789 },\r
790 {\r
791 0x05,\r
792 L"OM-primary, OM-secondary",\r
793 PCIBlankEntry\r
794 },\r
795 {\r
796 0x06,\r
797 L"PI-primary, OM-secondary",\r
798 PCIBlankEntry\r
799 },\r
800 {\r
801 0x07,\r
802 L"OM/PI-primary, OM-secondary",\r
803 PCIBlankEntry\r
804 },\r
805 {\r
806 0x08,\r
807 L"OM-secondary",\r
808 PCIBlankEntry\r
809 },\r
810 {\r
811 0x09,\r
812 L"OM-primary, PI-secondary",\r
813 PCIBlankEntry\r
814 },\r
815 {\r
816 0x0a,\r
817 L"PI-primary, PI-secondary",\r
818 PCIBlankEntry\r
819 },\r
820 {\r
821 0x0b,\r
822 L"OM/PI-primary, PI-secondary",\r
823 PCIBlankEntry\r
824 },\r
825 {\r
826 0x0c,\r
827 L"OM-secondary",\r
828 PCIBlankEntry\r
829 },\r
830 {\r
831 0x0d,\r
832 L"OM-primary, OM/PI-secondary",\r
833 PCIBlankEntry\r
834 },\r
835 {\r
836 0x0e,\r
837 L"PI-primary, OM/PI-secondary",\r
838 PCIBlankEntry\r
839 },\r
840 {\r
841 0x0f,\r
842 L"OM/PI-primary, OM/PI-secondary",\r
843 PCIBlankEntry\r
844 },\r
845 {\r
846 0x80,\r
847 L"Master",\r
848 PCIBlankEntry\r
849 },\r
850 {\r
851 0x81,\r
852 L"Master, OM-primary",\r
853 PCIBlankEntry\r
854 },\r
855 {\r
856 0x82,\r
857 L"Master, PI-primary",\r
858 PCIBlankEntry\r
859 },\r
860 {\r
861 0x83,\r
862 L"Master, OM/PI-primary",\r
863 PCIBlankEntry\r
864 },\r
865 {\r
866 0x84,\r
867 L"Master, OM-secondary",\r
868 PCIBlankEntry\r
869 },\r
870 {\r
871 0x85,\r
872 L"Master, OM-primary, OM-secondary",\r
873 PCIBlankEntry\r
874 },\r
875 {\r
876 0x86,\r
877 L"Master, PI-primary, OM-secondary",\r
878 PCIBlankEntry\r
879 },\r
880 {\r
881 0x87,\r
882 L"Master, OM/PI-primary, OM-secondary",\r
883 PCIBlankEntry\r
884 },\r
885 {\r
886 0x88,\r
887 L"Master, OM-secondary",\r
888 PCIBlankEntry\r
889 },\r
890 {\r
891 0x89,\r
892 L"Master, OM-primary, PI-secondary",\r
893 PCIBlankEntry\r
894 },\r
895 {\r
896 0x8a,\r
897 L"Master, PI-primary, PI-secondary",\r
898 PCIBlankEntry\r
899 },\r
900 {\r
901 0x8b,\r
902 L"Master, OM/PI-primary, PI-secondary",\r
903 PCIBlankEntry\r
904 },\r
905 {\r
906 0x8c,\r
907 L"Master, OM-secondary",\r
908 PCIBlankEntry\r
909 },\r
910 {\r
911 0x8d,\r
912 L"Master, OM-primary, OM/PI-secondary",\r
913 PCIBlankEntry\r
914 },\r
915 {\r
916 0x8e,\r
917 L"Master, PI-primary, OM/PI-secondary",\r
918 PCIBlankEntry\r
919 },\r
920 {\r
921 0x8f,\r
922 L"Master, OM/PI-primary, OM/PI-secondary",\r
923 PCIBlankEntry\r
924 },\r
925 {\r
926 0x00,\r
927 NULL,\r
928 /* null string ends the list */NULL\r
929 }\r
930};\r
931\r
932PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
933 {\r
934 0x00,\r
935 L"VGA compatible",\r
936 PCIBlankEntry\r
937 },\r
938 {\r
939 0x01,\r
940 L"8514 compatible",\r
941 PCIBlankEntry\r
942 },\r
943 {\r
944 0x00,\r
945 NULL,\r
946 /* null string ends the list */NULL\r
947 }\r
948};\r
949\r
950PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
951 {\r
952 0x00,\r
953 L"",\r
954 PCIBlankEntry\r
955 },\r
956 {\r
957 0x01,\r
958 L"Subtractive decode",\r
959 PCIBlankEntry\r
960 },\r
961 {\r
962 0x00,\r
963 NULL,\r
964 /* null string ends the list */NULL\r
965 }\r
966};\r
967\r
968PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
969 {\r
970 0x00,\r
971 L"Generic XT-compatible",\r
972 PCIBlankEntry\r
973 },\r
974 {\r
975 0x01,\r
976 L"16450-compatible",\r
977 PCIBlankEntry\r
978 },\r
979 {\r
980 0x02,\r
981 L"16550-compatible",\r
982 PCIBlankEntry\r
983 },\r
984 {\r
985 0x03,\r
986 L"16650-compatible",\r
987 PCIBlankEntry\r
988 },\r
989 {\r
990 0x04,\r
991 L"16750-compatible",\r
992 PCIBlankEntry\r
993 },\r
994 {\r
995 0x05,\r
996 L"16850-compatible",\r
997 PCIBlankEntry\r
998 },\r
999 {\r
1000 0x06,\r
1001 L"16950-compatible",\r
1002 PCIBlankEntry\r
1003 },\r
1004 {\r
1005 0x00,\r
1006 NULL,\r
1007 /* null string ends the list */NULL\r
1008 }\r
1009};\r
1010\r
1011PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1012 {\r
1013 0x00,\r
1014 L"",\r
1015 PCIBlankEntry\r
1016 },\r
1017 {\r
1018 0x01,\r
1019 L"Bi-directional",\r
1020 PCIBlankEntry\r
1021 },\r
1022 {\r
1023 0x02,\r
1024 L"ECP 1.X-compliant",\r
1025 PCIBlankEntry\r
1026 },\r
1027 {\r
1028 0x03,\r
1029 L"IEEE 1284",\r
1030 PCIBlankEntry\r
1031 },\r
1032 {\r
1033 0xfe,\r
1034 L"IEEE 1284 target (not a controller)",\r
1035 PCIBlankEntry\r
1036 },\r
1037 {\r
1038 0x00,\r
1039 NULL,\r
1040 /* null string ends the list */NULL\r
1041 }\r
1042};\r
1043\r
1044PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1045 {\r
1046 0x00,\r
1047 L"Generic",\r
1048 PCIBlankEntry\r
1049 },\r
1050 {\r
1051 0x01,\r
1052 L"Hayes-compatible 16450",\r
1053 PCIBlankEntry\r
1054 },\r
1055 {\r
1056 0x02,\r
1057 L"Hayes-compatible 16550",\r
1058 PCIBlankEntry\r
1059 },\r
1060 {\r
1061 0x03,\r
1062 L"Hayes-compatible 16650",\r
1063 PCIBlankEntry\r
1064 },\r
1065 {\r
1066 0x04,\r
1067 L"Hayes-compatible 16750",\r
1068 PCIBlankEntry\r
1069 },\r
1070 {\r
1071 0x00,\r
1072 NULL,\r
1073 /* null string ends the list */NULL\r
1074 }\r
1075};\r
1076\r
1077PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1078 {\r
1079 0x00,\r
1080 L"Generic 8259",\r
1081 PCIBlankEntry\r
1082 },\r
1083 {\r
1084 0x01,\r
1085 L"ISA",\r
1086 PCIBlankEntry\r
1087 },\r
1088 {\r
1089 0x02,\r
1090 L"EISA",\r
1091 PCIBlankEntry\r
1092 },\r
1093 {\r
1094 0x10,\r
1095 L"IO APIC",\r
1096 PCIBlankEntry\r
1097 },\r
1098 {\r
1099 0x20,\r
1100 L"IO(x) APIC interrupt controller",\r
1101 PCIBlankEntry\r
1102 },\r
1103 {\r
1104 0x00,\r
1105 NULL,\r
1106 /* null string ends the list */NULL\r
1107 }\r
1108};\r
1109\r
1110PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1111 {\r
1112 0x00,\r
1113 L"Generic 8237",\r
1114 PCIBlankEntry\r
1115 },\r
1116 {\r
1117 0x01,\r
1118 L"ISA",\r
1119 PCIBlankEntry\r
1120 },\r
1121 {\r
1122 0x02,\r
1123 L"EISA",\r
1124 PCIBlankEntry\r
1125 },\r
1126 {\r
1127 0x00,\r
1128 NULL,\r
1129 /* null string ends the list */NULL\r
1130 }\r
1131};\r
1132\r
1133PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1134 {\r
1135 0x00,\r
1136 L"Generic 8254",\r
1137 PCIBlankEntry\r
1138 },\r
1139 {\r
1140 0x01,\r
1141 L"ISA",\r
1142 PCIBlankEntry\r
1143 },\r
1144 {\r
1145 0x02,\r
1146 L"EISA",\r
1147 PCIBlankEntry\r
1148 },\r
1149 {\r
1150 0x00,\r
1151 NULL,\r
1152 /* null string ends the list */NULL\r
1153 }\r
1154};\r
1155\r
1156PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1157 {\r
1158 0x00,\r
1159 L"Generic",\r
1160 PCIBlankEntry\r
1161 },\r
1162 {\r
1163 0x01,\r
1164 L"ISA",\r
1165 PCIBlankEntry\r
1166 },\r
1167 {\r
1168 0x02,\r
1169 L"EISA",\r
1170 PCIBlankEntry\r
1171 },\r
1172 {\r
1173 0x00,\r
1174 NULL,\r
1175 /* null string ends the list */NULL\r
1176 }\r
1177};\r
1178\r
1179PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1180 {\r
1181 0x00,\r
1182 L"Generic",\r
1183 PCIBlankEntry\r
1184 },\r
1185 {\r
1186 0x10,\r
1187 L"",\r
1188 PCIBlankEntry\r
1189 },\r
1190 {\r
1191 0x00,\r
1192 NULL,\r
1193 /* null string ends the list */NULL\r
1194 }\r
1195};\r
1196\r
1197PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1198 {\r
1199 0x00,\r
1200 L"Universal Host Controller spec",\r
1201 PCIBlankEntry\r
1202 },\r
1203 {\r
1204 0x10,\r
1205 L"Open Host Controller spec",\r
1206 PCIBlankEntry\r
1207 },\r
1208 {\r
1209 0x80,\r
1210 L"No specific programming interface",\r
1211 PCIBlankEntry\r
1212 },\r
1213 {\r
1214 0xfe,\r
1215 L"(Not Host Controller)",\r
1216 PCIBlankEntry\r
1217 },\r
1218 {\r
1219 0x00,\r
1220 NULL,\r
1221 /* null string ends the list */NULL\r
1222 }\r
1223};\r
1224\r
1225PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1226 {\r
1227 0x00,\r
1228 L"",\r
1229 PCIBlankEntry\r
1230 },\r
1231 {\r
1232 0x10,\r
1233 L"Using 1394 OpenHCI spec",\r
1234 PCIBlankEntry\r
1235 },\r
1236 {\r
1237 0x00,\r
1238 NULL,\r
1239 /* null string ends the list */NULL\r
1240 }\r
1241};\r
1242\r
1243PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1244 {\r
1245 0x00,\r
1246 L"Message FIFO at offset 40h",\r
1247 PCIBlankEntry\r
1248 },\r
1249 {\r
1250 0x01,\r
1251 L"",\r
1252 PCIBlankEntry\r
1253 },\r
1254 {\r
1255 0x00,\r
1256 NULL,\r
1257 /* null string ends the list */NULL\r
1258 }\r
1259};\r
1260\r
5d73d92f 1261\r
a1d4bfcc 1262/**\r
5d73d92f 1263 Generates printable Unicode strings that represent PCI device class,\r
1264 subclass and programmed I/F based on a value passed to the function.\r
1265\r
a1d4bfcc 1266 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
5d73d92f 1267 PCI device. The encodings are:\r
1268 bits 23:16 - Base Class Code\r
1269 bits 15:8 - Sub-Class Code\r
1270 bits 7:0 - Programming Interface\r
4ff7e37b 1271 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
5d73d92f 1272 printable class strings corresponding to ClassCode. The\r
1273 caller must not modify the strings that are pointed by\r
1274 the fields in ClassStrings.\r
5d73d92f 1275**/\r
a1d4bfcc 1276VOID\r
1277PciGetClassStrings (\r
1278 IN UINT32 ClassCode,\r
1279 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1280 )\r
5d73d92f 1281{\r
1282 INTN Index;\r
1283 UINT8 Code;\r
1284 PCI_CLASS_ENTRY *CurrentClass;\r
1285\r
1286 //\r
1287 // Assume no strings found\r
1288 //\r
1289 ClassStrings->BaseClass = L"UNDEFINED";\r
1290 ClassStrings->SubClass = L"UNDEFINED";\r
1291 ClassStrings->PIFClass = L"UNDEFINED";\r
1292\r
1293 CurrentClass = gClassStringList;\r
1294 Code = (UINT8) (ClassCode >> 16);\r
1295 Index = 0;\r
1296\r
1297 //\r
1298 // Go through all entries of the base class, until the entry with a matching\r
1299 // base class code is found. If reaches an entry with a null description\r
1300 // text, the last entry is met, which means no text for the base class was\r
1301 // found, so no more action is needed.\r
1302 //\r
1303 while (Code != CurrentClass[Index].Code) {\r
1304 if (NULL == CurrentClass[Index].DescText) {\r
1305 return ;\r
1306 }\r
1307\r
1308 Index++;\r
1309 }\r
1310 //\r
1311 // A base class was found. Assign description, and check if this class has\r
1312 // sub-class defined. If sub-class defined, no more action is needed,\r
1313 // otherwise, continue to find description for the sub-class code.\r
1314 //\r
1315 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1316 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1317 return ;\r
1318 }\r
1319 //\r
1320 // find Subclass entry\r
1321 //\r
1322 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1323 Code = (UINT8) (ClassCode >> 8);\r
1324 Index = 0;\r
1325\r
1326 //\r
1327 // Go through all entries of the sub-class, until the entry with a matching\r
1328 // sub-class code is found. If reaches an entry with a null description\r
1329 // text, the last entry is met, which means no text for the sub-class was\r
1330 // found, so no more action is needed.\r
1331 //\r
1332 while (Code != CurrentClass[Index].Code) {\r
1333 if (NULL == CurrentClass[Index].DescText) {\r
1334 return ;\r
1335 }\r
1336\r
1337 Index++;\r
1338 }\r
1339 //\r
1340 // A class was found for the sub-class code. Assign description, and check if\r
1341 // this sub-class has programming interface defined. If no, no more action is\r
1342 // needed, otherwise, continue to find description for the programming\r
1343 // interface.\r
1344 //\r
1345 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1346 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1347 return ;\r
1348 }\r
1349 //\r
1350 // Find programming interface entry\r
1351 //\r
1352 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1353 Code = (UINT8) ClassCode;\r
1354 Index = 0;\r
1355\r
1356 //\r
1357 // Go through all entries of the I/F entries, until the entry with a\r
1358 // matching I/F code is found. If reaches an entry with a null description\r
1359 // text, the last entry is met, which means no text was found, so no more\r
1360 // action is needed.\r
1361 //\r
1362 while (Code != CurrentClass[Index].Code) {\r
1363 if (NULL == CurrentClass[Index].DescText) {\r
1364 return ;\r
1365 }\r
1366\r
1367 Index++;\r
1368 }\r
1369 //\r
1370 // A class was found for the I/F code. Assign description, done!\r
1371 //\r
1372 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1373 return ;\r
1374}\r
1375\r
a1d4bfcc 1376/**\r
1377 Print strings that represent PCI device class, subclass and programmed I/F.\r
1378\r
1379 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1380 configuation space.\r
1381 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1382**/\r
5d73d92f 1383VOID\r
1384PciPrintClassCode (\r
1385 IN UINT8 *ClassCodePtr,\r
1386 IN BOOLEAN IncludePIF\r
1387 )\r
5d73d92f 1388{\r
1389 UINT32 ClassCode;\r
1390 PCI_CLASS_STRINGS ClassStrings;\r
1391 CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];\r
1392\r
1393 ClassCode = 0;\r
1394 ClassCode |= ClassCodePtr[0];\r
1395 ClassCode |= (ClassCodePtr[1] << 8);\r
1396 ClassCode |= (ClassCodePtr[2] << 16);\r
1397\r
1398 //\r
1399 // Get name from class code\r
1400 //\r
1401 PciGetClassStrings (ClassCode, &ClassStrings);\r
1402\r
1403 if (IncludePIF) {\r
1404 //\r
1405 // Only print base class and sub class name\r
1406 //\r
1407 ShellPrintEx(-1,-1, L"%s - %s - %s",\r
1408 ClassStrings.BaseClass,\r
1409 ClassStrings.SubClass,\r
1410 ClassStrings.PIFClass\r
1411 );\r
1412\r
1413 } else {\r
1414 //\r
1415 // Print base class, sub class, and programming inferface name\r
1416 //\r
1417 UnicodeSPrint (\r
1418 OutputString,\r
1419 PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),\r
1420 L"%s - %s",\r
1421 ClassStrings.BaseClass,\r
1422 ClassStrings.SubClass\r
1423 );\r
1424\r
1425 OutputString[PCI_CLASS_STRING_LIMIT] = 0;\r
1426 ShellPrintEx(-1,-1, L"%s", OutputString);\r
1427 }\r
1428}\r
1429\r
a1d4bfcc 1430/**\r
1431 This function finds out the protocol which is in charge of the given\r
1432 segment, and its bus range covers the current bus number. It lookes\r
1433 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1434 criteria is found.\r
1435\r
1436 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1437 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1438 @param[in] Segment Segment number of device we are dealing with.\r
1439 @param[in] Bus Bus number of device we are dealing with.\r
1440 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1441\r
1442 @retval EFI_SUCCESS The command completed successfully.\r
1443 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 1444\r
a1d4bfcc 1445**/\r
5d73d92f 1446EFI_STATUS\r
1447PciFindProtocolInterface (\r
1448 IN EFI_HANDLE *HandleBuf,\r
1449 IN UINTN HandleCount,\r
1450 IN UINT16 Segment,\r
1451 IN UINT16 Bus,\r
1452 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1453 );\r
1454\r
a1d4bfcc 1455/**\r
1456 This function gets the protocol interface from the given handle, and\r
1457 obtains its address space descriptors.\r
1458\r
1459 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1460 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1461 @param[out] Descriptors Points to the address space descriptors.\r
1462\r
1463 @retval EFI_SUCCESS The command completed successfully\r
1464**/\r
5d73d92f 1465EFI_STATUS\r
1466PciGetProtocolAndResource (\r
1467 IN EFI_HANDLE Handle,\r
1468 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1469 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1470 );\r
1471\r
a1d4bfcc 1472/**\r
1473 This function get the next bus range of given address space descriptors.\r
1474 It also moves the pointer backward a node, to get prepared to be called\r
1475 again.\r
1476\r
4ff7e37b
ED		 1477 @param[in, out] Descriptors Points to current position of a serial of address space\r
1478 descriptors.\r
1479 @param[out] MinBus The lower range of bus number.\r
1480 @param[out] MaxBus The upper range of bus number.\r
1481 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 1482\r
1483 @retval EFI_SUCCESS The command completed successfully.\r
1484**/\r
5d73d92f 1485EFI_STATUS\r
1486PciGetNextBusRange (\r
1487 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1488 OUT UINT16 *MinBus,\r
1489 OUT UINT16 *MaxBus,\r
1490 OUT BOOLEAN *IsEnd\r
1491 );\r
1492\r
a1d4bfcc 1493/**\r
1494 Explain the data in PCI configuration space. The part which is common for\r
1495 PCI device and bridge is interpreted in this function. It calls other\r
1496 functions to interpret data unique for device or bridge.\r
1497\r
1498 @param[in] ConfigSpace Data in PCI configuration space.\r
1499 @param[in] Address Address used to access configuration space of this PCI device.\r
1500 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1501\r
1502 @retval EFI_SUCCESS The command completed successfully.\r
1503**/\r
5d73d92f 1504EFI_STATUS\r
1505PciExplainData (\r
1506 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1507 IN UINT64 Address,\r
1508 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1509 );\r
1510\r
a1d4bfcc 1511/**\r
1512 Explain the device specific part of data in PCI configuration space.\r
1513\r
1514 @param[in] Device Data in PCI configuration space.\r
1515 @param[in] Address Address used to access configuration space of this PCI device.\r
1516 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1517\r
1518 @retval EFI_SUCCESS The command completed successfully.\r
1519**/\r
5d73d92f 1520EFI_STATUS\r
1521PciExplainDeviceData (\r
1522 IN PCI_DEVICE_HEADER *Device,\r
1523 IN UINT64 Address,\r
1524 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1525 );\r
1526\r
a1d4bfcc 1527/**\r
1528 Explain the bridge specific part of data in PCI configuration space.\r
1529\r
1530 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1531 @param[in] Address Address used to access configuration space of this PCI device.\r
1532 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1533\r
1534 @retval EFI_SUCCESS The command completed successfully.\r
1535**/\r
5d73d92f 1536EFI_STATUS\r
1537PciExplainBridgeData (\r
a1d4bfcc 1538 IN PCI_BRIDGE_HEADER *Bridge,\r
1539 IN UINT64 Address,\r
1540 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
5d73d92f 1541 );\r
1542\r
a1d4bfcc 1543/**\r
1544 Explain the Base Address Register(Bar) in PCI configuration space.\r
1545\r
4ff7e37b
ED		 1546 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1547 @param[in] Command Points to the register Command.\r
1548 @param[in] Address Address used to access configuration space of this PCI device.\r
1549 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1550 @param[in, out] Index The Index.\r
a1d4bfcc 1551\r
1552 @retval EFI_SUCCESS The command completed successfully.\r
1553**/\r
5d73d92f 1554EFI_STATUS\r
1555PciExplainBar (\r
1556 IN UINT32 *Bar,\r
1557 IN UINT16 *Command,\r
1558 IN UINT64 Address,\r
1559 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1560 IN OUT UINTN *Index\r
1561 );\r
1562\r
a1d4bfcc 1563/**\r
1564 Explain the cardbus specific part of data in PCI configuration space.\r
1565\r
1566 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1567 @param[in] Address Address used to access configuration space of this PCI device.\r
1568 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1569\r
1570 @retval EFI_SUCCESS The command completed successfully.\r
1571**/\r
5d73d92f 1572EFI_STATUS\r
1573PciExplainCardBusData (\r
1574 IN PCI_CARDBUS_HEADER *CardBus,\r
1575 IN UINT64 Address,\r
1576 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1577 );\r
1578\r
a1d4bfcc 1579/**\r
1580 Explain each meaningful bit of register Status. The definition of Status is\r
1581 slightly different depending on the PCI header type.\r
1582\r
1583 @param[in] Status Points to the content of register Status.\r
1584 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1585 status).\r
1586 @param[in] HeaderType Header type of this PCI device.\r
1587\r
1588 @retval EFI_SUCCESS The command completed successfully.\r
1589**/\r
5d73d92f 1590EFI_STATUS\r
1591PciExplainStatus (\r
1592 IN UINT16 *Status,\r
1593 IN BOOLEAN MainStatus,\r
1594 IN PCI_HEADER_TYPE HeaderType\r
1595 );\r
1596\r
a1d4bfcc 1597/**\r
1598 Explain each meaningful bit of register Command.\r
1599\r
1600 @param[in] Command Points to the content of register Command.\r
1601\r
1602 @retval EFI_SUCCESS The command completed successfully.\r
1603**/\r
5d73d92f 1604EFI_STATUS\r
1605PciExplainCommand (\r
1606 IN UINT16 *Command\r
1607 );\r
1608\r
a1d4bfcc 1609/**\r
1610 Explain each meaningful bit of register Bridge Control.\r
1611\r
1612 @param[in] BridgeControl Points to the content of register Bridge Control.\r
1613 @param[in] HeaderType The headertype.\r
1614\r
1615 @retval EFI_SUCCESS The command completed successfully.\r
1616**/\r
5d73d92f 1617EFI_STATUS\r
1618PciExplainBridgeControl (\r
1619 IN UINT16 *BridgeControl,\r
1620 IN PCI_HEADER_TYPE HeaderType\r
1621 );\r
1622\r
a1d4bfcc 1623/**\r
1624 Print each capability structure.\r
1625\r
1626 @param[in] IoDev The pointer to the deivce.\r
1627 @param[in] Address The address to start at.\r
1628 @param[in] CapPtr The offset from the address.\r
1629\r
1630 @retval EFI_SUCCESS The operation was successful.\r
1631**/\r
5d73d92f 1632EFI_STATUS\r
1633PciExplainCapabilityStruct (\r
1634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1635 IN UINT64 Address,\r
1636 IN UINT8 CapPtr\r
1637 );\r
1638\r
a1d4bfcc 1639/**\r
1640 Display Pcie device structure.\r
1641\r
1642 @param[in] IoDev The pointer to the root pci protocol.\r
1643 @param[in] Address The Address to start at.\r
1644 @param[in] CapabilityPtr The offset from the address to start.\r
1645**/\r
5d73d92f 1646EFI_STATUS\r
1647PciExplainPciExpress (\r
1648 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1649 IN UINT64 Address,\r
1650 IN UINT8 CapabilityPtr\r
1651 );\r
1652\r
a1d4bfcc 1653/**\r
1654 Print out information of the capability information.\r
1655\r
1656 @param[in] PciExpressCap The pointer to the structure about the device.\r
1657\r
1658 @retval EFI_SUCCESS The operation was successful.\r
1659**/\r
5d73d92f 1660EFI_STATUS\r
1661ExplainPcieCapReg (\r
1662 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1663 );\r
1664\r
1665/**\r
1666 Print out information of the device capability information.\r
1667\r
1668 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1669\r
a1d4bfcc 1670 @retval EFI_SUCCESS The operation was successful.\r
1671**/\r
5d73d92f 1672EFI_STATUS\r
1673ExplainPcieDeviceCap (\r
1674 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1675 );\r
1676\r
1677/**\r
1678 Print out information of the device control information.\r
5d73d92f 1679\r
a1d4bfcc 1680 @param[in] PciExpressCap The pointer to the structure about the device.\r
1681\r
1682 @retval EFI_SUCCESS The operation was successful.\r
1683**/\r
5d73d92f 1684EFI_STATUS\r
1685ExplainPcieDeviceControl (\r
1686 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1687 );\r
5d73d92f 1688\r
a1d4bfcc 1689/**\r
1690 Print out information of the device status information.\r
1691\r
1692 @param[in] PciExpressCap The pointer to the structure about the device.\r
1693\r
1694 @retval EFI_SUCCESS The operation was successful.\r
1695**/\r
5d73d92f 1696EFI_STATUS\r
1697ExplainPcieDeviceStatus (\r
1698 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1699 );\r
1700\r
1701/**\r
1702 Print out information of the device link information.\r
1703\r
1704 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1705\r
a1d4bfcc 1706 @retval EFI_SUCCESS The operation was successful.\r
1707**/\r
5d73d92f 1708EFI_STATUS\r
1709ExplainPcieLinkCap (\r
1710 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1711 );\r
1712\r
1713/**\r
1714 Print out information of the device link control information.\r
5d73d92f 1715\r
a1d4bfcc 1716 @param[in] PciExpressCap The pointer to the structure about the device.\r
1717\r
1718 @retval EFI_SUCCESS The operation was successful.\r
1719**/\r
5d73d92f 1720EFI_STATUS\r
1721ExplainPcieLinkControl (\r
1722 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1723 );\r
5d73d92f 1724\r
a1d4bfcc 1725/**\r
1726 Print out information of the device link status information.\r
1727\r
1728 @param[in] PciExpressCap The pointer to the structure about the device.\r
1729\r
1730 @retval EFI_SUCCESS The operation was successful.\r
1731**/\r
5d73d92f 1732EFI_STATUS\r
1733ExplainPcieLinkStatus (\r
1734 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1735 );\r
1736\r
1737/**\r
1738 Print out information of the device slot information.\r
1739\r
1740 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1741\r
a1d4bfcc 1742 @retval EFI_SUCCESS The operation was successful.\r
1743**/\r
5d73d92f 1744EFI_STATUS\r
1745ExplainPcieSlotCap (\r
1746 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1747 );\r
1748\r
1749/**\r
1750 Print out information of the device slot control information.\r
5d73d92f 1751\r
a1d4bfcc 1752 @param[in] PciExpressCap The pointer to the structure about the device.\r
1753\r
1754 @retval EFI_SUCCESS The operation was successful.\r
1755**/\r
5d73d92f 1756EFI_STATUS\r
1757ExplainPcieSlotControl (\r
1758 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1759 );\r
5d73d92f 1760\r
a1d4bfcc 1761/**\r
1762 Print out information of the device slot status information.\r
1763\r
1764 @param[in] PciExpressCap The pointer to the structure about the device.\r
1765\r
1766 @retval EFI_SUCCESS The operation was successful.\r
1767**/\r
5d73d92f 1768EFI_STATUS\r
1769ExplainPcieSlotStatus (\r
1770 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1771 );\r
1772\r
1773/**\r
1774 Print out information of the device root information.\r
1775\r
1776 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1777\r
a1d4bfcc 1778 @retval EFI_SUCCESS The operation was successful.\r
1779**/\r
5d73d92f 1780EFI_STATUS\r
1781ExplainPcieRootControl (\r
1782 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1783 );\r
1784\r
1785/**\r
1786 Print out information of the device root capability information.\r
5d73d92f 1787\r
a1d4bfcc 1788 @param[in] PciExpressCap The pointer to the structure about the device.\r
1789\r
1790 @retval EFI_SUCCESS The operation was successful.\r
1791**/\r
5d73d92f 1792EFI_STATUS\r
1793ExplainPcieRootCap (\r
1794 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1795 );\r
5d73d92f 1796\r
a1d4bfcc 1797/**\r
1798 Print out information of the device root status information.\r
1799\r
1800 @param[in] PciExpressCap The pointer to the structure about the device.\r
1801\r
1802 @retval EFI_SUCCESS The operation was successful.\r
1803**/\r
5d73d92f 1804EFI_STATUS\r
1805ExplainPcieRootStatus (\r
1806 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1807 );\r
5d73d92f 1808\r
1809typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1810\r
1811typedef enum {\r
1812 FieldWidthUINT8,\r
1813 FieldWidthUINT16,\r
1814 FieldWidthUINT32\r
1815} PCIE_CAPREG_FIELD_WIDTH;\r
1816\r
1817typedef enum {\r
1818 PcieExplainTypeCommon,\r
1819 PcieExplainTypeDevice,\r
1820 PcieExplainTypeLink,\r
1821 PcieExplainTypeSlot,\r
1822 PcieExplainTypeRoot,\r
1823 PcieExplainTypeMax\r
1824} PCIE_EXPLAIN_TYPE;\r
1825\r
1826typedef struct\r
1827{\r
1828 UINT16 Token;\r
1829 UINTN Offset;\r
1830 PCIE_CAPREG_FIELD_WIDTH Width;\r
1831 PCIE_EXPLAIN_FUNCTION Func;\r
1832 PCIE_EXPLAIN_TYPE Type;\r
1833} PCIE_EXPLAIN_STRUCT;\r
1834\r
1835PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1836 {\r
1837 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1838 0x00,\r
1839 FieldWidthUINT8,\r
1840 NULL,\r
1841 PcieExplainTypeCommon\r
1842 },\r
1843 {\r
1844 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1845 0x01,\r
1846 FieldWidthUINT8,\r
1847 NULL,\r
1848 PcieExplainTypeCommon\r
1849 },\r
1850 {\r
1851 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1852 0x02,\r
1853 FieldWidthUINT16,\r
1854 ExplainPcieCapReg,\r
1855 PcieExplainTypeCommon\r
1856 },\r
1857 {\r
1858 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1859 0x04,\r
1860 FieldWidthUINT32,\r
1861 ExplainPcieDeviceCap,\r
1862 PcieExplainTypeDevice\r
1863 },\r
1864 {\r
1865 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1866 0x08,\r
1867 FieldWidthUINT16,\r
1868 ExplainPcieDeviceControl,\r
1869 PcieExplainTypeDevice\r
1870 },\r
1871 {\r
1872 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1873 0x0a,\r
1874 FieldWidthUINT16,\r
1875 ExplainPcieDeviceStatus,\r
1876 PcieExplainTypeDevice\r
1877 },\r
1878 {\r
1879 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1880 0x0c,\r
1881 FieldWidthUINT32,\r
1882 ExplainPcieLinkCap,\r
1883 PcieExplainTypeLink\r
1884 },\r
1885 {\r
1886 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1887 0x10,\r
1888 FieldWidthUINT16,\r
1889 ExplainPcieLinkControl,\r
1890 PcieExplainTypeLink\r
1891 },\r
1892 {\r
1893 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1894 0x12,\r
1895 FieldWidthUINT16,\r
1896 ExplainPcieLinkStatus,\r
1897 PcieExplainTypeLink\r
1898 },\r
1899 {\r
1900 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1901 0x14,\r
1902 FieldWidthUINT32,\r
1903 ExplainPcieSlotCap,\r
1904 PcieExplainTypeSlot\r
1905 },\r
1906 {\r
1907 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1908 0x18,\r
1909 FieldWidthUINT16,\r
1910 ExplainPcieSlotControl,\r
1911 PcieExplainTypeSlot\r
1912 },\r
1913 {\r
1914 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1915 0x1a,\r
1916 FieldWidthUINT16,\r
1917 ExplainPcieSlotStatus,\r
1918 PcieExplainTypeSlot\r
1919 },\r
1920 {\r
1921 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1922 0x1c,\r
1923 FieldWidthUINT16,\r
1924 ExplainPcieRootControl,\r
1925 PcieExplainTypeRoot\r
1926 },\r
1927 {\r
1928 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1929 0x1e,\r
1930 FieldWidthUINT16,\r
1931 ExplainPcieRootCap,\r
1932 PcieExplainTypeRoot\r
1933 },\r
1934 {\r
1935 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1936 0x20,\r
1937 FieldWidthUINT32,\r
1938 ExplainPcieRootStatus,\r
1939 PcieExplainTypeRoot\r
1940 },\r
1941 {\r
1942 0,\r
1943 0,\r
1944 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1945 NULL,\r
1946 PcieExplainTypeMax\r
1947 }\r
1948};\r
1949\r
1950//\r
1951// Global Variables\r
1952//\r
1953PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1954STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1955 {L"-s", TypeValue},\r
1956 {L"-i", TypeFlag},\r
1957 {NULL, TypeMax}\r
1958 };\r
1959\r
1960CHAR16 *DevicePortTypeTable[] = {\r
1961 L"PCI Express Endpoint",\r
1962 L"Legacy PCI Express Endpoint",\r
1963 L"Unknown Type",\r
1964 L"Unknonw Type",\r
1965 L"Root Port of PCI Express Root Complex",\r
1966 L"Upstream Port of PCI Express Switch",\r
1967 L"Downstream Port of PCI Express Switch",\r
1968 L"PCI Express to PCI/PCI-X Bridge",\r
1969 L"PCI/PCI-X to PCI Express Bridge",\r
1970 L"Root Complex Integrated Endpoint",\r
1971 L"Root Complex Event Collector"\r
1972};\r
1973\r
1974CHAR16 *L0sLatencyStrTable[] = {\r
1975 L"Less than 64ns",\r
1976 L"64ns to less than 128ns",\r
1977 L"128ns to less than 256ns",\r
1978 L"256ns to less than 512ns",\r
1979 L"512ns to less than 1us",\r
1980 L"1us to less than 2us",\r
1981 L"2us-4us",\r
1982 L"More than 4us"\r
1983};\r
1984\r
1985CHAR16 *L1LatencyStrTable[] = {\r
1986 L"Less than 1us",\r
1987 L"1us to less than 2us",\r
1988 L"2us to less than 4us",\r
1989 L"4us to less than 8us",\r
1990 L"8us to less than 16us",\r
1991 L"16us to less than 32us",\r
1992 L"32us-64us",\r
1993 L"More than 64us"\r
1994};\r
1995\r
1996CHAR16 *ASPMCtrlStrTable[] = {\r
1997 L"Disabled",\r
1998 L"L0s Entry Enabled",\r
1999 L"L1 Entry Enabled",\r
2000 L"L0s and L1 Entry Enabled"\r
2001};\r
2002\r
2003CHAR16 *SlotPwrLmtScaleTable[] = {\r
2004 L"1.0x",\r
2005 L"0.1x",\r
2006 L"0.01x",\r
2007 L"0.001x"\r
2008};\r
2009\r
2010CHAR16 *IndicatorTable[] = {\r
2011 L"Reserved",\r
2012 L"On",\r
2013 L"Blink",\r
2014 L"Off"\r
2015};\r
2016\r
2017\r
a1d4bfcc 2018/**\r
2019 Function for 'pci' command.\r
2020\r
2021 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2022 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2023**/\r
5d73d92f 2024SHELL_STATUS\r
2025EFIAPI\r
2026ShellCommandRunPci (\r
2027 IN EFI_HANDLE ImageHandle,\r
2028 IN EFI_SYSTEM_TABLE *SystemTable\r
2029 )\r
2030{\r
2031 UINT16 Segment;\r
2032 UINT16 Bus;\r
2033 UINT16 Device;\r
2034 UINT16 Func;\r
2035 UINT64 Address;\r
2036 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2037 EFI_STATUS Status;\r
2038 PCI_COMMON_HEADER PciHeader;\r
2039 PCI_CONFIG_SPACE ConfigSpace;\r
2040 UINTN ScreenCount;\r
2041 UINTN TempColumn;\r
2042 UINTN ScreenSize;\r
2043 BOOLEAN ExplainData;\r
2044 UINTN Index;\r
2045 UINTN SizeOfHeader;\r
2046 BOOLEAN PrintTitle;\r
2047 UINTN HandleBufSize;\r
2048 EFI_HANDLE *HandleBuf;\r
2049 UINTN HandleCount;\r
2050 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2051 UINT16 MinBus;\r
2052 UINT16 MaxBus;\r
2053 BOOLEAN IsEnd;\r
2054 LIST_ENTRY *Package;\r
2055 CHAR16 *ProblemParam;\r
2056 SHELL_STATUS ShellStatus;\r
5d73d92f 2057 CONST CHAR16 *Temp;\r
2058\r
2059 ShellStatus = SHELL_SUCCESS;\r
2060 Status = EFI_SUCCESS;\r
2061 Address = 0;\r
5d73d92f 2062 IoDev = NULL;\r
2063 HandleBuf = NULL;\r
2064 Package = NULL;\r
2065\r
2066 //\r
2067 // initialize the shell lib (we must be in non-auto-init...)\r
2068 //\r
2069 Status = ShellInitialize();\r
2070 ASSERT_EFI_ERROR(Status);\r
2071\r
2072 Status = CommandInit();\r
2073 ASSERT_EFI_ERROR(Status);\r
2074\r
2075 //\r
2076 // parse the command line\r
2077 //\r
2078 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2079 if (EFI_ERROR(Status)) {\r
2080 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
2081 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
2082 FreePool(ProblemParam);\r
2083 ShellStatus = SHELL_INVALID_PARAMETER;\r
2084 } else {\r
2085 ASSERT(FALSE);\r
2086 }\r
2087 } else {\r
2088\r
3737ac2b 2089 if (ShellCommandLineGetCount(Package) == 2) {\r
2090 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
2091 ShellStatus = SHELL_INVALID_PARAMETER;\r
2092 goto Done;\r
2093 }\r
5d73d92f 2094\r
3737ac2b 2095 if (ShellCommandLineGetCount(Package) > 4) {\r
2096 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
2097 ShellStatus = SHELL_INVALID_PARAMETER;\r
2098 goto Done;\r
2099 }\r
2100 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
2101 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
2102 ShellStatus = SHELL_INVALID_PARAMETER;\r
2103 goto Done;\r
2104 }\r
5d73d92f 2105 //\r
2106 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2107 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2108 // space for handles and call it again.\r
2109 //\r
2110 HandleBufSize = sizeof (EFI_HANDLE);\r
3737ac2b 2111 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
5d73d92f 2112 if (HandleBuf == NULL) {\r
2113 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2114 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2115 goto Done;\r
2116 }\r
2117\r
2118 Status = gBS->LocateHandle (\r
2119 ByProtocol,\r
2120 &gEfiPciRootBridgeIoProtocolGuid,\r
2121 NULL,\r
2122 &HandleBufSize,\r
2123 HandleBuf\r
2124 );\r
2125\r
2126 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2127 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2128 if (HandleBuf == NULL) {\r
2129 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2130 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2131 goto Done;\r
2132 }\r
2133\r
2134 Status = gBS->LocateHandle (\r
2135 ByProtocol,\r
2136 &gEfiPciRootBridgeIoProtocolGuid,\r
2137 NULL,\r
2138 &HandleBufSize,\r
2139 HandleBuf\r
2140 );\r
2141 }\r
2142\r
2143 if (EFI_ERROR (Status)) {\r
2144 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
2145 ShellStatus = SHELL_NOT_FOUND;\r
2146 goto Done;\r
2147 }\r
2148\r
2149 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2150 //\r
2151 // Argument Count == 1(no other argument): enumerate all pci functions\r
2152 //\r
3737ac2b 2153 if (ShellCommandLineGetCount(Package) == 1) {\r
5d73d92f 2154 gST->ConOut->QueryMode (\r
2155 gST->ConOut,\r
2156 gST->ConOut->Mode->Mode,\r
2157 &TempColumn,\r
2158 &ScreenSize\r
2159 );\r
2160\r
2161 ScreenCount = 0;\r
2162 ScreenSize -= 4;\r
2163 if ((ScreenSize & 1) == 1) {\r
2164 ScreenSize -= 1;\r
2165 }\r
2166\r
2167 PrintTitle = TRUE;\r
2168\r
2169 //\r
2170 // For each handle, which decides a segment and a bus number range,\r
2171 // enumerate all devices on it.\r
2172 //\r
2173 for (Index = 0; Index < HandleCount; Index++) {\r
2174 Status = PciGetProtocolAndResource (\r
2175 HandleBuf[Index],\r
2176 &IoDev,\r
2177 &Descriptors\r
2178 );\r
2179 if (EFI_ERROR (Status)) {\r
2180 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2181 ShellStatus = SHELL_NOT_FOUND;\r
2182 goto Done;\r
2183 }\r
2184 //\r
2185 // No document say it's impossible for a RootBridgeIo protocol handle\r
2186 // to have more than one address space descriptors, so find out every\r
2187 // bus range and for each of them do device enumeration.\r
2188 //\r
2189 while (TRUE) {\r
2190 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2191\r
2192 if (EFI_ERROR (Status)) {\r
2193 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2194 ShellStatus = SHELL_NOT_FOUND;\r
2195 goto Done;\r
2196 }\r
2197\r
2198 if (IsEnd) {\r
2199 break;\r
2200 }\r
2201\r
2202 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2203 //\r
2204 // For each devices, enumerate all functions it contains\r
2205 //\r
2206 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2207 //\r
2208 // For each function, read its configuration space and print summary\r
2209 //\r
2210 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2211 if (ShellGetExecutionBreakFlag ()) {\r
2212 ShellStatus = SHELL_ABORTED;\r
2213 goto Done;\r
2214 }\r
2215 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2216 IoDev->Pci.Read (\r
2217 IoDev,\r
2218 EfiPciWidthUint16,\r
2219 Address,\r
2220 1,\r
2221 &PciHeader.VendorId\r
2222 );\r
2223\r
2224 //\r
2225 // If VendorId = 0xffff, there does not exist a device at this\r
2226 // location. For each device, if there is any function on it,\r
2227 // there must be 1 function at Function 0. So if Func = 0, there\r
2228 // will be no more functions in the same device, so we can break\r
2229 // loop to deal with the next device.\r
2230 //\r
2231 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2232 break;\r
2233 }\r
2234\r
2235 if (PciHeader.VendorId != 0xffff) {\r
2236\r
2237 if (PrintTitle) {\r
2238 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2239 PrintTitle = FALSE;\r
2240 }\r
2241\r
2242 IoDev->Pci.Read (\r
2243 IoDev,\r
2244 EfiPciWidthUint32,\r
2245 Address,\r
2246 sizeof (PciHeader) / sizeof (UINT32),\r
2247 &PciHeader\r
2248 );\r
2249\r
2250 ShellPrintHiiEx(\r
2251 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2252 IoDev->SegmentNumber,\r
2253 Bus,\r
2254 Device,\r
2255 Func\r
2256 );\r
2257\r
2258 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2259 ShellPrintHiiEx(\r
2260 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2261 PciHeader.VendorId,\r
2262 PciHeader.DeviceId,\r
2263 PciHeader.ClassCode[0]\r
2264 );\r
2265\r
2266 ScreenCount += 2;\r
2267 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2268 //\r
2269 // If ScreenSize == 0 we have the console redirected so don't\r
2270 // block updates\r
2271 //\r
2272 ScreenCount = 0;\r
2273 }\r
2274 //\r
2275 // If this is not a multi-function device, we can leave the loop\r
2276 // to deal with the next device.\r
2277 //\r
2278 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2279 break;\r
2280 }\r
2281 }\r
2282 }\r
2283 }\r
2284 }\r
2285 //\r
2286 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2287 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2288 // devices on all bus, we can leave loop.\r
2289 //\r
2290 if (Descriptors == NULL) {\r
2291 break;\r
2292 }\r
2293 }\r
2294 }\r
2295\r
2296 Status = EFI_SUCCESS;\r
2297 goto Done;\r
2298 }\r
2299\r
5d73d92f 2300 ExplainData = FALSE;\r
2301 Segment = 0;\r
2302 Bus = 0;\r
2303 Device = 0;\r
2304 Func = 0;\r
2305 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2306 ExplainData = TRUE;\r
2307 }\r
2308\r
2309 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2310 if (Temp != NULL) {\r
3737ac2b 2311 Segment = (UINT16) ShellStrToUintn (Temp);\r
5d73d92f 2312 }\r
2313\r
2314 //\r
2315 // The first Argument(except "-i") is assumed to be Bus number, second\r
2316 // to be Device number, and third to be Func number.\r
2317 //\r
2318 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2319 if (Temp != NULL) {\r
3737ac2b 2320 Bus = (UINT16)ShellStrToUintn(Temp);\r
5d73d92f 2321 if (Bus > MAX_BUS_NUMBER) {\r
2322 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2323 ShellStatus = SHELL_INVALID_PARAMETER;\r
2324 goto Done;\r
2325 }\r
2326 }\r
2327 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2328 if (Temp != NULL) {\r
3737ac2b 2329 Device = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2330 if (Device > MAX_DEVICE_NUMBER){\r
2331 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2332 ShellStatus = SHELL_INVALID_PARAMETER;\r
2333 goto Done;\r
2334 }\r
2335 }\r
2336\r
2337 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2338 if (Temp != NULL) {\r
3737ac2b 2339 Func = (UINT16) ShellStrToUintn(Temp);\r
5d73d92f 2340 if (Func > MAX_FUNCTION_NUMBER){\r
2341 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2342 ShellStatus = SHELL_INVALID_PARAMETER;\r
2343 goto Done;\r
2344 }\r
2345 }\r
2346\r
2347 //\r
2348 // Find the protocol interface who's in charge of current segment, and its\r
2349 // bus range covers the current bus\r
2350 //\r
2351 Status = PciFindProtocolInterface (\r
2352 HandleBuf,\r
2353 HandleCount,\r
2354 Segment,\r
2355 Bus,\r
2356 &IoDev\r
2357 );\r
2358\r
2359 if (EFI_ERROR (Status)) {\r
2360 ShellPrintHiiEx(\r
2361 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
2362 gShellDebug1HiiHandle,\r
2363 Segment,\r
2364 Bus\r
2365 );\r
2366 ShellStatus = SHELL_NOT_FOUND;\r
2367 goto Done;\r
2368 }\r
2369\r
2370 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2371 Status = IoDev->Pci.Read (\r
2372 IoDev,\r
2373 EfiPciWidthUint8,\r
2374 Address,\r
2375 sizeof (ConfigSpace),\r
2376 &ConfigSpace\r
2377 );\r
2378\r
2379 if (EFI_ERROR (Status)) {\r
2380 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2381 ShellStatus = SHELL_ACCESS_DENIED;\r
2382 goto Done;\r
2383 }\r
2384\r
2385 mConfigSpace = &ConfigSpace;\r
2386 ShellPrintHiiEx(\r
2387 -1,\r
2388 -1,\r
2389 NULL,\r
2390 STRING_TOKEN (STR_PCI_INFO),\r
2391 gShellDebug1HiiHandle,\r
2392 Segment,\r
2393 Bus,\r
2394 Device,\r
2395 Func,\r
2396 Segment,\r
2397 Bus,\r
2398 Device,\r
2399 Func\r
2400 );\r
2401\r
2402 //\r
2403 // Dump standard header of configuration space\r
2404 //\r
2405 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2406\r
a1d4bfcc 2407 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
5d73d92f 2408 ShellPrintEx(-1,-1, L"\r\n");\r
2409\r
2410 //\r
2411 // Dump device dependent Part of configuration space\r
2412 //\r
a1d4bfcc 2413 DumpHex (\r
5d73d92f 2414 2,\r
2415 SizeOfHeader,\r
2416 sizeof (ConfigSpace) - SizeOfHeader,\r
2417 ConfigSpace.Data\r
2418 );\r
2419\r
2420 //\r
2421 // If "-i" appears in command line, interpret data in configuration space\r
2422 //\r
2423 if (ExplainData) {\r
2424 Status = PciExplainData (&ConfigSpace, Address, IoDev);\r
2425 }\r
2426 }\r
2427Done:\r
2428 if (HandleBuf != NULL) {\r
2429 FreePool (HandleBuf);\r
2430 }\r
2431 if (Package != NULL) {\r
2432 ShellCommandLineFreeVarList (Package);\r
2433 }\r
2434 mConfigSpace = NULL;\r
2435 return ShellStatus;\r
2436}\r
2437\r
a1d4bfcc 2438/**\r
5d73d92f 2439 This function finds out the protocol which is in charge of the given\r
2440 segment, and its bus range covers the current bus number. It lookes\r
2441 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2442 criteria is found.\r
2443\r
a1d4bfcc 2444 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2445 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2446 @param[in] Segment Segment number of device we are dealing with.\r
2447 @param[in] Bus Bus number of device we are dealing with.\r
2448 @param[out] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2449\r
a1d4bfcc 2450 @retval EFI_SUCCESS The command completed successfully.\r
2451 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 2452\r
2453**/\r
a1d4bfcc 2454EFI_STATUS\r
2455PciFindProtocolInterface (\r
2456 IN EFI_HANDLE *HandleBuf,\r
2457 IN UINTN HandleCount,\r
2458 IN UINT16 Segment,\r
2459 IN UINT16 Bus,\r
2460 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2461 )\r
5d73d92f 2462{\r
2463 UINTN Index;\r
2464 EFI_STATUS Status;\r
5d73d92f 2465 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2466 UINT16 MinBus;\r
2467 UINT16 MaxBus;\r
2468 BOOLEAN IsEnd;\r
2469\r
5d73d92f 2470 //\r
2471 // Go through all handles, until the one meets the criteria is found\r
2472 //\r
2473 for (Index = 0; Index < HandleCount; Index++) {\r
2474 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2475 if (EFI_ERROR (Status)) {\r
2476 return Status;\r
2477 }\r
2478 //\r
2479 // When Descriptors == NULL, the Configuration() is not implemented,\r
2480 // so we only check the Segment number\r
2481 //\r
2482 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2483 return EFI_SUCCESS;\r
2484 }\r
2485\r
2486 if ((*IoDev)->SegmentNumber != Segment) {\r
2487 continue;\r
2488 }\r
2489\r
2490 while (TRUE) {\r
2491 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2492 if (EFI_ERROR (Status)) {\r
2493 return Status;\r
2494 }\r
2495\r
2496 if (IsEnd) {\r
2497 break;\r
2498 }\r
2499\r
2500 if (MinBus <= Bus && MaxBus >= Bus) {\r
2c46dd23 2501 return EFI_SUCCESS;\r
5d73d92f 2502 }\r
2503 }\r
2504 }\r
2505\r
2c46dd23 2506 return EFI_NOT_FOUND;\r
5d73d92f 2507}\r
2508\r
a1d4bfcc 2509/**\r
2510 This function gets the protocol interface from the given handle, and\r
2511 obtains its address space descriptors.\r
2512\r
2513 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
2514 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2515 @param[out] Descriptors Points to the address space descriptors.\r
2516\r
2517 @retval EFI_SUCCESS The command completed successfully\r
2518**/\r
5d73d92f 2519EFI_STATUS\r
2520PciGetProtocolAndResource (\r
2521 IN EFI_HANDLE Handle,\r
2522 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2523 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2524 )\r
5d73d92f 2525{\r
2526 EFI_STATUS Status;\r
2527\r
2528 //\r
2529 // Get inferface from protocol\r
2530 //\r
2531 Status = gBS->HandleProtocol (\r
2532 Handle,\r
2533 &gEfiPciRootBridgeIoProtocolGuid,\r
2534 (VOID**)IoDev\r
2535 );\r
2536\r
2537 if (EFI_ERROR (Status)) {\r
2538 return Status;\r
2539 }\r
2540 //\r
2541 // Call Configuration() to get address space descriptors\r
2542 //\r
2543 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2544 if (Status == EFI_UNSUPPORTED) {\r
2545 *Descriptors = NULL;\r
2546 return EFI_SUCCESS;\r
2547\r
2548 } else {\r
2549 return Status;\r
2550 }\r
2551}\r
2552\r
a1d4bfcc 2553/**\r
2554 This function get the next bus range of given address space descriptors.\r
2555 It also moves the pointer backward a node, to get prepared to be called\r
2556 again.\r
2557\r
4ff7e37b
ED		 2558 @param[in, out] Descriptors Points to current position of a serial of address space\r
2559 descriptors.\r
2560 @param[out] MinBus The lower range of bus number.\r
2561 @param[out] MaxBus The upper range of bus number.\r
2562 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 2563\r
2564 @retval EFI_SUCCESS The command completed successfully.\r
2565**/\r
5d73d92f 2566EFI_STATUS\r
2567PciGetNextBusRange (\r
2568 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2569 OUT UINT16 *MinBus,\r
2570 OUT UINT16 *MaxBus,\r
2571 OUT BOOLEAN *IsEnd\r
2572 )\r
5d73d92f 2573{\r
2574 *IsEnd = FALSE;\r
2575\r
2576 //\r
2577 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2578 // range is 0~PCI_MAX_BUS\r
2579 //\r
2580 if ((*Descriptors) == NULL) {\r
2581 *MinBus = 0;\r
2582 *MaxBus = PCI_MAX_BUS;\r
2583 return EFI_SUCCESS;\r
2584 }\r
2585 //\r
2586 // *Descriptors points to one or more address space descriptors, which\r
2587 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2588 // if a bus typed one is found and its bus range covers bus, this handle\r
2589 // is the handle we are looking for.\r
2590 //\r
5d73d92f 2591\r
2592 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2593 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2594 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2595 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2596 (*Descriptors)++;\r
3737ac2b 2597 return (EFI_SUCCESS);\r
5d73d92f 2598 }\r
2599\r
2600 (*Descriptors)++;\r
2601 }\r
2602\r
3737ac2b 2603 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2604 *IsEnd = TRUE;\r
2605 }\r
2606\r
5d73d92f 2607 return EFI_SUCCESS;\r
2608}\r
2609\r
a1d4bfcc 2610/**\r
5d73d92f 2611 Explain the data in PCI configuration space. The part which is common for\r
2612 PCI device and bridge is interpreted in this function. It calls other\r
2613 functions to interpret data unique for device or bridge.\r
2614\r
a1d4bfcc 2615 @param[in] ConfigSpace Data in PCI configuration space.\r
2616 @param[in] Address Address used to access configuration space of this PCI device.\r
2617 @param[in] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2618\r
a1d4bfcc 2619 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 2620**/\r
a1d4bfcc 2621EFI_STATUS\r
2622PciExplainData (\r
2623 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2624 IN UINT64 Address,\r
2625 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2626 )\r
5d73d92f 2627{\r
2628 PCI_COMMON_HEADER *Common;\r
2629 PCI_HEADER_TYPE HeaderType;\r
2630 EFI_STATUS Status;\r
2631 UINT8 CapPtr;\r
2632\r
2633 Common = &(ConfigSpace->Common);\r
2634\r
2635 Print (L"\n");\r
2636\r
2637 //\r
2638 // Print Vendor Id and Device Id\r
2639 //\r
2640 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2641 INDEX_OF (&(Common->VendorId)),\r
2642 Common->VendorId,\r
2643 INDEX_OF (&(Common->DeviceId)),\r
2644 Common->DeviceId\r
2645 );\r
2646\r
2647 //\r
2648 // Print register Command\r
2649 //\r
2650 PciExplainCommand (&(Common->Command));\r
2651\r
2652 //\r
2653 // Print register Status\r
2654 //\r
2655 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2656\r
2657 //\r
2658 // Print register Revision ID\r
2659 //\r
2660 ShellPrintEx(-1, -1, L"/r/n");\r
2661 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2662 INDEX_OF (&(Common->RevisionId)),\r
2663 Common->RevisionId\r
2664 );\r
2665\r
2666 //\r
2667 // Print register BIST\r
2668 //\r
a1d4bfcc 2669 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
2670 if ((Common->Bist & PCI_BIT_7) != 0) {\r
2671 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
5d73d92f 2672 } else {\r
2673 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2674 }\r
2675 //\r
2676 // Print register Cache Line Size\r
2677 //\r
2678 ShellPrintHiiEx(-1, -1, NULL,\r
2679 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2680 gShellDebug1HiiHandle,\r
2681 INDEX_OF (&(Common->CacheLineSize)),\r
2682 Common->CacheLineSize\r
2683 );\r
2684\r
2685 //\r
2686 // Print register Latency Timer\r
2687 //\r
2688 ShellPrintHiiEx(-1, -1, NULL,\r
2689 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2690 gShellDebug1HiiHandle,\r
2691 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2692 Common->PrimaryLatencyTimer\r
2693 );\r
2694\r
2695 //\r
2696 // Print register Header Type\r
2697 //\r
2698 ShellPrintHiiEx(-1, -1, NULL,\r
2699 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2700 gShellDebug1HiiHandle,\r
2701 INDEX_OF (&(Common->HeaderType)),\r
2702 Common->HeaderType\r
2703 );\r
2704\r
2705 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2706 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2707\r
2708 } else {\r
2709 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2710 }\r
2711\r
2712 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2713 switch (HeaderType) {\r
2714 case PciDevice:\r
2715 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2716 break;\r
2717\r
2718 case PciP2pBridge:\r
2719 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2720 break;\r
2721\r
2722 case PciCardBusBridge:\r
2723 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2724 break;\r
2725\r
2726 default:\r
2727 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2728 HeaderType = PciUndefined;\r
2729 }\r
2730\r
2731 //\r
2732 // Print register Class Code\r
2733 //\r
2734 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2735 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
2736 Print (L"\n");\r
2737\r
2738 if (ShellGetExecutionBreakFlag()) {\r
2739 return EFI_SUCCESS;\r
2740 }\r
2741\r
2742 //\r
2743 // Interpret remaining part of PCI configuration header depending on\r
2744 // HeaderType\r
2745 //\r
2746 CapPtr = 0;\r
2747 Status = EFI_SUCCESS;\r
2748 switch (HeaderType) {\r
2749 case PciDevice:\r
2750 Status = PciExplainDeviceData (\r
2751 &(ConfigSpace->NonCommon.Device),\r
2752 Address,\r
2753 IoDev\r
2754 );\r
2755 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2756 break;\r
2757\r
2758 case PciP2pBridge:\r
2759 Status = PciExplainBridgeData (\r
2760 &(ConfigSpace->NonCommon.Bridge),\r
2761 Address,\r
2762 IoDev\r
2763 );\r
2764 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2765 break;\r
2766\r
2767 case PciCardBusBridge:\r
2768 Status = PciExplainCardBusData (\r
2769 &(ConfigSpace->NonCommon.CardBus),\r
2770 Address,\r
2771 IoDev\r
2772 );\r
2773 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2774 break;\r
d8f8021c 2775 case PciUndefined:\r
2776 default:\r
2777 break;\r
5d73d92f 2778 }\r
2779 //\r
2780 // If Status bit4 is 1, dump or explain capability structure\r
2781 //\r
2782 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
2783 PciExplainCapabilityStruct (IoDev, Address, CapPtr);\r
2784 }\r
2785\r
2786 return Status;\r
2787}\r
2788\r
a1d4bfcc 2789/**\r
2790 Explain the device specific part of data in PCI configuration space.\r
2791\r
2792 @param[in] Device Data in PCI configuration space.\r
2793 @param[in] Address Address used to access configuration space of this PCI device.\r
2794 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2795\r
2796 @retval EFI_SUCCESS The command completed successfully.\r
2797**/\r
5d73d92f 2798EFI_STATUS\r
2799PciExplainDeviceData (\r
2800 IN PCI_DEVICE_HEADER *Device,\r
2801 IN UINT64 Address,\r
2802 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2803 )\r
5d73d92f 2804{\r
2805 UINTN Index;\r
2806 BOOLEAN BarExist;\r
2807 EFI_STATUS Status;\r
2808 UINTN BarCount;\r
2809\r
2810 //\r
2811 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2812 // exist. If these no Bar for this function, print "none", otherwise\r
2813 // list detail information about this Bar.\r
2814 //\r
2815 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2816\r
2817 BarExist = FALSE;\r
2818 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2819 for (Index = 0; Index < BarCount; Index++) {\r
2820 if (Device->Bar[Index] == 0) {\r
2821 continue;\r
2822 }\r
2823\r
2824 if (!BarExist) {\r
2825 BarExist = TRUE;\r
2826 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
2827 Print (L" --------------------------------------------------------------------------");\r
2828 }\r
2829\r
2830 Status = PciExplainBar (\r
2831 &(Device->Bar[Index]),\r
2832 &(mConfigSpace->Common.Command),\r
2833 Address,\r
2834 IoDev,\r
2835 &Index\r
2836 );\r
2837\r
2838 if (EFI_ERROR (Status)) {\r
2839 break;\r
2840 }\r
2841 }\r
2842\r
2843 if (!BarExist) {\r
2844 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2845\r
2846 } else {\r
2847 Print (L"\n --------------------------------------------------------------------------");\r
2848 }\r
2849\r
2850 //\r
2851 // Print register Expansion ROM Base Address\r
2852 //\r
2853 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2854 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2855\r
2856 } else {\r
2857 ShellPrintHiiEx(-1, -1, NULL,\r
2858 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2859 gShellDebug1HiiHandle,\r
2860 INDEX_OF (&(Device->ROMBar)),\r
2861 Device->ROMBar\r
2862 );\r
2863 }\r
2864 //\r
2865 // Print register Cardbus CIS ptr\r
2866 //\r
2867 ShellPrintHiiEx(-1, -1, NULL,\r
2868 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2869 gShellDebug1HiiHandle,\r
2870 INDEX_OF (&(Device->CardBusCISPtr)),\r
2871 Device->CardBusCISPtr\r
2872 );\r
2873\r
2874 //\r
2875 // Print register Sub-vendor ID and subsystem ID\r
2876 //\r
2877 ShellPrintHiiEx(-1, -1, NULL,\r
2878 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2879 gShellDebug1HiiHandle,\r
2880 INDEX_OF (&(Device->SubVendorId)),\r
2881 Device->SubVendorId\r
2882 );\r
2883\r
2884 ShellPrintHiiEx(-1, -1, NULL,\r
2885 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2886 gShellDebug1HiiHandle,\r
2887 INDEX_OF (&(Device->SubSystemId)),\r
2888 Device->SubSystemId\r
2889 );\r
2890\r
2891 //\r
2892 // Print register Capabilities Ptr\r
2893 //\r
2894 ShellPrintHiiEx(-1, -1, NULL,\r
2895 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2896 gShellDebug1HiiHandle,\r
2897 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2898 Device->CapabilitiesPtr\r
2899 );\r
2900\r
2901 //\r
2902 // Print register Interrupt Line and interrupt pin\r
2903 //\r
2904 ShellPrintHiiEx(-1, -1, NULL,\r
2905 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2906 gShellDebug1HiiHandle,\r
2907 INDEX_OF (&(Device->InterruptLine)),\r
2908 Device->InterruptLine\r
2909 );\r
2910\r
2911 ShellPrintHiiEx(-1, -1, NULL,\r
2912 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2913 gShellDebug1HiiHandle,\r
2914 INDEX_OF (&(Device->InterruptPin)),\r
2915 Device->InterruptPin\r
2916 );\r
2917\r
2918 //\r
2919 // Print register Min_Gnt and Max_Lat\r
2920 //\r
2921 ShellPrintHiiEx(-1, -1, NULL,\r
2922 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2923 gShellDebug1HiiHandle,\r
2924 INDEX_OF (&(Device->MinGnt)),\r
2925 Device->MinGnt\r
2926 );\r
2927\r
2928 ShellPrintHiiEx(-1, -1, NULL,\r
2929 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2930 gShellDebug1HiiHandle,\r
2931 INDEX_OF (&(Device->MaxLat)),\r
2932 Device->MaxLat\r
2933 );\r
2934\r
2935 return EFI_SUCCESS;\r
2936}\r
2937\r
a1d4bfcc 2938/**\r
2939 Explain the bridge specific part of data in PCI configuration space.\r
2940\r
2941 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
2942 @param[in] Address Address used to access configuration space of this PCI device.\r
2943 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2944\r
2945 @retval EFI_SUCCESS The command completed successfully.\r
2946**/\r
5d73d92f 2947EFI_STATUS\r
2948PciExplainBridgeData (\r
2949 IN PCI_BRIDGE_HEADER *Bridge,\r
2950 IN UINT64 Address,\r
2951 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2952 )\r
5d73d92f 2953{\r
2954 UINTN Index;\r
2955 BOOLEAN BarExist;\r
2956 UINTN BarCount;\r
2957 UINT32 IoAddress32;\r
2958 EFI_STATUS Status;\r
2959\r
2960 //\r
2961 // Print Base Address Registers. When Bar = 0, this Bar does not\r
2962 // exist. If these no Bar for this function, print "none", otherwise\r
2963 // list detail information about this Bar.\r
2964 //\r
2965 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
2966\r
2967 BarExist = FALSE;\r
2968 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
2969\r
2970 for (Index = 0; Index < BarCount; Index++) {\r
2971 if (Bridge->Bar[Index] == 0) {\r
2972 continue;\r
2973 }\r
2974\r
2975 if (!BarExist) {\r
2976 BarExist = TRUE;\r
2977 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
2978 Print (L" --------------------------------------------------------------------------");\r
2979 }\r
2980\r
2981 Status = PciExplainBar (\r
2982 &(Bridge->Bar[Index]),\r
2983 &(mConfigSpace->Common.Command),\r
2984 Address,\r
2985 IoDev,\r
2986 &Index\r
2987 );\r
2988\r
2989 if (EFI_ERROR (Status)) {\r
2990 break;\r
2991 }\r
2992 }\r
2993\r
2994 if (!BarExist) {\r
2995 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2996 } else {\r
2997 Print (L"\n --------------------------------------------------------------------------");\r
2998 }\r
2999\r
3000 //\r
3001 // Expansion register ROM Base Address\r
3002 //\r
3003 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
3004 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
3005\r
3006 } else {\r
3007 ShellPrintHiiEx(-1, -1, NULL,\r
3008 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3009 gShellDebug1HiiHandle,\r
3010 INDEX_OF (&(Bridge->ROMBar)),\r
3011 Bridge->ROMBar\r
3012 );\r
3013 }\r
3014 //\r
3015 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3016 //\r
3017 ShellPrintHiiEx(-1, -1, NULL,\r
3018 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3019 gShellDebug1HiiHandle,\r
3020 INDEX_OF (&(Bridge->PrimaryBus)),\r
3021 INDEX_OF (&(Bridge->SecondaryBus)),\r
3022 INDEX_OF (&(Bridge->SubordinateBus))\r
3023 );\r
3024\r
3025 Print (L" ------------------------------------------------------\n");\r
3026\r
3027 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3028 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3029 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3030\r
3031 //\r
3032 // Print register Secondary Latency Timer\r
3033 //\r
3034 ShellPrintHiiEx(-1, -1, NULL,\r
3035 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3036 gShellDebug1HiiHandle,\r
3037 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3038 Bridge->SecondaryLatencyTimer\r
3039 );\r
3040\r
3041 //\r
3042 // Print register Secondary Status\r
3043 //\r
3044 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3045\r
3046 //\r
3047 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3048 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3049 // base and limit address are listed.\r
3050 //\r
3051 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
3052 Print (L"----------------------------------------------------------------------\n");\r
3053\r
3054 //\r
3055 // IO Base & Limit\r
3056 //\r
3057 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
3058 IoAddress32 &= 0xfffff000;\r
3059 ShellPrintHiiEx(-1, -1, NULL,\r
3060 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3061 gShellDebug1HiiHandle,\r
3062 INDEX_OF (&(Bridge->IoBase)),\r
3063 IoAddress32\r
3064 );\r
3065\r
3066 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
3067 IoAddress32 |= 0x00000fff;\r
3068 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3069\r
3070 //\r
3071 // Memory Base & Limit\r
3072 //\r
3073 ShellPrintHiiEx(-1, -1, NULL,\r
3074 STRING_TOKEN (STR_PCI2_MEMORY),\r
3075 gShellDebug1HiiHandle,\r
3076 INDEX_OF (&(Bridge->MemoryBase)),\r
3077 (Bridge->MemoryBase << 16) & 0xfff00000\r
3078 );\r
3079\r
3080 ShellPrintHiiEx(-1, -1, NULL,\r
3081 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3082 gShellDebug1HiiHandle,\r
3083 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3084 );\r
3085\r
3086 //\r
3087 // Pre-fetch-able Memory Base & Limit\r
3088 //\r
3089 ShellPrintHiiEx(-1, -1, NULL,\r
3090 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3091 gShellDebug1HiiHandle,\r
3092 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
3093 Bridge->PrefetchableBaseUpper,\r
3094 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
3095 );\r
3096\r
3097 ShellPrintHiiEx(-1, -1, NULL,\r
3098 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3099 gShellDebug1HiiHandle,\r
3100 Bridge->PrefetchableLimitUpper,\r
3101 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3102 );\r
3103\r
3104 //\r
3105 // Print register Capabilities Pointer\r
3106 //\r
3107 ShellPrintHiiEx(-1, -1, NULL,\r
3108 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3109 gShellDebug1HiiHandle,\r
3110 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3111 Bridge->CapabilitiesPtr\r
3112 );\r
3113\r
3114 //\r
3115 // Print register Bridge Control\r
3116 //\r
3117 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3118\r
3119 //\r
3120 // Print register Interrupt Line & PIN\r
3121 //\r
3122 ShellPrintHiiEx(-1, -1, NULL,\r
3123 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3124 gShellDebug1HiiHandle,\r
3125 INDEX_OF (&(Bridge->InterruptLine)),\r
3126 Bridge->InterruptLine\r
3127 );\r
3128\r
3129 ShellPrintHiiEx(-1, -1, NULL,\r
3130 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3131 gShellDebug1HiiHandle,\r
3132 INDEX_OF (&(Bridge->InterruptPin)),\r
3133 Bridge->InterruptPin\r
3134 );\r
3135\r
3136 return EFI_SUCCESS;\r
3137}\r
3138\r
a1d4bfcc 3139/**\r
3140 Explain the Base Address Register(Bar) in PCI configuration space.\r
3141\r
4ff7e37b
ED		 3142 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3143 @param[in] Command Points to the register Command.\r
3144 @param[in] Address Address used to access configuration space of this PCI device.\r
3145 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3146 @param[in, out] Index The Index.\r
a1d4bfcc 3147\r
3148 @retval EFI_SUCCESS The command completed successfully.\r
3149**/\r
5d73d92f 3150EFI_STATUS\r
3151PciExplainBar (\r
3152 IN UINT32 *Bar,\r
3153 IN UINT16 *Command,\r
3154 IN UINT64 Address,\r
3155 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3156 IN OUT UINTN *Index\r
3157 )\r
5d73d92f 3158{\r
3159 UINT16 OldCommand;\r
3160 UINT16 NewCommand;\r
3161 UINT64 Bar64;\r
3162 UINT32 OldBar32;\r
3163 UINT32 NewBar32;\r
3164 UINT64 OldBar64;\r
3165 UINT64 NewBar64;\r
3166 BOOLEAN IsMem;\r
3167 BOOLEAN IsBar32;\r
3168 UINT64 RegAddress;\r
3169\r
3170 IsBar32 = TRUE;\r
3171 Bar64 = 0;\r
3172 NewBar32 = 0;\r
3173 NewBar64 = 0;\r
3174\r
3175 //\r
3176 // According the bar type, list detail about this bar, for example: 32 or\r
3177 // 64 bits; pre-fetchable or not.\r
3178 //\r
3179 if ((*Bar & PCI_BIT_0) == 0) {\r
3180 //\r
3181 // This bar is of memory type\r
3182 //\r
3183 IsMem = TRUE;\r
3184\r
3185 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3186 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3187 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3188 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3189\r
3190 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3191 Bar64 = 0x0;\r
3192 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
46cb4043 3193 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
2b578de0 3194 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
5d73d92f 3195 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3196 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3197 IsBar32 = FALSE;\r
3198 *Index += 1;\r
3199\r
3200 } else {\r
3201 //\r
3202 // Reserved\r
3203 //\r
3204 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3205 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3206 }\r
3207\r
3208 if ((*Bar & PCI_BIT_3) == 0) {\r
3209 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3210\r
3211 } else {\r
3212 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3213 }\r
3214\r
3215 } else {\r
3216 //\r
3217 // This bar is of io type\r
3218 //\r
3219 IsMem = FALSE;\r
3220 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
3221 Print (L"I/O ");\r
3222 }\r
3223\r
3224 //\r
3225 // Get BAR length(or the amount of resource this bar demands for). To get\r
3226 // Bar length, first we should temporarily disable I/O and memory access\r
3227 // of this function(by set bits in the register Command), then write all\r
3228 // "1"s to this bar. The bar value read back is the amount of resource\r
3229 // this bar demands for.\r
3230 //\r
3231 //\r
3232 // Disable io & mem access\r
3233 //\r
3234 OldCommand = *Command;\r
3235 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3236 RegAddress = Address | INDEX_OF (Command);\r
3237 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3238\r
3239 RegAddress = Address | INDEX_OF (Bar);\r
3240\r
3241 //\r
3242 // Read after write the BAR to get the size\r
3243 //\r
3244 if (IsBar32) {\r
3245 OldBar32 = *Bar;\r
3246 NewBar32 = 0xffffffff;\r
3247\r
3248 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3249 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3250 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3251\r
3252 if (IsMem) {\r
3253 NewBar32 = NewBar32 & 0xfffffff0;\r
3254 NewBar32 = (~NewBar32) + 1;\r
3255\r
3256 } else {\r
3257 NewBar32 = NewBar32 & 0xfffffffc;\r
3258 NewBar32 = (~NewBar32) + 1;\r
3259 NewBar32 = NewBar32 & 0x0000ffff;\r
3260 }\r
3261 } else {\r
3262\r
3263 OldBar64 = 0x0;\r
3264 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
2b578de0 3265 NewBar64 = 0xffffffffffffffffULL;\r
5d73d92f 3266\r
3267 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3268 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3269 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3270\r
3271 if (IsMem) {\r
2b578de0 3272 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
5d73d92f 3273 NewBar64 = (~NewBar64) + 1;\r
3274\r
3275 } else {\r
2b578de0 3276 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
5d73d92f 3277 NewBar64 = (~NewBar64) + 1;\r
3278 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3279 }\r
3280 }\r
3281 //\r
3282 // Enable io & mem access\r
3283 //\r
3284 RegAddress = Address | INDEX_OF (Command);\r
3285 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3286\r
3287 if (IsMem) {\r
3288 if (IsBar32) {\r
3289 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3290 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3291\r
3292 } else {\r
46cb4043 3293 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
5d73d92f 3294 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
3295 Print (L" ");\r
3296 ShellPrintHiiEx(-1, -1, NULL,\r
3297 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3298 gShellDebug1HiiHandle,\r
46cb4043 3299 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
5d73d92f 3300 );\r
2b578de0 3301 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
5d73d92f 3302\r
3303 }\r
3304 } else {\r
3305 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3306 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3307 }\r
3308\r
3309 return EFI_SUCCESS;\r
3310}\r
3311\r
a1d4bfcc 3312/**\r
3313 Explain the cardbus specific part of data in PCI configuration space.\r
3314\r
3315 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3316 @param[in] Address Address used to access configuration space of this PCI device.\r
3317 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3318\r
3319 @retval EFI_SUCCESS The command completed successfully.\r
3320**/\r
5d73d92f 3321EFI_STATUS\r
3322PciExplainCardBusData (\r
3323 IN PCI_CARDBUS_HEADER *CardBus,\r
3324 IN UINT64 Address,\r
3325 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3326 )\r
5d73d92f 3327{\r
3328 BOOLEAN Io32Bit;\r
3329 PCI_CARDBUS_DATA *CardBusData;\r
3330\r
3331 ShellPrintHiiEx(-1, -1, NULL,\r
3332 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3333 gShellDebug1HiiHandle,\r
3334 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3335 CardBus->CardBusSocketReg\r
3336 );\r
3337\r
3338 //\r
3339 // Print Secondary Status\r
3340 //\r
3341 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3342\r
3343 //\r
3344 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3345 // Subordinate bus number\r
3346 //\r
3347 ShellPrintHiiEx(-1, -1, NULL,\r
3348 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3349 gShellDebug1HiiHandle,\r
3350 INDEX_OF (&(CardBus->PciBusNumber)),\r
3351 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3352 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3353 );\r
3354\r
3355 Print (L" ------------------------------------------------------\n");\r
3356\r
3357 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3358 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3359 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3360\r
3361 //\r
3362 // Print CardBus Latency Timer\r
3363 //\r
3364 ShellPrintHiiEx(-1, -1, NULL,\r
3365 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3366 gShellDebug1HiiHandle,\r
3367 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3368 CardBus->CardBusLatencyTimer\r
3369 );\r
3370\r
3371 //\r
3372 // Print Memory/Io ranges this cardbus bridge forwards\r
3373 //\r
3374 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
3375 Print (L"----------------------------------------------------------------------\n");\r
3376\r
3377 ShellPrintHiiEx(-1, -1, NULL,\r
3378 STRING_TOKEN (STR_PCI2_MEM_3),\r
3379 gShellDebug1HiiHandle,\r
3380 INDEX_OF (&(CardBus->MemoryBase0)),\r
3381 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3382 CardBus->MemoryBase0 & 0xfffff000,\r
3383 CardBus->MemoryLimit0 | 0x00000fff\r
3384 );\r
3385\r
3386 ShellPrintHiiEx(-1, -1, NULL,\r
3387 STRING_TOKEN (STR_PCI2_MEM_3),\r
3388 gShellDebug1HiiHandle,\r
3389 INDEX_OF (&(CardBus->MemoryBase1)),\r
3390 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3391 CardBus->MemoryBase1 & 0xfffff000,\r
3392 CardBus->MemoryLimit1 | 0x00000fff\r
3393 );\r
3394\r
3395 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3396 ShellPrintHiiEx(-1, -1, NULL,\r
3397 STRING_TOKEN (STR_PCI2_IO_2),\r
3398 gShellDebug1HiiHandle,\r
3399 INDEX_OF (&(CardBus->IoBase0)),\r
3400 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3401 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3402 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3403 );\r
3404\r
3405 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3406 ShellPrintHiiEx(-1, -1, NULL,\r
3407 STRING_TOKEN (STR_PCI2_IO_2),\r
3408 gShellDebug1HiiHandle,\r
3409 INDEX_OF (&(CardBus->IoBase1)),\r
3410 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3411 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3412 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3413 );\r
3414\r
3415 //\r
3416 // Print register Interrupt Line & PIN\r
3417 //\r
3418 ShellPrintHiiEx(-1, -1, NULL,\r
3419 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3420 gShellDebug1HiiHandle,\r
3421 INDEX_OF (&(CardBus->InterruptLine)),\r
3422 CardBus->InterruptLine,\r
3423 INDEX_OF (&(CardBus->InterruptPin)),\r
3424 CardBus->InterruptPin\r
3425 );\r
3426\r
3427 //\r
3428 // Print register Bridge Control\r
3429 //\r
3430 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3431\r
3432 //\r
3433 // Print some registers in data region of PCI configuration space for cardbus\r
3434 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3435 // Address.\r
3436 //\r
3437 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3438\r
3439 ShellPrintHiiEx(-1, -1, NULL,\r
3440 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3441 gShellDebug1HiiHandle,\r
3442 INDEX_OF (&(CardBusData->SubVendorId)),\r
3443 CardBusData->SubVendorId,\r
3444 INDEX_OF (&(CardBusData->SubSystemId)),\r
3445 CardBusData->SubSystemId\r
3446 );\r
3447\r
3448 ShellPrintHiiEx(-1, -1, NULL,\r
3449 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3450 gShellDebug1HiiHandle,\r
3451 INDEX_OF (&(CardBusData->LegacyBase)),\r
3452 CardBusData->LegacyBase\r
3453 );\r
3454\r
3455 return EFI_SUCCESS;\r
3456}\r
3457\r
a1d4bfcc 3458/**\r
3459 Explain each meaningful bit of register Status. The definition of Status is\r
3460 slightly different depending on the PCI header type.\r
3461\r
3462 @param[in] Status Points to the content of register Status.\r
3463 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3464 status).\r
3465 @param[in] HeaderType Header type of this PCI device.\r
3466\r
3467 @retval EFI_SUCCESS The command completed successfully.\r
3468**/\r
5d73d92f 3469EFI_STATUS\r
3470PciExplainStatus (\r
3471 IN UINT16 *Status,\r
3472 IN BOOLEAN MainStatus,\r
3473 IN PCI_HEADER_TYPE HeaderType\r
3474 )\r
5d73d92f 3475{\r
3476 if (MainStatus) {\r
3477 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3478\r
3479 } else {\r
3480 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3481 }\r
3482\r
3483 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3484\r
3485 //\r
3486 // Bit 5 is meaningless for CardBus Bridge\r
3487 //\r
3488 if (HeaderType == PciCardBusBridge) {\r
3489 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3490\r
3491 } else {\r
3492 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3493 }\r
3494\r
3495 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3496\r
3497 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3498 //\r
3499 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3500 //\r
3501 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3502 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3503 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3504\r
3505 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3506 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3507\r
3508 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3509 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3510\r
3511 } else {\r
3512 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3513 }\r
3514\r
3515 ShellPrintHiiEx(-1, -1, NULL,\r
3516 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3517 gShellDebug1HiiHandle,\r
3518 (*Status & PCI_BIT_11) != 0\r
3519 );\r
3520\r
3521 ShellPrintHiiEx(-1, -1, NULL,\r
3522 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3523 gShellDebug1HiiHandle,\r
3524 (*Status & PCI_BIT_12) != 0\r
3525 );\r
3526\r
3527 ShellPrintHiiEx(-1, -1, NULL,\r
3528 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3529 gShellDebug1HiiHandle,\r
3530 (*Status & PCI_BIT_13) != 0\r
3531 );\r
3532\r
3533 if (MainStatus) {\r
3534 ShellPrintHiiEx(-1, -1, NULL,\r
3535 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3536 gShellDebug1HiiHandle,\r
3537 (*Status & PCI_BIT_14) != 0\r
3538 );\r
3539\r
3540 } else {\r
3541 ShellPrintHiiEx(-1, -1, NULL,\r
3542 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3543 gShellDebug1HiiHandle,\r
3544 (*Status & PCI_BIT_14) != 0\r
3545 );\r
3546 }\r
3547\r
3548 ShellPrintHiiEx(-1, -1, NULL,\r
3549 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3550 gShellDebug1HiiHandle,\r
3551 (*Status & PCI_BIT_15) != 0\r
3552 );\r
3553\r
3554 return EFI_SUCCESS;\r
3555}\r
3556\r
a1d4bfcc 3557/**\r
5d73d92f 3558 Explain each meaningful bit of register Command.\r
3559\r
a1d4bfcc 3560 @param[in] Command Points to the content of register Command.\r
5d73d92f 3561\r
a1d4bfcc 3562 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 3563**/\r
a1d4bfcc 3564EFI_STATUS\r
3565PciExplainCommand (\r
3566 IN UINT16 *Command\r
3567 )\r
5d73d92f 3568{\r
3569 //\r
3570 // Print the binary value of register Command\r
3571 //\r
3572 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3573\r
3574 //\r
3575 // Explain register Command bit by bit\r
3576 //\r
3577 ShellPrintHiiEx(-1, -1, NULL,\r
3578 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3579 gShellDebug1HiiHandle,\r
3580 (*Command & PCI_BIT_0) != 0\r
3581 );\r
3582\r
3583 ShellPrintHiiEx(-1, -1, NULL,\r
3584 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3585 gShellDebug1HiiHandle,\r
3586 (*Command & PCI_BIT_1) != 0\r
3587 );\r
3588\r
3589 ShellPrintHiiEx(-1, -1, NULL,\r
3590 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3591 gShellDebug1HiiHandle,\r
3592 (*Command & PCI_BIT_2) != 0\r
3593 );\r
3594\r
3595 ShellPrintHiiEx(-1, -1, NULL,\r
3596 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3597 gShellDebug1HiiHandle,\r
3598 (*Command & PCI_BIT_3) != 0\r
3599 );\r
3600\r
3601 ShellPrintHiiEx(-1, -1, NULL,\r
3602 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3603 gShellDebug1HiiHandle,\r
3604 (*Command & PCI_BIT_4) != 0\r
3605 );\r
3606\r
3607 ShellPrintHiiEx(-1, -1, NULL,\r
3608 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3609 gShellDebug1HiiHandle,\r
3610 (*Command & PCI_BIT_5) != 0\r
3611 );\r
3612\r
3613 ShellPrintHiiEx(-1, -1, NULL,\r
3614 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3615 gShellDebug1HiiHandle,\r
3616 (*Command & PCI_BIT_6) != 0\r
3617 );\r
3618\r
3619 ShellPrintHiiEx(-1, -1, NULL,\r
3620 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3621 gShellDebug1HiiHandle,\r
3622 (*Command & PCI_BIT_7) != 0\r
3623 );\r
3624\r
3625 ShellPrintHiiEx(-1, -1, NULL,\r
3626 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3627 gShellDebug1HiiHandle,\r
3628 (*Command & PCI_BIT_8) != 0\r
3629 );\r
3630\r
3631 ShellPrintHiiEx(-1, -1, NULL,\r
3632 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3633 gShellDebug1HiiHandle,\r
3634 (*Command & PCI_BIT_9) != 0\r
3635 );\r
3636\r
3637 return EFI_SUCCESS;\r
3638}\r
3639\r
a1d4bfcc 3640/**\r
3641 Explain each meaningful bit of register Bridge Control.\r
3642\r
3643 @param[in] BridgeControl Points to the content of register Bridge Control.\r
3644 @param[in] HeaderType The headertype.\r
3645\r
3646 @retval EFI_SUCCESS The command completed successfully.\r
3647**/\r
5d73d92f 3648EFI_STATUS\r
3649PciExplainBridgeControl (\r
3650 IN UINT16 *BridgeControl,\r
3651 IN PCI_HEADER_TYPE HeaderType\r
3652 )\r
5d73d92f 3653{\r
3654 ShellPrintHiiEx(-1, -1, NULL,\r
3655 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3656 gShellDebug1HiiHandle,\r
3657 INDEX_OF (BridgeControl),\r
3658 *BridgeControl\r
3659 );\r
3660\r
3661 ShellPrintHiiEx(-1, -1, NULL,\r
3662 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3663 gShellDebug1HiiHandle,\r
3664 (*BridgeControl & PCI_BIT_0) != 0\r
3665 );\r
3666 ShellPrintHiiEx(-1, -1, NULL,\r
3667 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3668 gShellDebug1HiiHandle,\r
3669 (*BridgeControl & PCI_BIT_1) != 0\r
3670 );\r
3671 ShellPrintHiiEx(-1, -1, NULL,\r
3672 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3673 gShellDebug1HiiHandle,\r
3674 (*BridgeControl & PCI_BIT_2) != 0\r
3675 );\r
3676 ShellPrintHiiEx(-1, -1, NULL,\r
3677 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3678 gShellDebug1HiiHandle,\r
3679 (*BridgeControl & PCI_BIT_3) != 0\r
3680 );\r
3681 ShellPrintHiiEx(-1, -1, NULL,\r
3682 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3683 gShellDebug1HiiHandle,\r
3684 (*BridgeControl & PCI_BIT_5) != 0\r
3685 );\r
3686\r
3687 //\r
3688 // Register Bridge Control has some slight differences between P2P bridge\r
3689 // and Cardbus bridge from bit 6 to bit 11.\r
3690 //\r
3691 if (HeaderType == PciP2pBridge) {\r
3692 ShellPrintHiiEx(-1, -1, NULL,\r
3693 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3694 gShellDebug1HiiHandle,\r
3695 (*BridgeControl & PCI_BIT_6) != 0\r
3696 );\r
3697 ShellPrintHiiEx(-1, -1, NULL,\r
3698 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3699 gShellDebug1HiiHandle,\r
3700 (*BridgeControl & PCI_BIT_7) != 0\r
3701 );\r
3702 ShellPrintHiiEx(-1, -1, NULL,\r
3703 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3704 gShellDebug1HiiHandle,\r
3705 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3706 );\r
3707 ShellPrintHiiEx(-1, -1, NULL,\r
3708 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3709 gShellDebug1HiiHandle,\r
3710 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3711 );\r
3712 ShellPrintHiiEx(-1, -1, NULL,\r
3713 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3714 gShellDebug1HiiHandle,\r
3715 (*BridgeControl & PCI_BIT_10) != 0\r
3716 );\r
3717 ShellPrintHiiEx(-1, -1, NULL,\r
3718 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3719 gShellDebug1HiiHandle,\r
3720 (*BridgeControl & PCI_BIT_11) != 0\r
3721 );\r
3722\r
3723 } else {\r
3724 ShellPrintHiiEx(-1, -1, NULL,\r
3725 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3726 gShellDebug1HiiHandle,\r
3727 (*BridgeControl & PCI_BIT_6) != 0\r
3728 );\r
3729 ShellPrintHiiEx(-1, -1, NULL,\r
3730 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3731 gShellDebug1HiiHandle,\r
3732 (*BridgeControl & PCI_BIT_7) != 0\r
3733 );\r
3734 ShellPrintHiiEx(-1, -1, NULL,\r
3735 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3736 gShellDebug1HiiHandle,\r
3737 (*BridgeControl & PCI_BIT_10) != 0\r
3738 );\r
3739 }\r
3740\r
3741 return EFI_SUCCESS;\r
3742}\r
3743\r
a1d4bfcc 3744/**\r
3745 Print each capability structure.\r
3746\r
3747 @param[in] IoDev The pointer to the deivce.\r
3748 @param[in] Address The address to start at.\r
3749 @param[in] CapPtr The offset from the address.\r
3750\r
3751 @retval EFI_SUCCESS The operation was successful.\r
3752**/\r
5d73d92f 3753EFI_STATUS\r
3754PciExplainCapabilityStruct (\r
3755 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3756 IN UINT64 Address,\r
3757 IN UINT8 CapPtr\r
3758 )\r
3759{\r
3760 UINT8 CapabilityPtr;\r
3761 UINT16 CapabilityEntry;\r
3762 UINT8 CapabilityID;\r
3763 UINT64 RegAddress;\r
3764\r
3765 CapabilityPtr = CapPtr;\r
3766\r
3767 //\r
3768 // Go through the Capability list\r
3769 //\r
3770 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3771 RegAddress = Address + CapabilityPtr;\r
3772 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3773\r
3774 CapabilityID = (UINT8) CapabilityEntry;\r
3775\r
3776 //\r
3777 // Explain PciExpress data\r
3778 //\r
3779 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
3780 PciExplainPciExpress (IoDev, Address, CapabilityPtr);\r
3781 return EFI_SUCCESS;\r
3782 }\r
3783 //\r
3784 // Explain other capabilities here\r
3785 //\r
3786 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3787 }\r
3788\r
3789 return EFI_SUCCESS;\r
3790}\r
3791\r
a1d4bfcc 3792/**\r
3793 Print out information of the capability information.\r
3794\r
3795 @param[in] PciExpressCap The pointer to the structure about the device.\r
3796\r
3797 @retval EFI_SUCCESS The operation was successful.\r
3798**/\r
5d73d92f 3799EFI_STATUS\r
3800ExplainPcieCapReg (\r
3801 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3802 )\r
5d73d92f 3803{\r
3804 UINT16 PcieCapReg;\r
3805 CHAR16 *DevicePortType;\r
3806\r
3807 PcieCapReg = PciExpressCap->PcieCapReg;\r
3808 Print (\r
3809 L" Capability Version(3:0): %E0x%04x%N\n",\r
3810 PCIE_CAP_VERSION (PcieCapReg)\r
3811 );\r
3812 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3813 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3814 } else {\r
3815 DevicePortType = L"Unknown Type";\r
3816 }\r
3817 Print (\r
3818 L" Device/PortType(7:4): %E%s%N\n",\r
3819 DevicePortType\r
3820 );\r
3821 //\r
3822 // 'Slot Implemented' is only valid for:\r
3823 // a) Root Port of PCI Express Root Complex, or\r
3824 // b) Downstream Port of PCI Express Switch\r
3825 //\r
3826 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3827 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
3828 Print (\r
3829 L" Slot Implemented(8): %E%d%N\n",\r
3830 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3831 );\r
3832 }\r
3833 Print (\r
3834 L" Interrupt Message Number(13:9): %E0x%05x%N\n",\r
3835 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3836 );\r
3837 return EFI_SUCCESS;\r
3838}\r
3839\r
a1d4bfcc 3840/**\r
3841 Print out information of the device capability information.\r
3842\r
3843 @param[in] PciExpressCap The pointer to the structure about the device.\r
3844\r
3845 @retval EFI_SUCCESS The operation was successful.\r
3846**/\r
5d73d92f 3847EFI_STATUS\r
3848ExplainPcieDeviceCap (\r
3849 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3850 )\r
5d73d92f 3851{\r
3852 UINT16 PcieCapReg;\r
3853 UINT32 PcieDeviceCap;\r
3854 UINT8 DevicePortType;\r
3855 UINT8 L0sLatency;\r
3856 UINT8 L1Latency;\r
3857\r
3858 PcieCapReg = PciExpressCap->PcieCapReg;\r
3859 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3860 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
3861 Print (L" Max_Payload_Size Supported(2:0): ");\r
3862 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
3863 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
3864 } else {\r
3865 Print (L"%EUnknown%N\n");\r
3866 }\r
3867 Print (\r
3868 L" Phantom Functions Supported(4:3): %E%d%N\n",\r
3869 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3870 );\r
3871 Print (\r
3872 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",\r
3873 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3874 );\r
3875 //\r
3876 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3877 //\r
3878 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
a1d4bfcc 3879 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
3880 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
5d73d92f 3881 Print (L" Endpoint L0s Acceptable Latency(8:6): ");\r
3882 if (L0sLatency < 4) {\r
3883 Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));\r
3884 } else {\r
3885 if (L0sLatency < 7) {\r
3886 Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));\r
3887 } else {\r
3888 Print (L"%ENo limit%N\n");\r
3889 }\r
3890 }\r
3891 Print (L" Endpoint L1 Acceptable Latency(11:9): ");\r
3892 if (L1Latency < 7) {\r
3893 Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));\r
3894 } else {\r
3895 Print (L"%ENo limit%N\n");\r
3896 }\r
3897 }\r
3898 Print (\r
3899 L" Role-based Error Reporting(15): %E%d%N\n",\r
3900 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3901 );\r
3902 //\r
3903 // Only valid for Upstream Port:\r
3904 // a) Captured Slot Power Limit Value\r
3905 // b) Captured Slot Power Scale\r
3906 //\r
3907 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
3908 Print (\r
3909 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",\r
3910 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3911 );\r
3912 Print (\r
3913 L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",\r
3914 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3915 );\r
3916 }\r
3917 //\r
3918 // Function Level Reset Capability is only valid for Endpoint\r
3919 //\r
3920 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
3921 Print (\r
3922 L" Function Level Reset Capability(28): %E%d%N\n",\r
3923 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3924 );\r
3925 }\r
3926 return EFI_SUCCESS;\r
3927}\r
3928\r
a1d4bfcc 3929/**\r
3930 Print out information of the device control information.\r
3931\r
3932 @param[in] PciExpressCap The pointer to the structure about the device.\r
3933\r
3934 @retval EFI_SUCCESS The operation was successful.\r
3935**/\r
5d73d92f 3936EFI_STATUS\r
3937ExplainPcieDeviceControl (\r
3938 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3939 )\r
5d73d92f 3940{\r
3941 UINT16 PcieCapReg;\r
3942 UINT16 PcieDeviceControl;\r
3943\r
3944 PcieCapReg = PciExpressCap->PcieCapReg;\r
3945 PcieDeviceControl = PciExpressCap->DeviceControl;\r
3946 Print (\r
3947 L" Correctable Error Reporting Enable(0): %E%d%N\n",\r
3948 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3949 );\r
3950 Print (\r
3951 L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",\r
3952 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3953 );\r
3954 Print (\r
3955 L" Fatal Error Reporting Enable(2): %E%d%N\n",\r
3956 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3957 );\r
3958 Print (\r
3959 L" Unsupported Request Reporting Enable(3): %E%d%N\n",\r
3960 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
3961 );\r
3962 Print (\r
3963 L" Enable Relaxed Ordering(4): %E%d%N\n",\r
3964 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
3965 );\r
3966 Print (L" Max_Payload_Size(7:5): ");\r
3967 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
3968 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
3969 } else {\r
3970 Print (L"%EUnknown%N\n");\r
3971 }\r
3972 Print (\r
3973 L" Extended Tag Field Enable(8): %E%d%N\n",\r
3974 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
3975 );\r
3976 Print (\r
3977 L" Phantom Functions Enable(9): %E%d%N\n",\r
3978 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
3979 );\r
3980 Print (\r
3981 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",\r
3982 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
3983 );\r
3984 Print (\r
3985 L" Enable No Snoop(11): %E%d%N\n",\r
3986 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
3987 );\r
3988 Print (L" Max_Read_Request_Size(14:12): ");\r
3989 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
3990 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
3991 } else {\r
3992 Print (L"%EUnknown%N\n");\r
3993 }\r
3994 //\r
3995 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
3996 //\r
3997 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
3998 Print (\r
3999 L" Bridge Configuration Retry Enable(15): %E%d%N\n",\r
4000 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
4001 );\r
4002 }\r
4003 return EFI_SUCCESS;\r
4004}\r
4005\r
a1d4bfcc 4006/**\r
4007 Print out information of the device status information.\r
4008\r
4009 @param[in] PciExpressCap The pointer to the structure about the device.\r
4010\r
4011 @retval EFI_SUCCESS The operation was successful.\r
4012**/\r
5d73d92f 4013EFI_STATUS\r
4014ExplainPcieDeviceStatus (\r
4015 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4016 )\r
5d73d92f 4017{\r
4018 UINT16 PcieDeviceStatus;\r
4019\r
4020 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
4021 Print (\r
4022 L" Correctable Error Detected(0): %E%d%N\n",\r
4023 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
4024 );\r
4025 Print (\r
4026 L" Non-Fatal Error Detected(1): %E%d%N\n",\r
4027 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
4028 );\r
4029 Print (\r
4030 L" Fatal Error Detected(2): %E%d%N\n",\r
4031 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
4032 );\r
4033 Print (\r
4034 L" Unsupported Request Detected(3): %E%d%N\n",\r
4035 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
4036 );\r
4037 Print (\r
4038 L" AUX Power Detected(4): %E%d%N\n",\r
4039 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
4040 );\r
4041 Print (\r
4042 L" Transactions Pending(5): %E%d%N\n",\r
4043 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
4044 );\r
4045 return EFI_SUCCESS;\r
4046}\r
4047\r
a1d4bfcc 4048/**\r
4049 Print out information of the device link information.\r
4050\r
4051 @param[in] PciExpressCap The pointer to the structure about the device.\r
4052\r
4053 @retval EFI_SUCCESS The operation was successful.\r
4054**/\r
5d73d92f 4055EFI_STATUS\r
4056ExplainPcieLinkCap (\r
4057 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4058 )\r
5d73d92f 4059{\r
4060 UINT32 PcieLinkCap;\r
4061 CHAR16 *SupLinkSpeeds;\r
a1d4bfcc 4062 CHAR16 *AspmValue;\r
5d73d92f 4063\r
4064 PcieLinkCap = PciExpressCap->LinkCap;\r
4065 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {\r
4066 case 1:\r
4067 SupLinkSpeeds = L"2.5 GT/s";\r
4068 break;\r
4069 case 2:\r
4070 SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";\r
4071 break;\r
4072 default:\r
4073 SupLinkSpeeds = L"Unknown";\r
4074 break;\r
4075 }\r
4076 Print (\r
4077 L" Supported Link Speeds(3:0): %E%s supported%N\n",\r
4078 SupLinkSpeeds\r
4079 );\r
4080 Print (\r
4081 L" Maximum Link Width(9:4): %Ex%d%N\n",\r
4082 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
4083 );\r
4084 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
4085 case 1:\r
a1d4bfcc 4086 AspmValue = L"L0s Entry";\r
5d73d92f 4087 break;\r
4088 case 3:\r
a1d4bfcc 4089 AspmValue = L"L0s and L1";\r
5d73d92f 4090 break;\r
4091 default:\r
a1d4bfcc 4092 AspmValue = L"Reserved";\r
5d73d92f 4093 break;\r
4094 }\r
4095 Print (\r
4096 L" Active State Power Management Support(11:10): %E%s Supported%N\n",\r
a1d4bfcc 4097 AspmValue\r
5d73d92f 4098 );\r
4099 Print (\r
4100 L" L0s Exit Latency(14:12): %E%s%N\n",\r
a1d4bfcc 4101 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4102 );\r
4103 Print (\r
4104 L" L1 Exit Latency(17:15): %E%s%N\n",\r
a1d4bfcc 4105 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4106 );\r
4107 Print (\r
4108 L" Clock Power Management(18): %E%d%N\n",\r
4109 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4110 );\r
4111 Print (\r
4112 L" Surprise Down Error Reporting Capable(19): %E%d%N\n",\r
4113 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4114 );\r
4115 Print (\r
4116 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",\r
4117 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4118 );\r
4119 Print (\r
4120 L" Link Bandwidth Notification Capability(21): %E%d%N\n",\r
4121 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4122 );\r
4123 Print (\r
4124 L" Port Number(31:24): %E0x%02x%N\n",\r
4125 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4126 );\r
4127 return EFI_SUCCESS;\r
4128}\r
4129\r
a1d4bfcc 4130/**\r
4131 Print out information of the device link control information.\r
4132\r
4133 @param[in] PciExpressCap The pointer to the structure about the device.\r
4134\r
4135 @retval EFI_SUCCESS The operation was successful.\r
4136**/\r
5d73d92f 4137EFI_STATUS\r
4138ExplainPcieLinkControl (\r
4139 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4140 )\r
5d73d92f 4141{\r
4142 UINT16 PcieLinkControl;\r
4143 UINT8 DevicePortType;\r
4144\r
4145 PcieLinkControl = PciExpressCap->LinkControl;\r
4146 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
4147 Print (\r
4148 L" Active State Power Management Control(1:0): %E%s%N\n",\r
4149 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4150 );\r
4151 //\r
4152 // RCB is not applicable to switches\r
4153 //\r
4154 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
4155 Print (\r
4156 L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",\r
4157 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4158 );\r
4159 }\r
4160 //\r
4161 // Link Disable is reserved on\r
4162 // a) Endpoints\r
4163 // b) PCI Express to PCI/PCI-X bridges\r
4164 // c) Upstream Ports of Switches\r
4165 //\r
4166 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4167 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4168 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
4169 Print (\r
4170 L" Link Disable(4): %E%d%N\n",\r
4171 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4172 );\r
4173 }\r
4174 Print (\r
4175 L" Common Clock Configuration(6): %E%d%N\n",\r
4176 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4177 );\r
4178 Print (\r
4179 L" Extended Synch(7): %E%d%N\n",\r
4180 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4181 );\r
4182 Print (\r
4183 L" Enable Clock Power Management(8): %E%d%N\n",\r
4184 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4185 );\r
4186 Print (\r
4187 L" Hardware Autonomous Width Disable(9): %E%d%N\n",\r
4188 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4189 );\r
4190 Print (\r
4191 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",\r
4192 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4193 );\r
4194 Print (\r
4195 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",\r
4196 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4197 );\r
4198 return EFI_SUCCESS;\r
4199}\r
4200\r
a1d4bfcc 4201/**\r
4202 Print out information of the device link status information.\r
4203\r
4204 @param[in] PciExpressCap The pointer to the structure about the device.\r
4205\r
4206 @retval EFI_SUCCESS The operation was successful.\r
4207**/\r
5d73d92f 4208EFI_STATUS\r
4209ExplainPcieLinkStatus (\r
4210 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4211 )\r
5d73d92f 4212{\r
4213 UINT16 PcieLinkStatus;\r
4214 CHAR16 *SupLinkSpeeds;\r
4215\r
4216 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4217 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4218 case 1:\r
4219 SupLinkSpeeds = L"2.5 GT/s";\r
4220 break;\r
4221 case 2:\r
4222 SupLinkSpeeds = L"5.0 GT/s";\r
4223 break;\r
4224 default:\r
4225 SupLinkSpeeds = L"Reserved";\r
4226 break;\r
4227 }\r
4228 Print (\r
4229 L" Current Link Speed(3:0): %E%s%N\n",\r
4230 SupLinkSpeeds\r
4231 );\r
4232 Print (\r
4233 L" Negotiated Link Width(9:4): %Ex%d%N\n",\r
4234 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4235 );\r
4236 Print (\r
4237 L" Link Training(11): %E%d%N\n",\r
4238 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4239 );\r
4240 Print (\r
4241 L" Slot Clock Configuration(12): %E%d%N\n",\r
4242 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4243 );\r
4244 Print (\r
4245 L" Data Link Layer Link Active(13): %E%d%N\n",\r
4246 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4247 );\r
4248 Print (\r
4249 L" Link Bandwidth Management Status(14): %E%d%N\n",\r
4250 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4251 );\r
4252 Print (\r
4253 L" Link Autonomous Bandwidth Status(15): %E%d%N\n",\r
4254 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4255 );\r
4256 return EFI_SUCCESS;\r
4257}\r
4258\r
a1d4bfcc 4259/**\r
4260 Print out information of the device slot information.\r
4261\r
4262 @param[in] PciExpressCap The pointer to the structure about the device.\r
4263\r
4264 @retval EFI_SUCCESS The operation was successful.\r
4265**/\r
5d73d92f 4266EFI_STATUS\r
4267ExplainPcieSlotCap (\r
4268 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4269 )\r
5d73d92f 4270{\r
4271 UINT32 PcieSlotCap;\r
4272\r
4273 PcieSlotCap = PciExpressCap->SlotCap;\r
4274\r
4275 Print (\r
4276 L" Attention Button Present(0): %E%d%N\n",\r
4277 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4278 );\r
4279 Print (\r
4280 L" Power Controller Present(1): %E%d%N\n",\r
4281 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4282 );\r
4283 Print (\r
4284 L" MRL Sensor Present(2): %E%d%N\n",\r
4285 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4286 );\r
4287 Print (\r
4288 L" Attention Indicator Present(3): %E%d%N\n",\r
4289 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4290 );\r
4291 Print (\r
4292 L" Power Indicator Present(4): %E%d%N\n",\r
4293 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4294 );\r
4295 Print (\r
4296 L" Hot-Plug Surprise(5): %E%d%N\n",\r
4297 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4298 );\r
4299 Print (\r
4300 L" Hot-Plug Capable(6): %E%d%N\n",\r
4301 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4302 );\r
4303 Print (\r
4304 L" Slot Power Limit Value(14:7): %E0x%02x%N\n",\r
4305 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4306 );\r
4307 Print (\r
4308 L" Slot Power Limit Scale(16:15): %E%s%N\n",\r
4309 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4310 );\r
4311 Print (\r
4312 L" Electromechanical Interlock Present(17): %E%d%N\n",\r
4313 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4314 );\r
4315 Print (\r
4316 L" No Command Completed Support(18): %E%d%N\n",\r
4317 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4318 );\r
4319 Print (\r
4320 L" Physical Slot Number(31:19): %E%d%N\n",\r
4321 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4322 );\r
4323\r
4324 return EFI_SUCCESS;\r
4325}\r
4326\r
a1d4bfcc 4327/**\r
4328 Print out information of the device slot control information.\r
4329\r
4330 @param[in] PciExpressCap The pointer to the structure about the device.\r
4331\r
4332 @retval EFI_SUCCESS The operation was successful.\r
4333**/\r
5d73d92f 4334EFI_STATUS\r
4335ExplainPcieSlotControl (\r
4336 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4337 )\r
5d73d92f 4338{\r
4339 UINT16 PcieSlotControl;\r
4340\r
4341 PcieSlotControl = PciExpressCap->SlotControl;\r
4342 Print (\r
4343 L" Attention Button Pressed Enable(0): %E%d%N\n",\r
4344 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4345 );\r
4346 Print (\r
4347 L" Power Fault Detected Enable(1): %E%d%N\n",\r
4348 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4349 );\r
4350 Print (\r
4351 L" MRL Sensor Changed Enable(2): %E%d%N\n",\r
4352 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4353 );\r
4354 Print (\r
4355 L" Presence Detect Changed Enable(3): %E%d%N\n",\r
4356 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4357 );\r
4358 Print (\r
4359 L" Command Completed Interrupt Enable(4): %E%d%N\n",\r
4360 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4361 );\r
4362 Print (\r
4363 L" Hot-Plug Interrupt Enable(5): %E%d%N\n",\r
4364 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4365 );\r
4366 Print (\r
4367 L" Attention Indicator Control(7:6): %E%s%N\n",\r
4368 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4369 );\r
4370 Print (\r
4371 L" Power Indicator Control(9:8): %E%s%N\n",\r
4372 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4373 );\r
4374 Print (L" Power Controller Control(10): %EPower ");\r
4375 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
4376 Print (L"Off%N\n");\r
4377 } else {\r
4378 Print (L"On%N\n");\r
4379 }\r
4380 Print (\r
4381 L" Electromechanical Interlock Control(11): %E%d%N\n",\r
4382 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4383 );\r
4384 Print (\r
4385 L" Data Link Layer State Changed Enable(12): %E%d%N\n",\r
4386 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4387 );\r
4388 return EFI_SUCCESS;\r
4389}\r
4390\r
a1d4bfcc 4391/**\r
4392 Print out information of the device slot status information.\r
4393\r
4394 @param[in] PciExpressCap The pointer to the structure about the device.\r
4395\r
4396 @retval EFI_SUCCESS The operation was successful.\r
4397**/\r
5d73d92f 4398EFI_STATUS\r
4399ExplainPcieSlotStatus (\r
4400 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4401 )\r
5d73d92f 4402{\r
4403 UINT16 PcieSlotStatus;\r
4404\r
4405 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4406\r
4407 Print (\r
4408 L" Attention Button Pressed(0): %E%d%N\n",\r
4409 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4410 );\r
4411 Print (\r
4412 L" Power Fault Detected(1): %E%d%N\n",\r
4413 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4414 );\r
4415 Print (\r
4416 L" MRL Sensor Changed(2): %E%d%N\n",\r
4417 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4418 );\r
4419 Print (\r
4420 L" Presence Detect Changed(3): %E%d%N\n",\r
4421 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4422 );\r
4423 Print (\r
4424 L" Command Completed(4): %E%d%N\n",\r
4425 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4426 );\r
4427 Print (L" MRL Sensor State(5): %EMRL ");\r
4428 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
4429 Print (L" Opened%N\n");\r
4430 } else {\r
4431 Print (L" Closed%N\n");\r
4432 }\r
4433 Print (L" Presence Detect State(6): ");\r
4434 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
4435 Print (L"%ECard Present in slot%N\n");\r
4436 } else {\r
4437 Print (L"%ESlot Empty%N\n");\r
4438 }\r
4439 Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
4440 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
4441 Print (L"Engaged%N\n");\r
4442 } else {\r
4443 Print (L"Disengaged%N\n");\r
4444 }\r
4445 Print (\r
4446 L" Data Link Layer State Changed(8): %E%d%N\n",\r
4447 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4448 );\r
4449 return EFI_SUCCESS;\r
4450}\r
4451\r
a1d4bfcc 4452/**\r
4453 Print out information of the device root information.\r
4454\r
4455 @param[in] PciExpressCap The pointer to the structure about the device.\r
4456\r
4457 @retval EFI_SUCCESS The operation was successful.\r
4458**/\r
5d73d92f 4459EFI_STATUS\r
4460ExplainPcieRootControl (\r
4461 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4462 )\r
5d73d92f 4463{\r
4464 UINT16 PcieRootControl;\r
4465\r
4466 PcieRootControl = PciExpressCap->RootControl;\r
4467\r
4468 Print (\r
4469 L" System Error on Correctable Error Enable(0): %E%d%N\n",\r
4470 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4471 );\r
4472 Print (\r
4473 L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",\r
4474 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4475 );\r
4476 Print (\r
4477 L" System Error on Fatal Error Enable(2): %E%d%N\n",\r
4478 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4479 );\r
4480 Print (\r
4481 L" PME Interrupt Enable(3): %E%d%N\n",\r
4482 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4483 );\r
4484 Print (\r
4485 L" CRS Software Visibility Enable(4): %E%d%N\n",\r
4486 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4487 );\r
4488\r
4489 return EFI_SUCCESS;\r
4490}\r
4491\r
a1d4bfcc 4492/**\r
4493 Print out information of the device root capability information.\r
4494\r
4495 @param[in] PciExpressCap The pointer to the structure about the device.\r
4496\r
4497 @retval EFI_SUCCESS The operation was successful.\r
4498**/\r
5d73d92f 4499EFI_STATUS\r
4500ExplainPcieRootCap (\r
4501 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4502 )\r
5d73d92f 4503{\r
4504 UINT16 PcieRootCap;\r
4505\r
4506 PcieRootCap = PciExpressCap->RsvdP;\r
4507\r
4508 Print (\r
4509 L" CRS Software Visibility(0): %E%d%N\n",\r
4510 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4511 );\r
4512\r
4513 return EFI_SUCCESS;\r
4514}\r
4515\r
a1d4bfcc 4516/**\r
4517 Print out information of the device root status information.\r
4518\r
4519 @param[in] PciExpressCap The pointer to the structure about the device.\r
4520\r
4521 @retval EFI_SUCCESS The operation was successful.\r
4522**/\r
5d73d92f 4523EFI_STATUS\r
4524ExplainPcieRootStatus (\r
4525 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4526 )\r
5d73d92f 4527{\r
4528 UINT32 PcieRootStatus;\r
4529\r
4530 PcieRootStatus = PciExpressCap->RootStatus;\r
4531\r
4532 Print (\r
4533 L" PME Requester ID(15:0): %E0x%04x%N\n",\r
4534 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4535 );\r
4536 Print (\r
4537 L" PME Status(16): %E%d%N\n",\r
4538 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4539 );\r
4540 Print (\r
4541 L" PME Pending(17): %E%d%N\n",\r
4542 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4543 );\r
4544 return EFI_SUCCESS;\r
4545}\r
4546\r
a1d4bfcc 4547/**\r
4548 Display Pcie device structure.\r
4549\r
4550 @param[in] IoDev The pointer to the root pci protocol.\r
4551 @param[in] Address The Address to start at.\r
4552 @param[in] CapabilityPtr The offset from the address to start.\r
4553**/\r
5d73d92f 4554EFI_STATUS\r
4555PciExplainPciExpress (\r
4556 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
4557 IN UINT64 Address,\r
4558 IN UINT8 CapabilityPtr\r
4559 )\r
4560{\r
4561\r
4562 PCIE_CAP_STURCTURE PciExpressCap;\r
4563 EFI_STATUS Status;\r
4564 UINT64 CapRegAddress;\r
4565 UINT8 Bus;\r
4566 UINT8 Dev;\r
4567 UINT8 Func;\r
4568 UINT8 *ExRegBuffer;\r
4569 UINTN ExtendRegSize;\r
4570 UINT64 Pciex_Address;\r
4571 UINT8 DevicePortType;\r
4572 UINTN Index;\r
4573 UINT8 *RegAddr;\r
4574 UINTN RegValue;\r
4575\r
4576 CapRegAddress = Address + CapabilityPtr;\r
4577 IoDev->Pci.Read (\r
4578 IoDev,\r
4579 EfiPciWidthUint32,\r
4580 CapRegAddress,\r
4581 sizeof (PciExpressCap) / sizeof (UINT32),\r
4582 &PciExpressCap\r
4583 );\r
4584\r
4585 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
4586\r
4587 Print (L"\nPci Express device capability structure:\n");\r
4588\r
4589 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
4590 if (ShellGetExecutionBreakFlag()) {\r
4591 goto Done;\r
4592 }\r
4593 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
4594 switch (PcieExplainList[Index].Width) {\r
4595 case FieldWidthUINT8:\r
4596 RegValue = *(UINT8 *) RegAddr;\r
4597 break;\r
4598 case FieldWidthUINT16:\r
4599 RegValue = *(UINT16 *) RegAddr;\r
4600 break;\r
4601 case FieldWidthUINT32:\r
4602 RegValue = *(UINT32 *) RegAddr;\r
4603 break;\r
4604 default:\r
4605 RegValue = 0;\r
4606 break;\r
4607 }\r
4608 ShellPrintHiiEx(-1, -1, NULL,\r
4609 PcieExplainList[Index].Token,\r
4610 gShellDebug1HiiHandle,\r
4611 PcieExplainList[Index].Offset,\r
4612 RegValue\r
4613 );\r
4614 if (PcieExplainList[Index].Func == NULL) {\r
4615 continue;\r
4616 }\r
4617 switch (PcieExplainList[Index].Type) {\r
4618 case PcieExplainTypeLink:\r
4619 //\r
4620 // Link registers should not be used by\r
4621 // a) Root Complex Integrated Endpoint\r
4622 // b) Root Complex Event Collector\r
4623 //\r
4624 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
4625 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
4626 continue;\r
4627 }\r
4628 break;\r
4629 case PcieExplainTypeSlot:\r
4630 //\r
4631 // Slot registers are only valid for\r
4632 // a) Root Port of PCI Express Root Complex\r
4633 // b) Downstream Port of PCI Express Switch\r
4634 // and when SlotImplemented bit is set in PCIE cap register.\r
4635 //\r
4636 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
4637 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
4638 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
4639 continue;\r
4640 }\r
4641 break;\r
4642 case PcieExplainTypeRoot:\r
4643 //\r
4644 // Root registers are only valid for\r
4645 // Root Port of PCI Express Root Complex\r
4646 //\r
4647 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
4648 continue;\r
4649 }\r
4650 break;\r
4651 default:\r
4652 break;\r
4653 }\r
4654 PcieExplainList[Index].Func (&PciExpressCap);\r
4655 }\r
4656\r
4657 Bus = (UINT8) (RShiftU64 (Address, 24));\r
4658 Dev = (UINT8) (RShiftU64 (Address, 16));\r
4659 Func = (UINT8) (RShiftU64 (Address, 8));\r
4660\r
4661 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);\r
4662\r
4663 ExtendRegSize = 0x1000 - 0x100;\r
4664\r
3737ac2b 4665 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
5d73d92f 4666\r
4667 //\r
4668 // PciRootBridgeIo protocol should support pci express extend space IO\r
4669 // (Begins at offset 0x100)\r
4670 //\r
4671 Status = IoDev->Pci.Read (\r
4672 IoDev,\r
4673 EfiPciWidthUint32,\r
4674 Pciex_Address,\r
4675 (ExtendRegSize) / sizeof (UINT32),\r
4676 (VOID *) (ExRegBuffer)\r
4677 );\r
4678 if (EFI_ERROR (Status)) {\r
4679 FreePool ((VOID *) ExRegBuffer);\r
4680 return EFI_UNSUPPORTED;\r
4681 }\r
4682 //\r
4683 // Start outputing PciEx extend space( 0xFF-0xFFF)\r
4684 //\r
4685 Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");\r
4686\r
d8f8021c 4687 if (ExRegBuffer != NULL) {\r
4688 DumpHex (\r
4689 2,\r
4690 0x100,\r
4691 ExtendRegSize,\r
4692 (VOID *) (ExRegBuffer)\r
4693 );\r
5d73d92f 4694\r
d8f8021c 4695 FreePool ((VOID *) ExRegBuffer);\r
4696 }\r
5d73d92f 4697\r
4698Done:\r
4699 return EFI_SUCCESS;\r
4700}\r
EFI Development Kit II mirror for PVE