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ShellPkg: add the last PCIe extended capability decodings
[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c
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5d73d92f 1/** @file\r
2 Main file for Pci shell Debug1 function.\r
3\r
c37e0f16 4 Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
705bffb5 5 Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>\r
5d73d92f 6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "UefiShellDebug1CommandsLib.h"\r
17#include <Protocol/PciRootBridgeIo.h>\r
18#include <Library/ShellLib.h>\r
19#include <IndustryStandard/Pci.h>\r
20#include <IndustryStandard/Acpi.h>\r
21#include "Pci.h"\r
22\r
23#define PCI_CLASS_STRING_LIMIT 54\r
24//\r
25// Printable strings for Pci class code\r
26//\r
27typedef struct {\r
28 CHAR16 *BaseClass; // Pointer to the PCI base class string\r
29 CHAR16 *SubClass; // Pointer to the PCI sub class string\r
30 CHAR16 *PIFClass; // Pointer to the PCI programming interface string\r
31} PCI_CLASS_STRINGS;\r
32\r
33//\r
34// a structure holding a single entry, which also points to its lower level\r
35// class\r
36//\r
37typedef struct PCI_CLASS_ENTRY_TAG {\r
38 UINT8 Code; // Class, subclass or I/F code\r
39 CHAR16 *DescText; // Description string\r
40 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any\r
41} PCI_CLASS_ENTRY;\r
42\r
43//\r
44// Declarations of entries which contain printable strings for class codes\r
45// in PCI configuration space\r
46//\r
47PCI_CLASS_ENTRY PCIBlankEntry[];\r
48PCI_CLASS_ENTRY PCISubClass_00[];\r
49PCI_CLASS_ENTRY PCISubClass_01[];\r
50PCI_CLASS_ENTRY PCISubClass_02[];\r
51PCI_CLASS_ENTRY PCISubClass_03[];\r
52PCI_CLASS_ENTRY PCISubClass_04[];\r
53PCI_CLASS_ENTRY PCISubClass_05[];\r
54PCI_CLASS_ENTRY PCISubClass_06[];\r
55PCI_CLASS_ENTRY PCISubClass_07[];\r
56PCI_CLASS_ENTRY PCISubClass_08[];\r
57PCI_CLASS_ENTRY PCISubClass_09[];\r
58PCI_CLASS_ENTRY PCISubClass_0a[];\r
59PCI_CLASS_ENTRY PCISubClass_0b[];\r
60PCI_CLASS_ENTRY PCISubClass_0c[];\r
61PCI_CLASS_ENTRY PCISubClass_0d[];\r
62PCI_CLASS_ENTRY PCISubClass_0e[];\r
63PCI_CLASS_ENTRY PCISubClass_0f[];\r
64PCI_CLASS_ENTRY PCISubClass_10[];\r
65PCI_CLASS_ENTRY PCISubClass_11[];\r
66PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
67PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
68PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
69PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
70PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
71PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
72PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
73PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
74PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
75PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
76PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
77PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
78PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
79PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
80\r
81//\r
82// Base class strings entries\r
83//\r
84PCI_CLASS_ENTRY gClassStringList[] = {\r
85 {\r
86 0x00,\r
87 L"Pre 2.0 device",\r
88 PCISubClass_00\r
89 },\r
90 {\r
91 0x01,\r
92 L"Mass Storage Controller",\r
93 PCISubClass_01\r
94 },\r
95 {\r
96 0x02,\r
97 L"Network Controller",\r
98 PCISubClass_02\r
99 },\r
100 {\r
101 0x03,\r
102 L"Display Controller",\r
103 PCISubClass_03\r
104 },\r
105 {\r
106 0x04,\r
107 L"Multimedia Device",\r
108 PCISubClass_04\r
109 },\r
110 {\r
111 0x05,\r
112 L"Memory Controller",\r
113 PCISubClass_05\r
114 },\r
115 {\r
116 0x06,\r
117 L"Bridge Device",\r
118 PCISubClass_06\r
119 },\r
120 {\r
121 0x07,\r
122 L"Simple Communications Controllers",\r
123 PCISubClass_07\r
124 },\r
125 {\r
126 0x08,\r
127 L"Base System Peripherals",\r
128 PCISubClass_08\r
129 },\r
130 {\r
131 0x09,\r
132 L"Input Devices",\r
133 PCISubClass_09\r
134 },\r
135 {\r
136 0x0a,\r
137 L"Docking Stations",\r
138 PCISubClass_0a\r
139 },\r
140 {\r
141 0x0b,\r
142 L"Processors",\r
143 PCISubClass_0b\r
144 },\r
145 {\r
146 0x0c,\r
147 L"Serial Bus Controllers",\r
148 PCISubClass_0c\r
149 },\r
150 {\r
151 0x0d,\r
152 L"Wireless Controllers",\r
153 PCISubClass_0d\r
154 },\r
155 {\r
156 0x0e,\r
157 L"Intelligent IO Controllers",\r
158 PCISubClass_0e\r
159 },\r
160 {\r
161 0x0f,\r
162 L"Satellite Communications Controllers",\r
163 PCISubClass_0f\r
164 },\r
165 {\r
166 0x10,\r
167 L"Encryption/Decryption Controllers",\r
168 PCISubClass_10\r
169 },\r
170 {\r
171 0x11,\r
172 L"Data Acquisition & Signal Processing Controllers",\r
173 PCISubClass_11\r
174 },\r
175 {\r
176 0xff,\r
177 L"Device does not fit in any defined classes",\r
178 PCIBlankEntry\r
179 },\r
180 {\r
181 0x00,\r
182 NULL,\r
183 /* null string ends the list */NULL\r
184 }\r
185};\r
186\r
187//\r
188// Subclass strings entries\r
189//\r
190PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
191 {\r
192 0x00,\r
193 L"",\r
194 PCIBlankEntry\r
195 },\r
196 {\r
197 0x00,\r
198 NULL,\r
199 /* null string ends the list */NULL\r
200 }\r
201};\r
202\r
203PCI_CLASS_ENTRY PCISubClass_00[] = {\r
204 {\r
205 0x00,\r
206 L"All devices other than VGA",\r
207 PCIBlankEntry\r
208 },\r
209 {\r
210 0x01,\r
211 L"VGA-compatible devices",\r
212 PCIBlankEntry\r
213 },\r
214 {\r
215 0x00,\r
216 NULL,\r
217 /* null string ends the list */NULL\r
218 }\r
219};\r
220\r
221PCI_CLASS_ENTRY PCISubClass_01[] = {\r
222 {\r
223 0x00,\r
224 L"SCSI controller",\r
225 PCIBlankEntry\r
226 },\r
227 {\r
228 0x01,\r
229 L"IDE controller",\r
230 PCIPIFClass_0101\r
231 },\r
232 {\r
233 0x02,\r
234 L"Floppy disk controller",\r
235 PCIBlankEntry\r
236 },\r
237 {\r
238 0x03,\r
239 L"IPI controller",\r
240 PCIBlankEntry\r
241 },\r
242 {\r
243 0x04,\r
244 L"RAID controller",\r
245 PCIBlankEntry\r
246 },\r
247 {\r
248 0x80,\r
249 L"Other mass storage controller",\r
250 PCIBlankEntry\r
251 },\r
252 {\r
253 0x00,\r
254 NULL,\r
255 /* null string ends the list */NULL\r
256 }\r
257};\r
258\r
259PCI_CLASS_ENTRY PCISubClass_02[] = {\r
260 {\r
261 0x00,\r
262 L"Ethernet controller",\r
263 PCIBlankEntry\r
264 },\r
265 {\r
266 0x01,\r
267 L"Token ring controller",\r
268 PCIBlankEntry\r
269 },\r
270 {\r
271 0x02,\r
272 L"FDDI controller",\r
273 PCIBlankEntry\r
274 },\r
275 {\r
276 0x03,\r
277 L"ATM controller",\r
278 PCIBlankEntry\r
279 },\r
280 {\r
281 0x04,\r
282 L"ISDN controller",\r
283 PCIBlankEntry\r
284 },\r
285 {\r
286 0x80,\r
287 L"Other network controller",\r
288 PCIBlankEntry\r
289 },\r
290 {\r
291 0x00,\r
292 NULL,\r
293 /* null string ends the list */NULL\r
294 }\r
295};\r
296\r
297PCI_CLASS_ENTRY PCISubClass_03[] = {\r
298 {\r
299 0x00,\r
300 L"VGA/8514 controller",\r
301 PCIPIFClass_0300\r
302 },\r
303 {\r
304 0x01,\r
305 L"XGA controller",\r
306 PCIBlankEntry\r
307 },\r
308 {\r
309 0x02,\r
310 L"3D controller",\r
311 PCIBlankEntry\r
312 },\r
313 {\r
314 0x80,\r
315 L"Other display controller",\r
316 PCIBlankEntry\r
317 },\r
318 {\r
319 0x00,\r
320 NULL,\r
321 /* null string ends the list */PCIBlankEntry\r
322 }\r
323};\r
324\r
325PCI_CLASS_ENTRY PCISubClass_04[] = {\r
326 {\r
327 0x00,\r
328 L"Video device",\r
329 PCIBlankEntry\r
330 },\r
331 {\r
332 0x01,\r
333 L"Audio device",\r
334 PCIBlankEntry\r
335 },\r
336 {\r
337 0x02,\r
338 L"Computer Telephony device",\r
339 PCIBlankEntry\r
340 },\r
341 {\r
342 0x80,\r
343 L"Other multimedia device",\r
344 PCIBlankEntry\r
345 },\r
346 {\r
347 0x00,\r
348 NULL,\r
349 /* null string ends the list */NULL\r
350 }\r
351};\r
352\r
353PCI_CLASS_ENTRY PCISubClass_05[] = {\r
354 {\r
355 0x00,\r
356 L"RAM memory controller",\r
357 PCIBlankEntry\r
358 },\r
359 {\r
360 0x01,\r
361 L"Flash memory controller",\r
362 PCIBlankEntry\r
363 },\r
364 {\r
365 0x80,\r
366 L"Other memory controller",\r
367 PCIBlankEntry\r
368 },\r
369 {\r
370 0x00,\r
371 NULL,\r
372 /* null string ends the list */NULL\r
373 }\r
374};\r
375\r
376PCI_CLASS_ENTRY PCISubClass_06[] = {\r
377 {\r
378 0x00,\r
379 L"Host/PCI bridge",\r
380 PCIBlankEntry\r
381 },\r
382 {\r
383 0x01,\r
384 L"PCI/ISA bridge",\r
385 PCIBlankEntry\r
386 },\r
387 {\r
388 0x02,\r
389 L"PCI/EISA bridge",\r
390 PCIBlankEntry\r
391 },\r
392 {\r
393 0x03,\r
394 L"PCI/Micro Channel bridge",\r
395 PCIBlankEntry\r
396 },\r
397 {\r
398 0x04,\r
399 L"PCI/PCI bridge",\r
400 PCIPIFClass_0604\r
401 },\r
402 {\r
403 0x05,\r
404 L"PCI/PCMCIA bridge",\r
405 PCIBlankEntry\r
406 },\r
407 {\r
408 0x06,\r
409 L"NuBus bridge",\r
410 PCIBlankEntry\r
411 },\r
412 {\r
413 0x07,\r
414 L"CardBus bridge",\r
415 PCIBlankEntry\r
416 },\r
417 {\r
418 0x08,\r
419 L"RACEway bridge",\r
420 PCIBlankEntry\r
421 },\r
422 {\r
423 0x80,\r
424 L"Other bridge type",\r
425 PCIBlankEntry\r
426 },\r
427 {\r
428 0x00,\r
429 NULL,\r
430 /* null string ends the list */NULL\r
431 }\r
432};\r
433\r
434PCI_CLASS_ENTRY PCISubClass_07[] = {\r
435 {\r
436 0x00,\r
437 L"Serial controller",\r
438 PCIPIFClass_0700\r
439 },\r
440 {\r
441 0x01,\r
442 L"Parallel port",\r
443 PCIPIFClass_0701\r
444 },\r
445 {\r
446 0x02,\r
447 L"Multiport serial controller",\r
448 PCIBlankEntry\r
449 },\r
450 {\r
451 0x03,\r
452 L"Modem",\r
453 PCIPIFClass_0703\r
454 },\r
455 {\r
456 0x80,\r
457 L"Other communication device",\r
458 PCIBlankEntry\r
459 },\r
460 {\r
461 0x00,\r
462 NULL,\r
463 /* null string ends the list */NULL\r
464 }\r
465};\r
466\r
467PCI_CLASS_ENTRY PCISubClass_08[] = {\r
468 {\r
469 0x00,\r
470 L"PIC",\r
471 PCIPIFClass_0800\r
472 },\r
473 {\r
474 0x01,\r
475 L"DMA controller",\r
476 PCIPIFClass_0801\r
477 },\r
478 {\r
479 0x02,\r
480 L"System timer",\r
481 PCIPIFClass_0802\r
482 },\r
483 {\r
484 0x03,\r
485 L"RTC controller",\r
486 PCIPIFClass_0803\r
487 },\r
488 {\r
489 0x04,\r
490 L"Generic PCI Hot-Plug controller",\r
491 PCIBlankEntry\r
492 },\r
493 {\r
494 0x80,\r
495 L"Other system peripheral",\r
496 PCIBlankEntry\r
497 },\r
498 {\r
499 0x00,\r
500 NULL,\r
501 /* null string ends the list */NULL\r
502 }\r
503};\r
504\r
505PCI_CLASS_ENTRY PCISubClass_09[] = {\r
506 {\r
507 0x00,\r
508 L"Keyboard controller",\r
509 PCIBlankEntry\r
510 },\r
511 {\r
512 0x01,\r
513 L"Digitizer (pen)",\r
514 PCIBlankEntry\r
515 },\r
516 {\r
517 0x02,\r
518 L"Mouse controller",\r
519 PCIBlankEntry\r
520 },\r
521 {\r
522 0x03,\r
523 L"Scanner controller",\r
524 PCIBlankEntry\r
525 },\r
526 {\r
527 0x04,\r
528 L"Gameport controller",\r
529 PCIPIFClass_0904\r
530 },\r
531 {\r
532 0x80,\r
533 L"Other input controller",\r
534 PCIBlankEntry\r
535 },\r
536 {\r
537 0x00,\r
538 NULL,\r
539 /* null string ends the list */NULL\r
540 }\r
541};\r
542\r
543PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
544 {\r
545 0x00,\r
546 L"Generic docking station",\r
547 PCIBlankEntry\r
548 },\r
549 {\r
550 0x80,\r
551 L"Other type of docking station",\r
552 PCIBlankEntry\r
553 },\r
554 {\r
555 0x00,\r
556 NULL,\r
557 /* null string ends the list */NULL\r
558 }\r
559};\r
560\r
561PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
562 {\r
563 0x00,\r
564 L"386",\r
565 PCIBlankEntry\r
566 },\r
567 {\r
568 0x01,\r
569 L"486",\r
570 PCIBlankEntry\r
571 },\r
572 {\r
573 0x02,\r
574 L"Pentium",\r
575 PCIBlankEntry\r
576 },\r
577 {\r
578 0x10,\r
579 L"Alpha",\r
580 PCIBlankEntry\r
581 },\r
582 {\r
583 0x20,\r
584 L"PowerPC",\r
585 PCIBlankEntry\r
586 },\r
587 {\r
588 0x30,\r
589 L"MIPS",\r
590 PCIBlankEntry\r
591 },\r
592 {\r
593 0x40,\r
594 L"Co-processor",\r
595 PCIBlankEntry\r
596 },\r
597 {\r
598 0x80,\r
599 L"Other processor",\r
600 PCIBlankEntry\r
601 },\r
602 {\r
603 0x00,\r
604 NULL,\r
605 /* null string ends the list */NULL\r
606 }\r
607};\r
608\r
609PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
610 {\r
611 0x00,\r
612 L"Firewire(IEEE 1394)",\r
613 PCIPIFClass_0c03\r
614 },\r
615 {\r
616 0x01,\r
617 L"ACCESS.bus",\r
618 PCIBlankEntry\r
619 },\r
620 {\r
621 0x02,\r
622 L"SSA",\r
623 PCIBlankEntry\r
624 },\r
625 {\r
626 0x03,\r
627 L"USB",\r
628 PCIPIFClass_0c00\r
629 },\r
630 {\r
631 0x04,\r
632 L"Fibre Channel",\r
633 PCIBlankEntry\r
634 },\r
635 {\r
636 0x05,\r
637 L"System Management Bus",\r
638 PCIBlankEntry\r
639 },\r
640 {\r
641 0x80,\r
642 L"Other bus type",\r
643 PCIBlankEntry\r
644 },\r
645 {\r
646 0x00,\r
647 NULL,\r
648 /* null string ends the list */NULL\r
649 }\r
650};\r
651\r
652PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
653 {\r
654 0x00,\r
655 L"iRDA compatible controller",\r
656 PCIBlankEntry\r
657 },\r
658 {\r
659 0x01,\r
660 L"Consumer IR controller",\r
661 PCIBlankEntry\r
662 },\r
663 {\r
664 0x10,\r
665 L"RF controller",\r
666 PCIBlankEntry\r
667 },\r
668 {\r
669 0x80,\r
670 L"Other type of wireless controller",\r
671 PCIBlankEntry\r
672 },\r
673 {\r
674 0x00,\r
675 NULL,\r
676 /* null string ends the list */NULL\r
677 }\r
678};\r
679\r
680PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
681 {\r
682 0x00,\r
683 L"I2O Architecture",\r
684 PCIPIFClass_0e00\r
685 },\r
686 {\r
687 0x00,\r
688 NULL,\r
689 /* null string ends the list */NULL\r
690 }\r
691};\r
692\r
693PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
694 {\r
695 0x00,\r
696 L"TV",\r
697 PCIBlankEntry\r
698 },\r
699 {\r
700 0x01,\r
701 L"Audio",\r
702 PCIBlankEntry\r
703 },\r
704 {\r
705 0x02,\r
706 L"Voice",\r
707 PCIBlankEntry\r
708 },\r
709 {\r
710 0x03,\r
711 L"Data",\r
712 PCIBlankEntry\r
713 },\r
714 {\r
715 0x00,\r
716 NULL,\r
717 /* null string ends the list */NULL\r
718 }\r
719};\r
720\r
721PCI_CLASS_ENTRY PCISubClass_10[] = {\r
722 {\r
723 0x00,\r
724 L"Network & computing Encrypt/Decrypt",\r
725 PCIBlankEntry\r
726 },\r
727 {\r
728 0x01,\r
729 L"Entertainment Encrypt/Decrypt",\r
730 PCIBlankEntry\r
731 },\r
732 {\r
733 0x80,\r
734 L"Other Encrypt/Decrypt",\r
735 PCIBlankEntry\r
736 },\r
737 {\r
738 0x00,\r
739 NULL,\r
740 /* null string ends the list */NULL\r
741 }\r
742};\r
743\r
744PCI_CLASS_ENTRY PCISubClass_11[] = {\r
745 {\r
746 0x00,\r
747 L"DPIO modules",\r
748 PCIBlankEntry\r
749 },\r
750 {\r
751 0x80,\r
752 L"Other DAQ & SP controllers",\r
753 PCIBlankEntry\r
754 },\r
755 {\r
756 0x00,\r
757 NULL,\r
758 /* null string ends the list */NULL\r
759 }\r
760};\r
761\r
762//\r
763// Programming Interface entries\r
764//\r
765PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
766 {\r
767 0x00,\r
768 L"",\r
769 PCIBlankEntry\r
770 },\r
771 {\r
772 0x01,\r
773 L"OM-primary",\r
774 PCIBlankEntry\r
775 },\r
776 {\r
777 0x02,\r
778 L"PI-primary",\r
779 PCIBlankEntry\r
780 },\r
781 {\r
782 0x03,\r
783 L"OM/PI-primary",\r
784 PCIBlankEntry\r
785 },\r
786 {\r
787 0x04,\r
788 L"OM-secondary",\r
789 PCIBlankEntry\r
790 },\r
791 {\r
792 0x05,\r
793 L"OM-primary, OM-secondary",\r
794 PCIBlankEntry\r
795 },\r
796 {\r
797 0x06,\r
798 L"PI-primary, OM-secondary",\r
799 PCIBlankEntry\r
800 },\r
801 {\r
802 0x07,\r
803 L"OM/PI-primary, OM-secondary",\r
804 PCIBlankEntry\r
805 },\r
806 {\r
807 0x08,\r
808 L"OM-secondary",\r
809 PCIBlankEntry\r
810 },\r
811 {\r
812 0x09,\r
813 L"OM-primary, PI-secondary",\r
814 PCIBlankEntry\r
815 },\r
816 {\r
817 0x0a,\r
818 L"PI-primary, PI-secondary",\r
819 PCIBlankEntry\r
820 },\r
821 {\r
822 0x0b,\r
823 L"OM/PI-primary, PI-secondary",\r
824 PCIBlankEntry\r
825 },\r
826 {\r
827 0x0c,\r
828 L"OM-secondary",\r
829 PCIBlankEntry\r
830 },\r
831 {\r
832 0x0d,\r
833 L"OM-primary, OM/PI-secondary",\r
834 PCIBlankEntry\r
835 },\r
836 {\r
837 0x0e,\r
838 L"PI-primary, OM/PI-secondary",\r
839 PCIBlankEntry\r
840 },\r
841 {\r
842 0x0f,\r
843 L"OM/PI-primary, OM/PI-secondary",\r
844 PCIBlankEntry\r
845 },\r
846 {\r
847 0x80,\r
848 L"Master",\r
849 PCIBlankEntry\r
850 },\r
851 {\r
852 0x81,\r
853 L"Master, OM-primary",\r
854 PCIBlankEntry\r
855 },\r
856 {\r
857 0x82,\r
858 L"Master, PI-primary",\r
859 PCIBlankEntry\r
860 },\r
861 {\r
862 0x83,\r
863 L"Master, OM/PI-primary",\r
864 PCIBlankEntry\r
865 },\r
866 {\r
867 0x84,\r
868 L"Master, OM-secondary",\r
869 PCIBlankEntry\r
870 },\r
871 {\r
872 0x85,\r
873 L"Master, OM-primary, OM-secondary",\r
874 PCIBlankEntry\r
875 },\r
876 {\r
877 0x86,\r
878 L"Master, PI-primary, OM-secondary",\r
879 PCIBlankEntry\r
880 },\r
881 {\r
882 0x87,\r
883 L"Master, OM/PI-primary, OM-secondary",\r
884 PCIBlankEntry\r
885 },\r
886 {\r
887 0x88,\r
888 L"Master, OM-secondary",\r
889 PCIBlankEntry\r
890 },\r
891 {\r
892 0x89,\r
893 L"Master, OM-primary, PI-secondary",\r
894 PCIBlankEntry\r
895 },\r
896 {\r
897 0x8a,\r
898 L"Master, PI-primary, PI-secondary",\r
899 PCIBlankEntry\r
900 },\r
901 {\r
902 0x8b,\r
903 L"Master, OM/PI-primary, PI-secondary",\r
904 PCIBlankEntry\r
905 },\r
906 {\r
907 0x8c,\r
908 L"Master, OM-secondary",\r
909 PCIBlankEntry\r
910 },\r
911 {\r
912 0x8d,\r
913 L"Master, OM-primary, OM/PI-secondary",\r
914 PCIBlankEntry\r
915 },\r
916 {\r
917 0x8e,\r
918 L"Master, PI-primary, OM/PI-secondary",\r
919 PCIBlankEntry\r
920 },\r
921 {\r
922 0x8f,\r
923 L"Master, OM/PI-primary, OM/PI-secondary",\r
924 PCIBlankEntry\r
925 },\r
926 {\r
927 0x00,\r
928 NULL,\r
929 /* null string ends the list */NULL\r
930 }\r
931};\r
932\r
933PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
934 {\r
935 0x00,\r
936 L"VGA compatible",\r
937 PCIBlankEntry\r
938 },\r
939 {\r
940 0x01,\r
941 L"8514 compatible",\r
942 PCIBlankEntry\r
943 },\r
944 {\r
945 0x00,\r
946 NULL,\r
947 /* null string ends the list */NULL\r
948 }\r
949};\r
950\r
951PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
952 {\r
953 0x00,\r
954 L"",\r
955 PCIBlankEntry\r
956 },\r
957 {\r
958 0x01,\r
959 L"Subtractive decode",\r
960 PCIBlankEntry\r
961 },\r
962 {\r
963 0x00,\r
964 NULL,\r
965 /* null string ends the list */NULL\r
966 }\r
967};\r
968\r
969PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
970 {\r
971 0x00,\r
972 L"Generic XT-compatible",\r
973 PCIBlankEntry\r
974 },\r
975 {\r
976 0x01,\r
977 L"16450-compatible",\r
978 PCIBlankEntry\r
979 },\r
980 {\r
981 0x02,\r
982 L"16550-compatible",\r
983 PCIBlankEntry\r
984 },\r
985 {\r
986 0x03,\r
987 L"16650-compatible",\r
988 PCIBlankEntry\r
989 },\r
990 {\r
991 0x04,\r
992 L"16750-compatible",\r
993 PCIBlankEntry\r
994 },\r
995 {\r
996 0x05,\r
997 L"16850-compatible",\r
998 PCIBlankEntry\r
999 },\r
1000 {\r
1001 0x06,\r
1002 L"16950-compatible",\r
1003 PCIBlankEntry\r
1004 },\r
1005 {\r
1006 0x00,\r
1007 NULL,\r
1008 /* null string ends the list */NULL\r
1009 }\r
1010};\r
1011\r
1012PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
1013 {\r
1014 0x00,\r
1015 L"",\r
1016 PCIBlankEntry\r
1017 },\r
1018 {\r
1019 0x01,\r
1020 L"Bi-directional",\r
1021 PCIBlankEntry\r
1022 },\r
1023 {\r
1024 0x02,\r
1025 L"ECP 1.X-compliant",\r
1026 PCIBlankEntry\r
1027 },\r
1028 {\r
1029 0x03,\r
1030 L"IEEE 1284",\r
1031 PCIBlankEntry\r
1032 },\r
1033 {\r
1034 0xfe,\r
1035 L"IEEE 1284 target (not a controller)",\r
1036 PCIBlankEntry\r
1037 },\r
1038 {\r
1039 0x00,\r
1040 NULL,\r
1041 /* null string ends the list */NULL\r
1042 }\r
1043};\r
1044\r
1045PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
1046 {\r
1047 0x00,\r
1048 L"Generic",\r
1049 PCIBlankEntry\r
1050 },\r
1051 {\r
1052 0x01,\r
1053 L"Hayes-compatible 16450",\r
1054 PCIBlankEntry\r
1055 },\r
1056 {\r
1057 0x02,\r
1058 L"Hayes-compatible 16550",\r
1059 PCIBlankEntry\r
1060 },\r
1061 {\r
1062 0x03,\r
1063 L"Hayes-compatible 16650",\r
1064 PCIBlankEntry\r
1065 },\r
1066 {\r
1067 0x04,\r
1068 L"Hayes-compatible 16750",\r
1069 PCIBlankEntry\r
1070 },\r
1071 {\r
1072 0x00,\r
1073 NULL,\r
1074 /* null string ends the list */NULL\r
1075 }\r
1076};\r
1077\r
1078PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
1079 {\r
1080 0x00,\r
1081 L"Generic 8259",\r
1082 PCIBlankEntry\r
1083 },\r
1084 {\r
1085 0x01,\r
1086 L"ISA",\r
1087 PCIBlankEntry\r
1088 },\r
1089 {\r
1090 0x02,\r
1091 L"EISA",\r
1092 PCIBlankEntry\r
1093 },\r
1094 {\r
1095 0x10,\r
1096 L"IO APIC",\r
1097 PCIBlankEntry\r
1098 },\r
1099 {\r
1100 0x20,\r
1101 L"IO(x) APIC interrupt controller",\r
1102 PCIBlankEntry\r
1103 },\r
1104 {\r
1105 0x00,\r
1106 NULL,\r
1107 /* null string ends the list */NULL\r
1108 }\r
1109};\r
1110\r
1111PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
1112 {\r
1113 0x00,\r
1114 L"Generic 8237",\r
1115 PCIBlankEntry\r
1116 },\r
1117 {\r
1118 0x01,\r
1119 L"ISA",\r
1120 PCIBlankEntry\r
1121 },\r
1122 {\r
1123 0x02,\r
1124 L"EISA",\r
1125 PCIBlankEntry\r
1126 },\r
1127 {\r
1128 0x00,\r
1129 NULL,\r
1130 /* null string ends the list */NULL\r
1131 }\r
1132};\r
1133\r
1134PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
1135 {\r
1136 0x00,\r
1137 L"Generic 8254",\r
1138 PCIBlankEntry\r
1139 },\r
1140 {\r
1141 0x01,\r
1142 L"ISA",\r
1143 PCIBlankEntry\r
1144 },\r
1145 {\r
1146 0x02,\r
1147 L"EISA",\r
1148 PCIBlankEntry\r
1149 },\r
1150 {\r
1151 0x00,\r
1152 NULL,\r
1153 /* null string ends the list */NULL\r
1154 }\r
1155};\r
1156\r
1157PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
1158 {\r
1159 0x00,\r
1160 L"Generic",\r
1161 PCIBlankEntry\r
1162 },\r
1163 {\r
1164 0x01,\r
1165 L"ISA",\r
1166 PCIBlankEntry\r
1167 },\r
1168 {\r
1169 0x02,\r
1170 L"EISA",\r
1171 PCIBlankEntry\r
1172 },\r
1173 {\r
1174 0x00,\r
1175 NULL,\r
1176 /* null string ends the list */NULL\r
1177 }\r
1178};\r
1179\r
1180PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
1181 {\r
1182 0x00,\r
1183 L"Generic",\r
1184 PCIBlankEntry\r
1185 },\r
1186 {\r
1187 0x10,\r
1188 L"",\r
1189 PCIBlankEntry\r
1190 },\r
1191 {\r
1192 0x00,\r
1193 NULL,\r
1194 /* null string ends the list */NULL\r
1195 }\r
1196};\r
1197\r
1198PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
1199 {\r
1200 0x00,\r
1201 L"Universal Host Controller spec",\r
1202 PCIBlankEntry\r
1203 },\r
1204 {\r
1205 0x10,\r
1206 L"Open Host Controller spec",\r
1207 PCIBlankEntry\r
1208 },\r
1209 {\r
1210 0x80,\r
1211 L"No specific programming interface",\r
1212 PCIBlankEntry\r
1213 },\r
1214 {\r
1215 0xfe,\r
1216 L"(Not Host Controller)",\r
1217 PCIBlankEntry\r
1218 },\r
1219 {\r
1220 0x00,\r
1221 NULL,\r
1222 /* null string ends the list */NULL\r
1223 }\r
1224};\r
1225\r
1226PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
1227 {\r
1228 0x00,\r
1229 L"",\r
1230 PCIBlankEntry\r
1231 },\r
1232 {\r
1233 0x10,\r
1234 L"Using 1394 OpenHCI spec",\r
1235 PCIBlankEntry\r
1236 },\r
1237 {\r
1238 0x00,\r
1239 NULL,\r
1240 /* null string ends the list */NULL\r
1241 }\r
1242};\r
1243\r
1244PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
1245 {\r
1246 0x00,\r
1247 L"Message FIFO at offset 40h",\r
1248 PCIBlankEntry\r
1249 },\r
1250 {\r
1251 0x01,\r
1252 L"",\r
1253 PCIBlankEntry\r
1254 },\r
1255 {\r
1256 0x00,\r
1257 NULL,\r
1258 /* null string ends the list */NULL\r
1259 }\r
1260};\r
1261\r
5d73d92f 1262\r
a1d4bfcc 1263/**\r
5d73d92f 1264 Generates printable Unicode strings that represent PCI device class,\r
1265 subclass and programmed I/F based on a value passed to the function.\r
1266\r
a1d4bfcc 1267 @param[in] ClassCode Value representing the PCI "Class Code" register read from a\r
5d73d92f 1268 PCI device. The encodings are:\r
1269 bits 23:16 - Base Class Code\r
1270 bits 15:8 - Sub-Class Code\r
1271 bits 7:0 - Programming Interface\r
4ff7e37b 1272 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains\r
5d73d92f 1273 printable class strings corresponding to ClassCode. The\r
1274 caller must not modify the strings that are pointed by\r
1275 the fields in ClassStrings.\r
5d73d92f 1276**/\r
a1d4bfcc 1277VOID\r
1278PciGetClassStrings (\r
1279 IN UINT32 ClassCode,\r
1280 IN OUT PCI_CLASS_STRINGS *ClassStrings\r
1281 )\r
5d73d92f 1282{\r
1283 INTN Index;\r
1284 UINT8 Code;\r
1285 PCI_CLASS_ENTRY *CurrentClass;\r
1286\r
1287 //\r
1288 // Assume no strings found\r
1289 //\r
1290 ClassStrings->BaseClass = L"UNDEFINED";\r
1291 ClassStrings->SubClass = L"UNDEFINED";\r
1292 ClassStrings->PIFClass = L"UNDEFINED";\r
1293\r
1294 CurrentClass = gClassStringList;\r
1295 Code = (UINT8) (ClassCode >> 16);\r
1296 Index = 0;\r
1297\r
1298 //\r
1299 // Go through all entries of the base class, until the entry with a matching\r
1300 // base class code is found. If reaches an entry with a null description\r
1301 // text, the last entry is met, which means no text for the base class was\r
1302 // found, so no more action is needed.\r
1303 //\r
1304 while (Code != CurrentClass[Index].Code) {\r
1305 if (NULL == CurrentClass[Index].DescText) {\r
1306 return ;\r
1307 }\r
1308\r
1309 Index++;\r
1310 }\r
1311 //\r
1312 // A base class was found. Assign description, and check if this class has\r
1313 // sub-class defined. If sub-class defined, no more action is needed,\r
1314 // otherwise, continue to find description for the sub-class code.\r
1315 //\r
1316 ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
1317 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1318 return ;\r
1319 }\r
1320 //\r
1321 // find Subclass entry\r
1322 //\r
1323 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1324 Code = (UINT8) (ClassCode >> 8);\r
1325 Index = 0;\r
1326\r
1327 //\r
1328 // Go through all entries of the sub-class, until the entry with a matching\r
1329 // sub-class code is found. If reaches an entry with a null description\r
1330 // text, the last entry is met, which means no text for the sub-class was\r
1331 // found, so no more action is needed.\r
1332 //\r
1333 while (Code != CurrentClass[Index].Code) {\r
1334 if (NULL == CurrentClass[Index].DescText) {\r
1335 return ;\r
1336 }\r
1337\r
1338 Index++;\r
1339 }\r
1340 //\r
1341 // A class was found for the sub-class code. Assign description, and check if\r
1342 // this sub-class has programming interface defined. If no, no more action is\r
1343 // needed, otherwise, continue to find description for the programming\r
1344 // interface.\r
1345 //\r
1346 ClassStrings->SubClass = CurrentClass[Index].DescText;\r
1347 if (NULL == CurrentClass[Index].LowerLevelClass) {\r
1348 return ;\r
1349 }\r
1350 //\r
1351 // Find programming interface entry\r
1352 //\r
1353 CurrentClass = CurrentClass[Index].LowerLevelClass;\r
1354 Code = (UINT8) ClassCode;\r
1355 Index = 0;\r
1356\r
1357 //\r
1358 // Go through all entries of the I/F entries, until the entry with a\r
1359 // matching I/F code is found. If reaches an entry with a null description\r
1360 // text, the last entry is met, which means no text was found, so no more\r
1361 // action is needed.\r
1362 //\r
1363 while (Code != CurrentClass[Index].Code) {\r
1364 if (NULL == CurrentClass[Index].DescText) {\r
1365 return ;\r
1366 }\r
1367\r
1368 Index++;\r
1369 }\r
1370 //\r
1371 // A class was found for the I/F code. Assign description, done!\r
1372 //\r
1373 ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
1374 return ;\r
1375}\r
1376\r
a1d4bfcc 1377/**\r
1378 Print strings that represent PCI device class, subclass and programmed I/F.\r
1379\r
1380 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
1381 configuation space.\r
1382 @param[in] IncludePIF If the printed string should include the programming I/F part\r
1383**/\r
5d73d92f 1384VOID\r
1385PciPrintClassCode (\r
1386 IN UINT8 *ClassCodePtr,\r
1387 IN BOOLEAN IncludePIF\r
1388 )\r
5d73d92f 1389{\r
1390 UINT32 ClassCode;\r
1391 PCI_CLASS_STRINGS ClassStrings;\r
5d73d92f 1392\r
1393 ClassCode = 0;\r
1394 ClassCode |= ClassCodePtr[0];\r
1395 ClassCode |= (ClassCodePtr[1] << 8);\r
1396 ClassCode |= (ClassCodePtr[2] << 16);\r
1397\r
1398 //\r
1399 // Get name from class code\r
1400 //\r
1401 PciGetClassStrings (ClassCode, &ClassStrings);\r
1402\r
1403 if (IncludePIF) {\r
1404 //\r
c37e0f16 1405 // Print base class, sub class, and programming inferface name\r
5d73d92f 1406 //\r
c37e0f16 1407 ShellPrintEx (-1, -1, L"%s - %s - %s",\r
5d73d92f 1408 ClassStrings.BaseClass,\r
1409 ClassStrings.SubClass,\r
1410 ClassStrings.PIFClass\r
1411 );\r
1412\r
1413 } else {\r
1414 //\r
c37e0f16 1415 // Only print base class and sub class name\r
5d73d92f 1416 //\r
c37e0f16 1417 ShellPrintEx (-1, -1, L"%s - %s",\r
5d73d92f 1418 ClassStrings.BaseClass,\r
1419 ClassStrings.SubClass\r
c37e0f16 1420 );\r
5d73d92f 1421 }\r
1422}\r
1423\r
a1d4bfcc 1424/**\r
1425 This function finds out the protocol which is in charge of the given\r
1426 segment, and its bus range covers the current bus number. It lookes\r
1427 each instances of RootBridgeIoProtocol handle, until the one meets the\r
1428 criteria is found.\r
1429\r
1430 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1431 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
1432 @param[in] Segment Segment number of device we are dealing with.\r
1433 @param[in] Bus Bus number of device we are dealing with.\r
1434 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1435\r
1436 @retval EFI_SUCCESS The command completed successfully.\r
1437 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 1438\r
a1d4bfcc 1439**/\r
5d73d92f 1440EFI_STATUS\r
1441PciFindProtocolInterface (\r
1442 IN EFI_HANDLE *HandleBuf,\r
1443 IN UINTN HandleCount,\r
1444 IN UINT16 Segment,\r
1445 IN UINT16 Bus,\r
1446 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
1447 );\r
1448\r
a1d4bfcc 1449/**\r
1450 This function gets the protocol interface from the given handle, and\r
1451 obtains its address space descriptors.\r
1452\r
1453 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
1454 @param[out] IoDev Handle used to access configuration space of PCI device.\r
1455 @param[out] Descriptors Points to the address space descriptors.\r
1456\r
1457 @retval EFI_SUCCESS The command completed successfully\r
1458**/\r
5d73d92f 1459EFI_STATUS\r
1460PciGetProtocolAndResource (\r
1461 IN EFI_HANDLE Handle,\r
1462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
1463 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
1464 );\r
1465\r
a1d4bfcc 1466/**\r
1467 This function get the next bus range of given address space descriptors.\r
1468 It also moves the pointer backward a node, to get prepared to be called\r
1469 again.\r
1470\r
4ff7e37b
ED		 1471 @param[in, out] Descriptors Points to current position of a serial of address space\r
1472 descriptors.\r
1473 @param[out] MinBus The lower range of bus number.\r
1474 @param[out] MaxBus The upper range of bus number.\r
1475 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 1476\r
1477 @retval EFI_SUCCESS The command completed successfully.\r
1478**/\r
5d73d92f 1479EFI_STATUS\r
1480PciGetNextBusRange (\r
1481 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
1482 OUT UINT16 *MinBus,\r
1483 OUT UINT16 *MaxBus,\r
1484 OUT BOOLEAN *IsEnd\r
1485 );\r
1486\r
a1d4bfcc 1487/**\r
1488 Explain the data in PCI configuration space. The part which is common for\r
1489 PCI device and bridge is interpreted in this function. It calls other\r
1490 functions to interpret data unique for device or bridge.\r
1491\r
1492 @param[in] ConfigSpace Data in PCI configuration space.\r
1493 @param[in] Address Address used to access configuration space of this PCI device.\r
1494 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1495\r
1496 @retval EFI_SUCCESS The command completed successfully.\r
1497**/\r
5d73d92f 1498EFI_STATUS\r
1499PciExplainData (\r
1500 IN PCI_CONFIG_SPACE *ConfigSpace,\r
1501 IN UINT64 Address,\r
705bffb5
JC		 1502 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1503 IN CONST UINT16 EnhancedDump\r
5d73d92f 1504 );\r
1505\r
a1d4bfcc 1506/**\r
1507 Explain the device specific part of data in PCI configuration space.\r
1508\r
1509 @param[in] Device Data in PCI configuration space.\r
1510 @param[in] Address Address used to access configuration space of this PCI device.\r
1511 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1512\r
1513 @retval EFI_SUCCESS The command completed successfully.\r
1514**/\r
5d73d92f 1515EFI_STATUS\r
1516PciExplainDeviceData (\r
1517 IN PCI_DEVICE_HEADER *Device,\r
1518 IN UINT64 Address,\r
1519 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1520 );\r
1521\r
a1d4bfcc 1522/**\r
1523 Explain the bridge specific part of data in PCI configuration space.\r
1524\r
1525 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
1526 @param[in] Address Address used to access configuration space of this PCI device.\r
1527 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1528\r
1529 @retval EFI_SUCCESS The command completed successfully.\r
1530**/\r
5d73d92f 1531EFI_STATUS\r
1532PciExplainBridgeData (\r
a1d4bfcc 1533 IN PCI_BRIDGE_HEADER *Bridge,\r
1534 IN UINT64 Address,\r
1535 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
5d73d92f 1536 );\r
1537\r
a1d4bfcc 1538/**\r
1539 Explain the Base Address Register(Bar) in PCI configuration space.\r
1540\r
4ff7e37b
ED		 1541 @param[in] Bar Points to the Base Address Register intended to interpret.\r
1542 @param[in] Command Points to the register Command.\r
1543 @param[in] Address Address used to access configuration space of this PCI device.\r
1544 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1545 @param[in, out] Index The Index.\r
a1d4bfcc 1546\r
1547 @retval EFI_SUCCESS The command completed successfully.\r
1548**/\r
5d73d92f 1549EFI_STATUS\r
1550PciExplainBar (\r
1551 IN UINT32 *Bar,\r
1552 IN UINT16 *Command,\r
1553 IN UINT64 Address,\r
1554 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1555 IN OUT UINTN *Index\r
1556 );\r
1557\r
a1d4bfcc 1558/**\r
1559 Explain the cardbus specific part of data in PCI configuration space.\r
1560\r
1561 @param[in] CardBus CardBus specific region of PCI configuration space.\r
1562 @param[in] Address Address used to access configuration space of this PCI device.\r
1563 @param[in] IoDev Handle used to access configuration space of PCI device.\r
1564\r
1565 @retval EFI_SUCCESS The command completed successfully.\r
1566**/\r
5d73d92f 1567EFI_STATUS\r
1568PciExplainCardBusData (\r
1569 IN PCI_CARDBUS_HEADER *CardBus,\r
1570 IN UINT64 Address,\r
1571 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
1572 );\r
1573\r
a1d4bfcc 1574/**\r
1575 Explain each meaningful bit of register Status. The definition of Status is\r
1576 slightly different depending on the PCI header type.\r
1577\r
1578 @param[in] Status Points to the content of register Status.\r
1579 @param[in] MainStatus Indicates if this register is main status(not secondary\r
1580 status).\r
1581 @param[in] HeaderType Header type of this PCI device.\r
1582\r
1583 @retval EFI_SUCCESS The command completed successfully.\r
1584**/\r
5d73d92f 1585EFI_STATUS\r
1586PciExplainStatus (\r
1587 IN UINT16 *Status,\r
1588 IN BOOLEAN MainStatus,\r
1589 IN PCI_HEADER_TYPE HeaderType\r
1590 );\r
1591\r
a1d4bfcc 1592/**\r
1593 Explain each meaningful bit of register Command.\r
1594\r
1595 @param[in] Command Points to the content of register Command.\r
1596\r
1597 @retval EFI_SUCCESS The command completed successfully.\r
1598**/\r
5d73d92f 1599EFI_STATUS\r
1600PciExplainCommand (\r
1601 IN UINT16 *Command\r
1602 );\r
1603\r
a1d4bfcc 1604/**\r
1605 Explain each meaningful bit of register Bridge Control.\r
1606\r
1607 @param[in] BridgeControl Points to the content of register Bridge Control.\r
1608 @param[in] HeaderType The headertype.\r
1609\r
1610 @retval EFI_SUCCESS The command completed successfully.\r
1611**/\r
5d73d92f 1612EFI_STATUS\r
1613PciExplainBridgeControl (\r
1614 IN UINT16 *BridgeControl,\r
1615 IN PCI_HEADER_TYPE HeaderType\r
1616 );\r
1617\r
a1d4bfcc 1618/**\r
1619 Print each capability structure.\r
1620\r
1621 @param[in] IoDev The pointer to the deivce.\r
1622 @param[in] Address The address to start at.\r
1623 @param[in] CapPtr The offset from the address.\r
1624\r
1625 @retval EFI_SUCCESS The operation was successful.\r
1626**/\r
5d73d92f 1627EFI_STATUS\r
1628PciExplainCapabilityStruct (\r
1629 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1630 IN UINT64 Address,\r
705bffb5
JC		 1631 IN UINT8 CapPtr,\r
1632 IN CONST UINT16 EnhancedDump\r
5d73d92f 1633 );\r
1634\r
a1d4bfcc 1635/**\r
1636 Display Pcie device structure.\r
1637\r
1638 @param[in] IoDev The pointer to the root pci protocol.\r
1639 @param[in] Address The Address to start at.\r
1640 @param[in] CapabilityPtr The offset from the address to start.\r
1641**/\r
5d73d92f 1642EFI_STATUS\r
1643PciExplainPciExpress (\r
1644 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
1645 IN UINT64 Address,\r
705bffb5
JC		 1646 IN UINT8 CapabilityPtr,\r
1647 IN CONST UINT16 EnhancedDump\r
5d73d92f 1648 );\r
1649\r
a1d4bfcc 1650/**\r
1651 Print out information of the capability information.\r
1652\r
1653 @param[in] PciExpressCap The pointer to the structure about the device.\r
1654\r
1655 @retval EFI_SUCCESS The operation was successful.\r
1656**/\r
5d73d92f 1657EFI_STATUS\r
1658ExplainPcieCapReg (\r
1659 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1660 );\r
1661\r
1662/**\r
1663 Print out information of the device capability information.\r
1664\r
1665 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1666\r
a1d4bfcc 1667 @retval EFI_SUCCESS The operation was successful.\r
1668**/\r
5d73d92f 1669EFI_STATUS\r
1670ExplainPcieDeviceCap (\r
1671 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1672 );\r
1673\r
1674/**\r
1675 Print out information of the device control information.\r
5d73d92f 1676\r
a1d4bfcc 1677 @param[in] PciExpressCap The pointer to the structure about the device.\r
1678\r
1679 @retval EFI_SUCCESS The operation was successful.\r
1680**/\r
5d73d92f 1681EFI_STATUS\r
1682ExplainPcieDeviceControl (\r
1683 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1684 );\r
5d73d92f 1685\r
a1d4bfcc 1686/**\r
1687 Print out information of the device status information.\r
1688\r
1689 @param[in] PciExpressCap The pointer to the structure about the device.\r
1690\r
1691 @retval EFI_SUCCESS The operation was successful.\r
1692**/\r
5d73d92f 1693EFI_STATUS\r
1694ExplainPcieDeviceStatus (\r
1695 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1696 );\r
1697\r
1698/**\r
1699 Print out information of the device link information.\r
1700\r
1701 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1702\r
a1d4bfcc 1703 @retval EFI_SUCCESS The operation was successful.\r
1704**/\r
5d73d92f 1705EFI_STATUS\r
1706ExplainPcieLinkCap (\r
1707 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1708 );\r
1709\r
1710/**\r
1711 Print out information of the device link control information.\r
5d73d92f 1712\r
a1d4bfcc 1713 @param[in] PciExpressCap The pointer to the structure about the device.\r
1714\r
1715 @retval EFI_SUCCESS The operation was successful.\r
1716**/\r
5d73d92f 1717EFI_STATUS\r
1718ExplainPcieLinkControl (\r
1719 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1720 );\r
5d73d92f 1721\r
a1d4bfcc 1722/**\r
1723 Print out information of the device link status information.\r
1724\r
1725 @param[in] PciExpressCap The pointer to the structure about the device.\r
1726\r
1727 @retval EFI_SUCCESS The operation was successful.\r
1728**/\r
5d73d92f 1729EFI_STATUS\r
1730ExplainPcieLinkStatus (\r
1731 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1732 );\r
1733\r
1734/**\r
1735 Print out information of the device slot information.\r
1736\r
1737 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1738\r
a1d4bfcc 1739 @retval EFI_SUCCESS The operation was successful.\r
1740**/\r
5d73d92f 1741EFI_STATUS\r
1742ExplainPcieSlotCap (\r
1743 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1744 );\r
1745\r
1746/**\r
1747 Print out information of the device slot control information.\r
5d73d92f 1748\r
a1d4bfcc 1749 @param[in] PciExpressCap The pointer to the structure about the device.\r
1750\r
1751 @retval EFI_SUCCESS The operation was successful.\r
1752**/\r
5d73d92f 1753EFI_STATUS\r
1754ExplainPcieSlotControl (\r
1755 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1756 );\r
5d73d92f 1757\r
a1d4bfcc 1758/**\r
1759 Print out information of the device slot status information.\r
1760\r
1761 @param[in] PciExpressCap The pointer to the structure about the device.\r
1762\r
1763 @retval EFI_SUCCESS The operation was successful.\r
1764**/\r
5d73d92f 1765EFI_STATUS\r
1766ExplainPcieSlotStatus (\r
1767 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1768 );\r
1769\r
1770/**\r
1771 Print out information of the device root information.\r
1772\r
1773 @param[in] PciExpressCap The pointer to the structure about the device.\r
5d73d92f 1774\r
a1d4bfcc 1775 @retval EFI_SUCCESS The operation was successful.\r
1776**/\r
5d73d92f 1777EFI_STATUS\r
1778ExplainPcieRootControl (\r
1779 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1780 );\r
1781\r
1782/**\r
1783 Print out information of the device root capability information.\r
5d73d92f 1784\r
a1d4bfcc 1785 @param[in] PciExpressCap The pointer to the structure about the device.\r
1786\r
1787 @retval EFI_SUCCESS The operation was successful.\r
1788**/\r
5d73d92f 1789EFI_STATUS\r
1790ExplainPcieRootCap (\r
1791 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1792 );\r
5d73d92f 1793\r
a1d4bfcc 1794/**\r
1795 Print out information of the device root status information.\r
1796\r
1797 @param[in] PciExpressCap The pointer to the structure about the device.\r
1798\r
1799 @retval EFI_SUCCESS The operation was successful.\r
1800**/\r
5d73d92f 1801EFI_STATUS\r
1802ExplainPcieRootStatus (\r
1803 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 1804 );\r
5d73d92f 1805\r
1806typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
1807\r
1808typedef enum {\r
1809 FieldWidthUINT8,\r
1810 FieldWidthUINT16,\r
1811 FieldWidthUINT32\r
1812} PCIE_CAPREG_FIELD_WIDTH;\r
1813\r
1814typedef enum {\r
1815 PcieExplainTypeCommon,\r
1816 PcieExplainTypeDevice,\r
1817 PcieExplainTypeLink,\r
1818 PcieExplainTypeSlot,\r
1819 PcieExplainTypeRoot,\r
1820 PcieExplainTypeMax\r
1821} PCIE_EXPLAIN_TYPE;\r
1822\r
1823typedef struct\r
1824{\r
1825 UINT16 Token;\r
1826 UINTN Offset;\r
1827 PCIE_CAPREG_FIELD_WIDTH Width;\r
1828 PCIE_EXPLAIN_FUNCTION Func;\r
1829 PCIE_EXPLAIN_TYPE Type;\r
1830} PCIE_EXPLAIN_STRUCT;\r
1831\r
1832PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
1833 {\r
1834 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
1835 0x00,\r
1836 FieldWidthUINT8,\r
1837 NULL,\r
1838 PcieExplainTypeCommon\r
1839 },\r
1840 {\r
1841 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
1842 0x01,\r
1843 FieldWidthUINT8,\r
1844 NULL,\r
1845 PcieExplainTypeCommon\r
1846 },\r
1847 {\r
1848 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
1849 0x02,\r
1850 FieldWidthUINT16,\r
1851 ExplainPcieCapReg,\r
1852 PcieExplainTypeCommon\r
1853 },\r
1854 {\r
1855 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
1856 0x04,\r
1857 FieldWidthUINT32,\r
1858 ExplainPcieDeviceCap,\r
1859 PcieExplainTypeDevice\r
1860 },\r
1861 {\r
1862 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
1863 0x08,\r
1864 FieldWidthUINT16,\r
1865 ExplainPcieDeviceControl,\r
1866 PcieExplainTypeDevice\r
1867 },\r
1868 {\r
1869 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
1870 0x0a,\r
1871 FieldWidthUINT16,\r
1872 ExplainPcieDeviceStatus,\r
1873 PcieExplainTypeDevice\r
1874 },\r
1875 {\r
1876 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
1877 0x0c,\r
1878 FieldWidthUINT32,\r
1879 ExplainPcieLinkCap,\r
1880 PcieExplainTypeLink\r
1881 },\r
1882 {\r
1883 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
1884 0x10,\r
1885 FieldWidthUINT16,\r
1886 ExplainPcieLinkControl,\r
1887 PcieExplainTypeLink\r
1888 },\r
1889 {\r
1890 STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
1891 0x12,\r
1892 FieldWidthUINT16,\r
1893 ExplainPcieLinkStatus,\r
1894 PcieExplainTypeLink\r
1895 },\r
1896 {\r
1897 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
1898 0x14,\r
1899 FieldWidthUINT32,\r
1900 ExplainPcieSlotCap,\r
1901 PcieExplainTypeSlot\r
1902 },\r
1903 {\r
1904 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
1905 0x18,\r
1906 FieldWidthUINT16,\r
1907 ExplainPcieSlotControl,\r
1908 PcieExplainTypeSlot\r
1909 },\r
1910 {\r
1911 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
1912 0x1a,\r
1913 FieldWidthUINT16,\r
1914 ExplainPcieSlotStatus,\r
1915 PcieExplainTypeSlot\r
1916 },\r
1917 {\r
1918 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
1919 0x1c,\r
1920 FieldWidthUINT16,\r
1921 ExplainPcieRootControl,\r
1922 PcieExplainTypeRoot\r
1923 },\r
1924 {\r
1925 STRING_TOKEN (STR_PCIEX_RSVDP),\r
1926 0x1e,\r
1927 FieldWidthUINT16,\r
1928 ExplainPcieRootCap,\r
1929 PcieExplainTypeRoot\r
1930 },\r
1931 {\r
1932 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
1933 0x20,\r
1934 FieldWidthUINT32,\r
1935 ExplainPcieRootStatus,\r
1936 PcieExplainTypeRoot\r
1937 },\r
1938 {\r
1939 0,\r
1940 0,\r
1941 (PCIE_CAPREG_FIELD_WIDTH)0,\r
1942 NULL,\r
1943 PcieExplainTypeMax\r
1944 }\r
1945};\r
1946\r
1947//\r
1948// Global Variables\r
1949//\r
1950PCI_CONFIG_SPACE *mConfigSpace = NULL;\r
1951STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
1952 {L"-s", TypeValue},\r
1953 {L"-i", TypeFlag},\r
1954 {NULL, TypeMax}\r
1955 };\r
1956\r
1957CHAR16 *DevicePortTypeTable[] = {\r
1958 L"PCI Express Endpoint",\r
1959 L"Legacy PCI Express Endpoint",\r
1960 L"Unknown Type",\r
1961 L"Unknonw Type",\r
1962 L"Root Port of PCI Express Root Complex",\r
1963 L"Upstream Port of PCI Express Switch",\r
1964 L"Downstream Port of PCI Express Switch",\r
1965 L"PCI Express to PCI/PCI-X Bridge",\r
1966 L"PCI/PCI-X to PCI Express Bridge",\r
1967 L"Root Complex Integrated Endpoint",\r
1968 L"Root Complex Event Collector"\r
1969};\r
1970\r
1971CHAR16 *L0sLatencyStrTable[] = {\r
1972 L"Less than 64ns",\r
1973 L"64ns to less than 128ns",\r
1974 L"128ns to less than 256ns",\r
1975 L"256ns to less than 512ns",\r
1976 L"512ns to less than 1us",\r
1977 L"1us to less than 2us",\r
1978 L"2us-4us",\r
1979 L"More than 4us"\r
1980};\r
1981\r
1982CHAR16 *L1LatencyStrTable[] = {\r
1983 L"Less than 1us",\r
1984 L"1us to less than 2us",\r
1985 L"2us to less than 4us",\r
1986 L"4us to less than 8us",\r
1987 L"8us to less than 16us",\r
1988 L"16us to less than 32us",\r
1989 L"32us-64us",\r
1990 L"More than 64us"\r
1991};\r
1992\r
1993CHAR16 *ASPMCtrlStrTable[] = {\r
1994 L"Disabled",\r
1995 L"L0s Entry Enabled",\r
1996 L"L1 Entry Enabled",\r
1997 L"L0s and L1 Entry Enabled"\r
1998};\r
1999\r
2000CHAR16 *SlotPwrLmtScaleTable[] = {\r
2001 L"1.0x",\r
2002 L"0.1x",\r
2003 L"0.01x",\r
2004 L"0.001x"\r
2005};\r
2006\r
2007CHAR16 *IndicatorTable[] = {\r
2008 L"Reserved",\r
2009 L"On",\r
2010 L"Blink",\r
2011 L"Off"\r
2012};\r
2013\r
2014\r
a1d4bfcc 2015/**\r
2016 Function for 'pci' command.\r
2017\r
2018 @param[in] ImageHandle Handle to the Image (NULL if Internal).\r
2019 @param[in] SystemTable Pointer to the System Table (NULL if Internal).\r
2020**/\r
5d73d92f 2021SHELL_STATUS\r
2022EFIAPI\r
2023ShellCommandRunPci (\r
2024 IN EFI_HANDLE ImageHandle,\r
2025 IN EFI_SYSTEM_TABLE *SystemTable\r
2026 )\r
2027{\r
2028 UINT16 Segment;\r
2029 UINT16 Bus;\r
2030 UINT16 Device;\r
2031 UINT16 Func;\r
2032 UINT64 Address;\r
2033 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;\r
2034 EFI_STATUS Status;\r
2035 PCI_COMMON_HEADER PciHeader;\r
2036 PCI_CONFIG_SPACE ConfigSpace;\r
2037 UINTN ScreenCount;\r
2038 UINTN TempColumn;\r
2039 UINTN ScreenSize;\r
2040 BOOLEAN ExplainData;\r
2041 UINTN Index;\r
2042 UINTN SizeOfHeader;\r
2043 BOOLEAN PrintTitle;\r
2044 UINTN HandleBufSize;\r
2045 EFI_HANDLE *HandleBuf;\r
2046 UINTN HandleCount;\r
2047 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2048 UINT16 MinBus;\r
2049 UINT16 MaxBus;\r
2050 BOOLEAN IsEnd;\r
2051 LIST_ENTRY *Package;\r
2052 CHAR16 *ProblemParam;\r
2053 SHELL_STATUS ShellStatus;\r
5d73d92f 2054 CONST CHAR16 *Temp;\r
6855763e 2055 UINT64 RetVal;\r
705bffb5 2056 UINT16 EnhancedDump;\r
5d73d92f 2057\r
2058 ShellStatus = SHELL_SUCCESS;\r
2059 Status = EFI_SUCCESS;\r
2060 Address = 0;\r
5d73d92f 2061 IoDev = NULL;\r
2062 HandleBuf = NULL;\r
2063 Package = NULL;\r
2064\r
2065 //\r
2066 // initialize the shell lib (we must be in non-auto-init...)\r
2067 //\r
2068 Status = ShellInitialize();\r
2069 ASSERT_EFI_ERROR(Status);\r
2070\r
2071 Status = CommandInit();\r
2072 ASSERT_EFI_ERROR(Status);\r
2073\r
2074 //\r
2075 // parse the command line\r
2076 //\r
2077 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
2078 if (EFI_ERROR(Status)) {\r
2079 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
2080 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
2081 FreePool(ProblemParam);\r
2082 ShellStatus = SHELL_INVALID_PARAMETER;\r
2083 } else {\r
2084 ASSERT(FALSE);\r
2085 }\r
2086 } else {\r
2087\r
3737ac2b 2088 if (ShellCommandLineGetCount(Package) == 2) {\r
2089 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
2090 ShellStatus = SHELL_INVALID_PARAMETER;\r
2091 goto Done;\r
2092 }\r
5d73d92f 2093\r
3737ac2b 2094 if (ShellCommandLineGetCount(Package) > 4) {\r
2095 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
2096 ShellStatus = SHELL_INVALID_PARAMETER;\r
2097 goto Done;\r
2098 }\r
2099 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
2100 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
2101 ShellStatus = SHELL_INVALID_PARAMETER;\r
2102 goto Done;\r
2103 }\r
5d73d92f 2104 //\r
2105 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
2106 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
2107 // space for handles and call it again.\r
2108 //\r
2109 HandleBufSize = sizeof (EFI_HANDLE);\r
3737ac2b 2110 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
5d73d92f 2111 if (HandleBuf == NULL) {\r
2112 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2113 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2114 goto Done;\r
2115 }\r
2116\r
2117 Status = gBS->LocateHandle (\r
2118 ByProtocol,\r
2119 &gEfiPciRootBridgeIoProtocolGuid,\r
2120 NULL,\r
2121 &HandleBufSize,\r
2122 HandleBuf\r
2123 );\r
2124\r
2125 if (Status == EFI_BUFFER_TOO_SMALL) {\r
2126 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
2127 if (HandleBuf == NULL) {\r
2128 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
2129 ShellStatus = SHELL_OUT_OF_RESOURCES;\r
2130 goto Done;\r
2131 }\r
2132\r
2133 Status = gBS->LocateHandle (\r
2134 ByProtocol,\r
2135 &gEfiPciRootBridgeIoProtocolGuid,\r
2136 NULL,\r
2137 &HandleBufSize,\r
2138 HandleBuf\r
2139 );\r
2140 }\r
2141\r
2142 if (EFI_ERROR (Status)) {\r
2143 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
2144 ShellStatus = SHELL_NOT_FOUND;\r
2145 goto Done;\r
2146 }\r
2147\r
2148 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
2149 //\r
2150 // Argument Count == 1(no other argument): enumerate all pci functions\r
2151 //\r
3737ac2b 2152 if (ShellCommandLineGetCount(Package) == 1) {\r
5d73d92f 2153 gST->ConOut->QueryMode (\r
2154 gST->ConOut,\r
2155 gST->ConOut->Mode->Mode,\r
2156 &TempColumn,\r
2157 &ScreenSize\r
2158 );\r
2159\r
2160 ScreenCount = 0;\r
2161 ScreenSize -= 4;\r
2162 if ((ScreenSize & 1) == 1) {\r
2163 ScreenSize -= 1;\r
2164 }\r
2165\r
2166 PrintTitle = TRUE;\r
2167\r
2168 //\r
2169 // For each handle, which decides a segment and a bus number range,\r
2170 // enumerate all devices on it.\r
2171 //\r
2172 for (Index = 0; Index < HandleCount; Index++) {\r
2173 Status = PciGetProtocolAndResource (\r
2174 HandleBuf[Index],\r
2175 &IoDev,\r
2176 &Descriptors\r
2177 );\r
2178 if (EFI_ERROR (Status)) {\r
2179 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
2180 ShellStatus = SHELL_NOT_FOUND;\r
2181 goto Done;\r
2182 }\r
2183 //\r
2184 // No document say it's impossible for a RootBridgeIo protocol handle\r
2185 // to have more than one address space descriptors, so find out every\r
2186 // bus range and for each of them do device enumeration.\r
2187 //\r
2188 while (TRUE) {\r
2189 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2190\r
2191 if (EFI_ERROR (Status)) {\r
2192 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
2193 ShellStatus = SHELL_NOT_FOUND;\r
2194 goto Done;\r
2195 }\r
2196\r
2197 if (IsEnd) {\r
2198 break;\r
2199 }\r
2200\r
2201 for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
2202 //\r
2203 // For each devices, enumerate all functions it contains\r
2204 //\r
2205 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
2206 //\r
2207 // For each function, read its configuration space and print summary\r
2208 //\r
2209 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
2210 if (ShellGetExecutionBreakFlag ()) {\r
2211 ShellStatus = SHELL_ABORTED;\r
2212 goto Done;\r
2213 }\r
2214 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2215 IoDev->Pci.Read (\r
2216 IoDev,\r
2217 EfiPciWidthUint16,\r
2218 Address,\r
2219 1,\r
2220 &PciHeader.VendorId\r
2221 );\r
2222\r
2223 //\r
2224 // If VendorId = 0xffff, there does not exist a device at this\r
2225 // location. For each device, if there is any function on it,\r
2226 // there must be 1 function at Function 0. So if Func = 0, there\r
2227 // will be no more functions in the same device, so we can break\r
2228 // loop to deal with the next device.\r
2229 //\r
2230 if (PciHeader.VendorId == 0xffff && Func == 0) {\r
2231 break;\r
2232 }\r
2233\r
2234 if (PciHeader.VendorId != 0xffff) {\r
2235\r
2236 if (PrintTitle) {\r
2237 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
2238 PrintTitle = FALSE;\r
2239 }\r
2240\r
2241 IoDev->Pci.Read (\r
2242 IoDev,\r
2243 EfiPciWidthUint32,\r
2244 Address,\r
2245 sizeof (PciHeader) / sizeof (UINT32),\r
2246 &PciHeader\r
2247 );\r
2248\r
2249 ShellPrintHiiEx(\r
2250 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
2251 IoDev->SegmentNumber,\r
2252 Bus,\r
2253 Device,\r
2254 Func\r
2255 );\r
2256\r
2257 PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
2258 ShellPrintHiiEx(\r
2259 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
2260 PciHeader.VendorId,\r
2261 PciHeader.DeviceId,\r
2262 PciHeader.ClassCode[0]\r
2263 );\r
2264\r
2265 ScreenCount += 2;\r
2266 if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
2267 //\r
2268 // If ScreenSize == 0 we have the console redirected so don't\r
2269 // block updates\r
2270 //\r
2271 ScreenCount = 0;\r
2272 }\r
2273 //\r
2274 // If this is not a multi-function device, we can leave the loop\r
2275 // to deal with the next device.\r
2276 //\r
2277 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
2278 break;\r
2279 }\r
2280 }\r
2281 }\r
2282 }\r
2283 }\r
2284 //\r
2285 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
2286 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
2287 // devices on all bus, we can leave loop.\r
2288 //\r
2289 if (Descriptors == NULL) {\r
2290 break;\r
2291 }\r
2292 }\r
2293 }\r
2294\r
2295 Status = EFI_SUCCESS;\r
2296 goto Done;\r
2297 }\r
2298\r
5d73d92f 2299 ExplainData = FALSE;\r
2300 Segment = 0;\r
2301 Bus = 0;\r
2302 Device = 0;\r
2303 Func = 0;\r
2304 if (ShellCommandLineGetFlag(Package, L"-i")) {\r
2305 ExplainData = TRUE;\r
2306 }\r
2307\r
2308 Temp = ShellCommandLineGetValue(Package, L"-s");\r
2309 if (Temp != NULL) {\r
6855763e
CP		 2310 //\r
2311 // Input converted to hexadecimal number.\r
2312 //\r
2313 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2314 Segment = (UINT16) RetVal;\r
2315 } else {\r
2316 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2317 ShellStatus = SHELL_INVALID_PARAMETER;\r
2318 goto Done;\r
2319 }\r
5d73d92f 2320 }\r
2321\r
2322 //\r
2323 // The first Argument(except "-i") is assumed to be Bus number, second\r
2324 // to be Device number, and third to be Func number.\r
2325 //\r
2326 Temp = ShellCommandLineGetRawValue(Package, 1);\r
2327 if (Temp != NULL) {\r
6855763e
CP		 2328 //\r
2329 // Input converted to hexadecimal number.\r
2330 //\r
2331 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2332 Bus = (UINT16) RetVal;\r
2333 } else {\r
2334 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2335 ShellStatus = SHELL_INVALID_PARAMETER;\r
2336 goto Done;\r
2337 }\r
2338\r
5d73d92f 2339 if (Bus > MAX_BUS_NUMBER) {\r
2340 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2341 ShellStatus = SHELL_INVALID_PARAMETER;\r
2342 goto Done;\r
2343 }\r
2344 }\r
2345 Temp = ShellCommandLineGetRawValue(Package, 2);\r
2346 if (Temp != NULL) {\r
6855763e
CP		 2347 //\r
2348 // Input converted to hexadecimal number.\r
2349 //\r
2350 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2351 Device = (UINT16) RetVal;\r
2352 } else {\r
2353 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2354 ShellStatus = SHELL_INVALID_PARAMETER;\r
2355 goto Done;\r
2356 }\r
2357\r
5d73d92f 2358 if (Device > MAX_DEVICE_NUMBER){\r
2359 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2360 ShellStatus = SHELL_INVALID_PARAMETER;\r
2361 goto Done;\r
2362 }\r
2363 }\r
2364\r
2365 Temp = ShellCommandLineGetRawValue(Package, 3);\r
2366 if (Temp != NULL) {\r
6855763e
CP		 2367 //\r
2368 // Input converted to hexadecimal number.\r
2369 //\r
2370 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
2371 Func = (UINT16) RetVal;\r
2372 } else {\r
2373 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
2374 ShellStatus = SHELL_INVALID_PARAMETER;\r
2375 goto Done;\r
2376 }\r
2377\r
5d73d92f 2378 if (Func > MAX_FUNCTION_NUMBER){\r
2379 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
2380 ShellStatus = SHELL_INVALID_PARAMETER;\r
2381 goto Done;\r
2382 }\r
2383 }\r
2384\r
2385 //\r
2386 // Find the protocol interface who's in charge of current segment, and its\r
2387 // bus range covers the current bus\r
2388 //\r
2389 Status = PciFindProtocolInterface (\r
2390 HandleBuf,\r
2391 HandleCount,\r
2392 Segment,\r
2393 Bus,\r
2394 &IoDev\r
2395 );\r
2396\r
2397 if (EFI_ERROR (Status)) {\r
2398 ShellPrintHiiEx(\r
2399 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
5d73d92f 2400 Segment,\r
2401 Bus\r
2402 );\r
2403 ShellStatus = SHELL_NOT_FOUND;\r
2404 goto Done;\r
2405 }\r
2406\r
2407 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
2408 Status = IoDev->Pci.Read (\r
2409 IoDev,\r
2410 EfiPciWidthUint8,\r
2411 Address,\r
2412 sizeof (ConfigSpace),\r
2413 &ConfigSpace\r
2414 );\r
2415\r
2416 if (EFI_ERROR (Status)) {\r
2417 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
2418 ShellStatus = SHELL_ACCESS_DENIED;\r
2419 goto Done;\r
2420 }\r
2421\r
2422 mConfigSpace = &ConfigSpace;\r
2423 ShellPrintHiiEx(\r
2424 -1,\r
2425 -1,\r
2426 NULL,\r
2427 STRING_TOKEN (STR_PCI_INFO),\r
2428 gShellDebug1HiiHandle,\r
2429 Segment,\r
2430 Bus,\r
2431 Device,\r
2432 Func,\r
2433 Segment,\r
2434 Bus,\r
2435 Device,\r
2436 Func\r
2437 );\r
2438\r
2439 //\r
2440 // Dump standard header of configuration space\r
2441 //\r
2442 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
2443\r
a1d4bfcc 2444 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
5d73d92f 2445 ShellPrintEx(-1,-1, L"\r\n");\r
2446\r
2447 //\r
2448 // Dump device dependent Part of configuration space\r
2449 //\r
a1d4bfcc 2450 DumpHex (\r
5d73d92f 2451 2,\r
2452 SizeOfHeader,\r
2453 sizeof (ConfigSpace) - SizeOfHeader,\r
2454 ConfigSpace.Data\r
2455 );\r
2456\r
2457 //\r
2458 // If "-i" appears in command line, interpret data in configuration space\r
2459 //\r
2460 if (ExplainData) {\r
705bffb5
JC		 2461 EnhancedDump = 0;\r
2462 if (ShellCommandLineGetFlag(Package, L"-_e")) {\r
2463 EnhancedDump = 0xFFFF;\r
2464 Temp = ShellCommandLineGetValue(Package, L"-_e");\r
2465 if (Temp != NULL) {\r
2466 EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r
2467 }\r
2468 }\r
2469 Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r
5d73d92f 2470 }\r
2471 }\r
2472Done:\r
2473 if (HandleBuf != NULL) {\r
2474 FreePool (HandleBuf);\r
2475 }\r
2476 if (Package != NULL) {\r
2477 ShellCommandLineFreeVarList (Package);\r
2478 }\r
2479 mConfigSpace = NULL;\r
2480 return ShellStatus;\r
2481}\r
2482\r
a1d4bfcc 2483/**\r
5d73d92f 2484 This function finds out the protocol which is in charge of the given\r
2485 segment, and its bus range covers the current bus number. It lookes\r
2486 each instances of RootBridgeIoProtocol handle, until the one meets the\r
2487 criteria is found.\r
2488\r
a1d4bfcc 2489 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2490 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
2491 @param[in] Segment Segment number of device we are dealing with.\r
2492 @param[in] Bus Bus number of device we are dealing with.\r
2493 @param[out] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2494\r
a1d4bfcc 2495 @retval EFI_SUCCESS The command completed successfully.\r
2496 @retval EFI_INVALID_PARAMETER Invalid parameter.\r
5d73d92f 2497\r
2498**/\r
a1d4bfcc 2499EFI_STATUS\r
2500PciFindProtocolInterface (\r
2501 IN EFI_HANDLE *HandleBuf,\r
2502 IN UINTN HandleCount,\r
2503 IN UINT16 Segment,\r
2504 IN UINT16 Bus,\r
2505 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev\r
2506 )\r
5d73d92f 2507{\r
2508 UINTN Index;\r
2509 EFI_STATUS Status;\r
5d73d92f 2510 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
2511 UINT16 MinBus;\r
2512 UINT16 MaxBus;\r
2513 BOOLEAN IsEnd;\r
2514\r
5d73d92f 2515 //\r
2516 // Go through all handles, until the one meets the criteria is found\r
2517 //\r
2518 for (Index = 0; Index < HandleCount; Index++) {\r
2519 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
2520 if (EFI_ERROR (Status)) {\r
2521 return Status;\r
2522 }\r
2523 //\r
2524 // When Descriptors == NULL, the Configuration() is not implemented,\r
2525 // so we only check the Segment number\r
2526 //\r
2527 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
2528 return EFI_SUCCESS;\r
2529 }\r
2530\r
2531 if ((*IoDev)->SegmentNumber != Segment) {\r
2532 continue;\r
2533 }\r
2534\r
2535 while (TRUE) {\r
2536 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
2537 if (EFI_ERROR (Status)) {\r
2538 return Status;\r
2539 }\r
2540\r
2541 if (IsEnd) {\r
2542 break;\r
2543 }\r
2544\r
2545 if (MinBus <= Bus && MaxBus >= Bus) {\r
2c46dd23 2546 return EFI_SUCCESS;\r
5d73d92f 2547 }\r
2548 }\r
2549 }\r
2550\r
2c46dd23 2551 return EFI_NOT_FOUND;\r
5d73d92f 2552}\r
2553\r
a1d4bfcc 2554/**\r
2555 This function gets the protocol interface from the given handle, and\r
2556 obtains its address space descriptors.\r
2557\r
2558 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
2559 @param[out] IoDev Handle used to access configuration space of PCI device.\r
2560 @param[out] Descriptors Points to the address space descriptors.\r
2561\r
2562 @retval EFI_SUCCESS The command completed successfully\r
2563**/\r
5d73d92f 2564EFI_STATUS\r
2565PciGetProtocolAndResource (\r
2566 IN EFI_HANDLE Handle,\r
2567 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,\r
2568 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors\r
2569 )\r
5d73d92f 2570{\r
2571 EFI_STATUS Status;\r
2572\r
2573 //\r
2574 // Get inferface from protocol\r
2575 //\r
2576 Status = gBS->HandleProtocol (\r
2577 Handle,\r
2578 &gEfiPciRootBridgeIoProtocolGuid,\r
2579 (VOID**)IoDev\r
2580 );\r
2581\r
2582 if (EFI_ERROR (Status)) {\r
2583 return Status;\r
2584 }\r
2585 //\r
2586 // Call Configuration() to get address space descriptors\r
2587 //\r
2588 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
2589 if (Status == EFI_UNSUPPORTED) {\r
2590 *Descriptors = NULL;\r
2591 return EFI_SUCCESS;\r
2592\r
2593 } else {\r
2594 return Status;\r
2595 }\r
2596}\r
2597\r
a1d4bfcc 2598/**\r
2599 This function get the next bus range of given address space descriptors.\r
2600 It also moves the pointer backward a node, to get prepared to be called\r
2601 again.\r
2602\r
4ff7e37b
ED		 2603 @param[in, out] Descriptors Points to current position of a serial of address space\r
2604 descriptors.\r
2605 @param[out] MinBus The lower range of bus number.\r
2606 @param[out] MaxBus The upper range of bus number.\r
2607 @param[out] IsEnd Meet end of the serial of descriptors.\r
a1d4bfcc 2608\r
2609 @retval EFI_SUCCESS The command completed successfully.\r
2610**/\r
5d73d92f 2611EFI_STATUS\r
2612PciGetNextBusRange (\r
2613 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,\r
2614 OUT UINT16 *MinBus,\r
2615 OUT UINT16 *MaxBus,\r
2616 OUT BOOLEAN *IsEnd\r
2617 )\r
5d73d92f 2618{\r
2619 *IsEnd = FALSE;\r
2620\r
2621 //\r
2622 // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
2623 // range is 0~PCI_MAX_BUS\r
2624 //\r
2625 if ((*Descriptors) == NULL) {\r
2626 *MinBus = 0;\r
2627 *MaxBus = PCI_MAX_BUS;\r
2628 return EFI_SUCCESS;\r
2629 }\r
2630 //\r
2631 // *Descriptors points to one or more address space descriptors, which\r
2632 // ends with a end tagged descriptor. Examine each of the descriptors,\r
2633 // if a bus typed one is found and its bus range covers bus, this handle\r
2634 // is the handle we are looking for.\r
2635 //\r
5d73d92f 2636\r
2637 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
2638 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
2639 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
2640 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
2641 (*Descriptors)++;\r
3737ac2b 2642 return (EFI_SUCCESS);\r
5d73d92f 2643 }\r
2644\r
2645 (*Descriptors)++;\r
2646 }\r
2647\r
3737ac2b 2648 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
2649 *IsEnd = TRUE;\r
2650 }\r
2651\r
5d73d92f 2652 return EFI_SUCCESS;\r
2653}\r
2654\r
a1d4bfcc 2655/**\r
5d73d92f 2656 Explain the data in PCI configuration space. The part which is common for\r
2657 PCI device and bridge is interpreted in this function. It calls other\r
2658 functions to interpret data unique for device or bridge.\r
2659\r
a1d4bfcc 2660 @param[in] ConfigSpace Data in PCI configuration space.\r
2661 @param[in] Address Address used to access configuration space of this PCI device.\r
2662 @param[in] IoDev Handle used to access configuration space of PCI device.\r
5d73d92f 2663\r
a1d4bfcc 2664 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 2665**/\r
a1d4bfcc 2666EFI_STATUS\r
2667PciExplainData (\r
2668 IN PCI_CONFIG_SPACE *ConfigSpace,\r
2669 IN UINT64 Address,\r
705bffb5
JC		 2670 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
2671 IN CONST UINT16 EnhancedDump\r
a1d4bfcc 2672 )\r
5d73d92f 2673{\r
2674 PCI_COMMON_HEADER *Common;\r
2675 PCI_HEADER_TYPE HeaderType;\r
2676 EFI_STATUS Status;\r
2677 UINT8 CapPtr;\r
2678\r
2679 Common = &(ConfigSpace->Common);\r
2680\r
c37e0f16 2681 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 2682\r
2683 //\r
2684 // Print Vendor Id and Device Id\r
2685 //\r
2686 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
2687 INDEX_OF (&(Common->VendorId)),\r
2688 Common->VendorId,\r
2689 INDEX_OF (&(Common->DeviceId)),\r
2690 Common->DeviceId\r
2691 );\r
2692\r
2693 //\r
2694 // Print register Command\r
2695 //\r
2696 PciExplainCommand (&(Common->Command));\r
2697\r
2698 //\r
2699 // Print register Status\r
2700 //\r
2701 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
2702\r
2703 //\r
2704 // Print register Revision ID\r
2705 //\r
14b5e3fd 2706 ShellPrintEx(-1, -1, L"\r\n");\r
5d73d92f 2707 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
2708 INDEX_OF (&(Common->RevisionId)),\r
2709 Common->RevisionId\r
2710 );\r
2711\r
2712 //\r
2713 // Print register BIST\r
2714 //\r
a1d4bfcc 2715 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
2716 if ((Common->Bist & PCI_BIT_7) != 0) {\r
2717 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
5d73d92f 2718 } else {\r
2719 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
2720 }\r
2721 //\r
2722 // Print register Cache Line Size\r
2723 //\r
2724 ShellPrintHiiEx(-1, -1, NULL,\r
2725 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
2726 gShellDebug1HiiHandle,\r
2727 INDEX_OF (&(Common->CacheLineSize)),\r
2728 Common->CacheLineSize\r
2729 );\r
2730\r
2731 //\r
2732 // Print register Latency Timer\r
2733 //\r
2734 ShellPrintHiiEx(-1, -1, NULL,\r
2735 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
2736 gShellDebug1HiiHandle,\r
2737 INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
2738 Common->PrimaryLatencyTimer\r
2739 );\r
2740\r
2741 //\r
2742 // Print register Header Type\r
2743 //\r
2744 ShellPrintHiiEx(-1, -1, NULL,\r
2745 STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
2746 gShellDebug1HiiHandle,\r
2747 INDEX_OF (&(Common->HeaderType)),\r
2748 Common->HeaderType\r
2749 );\r
2750\r
2751 if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
2752 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
2753\r
2754 } else {\r
2755 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
2756 }\r
2757\r
2758 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
2759 switch (HeaderType) {\r
2760 case PciDevice:\r
2761 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
2762 break;\r
2763\r
2764 case PciP2pBridge:\r
2765 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
2766 break;\r
2767\r
2768 case PciCardBusBridge:\r
2769 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
2770 break;\r
2771\r
2772 default:\r
2773 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
2774 HeaderType = PciUndefined;\r
2775 }\r
2776\r
2777 //\r
2778 // Print register Class Code\r
2779 //\r
2780 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
2781 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
c37e0f16 2782 ShellPrintEx (-1, -1, L"\r\n");\r
5d73d92f 2783\r
2784 if (ShellGetExecutionBreakFlag()) {\r
2785 return EFI_SUCCESS;\r
2786 }\r
2787\r
2788 //\r
2789 // Interpret remaining part of PCI configuration header depending on\r
2790 // HeaderType\r
2791 //\r
2792 CapPtr = 0;\r
2793 Status = EFI_SUCCESS;\r
2794 switch (HeaderType) {\r
2795 case PciDevice:\r
2796 Status = PciExplainDeviceData (\r
2797 &(ConfigSpace->NonCommon.Device),\r
2798 Address,\r
2799 IoDev\r
2800 );\r
2801 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
2802 break;\r
2803\r
2804 case PciP2pBridge:\r
2805 Status = PciExplainBridgeData (\r
2806 &(ConfigSpace->NonCommon.Bridge),\r
2807 Address,\r
2808 IoDev\r
2809 );\r
2810 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
2811 break;\r
2812\r
2813 case PciCardBusBridge:\r
2814 Status = PciExplainCardBusData (\r
2815 &(ConfigSpace->NonCommon.CardBus),\r
2816 Address,\r
2817 IoDev\r
2818 );\r
2819 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
2820 break;\r
d8f8021c 2821 case PciUndefined:\r
2822 default:\r
2823 break;\r
5d73d92f 2824 }\r
2825 //\r
2826 // If Status bit4 is 1, dump or explain capability structure\r
2827 //\r
2828 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
705bffb5 2829 PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r
5d73d92f 2830 }\r
2831\r
2832 return Status;\r
2833}\r
2834\r
a1d4bfcc 2835/**\r
2836 Explain the device specific part of data in PCI configuration space.\r
2837\r
2838 @param[in] Device Data in PCI configuration space.\r
2839 @param[in] Address Address used to access configuration space of this PCI device.\r
2840 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2841\r
2842 @retval EFI_SUCCESS The command completed successfully.\r
2843**/\r
5d73d92f 2844EFI_STATUS\r
2845PciExplainDeviceData (\r
2846 IN PCI_DEVICE_HEADER *Device,\r
2847 IN UINT64 Address,\r
2848 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2849 )\r
5d73d92f 2850{\r
2851 UINTN Index;\r
2852 BOOLEAN BarExist;\r
2853 EFI_STATUS Status;\r
2854 UINTN BarCount;\r
2855\r
2856 //\r
2857 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
2858 // exist. If these no Bar for this function, print "none", otherwise\r
2859 // list detail information about this Bar.\r
2860 //\r
2861 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
2862\r
2863 BarExist = FALSE;\r
2864 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
2865 for (Index = 0; Index < BarCount; Index++) {\r
2866 if (Device->Bar[Index] == 0) {\r
2867 continue;\r
2868 }\r
2869\r
2870 if (!BarExist) {\r
2871 BarExist = TRUE;\r
2872 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 2873 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 2874 }\r
2875\r
2876 Status = PciExplainBar (\r
2877 &(Device->Bar[Index]),\r
2878 &(mConfigSpace->Common.Command),\r
2879 Address,\r
2880 IoDev,\r
2881 &Index\r
2882 );\r
2883\r
2884 if (EFI_ERROR (Status)) {\r
2885 break;\r
2886 }\r
2887 }\r
2888\r
2889 if (!BarExist) {\r
2890 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
2891\r
2892 } else {\r
c37e0f16 2893 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 2894 }\r
2895\r
2896 //\r
2897 // Print register Expansion ROM Base Address\r
2898 //\r
2899 if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
2900 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
2901\r
2902 } else {\r
2903 ShellPrintHiiEx(-1, -1, NULL,\r
2904 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
2905 gShellDebug1HiiHandle,\r
2906 INDEX_OF (&(Device->ROMBar)),\r
2907 Device->ROMBar\r
2908 );\r
2909 }\r
2910 //\r
2911 // Print register Cardbus CIS ptr\r
2912 //\r
2913 ShellPrintHiiEx(-1, -1, NULL,\r
2914 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
2915 gShellDebug1HiiHandle,\r
2916 INDEX_OF (&(Device->CardBusCISPtr)),\r
2917 Device->CardBusCISPtr\r
2918 );\r
2919\r
2920 //\r
2921 // Print register Sub-vendor ID and subsystem ID\r
2922 //\r
2923 ShellPrintHiiEx(-1, -1, NULL,\r
2924 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
2925 gShellDebug1HiiHandle,\r
2926 INDEX_OF (&(Device->SubVendorId)),\r
2927 Device->SubVendorId\r
2928 );\r
2929\r
2930 ShellPrintHiiEx(-1, -1, NULL,\r
2931 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
2932 gShellDebug1HiiHandle,\r
2933 INDEX_OF (&(Device->SubSystemId)),\r
2934 Device->SubSystemId\r
2935 );\r
2936\r
2937 //\r
2938 // Print register Capabilities Ptr\r
2939 //\r
2940 ShellPrintHiiEx(-1, -1, NULL,\r
2941 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
2942 gShellDebug1HiiHandle,\r
2943 INDEX_OF (&(Device->CapabilitiesPtr)),\r
2944 Device->CapabilitiesPtr\r
2945 );\r
2946\r
2947 //\r
2948 // Print register Interrupt Line and interrupt pin\r
2949 //\r
2950 ShellPrintHiiEx(-1, -1, NULL,\r
2951 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
2952 gShellDebug1HiiHandle,\r
2953 INDEX_OF (&(Device->InterruptLine)),\r
2954 Device->InterruptLine\r
2955 );\r
2956\r
2957 ShellPrintHiiEx(-1, -1, NULL,\r
2958 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
2959 gShellDebug1HiiHandle,\r
2960 INDEX_OF (&(Device->InterruptPin)),\r
2961 Device->InterruptPin\r
2962 );\r
2963\r
2964 //\r
2965 // Print register Min_Gnt and Max_Lat\r
2966 //\r
2967 ShellPrintHiiEx(-1, -1, NULL,\r
2968 STRING_TOKEN (STR_PCI2_MIN_GNT),\r
2969 gShellDebug1HiiHandle,\r
2970 INDEX_OF (&(Device->MinGnt)),\r
2971 Device->MinGnt\r
2972 );\r
2973\r
2974 ShellPrintHiiEx(-1, -1, NULL,\r
2975 STRING_TOKEN (STR_PCI2_MAX_LAT),\r
2976 gShellDebug1HiiHandle,\r
2977 INDEX_OF (&(Device->MaxLat)),\r
2978 Device->MaxLat\r
2979 );\r
2980\r
2981 return EFI_SUCCESS;\r
2982}\r
2983\r
a1d4bfcc 2984/**\r
2985 Explain the bridge specific part of data in PCI configuration space.\r
2986\r
2987 @param[in] Bridge Bridge specific data region in PCI configuration space.\r
2988 @param[in] Address Address used to access configuration space of this PCI device.\r
2989 @param[in] IoDev Handle used to access configuration space of PCI device.\r
2990\r
2991 @retval EFI_SUCCESS The command completed successfully.\r
2992**/\r
5d73d92f 2993EFI_STATUS\r
2994PciExplainBridgeData (\r
2995 IN PCI_BRIDGE_HEADER *Bridge,\r
2996 IN UINT64 Address,\r
2997 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
2998 )\r
5d73d92f 2999{\r
3000 UINTN Index;\r
3001 BOOLEAN BarExist;\r
3002 UINTN BarCount;\r
3003 UINT32 IoAddress32;\r
3004 EFI_STATUS Status;\r
3005\r
3006 //\r
3007 // Print Base Address Registers. When Bar = 0, this Bar does not\r
3008 // exist. If these no Bar for this function, print "none", otherwise\r
3009 // list detail information about this Bar.\r
3010 //\r
3011 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
3012\r
3013 BarExist = FALSE;\r
3014 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
3015\r
3016 for (Index = 0; Index < BarCount; Index++) {\r
3017 if (Bridge->Bar[Index] == 0) {\r
3018 continue;\r
3019 }\r
3020\r
3021 if (!BarExist) {\r
3022 BarExist = TRUE;\r
3023 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 3024 ShellPrintEx (-1, -1, L" --------------------------------------------------------------------------");\r
5d73d92f 3025 }\r
3026\r
3027 Status = PciExplainBar (\r
3028 &(Bridge->Bar[Index]),\r
3029 &(mConfigSpace->Common.Command),\r
3030 Address,\r
3031 IoDev,\r
3032 &Index\r
3033 );\r
3034\r
3035 if (EFI_ERROR (Status)) {\r
3036 break;\r
3037 }\r
3038 }\r
3039\r
3040 if (!BarExist) {\r
3041 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
3042 } else {\r
c37e0f16 3043 ShellPrintEx (-1, -1, L"\r\n --------------------------------------------------------------------------");\r
5d73d92f 3044 }\r
3045\r
3046 //\r
3047 // Expansion register ROM Base Address\r
3048 //\r
3049 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
3050 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
3051\r
3052 } else {\r
3053 ShellPrintHiiEx(-1, -1, NULL,\r
3054 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
3055 gShellDebug1HiiHandle,\r
3056 INDEX_OF (&(Bridge->ROMBar)),\r
3057 Bridge->ROMBar\r
3058 );\r
3059 }\r
3060 //\r
3061 // Print Bus Numbers(Primary, Secondary, and Subordinate\r
3062 //\r
3063 ShellPrintHiiEx(-1, -1, NULL,\r
3064 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
3065 gShellDebug1HiiHandle,\r
3066 INDEX_OF (&(Bridge->PrimaryBus)),\r
3067 INDEX_OF (&(Bridge->SecondaryBus)),\r
3068 INDEX_OF (&(Bridge->SubordinateBus))\r
3069 );\r
3070\r
c37e0f16 3071 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3072\r
3073 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
3074 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
3075 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
3076\r
3077 //\r
3078 // Print register Secondary Latency Timer\r
3079 //\r
3080 ShellPrintHiiEx(-1, -1, NULL,\r
3081 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
3082 gShellDebug1HiiHandle,\r
3083 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
3084 Bridge->SecondaryLatencyTimer\r
3085 );\r
3086\r
3087 //\r
3088 // Print register Secondary Status\r
3089 //\r
3090 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
3091\r
3092 //\r
3093 // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
3094 // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
3095 // base and limit address are listed.\r
3096 //\r
3097 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
c37e0f16 3098 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3099\r
3100 //\r
3101 // IO Base & Limit\r
3102 //\r
3103 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
3104 IoAddress32 &= 0xfffff000;\r
3105 ShellPrintHiiEx(-1, -1, NULL,\r
3106 STRING_TOKEN (STR_PCI2_TWO_VARS),\r
3107 gShellDebug1HiiHandle,\r
3108 INDEX_OF (&(Bridge->IoBase)),\r
3109 IoAddress32\r
3110 );\r
3111\r
3112 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
3113 IoAddress32 |= 0x00000fff;\r
3114 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
3115\r
3116 //\r
3117 // Memory Base & Limit\r
3118 //\r
3119 ShellPrintHiiEx(-1, -1, NULL,\r
3120 STRING_TOKEN (STR_PCI2_MEMORY),\r
3121 gShellDebug1HiiHandle,\r
3122 INDEX_OF (&(Bridge->MemoryBase)),\r
3123 (Bridge->MemoryBase << 16) & 0xfff00000\r
3124 );\r
3125\r
3126 ShellPrintHiiEx(-1, -1, NULL,\r
3127 STRING_TOKEN (STR_PCI2_ONE_VAR),\r
3128 gShellDebug1HiiHandle,\r
3129 (Bridge->MemoryLimit << 16) | 0x000fffff\r
3130 );\r
3131\r
3132 //\r
3133 // Pre-fetch-able Memory Base & Limit\r
3134 //\r
3135 ShellPrintHiiEx(-1, -1, NULL,\r
3136 STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
3137 gShellDebug1HiiHandle,\r
3138 INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
3139 Bridge->PrefetchableBaseUpper,\r
3140 (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
3141 );\r
3142\r
3143 ShellPrintHiiEx(-1, -1, NULL,\r
3144 STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
3145 gShellDebug1HiiHandle,\r
3146 Bridge->PrefetchableLimitUpper,\r
3147 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
3148 );\r
3149\r
3150 //\r
3151 // Print register Capabilities Pointer\r
3152 //\r
3153 ShellPrintHiiEx(-1, -1, NULL,\r
3154 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
3155 gShellDebug1HiiHandle,\r
3156 INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
3157 Bridge->CapabilitiesPtr\r
3158 );\r
3159\r
3160 //\r
3161 // Print register Bridge Control\r
3162 //\r
3163 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
3164\r
3165 //\r
3166 // Print register Interrupt Line & PIN\r
3167 //\r
3168 ShellPrintHiiEx(-1, -1, NULL,\r
3169 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
3170 gShellDebug1HiiHandle,\r
3171 INDEX_OF (&(Bridge->InterruptLine)),\r
3172 Bridge->InterruptLine\r
3173 );\r
3174\r
3175 ShellPrintHiiEx(-1, -1, NULL,\r
3176 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
3177 gShellDebug1HiiHandle,\r
3178 INDEX_OF (&(Bridge->InterruptPin)),\r
3179 Bridge->InterruptPin\r
3180 );\r
3181\r
3182 return EFI_SUCCESS;\r
3183}\r
3184\r
a1d4bfcc 3185/**\r
3186 Explain the Base Address Register(Bar) in PCI configuration space.\r
3187\r
4ff7e37b
ED		 3188 @param[in] Bar Points to the Base Address Register intended to interpret.\r
3189 @param[in] Command Points to the register Command.\r
3190 @param[in] Address Address used to access configuration space of this PCI device.\r
3191 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3192 @param[in, out] Index The Index.\r
a1d4bfcc 3193\r
3194 @retval EFI_SUCCESS The command completed successfully.\r
3195**/\r
5d73d92f 3196EFI_STATUS\r
3197PciExplainBar (\r
3198 IN UINT32 *Bar,\r
3199 IN UINT16 *Command,\r
3200 IN UINT64 Address,\r
3201 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3202 IN OUT UINTN *Index\r
3203 )\r
5d73d92f 3204{\r
3205 UINT16 OldCommand;\r
3206 UINT16 NewCommand;\r
3207 UINT64 Bar64;\r
3208 UINT32 OldBar32;\r
3209 UINT32 NewBar32;\r
3210 UINT64 OldBar64;\r
3211 UINT64 NewBar64;\r
3212 BOOLEAN IsMem;\r
3213 BOOLEAN IsBar32;\r
3214 UINT64 RegAddress;\r
3215\r
3216 IsBar32 = TRUE;\r
3217 Bar64 = 0;\r
3218 NewBar32 = 0;\r
3219 NewBar64 = 0;\r
3220\r
3221 //\r
3222 // According the bar type, list detail about this bar, for example: 32 or\r
3223 // 64 bits; pre-fetchable or not.\r
3224 //\r
3225 if ((*Bar & PCI_BIT_0) == 0) {\r
3226 //\r
3227 // This bar is of memory type\r
3228 //\r
3229 IsMem = TRUE;\r
3230\r
3231 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
3232 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3233 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3234 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
3235\r
3236 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
3237 Bar64 = 0x0;\r
3238 CopyMem (&Bar64, Bar, sizeof (UINT64));\r
46cb4043 3239 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
2b578de0 3240 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
5d73d92f 3241 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
3242 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
3243 IsBar32 = FALSE;\r
3244 *Index += 1;\r
3245\r
3246 } else {\r
3247 //\r
3248 // Reserved\r
3249 //\r
3250 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
3251 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
3252 }\r
3253\r
3254 if ((*Bar & PCI_BIT_3) == 0) {\r
3255 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
3256\r
3257 } else {\r
3258 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
3259 }\r
3260\r
3261 } else {\r
3262 //\r
3263 // This bar is of io type\r
3264 //\r
3265 IsMem = FALSE;\r
3266 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
c37e0f16 3267 ShellPrintEx (-1, -1, L"I/O ");\r
5d73d92f 3268 }\r
3269\r
3270 //\r
3271 // Get BAR length(or the amount of resource this bar demands for). To get\r
3272 // Bar length, first we should temporarily disable I/O and memory access\r
3273 // of this function(by set bits in the register Command), then write all\r
3274 // "1"s to this bar. The bar value read back is the amount of resource\r
3275 // this bar demands for.\r
3276 //\r
3277 //\r
3278 // Disable io & mem access\r
3279 //\r
3280 OldCommand = *Command;\r
3281 NewCommand = (UINT16) (OldCommand & 0xfffc);\r
3282 RegAddress = Address | INDEX_OF (Command);\r
3283 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
3284\r
3285 RegAddress = Address | INDEX_OF (Bar);\r
3286\r
3287 //\r
3288 // Read after write the BAR to get the size\r
3289 //\r
3290 if (IsBar32) {\r
3291 OldBar32 = *Bar;\r
3292 NewBar32 = 0xffffffff;\r
3293\r
3294 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3295 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
3296 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
3297\r
3298 if (IsMem) {\r
3299 NewBar32 = NewBar32 & 0xfffffff0;\r
3300 NewBar32 = (~NewBar32) + 1;\r
3301\r
3302 } else {\r
3303 NewBar32 = NewBar32 & 0xfffffffc;\r
3304 NewBar32 = (~NewBar32) + 1;\r
3305 NewBar32 = NewBar32 & 0x0000ffff;\r
3306 }\r
3307 } else {\r
3308\r
3309 OldBar64 = 0x0;\r
3310 CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
2b578de0 3311 NewBar64 = 0xffffffffffffffffULL;\r
5d73d92f 3312\r
3313 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3314 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
3315 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
3316\r
3317 if (IsMem) {\r
2b578de0 3318 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;\r
5d73d92f 3319 NewBar64 = (~NewBar64) + 1;\r
3320\r
3321 } else {\r
2b578de0 3322 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;\r
5d73d92f 3323 NewBar64 = (~NewBar64) + 1;\r
3324 NewBar64 = NewBar64 & 0x000000000000ffff;\r
3325 }\r
3326 }\r
3327 //\r
3328 // Enable io & mem access\r
3329 //\r
3330 RegAddress = Address | INDEX_OF (Command);\r
3331 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
3332\r
3333 if (IsMem) {\r
3334 if (IsBar32) {\r
3335 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
3336 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
3337\r
3338 } else {\r
46cb4043 3339 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
5d73d92f 3340 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
c37e0f16 3341 ShellPrintEx (-1, -1, L" ");\r
5d73d92f 3342 ShellPrintHiiEx(-1, -1, NULL,\r
3343 STRING_TOKEN (STR_PCI2_RSHIFT),\r
3344 gShellDebug1HiiHandle,\r
46cb4043 3345 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
5d73d92f 3346 );\r
2b578de0 3347 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
5d73d92f 3348\r
3349 }\r
3350 } else {\r
3351 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
3352 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
3353 }\r
3354\r
3355 return EFI_SUCCESS;\r
3356}\r
3357\r
a1d4bfcc 3358/**\r
3359 Explain the cardbus specific part of data in PCI configuration space.\r
3360\r
3361 @param[in] CardBus CardBus specific region of PCI configuration space.\r
3362 @param[in] Address Address used to access configuration space of this PCI device.\r
3363 @param[in] IoDev Handle used to access configuration space of PCI device.\r
3364\r
3365 @retval EFI_SUCCESS The command completed successfully.\r
3366**/\r
5d73d92f 3367EFI_STATUS\r
3368PciExplainCardBusData (\r
3369 IN PCI_CARDBUS_HEADER *CardBus,\r
3370 IN UINT64 Address,\r
3371 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
3372 )\r
5d73d92f 3373{\r
3374 BOOLEAN Io32Bit;\r
3375 PCI_CARDBUS_DATA *CardBusData;\r
3376\r
3377 ShellPrintHiiEx(-1, -1, NULL,\r
3378 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
3379 gShellDebug1HiiHandle,\r
3380 INDEX_OF (&(CardBus->CardBusSocketReg)),\r
3381 CardBus->CardBusSocketReg\r
3382 );\r
3383\r
3384 //\r
3385 // Print Secondary Status\r
3386 //\r
3387 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
3388\r
3389 //\r
3390 // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
3391 // Subordinate bus number\r
3392 //\r
3393 ShellPrintHiiEx(-1, -1, NULL,\r
3394 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
3395 gShellDebug1HiiHandle,\r
3396 INDEX_OF (&(CardBus->PciBusNumber)),\r
3397 INDEX_OF (&(CardBus->CardBusBusNumber)),\r
3398 INDEX_OF (&(CardBus->SubordinateBusNumber))\r
3399 );\r
3400\r
c37e0f16 3401 ShellPrintEx (-1, -1, L" ------------------------------------------------------\r\n");\r
5d73d92f 3402\r
3403 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
3404 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
3405 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
3406\r
3407 //\r
3408 // Print CardBus Latency Timer\r
3409 //\r
3410 ShellPrintHiiEx(-1, -1, NULL,\r
3411 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
3412 gShellDebug1HiiHandle,\r
3413 INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
3414 CardBus->CardBusLatencyTimer\r
3415 );\r
3416\r
3417 //\r
3418 // Print Memory/Io ranges this cardbus bridge forwards\r
3419 //\r
3420 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
c37e0f16 3421 ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
5d73d92f 3422\r
3423 ShellPrintHiiEx(-1, -1, NULL,\r
3424 STRING_TOKEN (STR_PCI2_MEM_3),\r
3425 gShellDebug1HiiHandle,\r
3426 INDEX_OF (&(CardBus->MemoryBase0)),\r
3427 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",\r
3428 CardBus->MemoryBase0 & 0xfffff000,\r
3429 CardBus->MemoryLimit0 | 0x00000fff\r
3430 );\r
3431\r
3432 ShellPrintHiiEx(-1, -1, NULL,\r
3433 STRING_TOKEN (STR_PCI2_MEM_3),\r
3434 gShellDebug1HiiHandle,\r
3435 INDEX_OF (&(CardBus->MemoryBase1)),\r
3436 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",\r
3437 CardBus->MemoryBase1 & 0xfffff000,\r
3438 CardBus->MemoryLimit1 | 0x00000fff\r
3439 );\r
3440\r
3441 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
3442 ShellPrintHiiEx(-1, -1, NULL,\r
3443 STRING_TOKEN (STR_PCI2_IO_2),\r
3444 gShellDebug1HiiHandle,\r
3445 INDEX_OF (&(CardBus->IoBase0)),\r
3446 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3447 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3448 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3449 );\r
3450\r
3451 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
3452 ShellPrintHiiEx(-1, -1, NULL,\r
3453 STRING_TOKEN (STR_PCI2_IO_2),\r
3454 gShellDebug1HiiHandle,\r
3455 INDEX_OF (&(CardBus->IoBase1)),\r
3456 Io32Bit ? L" 32 bit" : L" 16 bit",\r
3457 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
d8f8021c 3458 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
5d73d92f 3459 );\r
3460\r
3461 //\r
3462 // Print register Interrupt Line & PIN\r
3463 //\r
3464 ShellPrintHiiEx(-1, -1, NULL,\r
3465 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
3466 gShellDebug1HiiHandle,\r
3467 INDEX_OF (&(CardBus->InterruptLine)),\r
3468 CardBus->InterruptLine,\r
3469 INDEX_OF (&(CardBus->InterruptPin)),\r
3470 CardBus->InterruptPin\r
3471 );\r
3472\r
3473 //\r
3474 // Print register Bridge Control\r
3475 //\r
3476 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
3477\r
3478 //\r
3479 // Print some registers in data region of PCI configuration space for cardbus\r
3480 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
3481 // Address.\r
3482 //\r
3483 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
3484\r
3485 ShellPrintHiiEx(-1, -1, NULL,\r
3486 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
3487 gShellDebug1HiiHandle,\r
3488 INDEX_OF (&(CardBusData->SubVendorId)),\r
3489 CardBusData->SubVendorId,\r
3490 INDEX_OF (&(CardBusData->SubSystemId)),\r
3491 CardBusData->SubSystemId\r
3492 );\r
3493\r
3494 ShellPrintHiiEx(-1, -1, NULL,\r
3495 STRING_TOKEN (STR_PCI2_OPTIONAL),\r
3496 gShellDebug1HiiHandle,\r
3497 INDEX_OF (&(CardBusData->LegacyBase)),\r
3498 CardBusData->LegacyBase\r
3499 );\r
3500\r
3501 return EFI_SUCCESS;\r
3502}\r
3503\r
a1d4bfcc 3504/**\r
3505 Explain each meaningful bit of register Status. The definition of Status is\r
3506 slightly different depending on the PCI header type.\r
3507\r
3508 @param[in] Status Points to the content of register Status.\r
3509 @param[in] MainStatus Indicates if this register is main status(not secondary\r
3510 status).\r
3511 @param[in] HeaderType Header type of this PCI device.\r
3512\r
3513 @retval EFI_SUCCESS The command completed successfully.\r
3514**/\r
5d73d92f 3515EFI_STATUS\r
3516PciExplainStatus (\r
3517 IN UINT16 *Status,\r
3518 IN BOOLEAN MainStatus,\r
3519 IN PCI_HEADER_TYPE HeaderType\r
3520 )\r
5d73d92f 3521{\r
3522 if (MainStatus) {\r
3523 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3524\r
3525 } else {\r
3526 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
3527 }\r
3528\r
3529 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
3530\r
3531 //\r
3532 // Bit 5 is meaningless for CardBus Bridge\r
3533 //\r
3534 if (HeaderType == PciCardBusBridge) {\r
3535 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3536\r
3537 } else {\r
3538 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
3539 }\r
3540\r
3541 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
3542\r
3543 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
3544 //\r
3545 // Bit 9 and bit 10 together decides the DEVSEL timing\r
3546 //\r
3547 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
3548 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
3549 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
3550\r
3551 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
3552 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
3553\r
3554 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
3555 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
3556\r
3557 } else {\r
3558 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
3559 }\r
3560\r
3561 ShellPrintHiiEx(-1, -1, NULL,\r
3562 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
3563 gShellDebug1HiiHandle,\r
3564 (*Status & PCI_BIT_11) != 0\r
3565 );\r
3566\r
3567 ShellPrintHiiEx(-1, -1, NULL,\r
3568 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
3569 gShellDebug1HiiHandle,\r
3570 (*Status & PCI_BIT_12) != 0\r
3571 );\r
3572\r
3573 ShellPrintHiiEx(-1, -1, NULL,\r
3574 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
3575 gShellDebug1HiiHandle,\r
3576 (*Status & PCI_BIT_13) != 0\r
3577 );\r
3578\r
3579 if (MainStatus) {\r
3580 ShellPrintHiiEx(-1, -1, NULL,\r
3581 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
3582 gShellDebug1HiiHandle,\r
3583 (*Status & PCI_BIT_14) != 0\r
3584 );\r
3585\r
3586 } else {\r
3587 ShellPrintHiiEx(-1, -1, NULL,\r
3588 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
3589 gShellDebug1HiiHandle,\r
3590 (*Status & PCI_BIT_14) != 0\r
3591 );\r
3592 }\r
3593\r
3594 ShellPrintHiiEx(-1, -1, NULL,\r
3595 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
3596 gShellDebug1HiiHandle,\r
3597 (*Status & PCI_BIT_15) != 0\r
3598 );\r
3599\r
3600 return EFI_SUCCESS;\r
3601}\r
3602\r
a1d4bfcc 3603/**\r
5d73d92f 3604 Explain each meaningful bit of register Command.\r
3605\r
a1d4bfcc 3606 @param[in] Command Points to the content of register Command.\r
5d73d92f 3607\r
a1d4bfcc 3608 @retval EFI_SUCCESS The command completed successfully.\r
5d73d92f 3609**/\r
a1d4bfcc 3610EFI_STATUS\r
3611PciExplainCommand (\r
3612 IN UINT16 *Command\r
3613 )\r
5d73d92f 3614{\r
3615 //\r
3616 // Print the binary value of register Command\r
3617 //\r
3618 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
3619\r
3620 //\r
3621 // Explain register Command bit by bit\r
3622 //\r
3623 ShellPrintHiiEx(-1, -1, NULL,\r
3624 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
3625 gShellDebug1HiiHandle,\r
3626 (*Command & PCI_BIT_0) != 0\r
3627 );\r
3628\r
3629 ShellPrintHiiEx(-1, -1, NULL,\r
3630 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
3631 gShellDebug1HiiHandle,\r
3632 (*Command & PCI_BIT_1) != 0\r
3633 );\r
3634\r
3635 ShellPrintHiiEx(-1, -1, NULL,\r
3636 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
3637 gShellDebug1HiiHandle,\r
3638 (*Command & PCI_BIT_2) != 0\r
3639 );\r
3640\r
3641 ShellPrintHiiEx(-1, -1, NULL,\r
3642 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
3643 gShellDebug1HiiHandle,\r
3644 (*Command & PCI_BIT_3) != 0\r
3645 );\r
3646\r
3647 ShellPrintHiiEx(-1, -1, NULL,\r
3648 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
3649 gShellDebug1HiiHandle,\r
3650 (*Command & PCI_BIT_4) != 0\r
3651 );\r
3652\r
3653 ShellPrintHiiEx(-1, -1, NULL,\r
3654 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
3655 gShellDebug1HiiHandle,\r
3656 (*Command & PCI_BIT_5) != 0\r
3657 );\r
3658\r
3659 ShellPrintHiiEx(-1, -1, NULL,\r
3660 STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
3661 gShellDebug1HiiHandle,\r
3662 (*Command & PCI_BIT_6) != 0\r
3663 );\r
3664\r
3665 ShellPrintHiiEx(-1, -1, NULL,\r
3666 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
3667 gShellDebug1HiiHandle,\r
3668 (*Command & PCI_BIT_7) != 0\r
3669 );\r
3670\r
3671 ShellPrintHiiEx(-1, -1, NULL,\r
3672 STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
3673 gShellDebug1HiiHandle,\r
3674 (*Command & PCI_BIT_8) != 0\r
3675 );\r
3676\r
3677 ShellPrintHiiEx(-1, -1, NULL,\r
3678 STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
3679 gShellDebug1HiiHandle,\r
3680 (*Command & PCI_BIT_9) != 0\r
3681 );\r
3682\r
3683 return EFI_SUCCESS;\r
3684}\r
3685\r
a1d4bfcc 3686/**\r
3687 Explain each meaningful bit of register Bridge Control.\r
3688\r
3689 @param[in] BridgeControl Points to the content of register Bridge Control.\r
3690 @param[in] HeaderType The headertype.\r
3691\r
3692 @retval EFI_SUCCESS The command completed successfully.\r
3693**/\r
5d73d92f 3694EFI_STATUS\r
3695PciExplainBridgeControl (\r
3696 IN UINT16 *BridgeControl,\r
3697 IN PCI_HEADER_TYPE HeaderType\r
3698 )\r
5d73d92f 3699{\r
3700 ShellPrintHiiEx(-1, -1, NULL,\r
3701 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
3702 gShellDebug1HiiHandle,\r
3703 INDEX_OF (BridgeControl),\r
3704 *BridgeControl\r
3705 );\r
3706\r
3707 ShellPrintHiiEx(-1, -1, NULL,\r
3708 STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
3709 gShellDebug1HiiHandle,\r
3710 (*BridgeControl & PCI_BIT_0) != 0\r
3711 );\r
3712 ShellPrintHiiEx(-1, -1, NULL,\r
3713 STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
3714 gShellDebug1HiiHandle,\r
3715 (*BridgeControl & PCI_BIT_1) != 0\r
3716 );\r
3717 ShellPrintHiiEx(-1, -1, NULL,\r
3718 STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
3719 gShellDebug1HiiHandle,\r
3720 (*BridgeControl & PCI_BIT_2) != 0\r
3721 );\r
3722 ShellPrintHiiEx(-1, -1, NULL,\r
3723 STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
3724 gShellDebug1HiiHandle,\r
3725 (*BridgeControl & PCI_BIT_3) != 0\r
3726 );\r
3727 ShellPrintHiiEx(-1, -1, NULL,\r
3728 STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
3729 gShellDebug1HiiHandle,\r
3730 (*BridgeControl & PCI_BIT_5) != 0\r
3731 );\r
3732\r
3733 //\r
3734 // Register Bridge Control has some slight differences between P2P bridge\r
3735 // and Cardbus bridge from bit 6 to bit 11.\r
3736 //\r
3737 if (HeaderType == PciP2pBridge) {\r
3738 ShellPrintHiiEx(-1, -1, NULL,\r
3739 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
3740 gShellDebug1HiiHandle,\r
3741 (*BridgeControl & PCI_BIT_6) != 0\r
3742 );\r
3743 ShellPrintHiiEx(-1, -1, NULL,\r
3744 STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
3745 gShellDebug1HiiHandle,\r
3746 (*BridgeControl & PCI_BIT_7) != 0\r
3747 );\r
3748 ShellPrintHiiEx(-1, -1, NULL,\r
3749 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
3750 gShellDebug1HiiHandle,\r
3751 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
3752 );\r
3753 ShellPrintHiiEx(-1, -1, NULL,\r
3754 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
3755 gShellDebug1HiiHandle,\r
3756 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
3757 );\r
3758 ShellPrintHiiEx(-1, -1, NULL,\r
3759 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
3760 gShellDebug1HiiHandle,\r
3761 (*BridgeControl & PCI_BIT_10) != 0\r
3762 );\r
3763 ShellPrintHiiEx(-1, -1, NULL,\r
3764 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
3765 gShellDebug1HiiHandle,\r
3766 (*BridgeControl & PCI_BIT_11) != 0\r
3767 );\r
3768\r
3769 } else {\r
3770 ShellPrintHiiEx(-1, -1, NULL,\r
3771 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
3772 gShellDebug1HiiHandle,\r
3773 (*BridgeControl & PCI_BIT_6) != 0\r
3774 );\r
3775 ShellPrintHiiEx(-1, -1, NULL,\r
3776 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
3777 gShellDebug1HiiHandle,\r
3778 (*BridgeControl & PCI_BIT_7) != 0\r
3779 );\r
3780 ShellPrintHiiEx(-1, -1, NULL,\r
3781 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
3782 gShellDebug1HiiHandle,\r
3783 (*BridgeControl & PCI_BIT_10) != 0\r
3784 );\r
3785 }\r
3786\r
3787 return EFI_SUCCESS;\r
3788}\r
3789\r
a1d4bfcc 3790/**\r
3791 Print each capability structure.\r
3792\r
3793 @param[in] IoDev The pointer to the deivce.\r
3794 @param[in] Address The address to start at.\r
3795 @param[in] CapPtr The offset from the address.\r
3796\r
3797 @retval EFI_SUCCESS The operation was successful.\r
3798**/\r
5d73d92f 3799EFI_STATUS\r
3800PciExplainCapabilityStruct (\r
3801 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
3802 IN UINT64 Address,\r
705bffb5
JC		 3803 IN UINT8 CapPtr,\r
3804 IN CONST UINT16 EnhancedDump\r
5d73d92f 3805 )\r
3806{\r
3807 UINT8 CapabilityPtr;\r
3808 UINT16 CapabilityEntry;\r
3809 UINT8 CapabilityID;\r
3810 UINT64 RegAddress;\r
3811\r
3812 CapabilityPtr = CapPtr;\r
3813\r
3814 //\r
3815 // Go through the Capability list\r
3816 //\r
3817 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
3818 RegAddress = Address + CapabilityPtr;\r
3819 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
3820\r
3821 CapabilityID = (UINT8) CapabilityEntry;\r
3822\r
3823 //\r
3824 // Explain PciExpress data\r
3825 //\r
3826 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
705bffb5 3827 PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r
5d73d92f 3828 return EFI_SUCCESS;\r
3829 }\r
3830 //\r
3831 // Explain other capabilities here\r
3832 //\r
3833 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
3834 }\r
3835\r
3836 return EFI_SUCCESS;\r
3837}\r
3838\r
a1d4bfcc 3839/**\r
3840 Print out information of the capability information.\r
3841\r
3842 @param[in] PciExpressCap The pointer to the structure about the device.\r
3843\r
3844 @retval EFI_SUCCESS The operation was successful.\r
3845**/\r
5d73d92f 3846EFI_STATUS\r
3847ExplainPcieCapReg (\r
3848 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3849 )\r
5d73d92f 3850{\r
3851 UINT16 PcieCapReg;\r
3852 CHAR16 *DevicePortType;\r
3853\r
3854 PcieCapReg = PciExpressCap->PcieCapReg;\r
c37e0f16
CP		 3855 ShellPrintEx (-1, -1,\r
3856 L" Capability Version(3:0): %E0x%04x%N\r\n",\r
5d73d92f 3857 PCIE_CAP_VERSION (PcieCapReg)\r
3858 );\r
3859 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
3860 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
3861 } else {\r
3862 DevicePortType = L"Unknown Type";\r
3863 }\r
c37e0f16
CP		 3864 ShellPrintEx (-1, -1,\r
3865 L" Device/PortType(7:4): %E%s%N\r\n",\r
5d73d92f 3866 DevicePortType\r
3867 );\r
3868 //\r
3869 // 'Slot Implemented' is only valid for:\r
3870 // a) Root Port of PCI Express Root Complex, or\r
3871 // b) Downstream Port of PCI Express Switch\r
3872 //\r
3873 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
3874 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
c37e0f16
CP		 3875 ShellPrintEx (-1, -1,\r
3876 L" Slot Implemented(8): %E%d%N\r\n",\r
5d73d92f 3877 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
3878 );\r
3879 }\r
c37e0f16
CP		 3880 ShellPrintEx (-1, -1,\r
3881 L" Interrupt Message Number(13:9): %E0x%05x%N\r\n",\r
5d73d92f 3882 PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
3883 );\r
3884 return EFI_SUCCESS;\r
3885}\r
3886\r
a1d4bfcc 3887/**\r
3888 Print out information of the device capability information.\r
3889\r
3890 @param[in] PciExpressCap The pointer to the structure about the device.\r
3891\r
3892 @retval EFI_SUCCESS The operation was successful.\r
3893**/\r
5d73d92f 3894EFI_STATUS\r
3895ExplainPcieDeviceCap (\r
3896 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3897 )\r
5d73d92f 3898{\r
3899 UINT16 PcieCapReg;\r
3900 UINT32 PcieDeviceCap;\r
3901 UINT8 DevicePortType;\r
3902 UINT8 L0sLatency;\r
3903 UINT8 L1Latency;\r
3904\r
3905 PcieCapReg = PciExpressCap->PcieCapReg;\r
3906 PcieDeviceCap = PciExpressCap->PcieDeviceCap;\r
3907 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
c37e0f16 3908 ShellPrintEx (-1, -1, L" Max_Payload_Size Supported(2:0): ");\r
5d73d92f 3909 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
c37e0f16 3910 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
5d73d92f 3911 } else {\r
c37e0f16 3912 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 3913 }\r
c37e0f16
CP		 3914 ShellPrintEx (-1, -1,\r
3915 L" Phantom Functions Supported(4:3): %E%d%N\r\n",\r
5d73d92f 3916 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
3917 );\r
c37e0f16
CP		 3918 ShellPrintEx (-1, -1,\r
3919 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",\r
5d73d92f 3920 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
3921 );\r
3922 //\r
3923 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
3924 //\r
3925 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
a1d4bfcc 3926 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
3927 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
c37e0f16 3928 ShellPrintEx (-1, -1, L" Endpoint L0s Acceptable Latency(8:6): ");\r
5d73d92f 3929 if (L0sLatency < 4) {\r
c37e0f16 3930 ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
5d73d92f 3931 } else {\r
3932 if (L0sLatency < 7) {\r
c37e0f16 3933 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
5d73d92f 3934 } else {\r
c37e0f16 3935 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 3936 }\r
3937 }\r
c37e0f16 3938 ShellPrintEx (-1, -1, L" Endpoint L1 Acceptable Latency(11:9): ");\r
5d73d92f 3939 if (L1Latency < 7) {\r
c37e0f16 3940 ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
5d73d92f 3941 } else {\r
c37e0f16 3942 ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
5d73d92f 3943 }\r
3944 }\r
c37e0f16
CP		 3945 ShellPrintEx (-1, -1,\r
3946 L" Role-based Error Reporting(15): %E%d%N\r\n",\r
5d73d92f 3947 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
3948 );\r
3949 //\r
3950 // Only valid for Upstream Port:\r
3951 // a) Captured Slot Power Limit Value\r
3952 // b) Captured Slot Power Scale\r
3953 //\r
3954 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
c37e0f16
CP		 3955 ShellPrintEx (-1, -1,\r
3956 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",\r
5d73d92f 3957 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
3958 );\r
c37e0f16
CP		 3959 ShellPrintEx (-1, -1,\r
3960 L" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",\r
5d73d92f 3961 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
3962 );\r
3963 }\r
3964 //\r
3965 // Function Level Reset Capability is only valid for Endpoint\r
3966 //\r
3967 if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
c37e0f16
CP		 3968 ShellPrintEx (-1, -1,\r
3969 L" Function Level Reset Capability(28): %E%d%N\r\n",\r
5d73d92f 3970 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
3971 );\r
3972 }\r
3973 return EFI_SUCCESS;\r
3974}\r
3975\r
a1d4bfcc 3976/**\r
3977 Print out information of the device control information.\r
3978\r
3979 @param[in] PciExpressCap The pointer to the structure about the device.\r
3980\r
3981 @retval EFI_SUCCESS The operation was successful.\r
3982**/\r
5d73d92f 3983EFI_STATUS\r
3984ExplainPcieDeviceControl (\r
3985 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 3986 )\r
5d73d92f 3987{\r
3988 UINT16 PcieCapReg;\r
3989 UINT16 PcieDeviceControl;\r
3990\r
3991 PcieCapReg = PciExpressCap->PcieCapReg;\r
3992 PcieDeviceControl = PciExpressCap->DeviceControl;\r
c37e0f16
CP		 3993 ShellPrintEx (-1, -1,\r
3994 L" Correctable Error Reporting Enable(0): %E%d%N\r\n",\r
5d73d92f 3995 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
3996 );\r
c37e0f16
CP		 3997 ShellPrintEx (-1, -1,\r
3998 L" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",\r
5d73d92f 3999 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4000 );\r
c37e0f16
CP		 4001 ShellPrintEx (-1, -1,\r
4002 L" Fatal Error Reporting Enable(2): %E%d%N\r\n",\r
5d73d92f 4003 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
4004 );\r
c37e0f16
CP		 4005 ShellPrintEx (-1, -1,\r
4006 L" Unsupported Request Reporting Enable(3): %E%d%N\r\n",\r
5d73d92f 4007 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
4008 );\r
c37e0f16
CP		 4009 ShellPrintEx (-1, -1,\r
4010 L" Enable Relaxed Ordering(4): %E%d%N\r\n",\r
5d73d92f 4011 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
4012 );\r
c37e0f16 4013 ShellPrintEx (-1, -1, L" Max_Payload_Size(7:5): ");\r
5d73d92f 4014 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
c37e0f16 4015 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
5d73d92f 4016 } else {\r
c37e0f16 4017 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4018 }\r
c37e0f16
CP		 4019 ShellPrintEx (-1, -1,\r
4020 L" Extended Tag Field Enable(8): %E%d%N\r\n",\r
5d73d92f 4021 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
4022 );\r
c37e0f16
CP		 4023 ShellPrintEx (-1, -1,\r
4024 L" Phantom Functions Enable(9): %E%d%N\r\n",\r
5d73d92f 4025 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
4026 );\r
c37e0f16
CP		 4027 ShellPrintEx (-1, -1,\r
4028 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",\r
5d73d92f 4029 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
4030 );\r
c37e0f16
CP		 4031 ShellPrintEx (-1, -1,\r
4032 L" Enable No Snoop(11): %E%d%N\r\n",\r
5d73d92f 4033 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
4034 );\r
c37e0f16 4035 ShellPrintEx (-1, -1, L" Max_Read_Request_Size(14:12): ");\r
5d73d92f 4036 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
c37e0f16 4037 ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
5d73d92f 4038 } else {\r
c37e0f16 4039 ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
5d73d92f 4040 }\r
4041 //\r
4042 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
4043 //\r
4044 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
c37e0f16
CP		 4045 ShellPrintEx (-1, -1,\r
4046 L" Bridge Configuration Retry Enable(15): %E%d%N\r\n",\r
5d73d92f 4047 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
4048 );\r
4049 }\r
4050 return EFI_SUCCESS;\r
4051}\r
4052\r
a1d4bfcc 4053/**\r
4054 Print out information of the device status information.\r
4055\r
4056 @param[in] PciExpressCap The pointer to the structure about the device.\r
4057\r
4058 @retval EFI_SUCCESS The operation was successful.\r
4059**/\r
5d73d92f 4060EFI_STATUS\r
4061ExplainPcieDeviceStatus (\r
4062 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4063 )\r
5d73d92f 4064{\r
4065 UINT16 PcieDeviceStatus;\r
4066\r
4067 PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
c37e0f16
CP		 4068 ShellPrintEx (-1, -1,\r
4069 L" Correctable Error Detected(0): %E%d%N\r\n",\r
5d73d92f 4070 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
4071 );\r
c37e0f16
CP		 4072 ShellPrintEx (-1, -1,\r
4073 L" Non-Fatal Error Detected(1): %E%d%N\r\n",\r
5d73d92f 4074 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
4075 );\r
c37e0f16
CP		 4076 ShellPrintEx (-1, -1,\r
4077 L" Fatal Error Detected(2): %E%d%N\r\n",\r
5d73d92f 4078 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
4079 );\r
c37e0f16
CP		 4080 ShellPrintEx (-1, -1,\r
4081 L" Unsupported Request Detected(3): %E%d%N\r\n",\r
5d73d92f 4082 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
4083 );\r
c37e0f16
CP		 4084 ShellPrintEx (-1, -1,\r
4085 L" AUX Power Detected(4): %E%d%N\r\n",\r
5d73d92f 4086 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
4087 );\r
c37e0f16
CP		 4088 ShellPrintEx (-1, -1,\r
4089 L" Transactions Pending(5): %E%d%N\r\n",\r
5d73d92f 4090 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
4091 );\r
4092 return EFI_SUCCESS;\r
4093}\r
4094\r
a1d4bfcc 4095/**\r
4096 Print out information of the device link information.\r
4097\r
4098 @param[in] PciExpressCap The pointer to the structure about the device.\r
4099\r
4100 @retval EFI_SUCCESS The operation was successful.\r
4101**/\r
5d73d92f 4102EFI_STATUS\r
4103ExplainPcieLinkCap (\r
4104 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4105 )\r
5d73d92f 4106{\r
4107 UINT32 PcieLinkCap;\r
541ddf44 4108 CHAR16 *MaxLinkSpeed;\r
a1d4bfcc 4109 CHAR16 *AspmValue;\r
5d73d92f 4110\r
4111 PcieLinkCap = PciExpressCap->LinkCap;\r
541ddf44 4112 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
5d73d92f 4113 case 1:\r
541ddf44 4114 MaxLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4115 break;\r
4116 case 2:\r
541ddf44
CP		 4117 MaxLinkSpeed = L"5.0 GT/s";\r
4118 break;\r
4119 case 3:\r
4120 MaxLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4121 break;\r
4122 default:\r
541ddf44 4123 MaxLinkSpeed = L"Unknown";\r
5d73d92f 4124 break;\r
4125 }\r
c37e0f16 4126 ShellPrintEx (-1, -1,\r
541ddf44
CP		 4127 L" Maximum Link Speed(3:0): %E%s%N\r\n",\r
4128 MaxLinkSpeed\r
5d73d92f 4129 );\r
c37e0f16
CP		 4130 ShellPrintEx (-1, -1,\r
4131 L" Maximum Link Width(9:4): %Ex%d%N\r\n",\r
5d73d92f 4132 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
4133 );\r
4134 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
541ddf44
CP		 4135 case 0:\r
4136 AspmValue = L"Not";\r
4137 break;\r
5d73d92f 4138 case 1:\r
541ddf44
CP		 4139 AspmValue = L"L0s";\r
4140 break;\r
4141 case 2:\r
4142 AspmValue = L"L1";\r
5d73d92f 4143 break;\r
4144 case 3:\r
a1d4bfcc 4145 AspmValue = L"L0s and L1";\r
5d73d92f 4146 break;\r
4147 default:\r
a1d4bfcc 4148 AspmValue = L"Reserved";\r
5d73d92f 4149 break;\r
4150 }\r
c37e0f16
CP		 4151 ShellPrintEx (-1, -1,\r
4152 L" Active State Power Management Support(11:10): %E%s Supported%N\r\n",\r
a1d4bfcc 4153 AspmValue\r
5d73d92f 4154 );\r
c37e0f16
CP		 4155 ShellPrintEx (-1, -1,\r
4156 L" L0s Exit Latency(14:12): %E%s%N\r\n",\r
a1d4bfcc 4157 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4158 );\r
c37e0f16
CP		 4159 ShellPrintEx (-1, -1,\r
4160 L" L1 Exit Latency(17:15): %E%s%N\r\n",\r
a1d4bfcc 4161 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
5d73d92f 4162 );\r
c37e0f16
CP		 4163 ShellPrintEx (-1, -1,\r
4164 L" Clock Power Management(18): %E%d%N\r\n",\r
5d73d92f 4165 PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
4166 );\r
c37e0f16
CP		 4167 ShellPrintEx (-1, -1,\r
4168 L" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",\r
5d73d92f 4169 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
4170 );\r
c37e0f16
CP		 4171 ShellPrintEx (-1, -1,\r
4172 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",\r
5d73d92f 4173 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
4174 );\r
c37e0f16
CP		 4175 ShellPrintEx (-1, -1,\r
4176 L" Link Bandwidth Notification Capability(21): %E%d%N\r\n",\r
5d73d92f 4177 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
4178 );\r
c37e0f16
CP		 4179 ShellPrintEx (-1, -1,\r
4180 L" Port Number(31:24): %E0x%02x%N\r\n",\r
5d73d92f 4181 PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
4182 );\r
4183 return EFI_SUCCESS;\r
4184}\r
4185\r
a1d4bfcc 4186/**\r
4187 Print out information of the device link control information.\r
4188\r
4189 @param[in] PciExpressCap The pointer to the structure about the device.\r
4190\r
4191 @retval EFI_SUCCESS The operation was successful.\r
4192**/\r
5d73d92f 4193EFI_STATUS\r
4194ExplainPcieLinkControl (\r
4195 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4196 )\r
5d73d92f 4197{\r
4198 UINT16 PcieLinkControl;\r
4199 UINT8 DevicePortType;\r
4200\r
4201 PcieLinkControl = PciExpressCap->LinkControl;\r
4202 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
c37e0f16
CP		 4203 ShellPrintEx (-1, -1,\r
4204 L" Active State Power Management Control(1:0): %E%s%N\r\n",\r
5d73d92f 4205 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
4206 );\r
4207 //\r
4208 // RCB is not applicable to switches\r
4209 //\r
4210 if (!IS_PCIE_SWITCH(DevicePortType)) {\r
c37e0f16
CP		 4211 ShellPrintEx (-1, -1,\r
4212 L" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",\r
5d73d92f 4213 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
4214 );\r
4215 }\r
4216 //\r
4217 // Link Disable is reserved on\r
4218 // a) Endpoints\r
4219 // b) PCI Express to PCI/PCI-X bridges\r
4220 // c) Upstream Ports of Switches\r
4221 //\r
4222 if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
4223 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
4224 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
c37e0f16
CP		 4225 ShellPrintEx (-1, -1,\r
4226 L" Link Disable(4): %E%d%N\r\n",\r
5d73d92f 4227 PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
4228 );\r
4229 }\r
c37e0f16
CP		 4230 ShellPrintEx (-1, -1,\r
4231 L" Common Clock Configuration(6): %E%d%N\r\n",\r
5d73d92f 4232 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
4233 );\r
c37e0f16
CP		 4234 ShellPrintEx (-1, -1,\r
4235 L" Extended Synch(7): %E%d%N\r\n",\r
5d73d92f 4236 PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
4237 );\r
c37e0f16
CP		 4238 ShellPrintEx (-1, -1,\r
4239 L" Enable Clock Power Management(8): %E%d%N\r\n",\r
5d73d92f 4240 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
4241 );\r
c37e0f16
CP		 4242 ShellPrintEx (-1, -1,\r
4243 L" Hardware Autonomous Width Disable(9): %E%d%N\r\n",\r
5d73d92f 4244 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
4245 );\r
c37e0f16
CP		 4246 ShellPrintEx (-1, -1,\r
4247 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",\r
5d73d92f 4248 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
4249 );\r
c37e0f16
CP		 4250 ShellPrintEx (-1, -1,\r
4251 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",\r
5d73d92f 4252 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
4253 );\r
4254 return EFI_SUCCESS;\r
4255}\r
4256\r
a1d4bfcc 4257/**\r
4258 Print out information of the device link status information.\r
4259\r
4260 @param[in] PciExpressCap The pointer to the structure about the device.\r
4261\r
4262 @retval EFI_SUCCESS The operation was successful.\r
4263**/\r
5d73d92f 4264EFI_STATUS\r
4265ExplainPcieLinkStatus (\r
4266 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4267 )\r
5d73d92f 4268{\r
4269 UINT16 PcieLinkStatus;\r
541ddf44 4270 CHAR16 *CurLinkSpeed;\r
5d73d92f 4271\r
4272 PcieLinkStatus = PciExpressCap->LinkStatus;\r
4273 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
4274 case 1:\r
541ddf44 4275 CurLinkSpeed = L"2.5 GT/s";\r
5d73d92f 4276 break;\r
4277 case 2:\r
541ddf44
CP		 4278 CurLinkSpeed = L"5.0 GT/s";\r
4279 break;\r
4280 case 3:\r
4281 CurLinkSpeed = L"8.0 GT/s";\r
5d73d92f 4282 break;\r
4283 default:\r
541ddf44 4284 CurLinkSpeed = L"Reserved";\r
5d73d92f 4285 break;\r
4286 }\r
c37e0f16
CP		 4287 ShellPrintEx (-1, -1,\r
4288 L" Current Link Speed(3:0): %E%s%N\r\n",\r
541ddf44 4289 CurLinkSpeed\r
5d73d92f 4290 );\r
c37e0f16
CP		 4291 ShellPrintEx (-1, -1,\r
4292 L" Negotiated Link Width(9:4): %Ex%d%N\r\n",\r
5d73d92f 4293 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
4294 );\r
c37e0f16
CP		 4295 ShellPrintEx (-1, -1,\r
4296 L" Link Training(11): %E%d%N\r\n",\r
5d73d92f 4297 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
4298 );\r
c37e0f16
CP		 4299 ShellPrintEx (-1, -1,\r
4300 L" Slot Clock Configuration(12): %E%d%N\r\n",\r
5d73d92f 4301 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
4302 );\r
c37e0f16
CP		 4303 ShellPrintEx (-1, -1,\r
4304 L" Data Link Layer Link Active(13): %E%d%N\r\n",\r
5d73d92f 4305 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
4306 );\r
c37e0f16
CP		 4307 ShellPrintEx (-1, -1,\r
4308 L" Link Bandwidth Management Status(14): %E%d%N\r\n",\r
5d73d92f 4309 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
4310 );\r
c37e0f16
CP		 4311 ShellPrintEx (-1, -1,\r
4312 L" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",\r
5d73d92f 4313 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
4314 );\r
4315 return EFI_SUCCESS;\r
4316}\r
4317\r
a1d4bfcc 4318/**\r
4319 Print out information of the device slot information.\r
4320\r
4321 @param[in] PciExpressCap The pointer to the structure about the device.\r
4322\r
4323 @retval EFI_SUCCESS The operation was successful.\r
4324**/\r
5d73d92f 4325EFI_STATUS\r
4326ExplainPcieSlotCap (\r
4327 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4328 )\r
5d73d92f 4329{\r
4330 UINT32 PcieSlotCap;\r
4331\r
4332 PcieSlotCap = PciExpressCap->SlotCap;\r
4333\r
c37e0f16
CP		 4334 ShellPrintEx (-1, -1,\r
4335 L" Attention Button Present(0): %E%d%N\r\n",\r
5d73d92f 4336 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
4337 );\r
c37e0f16
CP		 4338 ShellPrintEx (-1, -1,\r
4339 L" Power Controller Present(1): %E%d%N\r\n",\r
5d73d92f 4340 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
4341 );\r
c37e0f16
CP		 4342 ShellPrintEx (-1, -1,\r
4343 L" MRL Sensor Present(2): %E%d%N\r\n",\r
5d73d92f 4344 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
4345 );\r
c37e0f16
CP		 4346 ShellPrintEx (-1, -1,\r
4347 L" Attention Indicator Present(3): %E%d%N\r\n",\r
5d73d92f 4348 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
4349 );\r
c37e0f16
CP		 4350 ShellPrintEx (-1, -1,\r
4351 L" Power Indicator Present(4): %E%d%N\r\n",\r
5d73d92f 4352 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
4353 );\r
c37e0f16
CP		 4354 ShellPrintEx (-1, -1,\r
4355 L" Hot-Plug Surprise(5): %E%d%N\r\n",\r
5d73d92f 4356 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
4357 );\r
c37e0f16
CP		 4358 ShellPrintEx (-1, -1,\r
4359 L" Hot-Plug Capable(6): %E%d%N\r\n",\r
5d73d92f 4360 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
4361 );\r
c37e0f16
CP		 4362 ShellPrintEx (-1, -1,\r
4363 L" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",\r
5d73d92f 4364 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
4365 );\r
c37e0f16
CP		 4366 ShellPrintEx (-1, -1,\r
4367 L" Slot Power Limit Scale(16:15): %E%s%N\r\n",\r
5d73d92f 4368 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
4369 );\r
c37e0f16
CP		 4370 ShellPrintEx (-1, -1,\r
4371 L" Electromechanical Interlock Present(17): %E%d%N\r\n",\r
5d73d92f 4372 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
4373 );\r
c37e0f16
CP		 4374 ShellPrintEx (-1, -1,\r
4375 L" No Command Completed Support(18): %E%d%N\r\n",\r
5d73d92f 4376 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
4377 );\r
c37e0f16
CP		 4378 ShellPrintEx (-1, -1,\r
4379 L" Physical Slot Number(31:19): %E%d%N\r\n",\r
5d73d92f 4380 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
4381 );\r
4382\r
4383 return EFI_SUCCESS;\r
4384}\r
4385\r
a1d4bfcc 4386/**\r
4387 Print out information of the device slot control information.\r
4388\r
4389 @param[in] PciExpressCap The pointer to the structure about the device.\r
4390\r
4391 @retval EFI_SUCCESS The operation was successful.\r
4392**/\r
5d73d92f 4393EFI_STATUS\r
4394ExplainPcieSlotControl (\r
4395 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4396 )\r
5d73d92f 4397{\r
4398 UINT16 PcieSlotControl;\r
4399\r
4400 PcieSlotControl = PciExpressCap->SlotControl;\r
c37e0f16
CP		 4401 ShellPrintEx (-1, -1,\r
4402 L" Attention Button Pressed Enable(0): %E%d%N\r\n",\r
5d73d92f 4403 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
4404 );\r
c37e0f16
CP		 4405 ShellPrintEx (-1, -1,\r
4406 L" Power Fault Detected Enable(1): %E%d%N\r\n",\r
5d73d92f 4407 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
4408 );\r
c37e0f16
CP		 4409 ShellPrintEx (-1, -1,\r
4410 L" MRL Sensor Changed Enable(2): %E%d%N\r\n",\r
5d73d92f 4411 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
4412 );\r
c37e0f16
CP		 4413 ShellPrintEx (-1, -1,\r
4414 L" Presence Detect Changed Enable(3): %E%d%N\r\n",\r
5d73d92f 4415 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
4416 );\r
c37e0f16
CP		 4417 ShellPrintEx (-1, -1,\r
4418 L" Command Completed Interrupt Enable(4): %E%d%N\r\n",\r
5d73d92f 4419 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
4420 );\r
c37e0f16
CP		 4421 ShellPrintEx (-1, -1,\r
4422 L" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",\r
5d73d92f 4423 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
4424 );\r
c37e0f16
CP		 4425 ShellPrintEx (-1, -1,\r
4426 L" Attention Indicator Control(7:6): %E%s%N\r\n",\r
5d73d92f 4427 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
4428 );\r
c37e0f16
CP		 4429 ShellPrintEx (-1, -1,\r
4430 L" Power Indicator Control(9:8): %E%s%N\r\n",\r
5d73d92f 4431 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
4432 );\r
c37e0f16 4433 ShellPrintEx (-1, -1, L" Power Controller Control(10): %EPower ");\r
5d73d92f 4434 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
c37e0f16 4435 ShellPrintEx (-1, -1, L"Off%N\r\n");\r
5d73d92f 4436 } else {\r
c37e0f16 4437 ShellPrintEx (-1, -1, L"On%N\r\n");\r
5d73d92f 4438 }\r
c37e0f16
CP		 4439 ShellPrintEx (-1, -1,\r
4440 L" Electromechanical Interlock Control(11): %E%d%N\r\n",\r
5d73d92f 4441 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
4442 );\r
c37e0f16
CP		 4443 ShellPrintEx (-1, -1,\r
4444 L" Data Link Layer State Changed Enable(12): %E%d%N\r\n",\r
5d73d92f 4445 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
4446 );\r
4447 return EFI_SUCCESS;\r
4448}\r
4449\r
a1d4bfcc 4450/**\r
4451 Print out information of the device slot status information.\r
4452\r
4453 @param[in] PciExpressCap The pointer to the structure about the device.\r
4454\r
4455 @retval EFI_SUCCESS The operation was successful.\r
4456**/\r
5d73d92f 4457EFI_STATUS\r
4458ExplainPcieSlotStatus (\r
4459 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4460 )\r
5d73d92f 4461{\r
4462 UINT16 PcieSlotStatus;\r
4463\r
4464 PcieSlotStatus = PciExpressCap->SlotStatus;\r
4465\r
c37e0f16
CP		 4466 ShellPrintEx (-1, -1,\r
4467 L" Attention Button Pressed(0): %E%d%N\r\n",\r
5d73d92f 4468 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
4469 );\r
c37e0f16
CP		 4470 ShellPrintEx (-1, -1,\r
4471 L" Power Fault Detected(1): %E%d%N\r\n",\r
5d73d92f 4472 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
4473 );\r
c37e0f16
CP		 4474 ShellPrintEx (-1, -1,\r
4475 L" MRL Sensor Changed(2): %E%d%N\r\n",\r
5d73d92f 4476 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
4477 );\r
c37e0f16
CP		 4478 ShellPrintEx (-1, -1,\r
4479 L" Presence Detect Changed(3): %E%d%N\r\n",\r
5d73d92f 4480 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
4481 );\r
c37e0f16
CP		 4482 ShellPrintEx (-1, -1,\r
4483 L" Command Completed(4): %E%d%N\r\n",\r
5d73d92f 4484 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
4485 );\r
c37e0f16 4486 ShellPrintEx (-1, -1, L" MRL Sensor State(5): %EMRL ");\r
5d73d92f 4487 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
c37e0f16 4488 ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
5d73d92f 4489 } else {\r
c37e0f16 4490 ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
5d73d92f 4491 }\r
c37e0f16 4492 ShellPrintEx (-1, -1, L" Presence Detect State(6): ");\r
5d73d92f 4493 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
c37e0f16 4494 ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
5d73d92f 4495 } else {\r
c37e0f16 4496 ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
5d73d92f 4497 }\r
c37e0f16 4498 ShellPrintEx (-1, -1, L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
5d73d92f 4499 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
c37e0f16 4500 ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
5d73d92f 4501 } else {\r
c37e0f16 4502 ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
5d73d92f 4503 }\r
c37e0f16
CP		 4504 ShellPrintEx (-1, -1,\r
4505 L" Data Link Layer State Changed(8): %E%d%N\r\n",\r
5d73d92f 4506 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
4507 );\r
4508 return EFI_SUCCESS;\r
4509}\r
4510\r
a1d4bfcc 4511/**\r
4512 Print out information of the device root information.\r
4513\r
4514 @param[in] PciExpressCap The pointer to the structure about the device.\r
4515\r
4516 @retval EFI_SUCCESS The operation was successful.\r
4517**/\r
5d73d92f 4518EFI_STATUS\r
4519ExplainPcieRootControl (\r
4520 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4521 )\r
5d73d92f 4522{\r
4523 UINT16 PcieRootControl;\r
4524\r
4525 PcieRootControl = PciExpressCap->RootControl;\r
4526\r
c37e0f16
CP		 4527 ShellPrintEx (-1, -1,\r
4528 L" System Error on Correctable Error Enable(0): %E%d%N\r\n",\r
5d73d92f 4529 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
4530 );\r
c37e0f16
CP		 4531 ShellPrintEx (-1, -1,\r
4532 L" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",\r
5d73d92f 4533 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
4534 );\r
c37e0f16
CP		 4535 ShellPrintEx (-1, -1,\r
4536 L" System Error on Fatal Error Enable(2): %E%d%N\r\n",\r
5d73d92f 4537 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
4538 );\r
c37e0f16
CP		 4539 ShellPrintEx (-1, -1,\r
4540 L" PME Interrupt Enable(3): %E%d%N\r\n",\r
5d73d92f 4541 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
4542 );\r
c37e0f16
CP		 4543 ShellPrintEx (-1, -1,\r
4544 L" CRS Software Visibility Enable(4): %E%d%N\r\n",\r
5d73d92f 4545 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
4546 );\r
4547\r
4548 return EFI_SUCCESS;\r
4549}\r
4550\r
a1d4bfcc 4551/**\r
4552 Print out information of the device root capability information.\r
4553\r
4554 @param[in] PciExpressCap The pointer to the structure about the device.\r
4555\r
4556 @retval EFI_SUCCESS The operation was successful.\r
4557**/\r
5d73d92f 4558EFI_STATUS\r
4559ExplainPcieRootCap (\r
4560 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4561 )\r
5d73d92f 4562{\r
4563 UINT16 PcieRootCap;\r
4564\r
4565 PcieRootCap = PciExpressCap->RsvdP;\r
4566\r
c37e0f16
CP		 4567 ShellPrintEx (-1, -1,\r
4568 L" CRS Software Visibility(0): %E%d%N\r\n",\r
5d73d92f 4569 PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
4570 );\r
4571\r
4572 return EFI_SUCCESS;\r
4573}\r
4574\r
a1d4bfcc 4575/**\r
4576 Print out information of the device root status information.\r
4577\r
4578 @param[in] PciExpressCap The pointer to the structure about the device.\r
4579\r
4580 @retval EFI_SUCCESS The operation was successful.\r
4581**/\r
5d73d92f 4582EFI_STATUS\r
4583ExplainPcieRootStatus (\r
4584 IN PCIE_CAP_STURCTURE *PciExpressCap\r
a1d4bfcc 4585 )\r
5d73d92f 4586{\r
4587 UINT32 PcieRootStatus;\r
4588\r
4589 PcieRootStatus = PciExpressCap->RootStatus;\r
4590\r
c37e0f16
CP		 4591 ShellPrintEx (-1, -1,\r
4592 L" PME Requester ID(15:0): %E0x%04x%N\r\n",\r
5d73d92f 4593 PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
4594 );\r
c37e0f16
CP		 4595 ShellPrintEx (-1, -1,\r
4596 L" PME Status(16): %E%d%N\r\n",\r
5d73d92f 4597 PCIE_CAP_PME_STATUS (PcieRootStatus)\r
4598 );\r
c37e0f16
CP		 4599 ShellPrintEx (-1, -1,\r
4600 L" PME Pending(17): %E%d%N\r\n",\r
5d73d92f 4601 PCIE_CAP_PME_PENDING (PcieRootStatus)\r
4602 );\r
4603 return EFI_SUCCESS;\r
4604}\r
4605\r
705bffb5
JC		 4606/**\r
4607 Function to interpret and print out the link control structure\r
4608\r
4609 @param[in] HeaderAddress The Address of this capability header.\r
4610 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4611**/\r
4612EFI_STATUS\r
4613EFIAPI\r
4614PrintInterpretedExtendedCompatibilityLinkControl (\r
4615 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4616 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4617 )\r
4618{\r
4619 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
4620 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
4621\r
4622 ShellPrintHiiEx(\r
4623 -1, -1, NULL, \r
4624 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
4625 gShellDebug1HiiHandle, \r
4626 Header->RootComplexLinkCapabilities,\r
4627 Header->RootComplexLinkControl,\r
4628 Header->RootComplexLinkStatus\r
4629 ); \r
4630 DumpHex (\r
4631 4,\r
4632 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4633 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
4634 (VOID *) (HeaderAddress)\r
4635 );\r
4636 return (EFI_SUCCESS);\r
4637}\r
4638\r
4639/**\r
4640 Function to interpret and print out the power budgeting structure\r
4641\r
4642 @param[in] HeaderAddress The Address of this capability header.\r
4643 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4644**/\r
4645EFI_STATUS\r
4646EFIAPI\r
4647PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
4648 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4649 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4650 )\r
4651{\r
4652 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
4653 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
4654\r
4655 ShellPrintHiiEx(\r
4656 -1, -1, NULL, \r
4657 STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
4658 gShellDebug1HiiHandle, \r
4659 Header->DataSelect,\r
4660 Header->Data,\r
4661 Header->PowerBudgetCapability\r
4662 ); \r
4663 DumpHex (\r
4664 4,\r
4665 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4666 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
4667 (VOID *) (HeaderAddress)\r
4668 );\r
4669 return (EFI_SUCCESS);\r
4670}\r
4671\r
4672/**\r
4673 Function to interpret and print out the ACS structure\r
4674\r
4675 @param[in] HeaderAddress The Address of this capability header.\r
4676 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4677**/\r
4678EFI_STATUS\r
4679EFIAPI\r
4680PrintInterpretedExtendedCompatibilityAcs (\r
4681 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4682 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4683 )\r
4684{\r
4685 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED *Header;\r
4686 UINT16 VectorSize;\r
4687 UINT16 LoopCounter;\r
4688\r
4689 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r
4690 VectorSize = 0;\r
4691\r
4692 ShellPrintHiiEx(\r
4693 -1, -1, NULL, \r
4694 STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
4695 gShellDebug1HiiHandle, \r
4696 Header->AcsCapability,\r
4697 Header->AcsControl\r
4698 ); \r
4699 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
4700 VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
4701 if (VectorSize == 0) {\r
4702 VectorSize = 256;\r
4703 }\r
4704 for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
4705 ShellPrintHiiEx(\r
4706 -1, -1, NULL, \r
4707 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
4708 gShellDebug1HiiHandle, \r
4709 LoopCounter + 1,\r
4710 Header->EgressControlVectorArray[LoopCounter]\r
4711 ); \r
4712 }\r
4713 }\r
4714 DumpHex (\r
4715 4,\r
4716 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4717 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
4718 (VOID *) (HeaderAddress)\r
4719 );\r
4720 return (EFI_SUCCESS);\r
4721}\r
4722\r
4723/**\r
4724 Function to interpret and print out the latency tolerance reporting structure\r
4725\r
4726 @param[in] HeaderAddress The Address of this capability header.\r
4727 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4728**/\r
4729EFI_STATUS\r
4730EFIAPI\r
4731PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
4732 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4733 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4734 )\r
4735{\r
4736 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
4737 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
4738\r
4739 ShellPrintHiiEx(\r
4740 -1, -1, NULL, \r
4741 STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
4742 gShellDebug1HiiHandle, \r
4743 Header->MaxSnoopLatency,\r
4744 Header->MaxNoSnoopLatency\r
4745 ); \r
4746 DumpHex (\r
4747 4,\r
4748 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4749 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
4750 (VOID *) (HeaderAddress)\r
4751 );\r
4752 return (EFI_SUCCESS);\r
4753}\r
4754\r
4755/**\r
4756 Function to interpret and print out the serial number structure\r
4757\r
4758 @param[in] HeaderAddress The Address of this capability header.\r
4759 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4760**/\r
4761EFI_STATUS\r
4762EFIAPI\r
4763PrintInterpretedExtendedCompatibilitySerialNumber (\r
4764 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4765 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4766 )\r
4767{\r
4768 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
4769 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
4770\r
4771 ShellPrintHiiEx(\r
4772 -1, -1, NULL, \r
4773 STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
4774 gShellDebug1HiiHandle, \r
4775 Header->SerialNumber\r
4776 ); \r
4777 DumpHex (\r
4778 4,\r
4779 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4780 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
4781 (VOID *) (HeaderAddress)\r
4782 );\r
4783 return (EFI_SUCCESS);\r
4784}\r
4785\r
4786/**\r
4787 Function to interpret and print out the RCRB structure\r
4788\r
4789 @param[in] HeaderAddress The Address of this capability header.\r
4790 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4791**/\r
4792EFI_STATUS\r
4793EFIAPI\r
4794PrintInterpretedExtendedCompatibilityRcrb (\r
4795 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4796 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4797 )\r
4798{\r
4799 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
4800 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
4801\r
4802 ShellPrintHiiEx(\r
4803 -1, -1, NULL, \r
4804 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
4805 gShellDebug1HiiHandle, \r
4806 Header->VendorId,\r
4807 Header->DeviceId,\r
4808 Header->RcrbCapabilities,\r
4809 Header->RcrbControl\r
4810 ); \r
4811 DumpHex (\r
4812 4,\r
4813 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4814 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
4815 (VOID *) (HeaderAddress)\r
4816 );\r
4817 return (EFI_SUCCESS);\r
4818}\r
4819\r
4820/**\r
4821 Function to interpret and print out the vendor specific structure\r
4822\r
4823 @param[in] HeaderAddress The Address of this capability header.\r
4824 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4825**/\r
4826EFI_STATUS\r
4827EFIAPI\r
4828PrintInterpretedExtendedCompatibilityVendorSpecific (\r
4829 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4830 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4831 )\r
4832{\r
4833 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
4834 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
4835\r
4836 ShellPrintHiiEx(\r
4837 -1, -1, NULL, \r
4838 STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
4839 gShellDebug1HiiHandle, \r
4840 Header->VendorSpecificHeader\r
4841 ); \r
4842 DumpHex (\r
4843 4,\r
4844 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4845 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r
4846 (VOID *) (HeaderAddress)\r
4847 );\r
4848 return (EFI_SUCCESS);\r
4849}\r
4850\r
4851/**\r
4852 Function to interpret and print out the Event Collector Endpoint Association structure\r
4853\r
4854 @param[in] HeaderAddress The Address of this capability header.\r
4855 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4856**/\r
4857EFI_STATUS\r
4858EFIAPI\r
4859PrintInterpretedExtendedCompatibilityECEA (\r
4860 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4861 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4862 )\r
4863{\r
4864 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
4865 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
4866\r
4867 ShellPrintHiiEx(\r
4868 -1, -1, NULL, \r
4869 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
4870 gShellDebug1HiiHandle, \r
4871 Header->AssociationBitmap\r
4872 ); \r
4873 DumpHex (\r
4874 4,\r
4875 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4876 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
4877 (VOID *) (HeaderAddress)\r
4878 );\r
4879 return (EFI_SUCCESS);\r
4880}\r
4881\r
4882/**\r
4883 Function to interpret and print out the ARI structure\r
4884\r
4885 @param[in] HeaderAddress The Address of this capability header.\r
4886 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4887**/\r
4888EFI_STATUS\r
4889EFIAPI\r
4890PrintInterpretedExtendedCompatibilityAri (\r
4891 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4892 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4893 )\r
4894{\r
4895 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
4896 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
4897\r
4898 ShellPrintHiiEx(\r
4899 -1, -1, NULL, \r
4900 STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
4901 gShellDebug1HiiHandle, \r
4902 Header->AriCapability,\r
4903 Header->AriControl\r
4904 ); \r
4905 DumpHex (\r
4906 4,\r
4907 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4908 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
4909 (VOID *) (HeaderAddress)\r
4910 );\r
4911 return (EFI_SUCCESS);\r
4912}\r
4913\r
4914/**\r
4915 Function to interpret and print out the DPA structure\r
4916\r
4917 @param[in] HeaderAddress The Address of this capability header.\r
4918 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4919**/\r
4920EFI_STATUS\r
4921EFIAPI\r
4922PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
4923 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4924 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4925 )\r
4926{\r
4927 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
4928 UINT8 LinkCount;\r
4929 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
4930\r
4931 ShellPrintHiiEx(\r
4932 -1, -1, NULL, \r
4933 STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
4934 gShellDebug1HiiHandle, \r
4935 Header->DpaCapability,\r
4936 Header->DpaLatencyIndicator,\r
4937 Header->DpaStatus,\r
4938 Header->DpaControl\r
4939 ); \r
4940 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
4941 ShellPrintHiiEx(\r
4942 -1, -1, NULL, \r
4943 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
4944 gShellDebug1HiiHandle, \r
4945 LinkCount+1,\r
4946 Header->DpaPowerAllocationArray[LinkCount]\r
4947 );\r
4948 }\r
4949 DumpHex (\r
4950 4,\r
4951 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4952 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r
4953 (VOID *) (HeaderAddress)\r
4954 );\r
4955 return (EFI_SUCCESS);\r
4956}\r
4957\r
4958/**\r
4959 Function to interpret and print out the link declaration structure\r
4960\r
4961 @param[in] HeaderAddress The Address of this capability header.\r
4962 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
4963**/\r
4964EFI_STATUS\r
4965EFIAPI\r
4966PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
4967 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
4968 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
4969 )\r
4970{\r
4971 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION *Header;\r
4972 UINT8 LinkCount;\r
4973 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
4974\r
4975 ShellPrintHiiEx(\r
4976 -1, -1, NULL, \r
4977 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
4978 gShellDebug1HiiHandle, \r
4979 Header->ElementSelfDescription\r
4980 );\r
4981\r
4982 for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
4983 ShellPrintHiiEx(\r
4984 -1, -1, NULL, \r
4985 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
4986 gShellDebug1HiiHandle, \r
4987 LinkCount+1,\r
4988 Header->LinkEntry[LinkCount]\r
4989 );\r
4990 }\r
4991 DumpHex (\r
4992 4,\r
4993 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
4994 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r
4995 (VOID *) (HeaderAddress)\r
4996 );\r
4997 return (EFI_SUCCESS);\r
4998}\r
4999\r
5000/**\r
5001 Function to interpret and print out the Advanced Error Reporting structure\r
5002\r
5003 @param[in] HeaderAddress The Address of this capability header.\r
5004 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5005**/\r
5006EFI_STATUS\r
5007EFIAPI\r
5008PrintInterpretedExtendedCompatibilityAer (\r
5009 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5010 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5011 )\r
5012{\r
5013 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
5014 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
5015\r
5016 ShellPrintHiiEx(\r
5017 -1, -1, NULL, \r
5018 STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
5019 gShellDebug1HiiHandle, \r
5020 Header->UncorrectableErrorStatus,\r
5021 Header->UncorrectableErrorMask,\r
5022 Header->UncorrectableErrorSeverity,\r
5023 Header->CorrectableErrorStatus,\r
5024 Header->CorrectableErrorMask,\r
5025 Header->AdvancedErrorCapabilitiesAndControl,\r
5026 Header->HeaderLog,\r
5027 Header->RootErrorCommand,\r
5028 Header->RootErrorStatus,\r
5029 Header->ErrorSourceIdentification,\r
5030 Header->CorrectableErrorSourceIdentification,\r
5031 Header->TlpPrefixLog[0],\r
5032 Header->TlpPrefixLog[1],\r
5033 Header->TlpPrefixLog[2],\r
5034 Header->TlpPrefixLog[3]\r
5035 );\r
5036 DumpHex (\r
5037 4,\r
5038 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5039 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
5040 (VOID *) (HeaderAddress)\r
5041 );\r
5042 return (EFI_SUCCESS);\r
5043}\r
5044\r
9f7f0697
JC		 5045/**\r
5046 Function to interpret and print out the multicast structure\r
5047\r
5048 @param[in] HeaderAddress The Address of this capability header.\r
5049 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5050 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5051**/\r
5052EFI_STATUS\r
5053EFIAPI\r
5054PrintInterpretedExtendedCompatibilityMulticast (\r
5055 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5056 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
5057 IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
5058 )\r
5059{\r
5060 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
5061 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
5062\r
5063 ShellPrintHiiEx(\r
5064 -1, -1, NULL, \r
5065 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
5066 gShellDebug1HiiHandle, \r
5067 Header->MultiCastCapability,\r
5068 Header->MulticastControl,\r
5069 Header->McBaseAddress,\r
5070 Header->McReceiveAddress,\r
5071 Header->McBlockAll,\r
5072 Header->McBlockUntranslated,\r
5073 Header->McOverlayBar\r
5074 );\r
5075\r
5076 DumpHex (\r
5077 4,\r
5078 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5079 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
5080 (VOID *) (HeaderAddress)\r
5081 );\r
5082\r
5083 return (EFI_SUCCESS);\r
5084}\r
5085\r
5086/**\r
5087 Function to interpret and print out the virtual channel and multi virtual channel structure\r
5088\r
5089 @param[in] HeaderAddress The Address of this capability header.\r
5090 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5091**/\r
5092EFI_STATUS\r
5093EFIAPI\r
5094PrintInterpretedExtendedCompatibilityVirtualChannel (\r
5095 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5096 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5097 )\r
5098{\r
5099 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
5100 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
5101 UINT32 ItemCount;\r
5102 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
5103\r
5104 ShellPrintHiiEx(\r
5105 -1, -1, NULL, \r
5106 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
5107 gShellDebug1HiiHandle, \r
5108 Header->ExtendedVcCount,\r
5109 Header->PortVcCapability1,\r
5110 Header->PortVcCapability2,\r
5111 Header->VcArbTableOffset,\r
5112 Header->PortVcControl,\r
5113 Header->PortVcStatus\r
5114 );\r
5115 for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
5116 CapabilityItem = &Header->Capability[ItemCount];\r
5117 ShellPrintHiiEx(\r
5118 -1, -1, NULL, \r
5119 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
5120 gShellDebug1HiiHandle, \r
5121 ItemCount+1,\r
5122 CapabilityItem->VcResourceCapability,\r
5123 CapabilityItem->PortArbTableOffset,\r
5124 CapabilityItem->VcResourceControl,\r
5125 CapabilityItem->VcResourceStatus\r
5126 );\r
5127 }\r
5128\r
5129 DumpHex (\r
5130 4,\r
5131 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5132 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r
5133 (VOID *) (HeaderAddress)\r
5134 );\r
5135\r
5136 return (EFI_SUCCESS);\r
5137}\r
5138\r
5139/**\r
5140 Function to interpret and print out the resizeable bar structure\r
5141\r
5142 @param[in] HeaderAddress The Address of this capability header.\r
5143 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5144**/\r
5145EFI_STATUS\r
5146EFIAPI\r
5147PrintInterpretedExtendedCompatibilityResizeableBar (\r
5148 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5149 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5150 )\r
5151{\r
5152 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
5153 UINT32 ItemCount;\r
5154 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
5155\r
5156 for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
5157 ShellPrintHiiEx(\r
5158 -1, -1, NULL, \r
5159 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
5160 gShellDebug1HiiHandle, \r
5161 ItemCount+1,\r
5162 Header->Capability[ItemCount].ResizableBarCapability,\r
5163 Header->Capability[ItemCount].ResizableBarControl\r
5164 );\r
5165 }\r
5166\r
5167 DumpHex (\r
5168 4,\r
5169 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5170 (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
5171 (VOID *) (HeaderAddress)\r
5172 );\r
5173\r
5174 return (EFI_SUCCESS);\r
5175}\r
5176\r
5177/**\r
5178 Function to interpret and print out the TPH structure\r
5179\r
5180 @param[in] HeaderAddress The Address of this capability header.\r
5181 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5182**/\r
5183EFI_STATUS\r
5184EFIAPI\r
5185PrintInterpretedExtendedCompatibilityTph (\r
5186 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5187 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
5188 )\r
5189{\r
5190 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
5191 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
5192\r
5193 ShellPrintHiiEx(\r
5194 -1, -1, NULL, \r
5195 STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
5196 gShellDebug1HiiHandle, \r
5197 Header->TphRequesterCapability,\r
5198 Header->TphRequesterControl\r
5199 );\r
5200 DumpHex (\r
5201 8,\r
5202 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
5203 GET_TPH_TABLE_SIZE(Header),\r
5204 (VOID *)Header->TphStTable\r
5205 );\r
5206\r
5207 DumpHex (\r
5208 4,\r
5209 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5210 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
5211 (VOID *) (HeaderAddress)\r
5212 );\r
5213\r
5214 return (EFI_SUCCESS);\r
5215}\r
5216\r
5217/**\r
5218 Function to interpret and print out the secondary PCIe capability structure\r
5219\r
5220 @param[in] HeaderAddress The Address of this capability header.\r
5221 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5222 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5223**/\r
5224EFI_STATUS\r
5225EFIAPI\r
5226PrintInterpretedExtendedCompatibilitySecondary (\r
5227 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5228 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
5229 IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
5230 )\r
5231{\r
5232 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
5233 Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
5234\r
5235 ShellPrintHiiEx(\r
5236 -1, -1, NULL, \r
5237 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
5238 gShellDebug1HiiHandle, \r
5239 Header->LinkControl3,\r
5240 Header->LaneErrorStatus\r
5241 );\r
5242 DumpHex (\r
5243 8,\r
5244 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
5245 PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
5246 (VOID *)Header->EqualizationControl\r
5247 );\r
5248\r
5249 DumpHex (\r
5250 4,\r
5251 EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
5252 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
5253 (VOID *) (HeaderAddress)\r
5254 );\r
5255\r
5256 return (EFI_SUCCESS);\r
5257}\r
5258\r
705bffb5
JC		 5259/**\r
5260 Display Pcie extended capability details\r
5261\r
5262 @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
5263 @param[in] HeaderAddress The address of this capability header.\r
5264 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
5265**/\r
5266EFI_STATUS\r
5267EFIAPI\r
5268PrintPciExtendedCapabilityDetails(\r
5269 IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
5270 IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
5271 IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
5272 )\r
5273{\r
5274 switch (HeaderAddress->CapabilityId){\r
5275 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
5276 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
5277 break;\r
5278 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
5279 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
5280 break;\r
5281 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
5282 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
5283 break;\r
5284 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
5285 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
5286 break;\r
5287 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
5288 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
5289 break;\r
5290 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
5291 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
5292 break;\r
5293 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
5294 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
5295 break;\r
5296 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
5297 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
5298 break;\r
5299 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
5300 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
5301 break;\r
5302 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
5303 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
5304 break;\r
5305 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
5306 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
5307 break;\r
5308 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
5309 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
5310 break;\r
705bffb5
JC		 5311 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
5312 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
9f7f0697 5313 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5314 break;\r
5315 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
9f7f0697
JC		 5316 //\r
5317 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
5318 //\r
5319 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
705bffb5
JC		 5320 break;\r
5321 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
9f7f0697 5322 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5323 break;\r
5324 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
9f7f0697 5325 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
705bffb5
JC		 5326 break;\r
5327 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
9f7f0697 5328 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
705bffb5 5329 break;\r
705bffb5
JC		 5330 default:\r
5331 ShellPrintEx (-1, -1,\r
5332 L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
5333 HeaderAddress->CapabilityId\r
5334 );\r
5335 return EFI_SUCCESS;\r
5336 break;\r
5337 };\r
5338\r
5339}\r
5340\r
a1d4bfcc 5341/**\r
5342 Display Pcie device structure.\r
5343\r
5344 @param[in] IoDev The pointer to the root pci protocol.\r
5345 @param[in] Address The Address to start at.\r
5346 @param[in] CapabilityPtr The offset from the address to start.\r
5347**/\r
5d73d92f 5348EFI_STATUS\r
5349PciExplainPciExpress (\r
5350 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
5351 IN UINT64 Address,\r
705bffb5
JC		 5352 IN UINT8 CapabilityPtr,\r
5353 IN CONST UINT16 EnhancedDump\r
5d73d92f 5354 )\r
5355{\r
5356\r
5357 PCIE_CAP_STURCTURE PciExpressCap;\r
5358 EFI_STATUS Status;\r
5359 UINT64 CapRegAddress;\r
5360 UINT8 Bus;\r
5361 UINT8 Dev;\r
5362 UINT8 Func;\r
5363 UINT8 *ExRegBuffer;\r
5364 UINTN ExtendRegSize;\r
5365 UINT64 Pciex_Address;\r
5366 UINT8 DevicePortType;\r
5367 UINTN Index;\r
5368 UINT8 *RegAddr;\r
5369 UINTN RegValue;\r
705bffb5 5370 PCI_EXP_EXT_HDR *ExtHdr;\r
5d73d92f 5371\r
5372 CapRegAddress = Address + CapabilityPtr;\r
5373 IoDev->Pci.Read (\r
5374 IoDev,\r
5375 EfiPciWidthUint32,\r
5376 CapRegAddress,\r
5377 sizeof (PciExpressCap) / sizeof (UINT32),\r
5378 &PciExpressCap\r
5379 );\r
5380\r
5381 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
5382\r
c37e0f16 5383 ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
5d73d92f 5384\r
5385 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
5386 if (ShellGetExecutionBreakFlag()) {\r
5387 goto Done;\r
5388 }\r
5389 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
5390 switch (PcieExplainList[Index].Width) {\r
5391 case FieldWidthUINT8:\r
5392 RegValue = *(UINT8 *) RegAddr;\r
5393 break;\r
5394 case FieldWidthUINT16:\r
5395 RegValue = *(UINT16 *) RegAddr;\r
5396 break;\r
5397 case FieldWidthUINT32:\r
5398 RegValue = *(UINT32 *) RegAddr;\r
5399 break;\r
5400 default:\r
5401 RegValue = 0;\r
5402 break;\r
5403 }\r
5404 ShellPrintHiiEx(-1, -1, NULL,\r
5405 PcieExplainList[Index].Token,\r
5406 gShellDebug1HiiHandle,\r
5407 PcieExplainList[Index].Offset,\r
5408 RegValue\r
5409 );\r
5410 if (PcieExplainList[Index].Func == NULL) {\r
5411 continue;\r
5412 }\r
5413 switch (PcieExplainList[Index].Type) {\r
5414 case PcieExplainTypeLink:\r
5415 //\r
5416 // Link registers should not be used by\r
5417 // a) Root Complex Integrated Endpoint\r
5418 // b) Root Complex Event Collector\r
5419 //\r
5420 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
5421 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
5422 continue;\r
5423 }\r
5424 break;\r
5425 case PcieExplainTypeSlot:\r
5426 //\r
5427 // Slot registers are only valid for\r
5428 // a) Root Port of PCI Express Root Complex\r
5429 // b) Downstream Port of PCI Express Switch\r
5430 // and when SlotImplemented bit is set in PCIE cap register.\r
5431 //\r
5432 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
5433 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
5434 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
5435 continue;\r
5436 }\r
5437 break;\r
5438 case PcieExplainTypeRoot:\r
5439 //\r
5440 // Root registers are only valid for\r
5441 // Root Port of PCI Express Root Complex\r
5442 //\r
5443 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
5444 continue;\r
5445 }\r
5446 break;\r
5447 default:\r
5448 break;\r
5449 }\r
5450 PcieExplainList[Index].Func (&PciExpressCap);\r
5451 }\r
5452\r
5453 Bus = (UINT8) (RShiftU64 (Address, 24));\r
5454 Dev = (UINT8) (RShiftU64 (Address, 16));\r
5455 Func = (UINT8) (RShiftU64 (Address, 8));\r
5456\r
705bffb5 5457 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
5d73d92f 5458\r
705bffb5 5459 ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
5d73d92f 5460\r
3737ac2b 5461 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
5d73d92f 5462\r
5463 //\r
5464 // PciRootBridgeIo protocol should support pci express extend space IO\r
705bffb5 5465 // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r
5d73d92f 5466 //\r
5467 Status = IoDev->Pci.Read (\r
5468 IoDev,\r
5469 EfiPciWidthUint32,\r
5470 Pciex_Address,\r
5471 (ExtendRegSize) / sizeof (UINT32),\r
5472 (VOID *) (ExRegBuffer)\r
5473 );\r
705bffb5
JC		 5474 if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r
5475 SHELL_FREE_NON_NULL(ExRegBuffer);\r
5d73d92f 5476 return EFI_UNSUPPORTED;\r
5477 }\r
5d73d92f 5478\r
705bffb5
JC		 5479 if (EnhancedDump == 0) {\r
5480 //\r
5481 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
5482 //\r
5483 ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
5484\r
d8f8021c 5485 DumpHex (\r
5486 2,\r
705bffb5 5487 EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
d8f8021c 5488 ExtendRegSize,\r
5489 (VOID *) (ExRegBuffer)\r
705bffb5
JC		 5490 );\r
5491 } else {\r
5492 ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r
5493 while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
5494 //\r
5495 // Process this item\r
5496 //\r
5497 if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r
5498 //\r
5499 // Print this item\r
5500 //\r
5501 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r
5502 }\r
5d73d92f 5503\r
705bffb5
JC		 5504 //\r
5505 // Advance to the next item if it exists\r
5506 //\r
5507 if (ExtHdr->NextCapabilityOffset != 0) {\r
5508 ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset);\r
5509 } else {\r
5510 break;\r
5511 }\r
5512 }\r
d8f8021c 5513 }\r
705bffb5 5514 SHELL_FREE_NON_NULL(ExRegBuffer);\r
5d73d92f 5515\r
5516Done:\r
5517 return EFI_SUCCESS;\r
5518}\r
EFI Development Kit II mirror for PVE