[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c

/** @file\r
  Main file for Pci shell Debug1 function.\r
\r
  Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>\r
  (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>  \r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "UefiShellDebug1CommandsLib.h"\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Library/ShellLib.h>\r
#include <IndustryStandard/Pci.h>\r
#include <IndustryStandard/Acpi.h>\r
#include "Pci.h"\r
\r
//\r
// Printable strings for Pci class code\r
//\r
typedef struct {\r
  CHAR16  *BaseClass; // Pointer to the PCI base class string\r
  CHAR16  *SubClass;  // Pointer to the PCI sub class string\r
  CHAR16  *PIFClass;  // Pointer to the PCI programming interface string\r
} PCI_CLASS_STRINGS;\r
\r
//\r
// a structure holding a single entry, which also points to its lower level\r
// class\r
//\r
typedef struct PCI_CLASS_ENTRY_TAG {\r
  UINT8                       Code;             // Class, subclass or I/F code\r
  CHAR16                      *DescText;        // Description string\r
  struct PCI_CLASS_ENTRY_TAG  *LowerLevelClass; // Subclass or I/F if any\r
} PCI_CLASS_ENTRY;\r
\r
//\r
// Declarations of entries which contain printable strings for class codes\r
// in PCI configuration space\r
//\r
PCI_CLASS_ENTRY PCIBlankEntry[];\r
PCI_CLASS_ENTRY PCISubClass_00[];\r
PCI_CLASS_ENTRY PCISubClass_01[];\r
PCI_CLASS_ENTRY PCISubClass_02[];\r
PCI_CLASS_ENTRY PCISubClass_03[];\r
PCI_CLASS_ENTRY PCISubClass_04[];\r
PCI_CLASS_ENTRY PCISubClass_05[];\r
PCI_CLASS_ENTRY PCISubClass_06[];\r
PCI_CLASS_ENTRY PCISubClass_07[];\r
PCI_CLASS_ENTRY PCISubClass_08[];\r
PCI_CLASS_ENTRY PCISubClass_09[];\r
PCI_CLASS_ENTRY PCISubClass_0a[];\r
PCI_CLASS_ENTRY PCISubClass_0b[];\r
PCI_CLASS_ENTRY PCISubClass_0c[];\r
PCI_CLASS_ENTRY PCISubClass_0d[];\r
PCI_CLASS_ENTRY PCISubClass_0e[];\r
PCI_CLASS_ENTRY PCISubClass_0f[];\r
PCI_CLASS_ENTRY PCISubClass_10[];\r
PCI_CLASS_ENTRY PCISubClass_11[];\r
PCI_CLASS_ENTRY PCISubClass_12[];\r
PCI_CLASS_ENTRY PCISubClass_13[];\r
PCI_CLASS_ENTRY PCIPIFClass_0100[];\r
PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
PCI_CLASS_ENTRY PCIPIFClass_0105[];\r
PCI_CLASS_ENTRY PCIPIFClass_0106[];\r
PCI_CLASS_ENTRY PCIPIFClass_0107[];\r
PCI_CLASS_ENTRY PCIPIFClass_0108[];\r
PCI_CLASS_ENTRY PCIPIFClass_0109[];\r
PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
PCI_CLASS_ENTRY PCIPIFClass_0609[];\r
PCI_CLASS_ENTRY PCIPIFClass_060b[];\r
PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
PCI_CLASS_ENTRY PCIPIFClass_0800[];\r
PCI_CLASS_ENTRY PCIPIFClass_0801[];\r
PCI_CLASS_ENTRY PCIPIFClass_0802[];\r
PCI_CLASS_ENTRY PCIPIFClass_0803[];\r
PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r
PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r
PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
\r
//\r
// Base class strings entries\r
//\r
PCI_CLASS_ENTRY gClassStringList[] = {\r
  {\r
    0x00,\r
    L"Pre 2.0 device",\r
    PCISubClass_00\r
  },\r
  {\r
    0x01,\r
    L"Mass Storage Controller",\r
    PCISubClass_01\r
  },\r
  {\r
    0x02,\r
    L"Network Controller",\r
    PCISubClass_02\r
  },\r
  {\r
    0x03,\r
    L"Display Controller",\r
    PCISubClass_03\r
  },\r
  {\r
    0x04,\r
    L"Multimedia Device",\r
    PCISubClass_04\r
  },\r
  {\r
    0x05,\r
    L"Memory Controller",\r
    PCISubClass_05\r
  },\r
  {\r
    0x06,\r
    L"Bridge Device",\r
    PCISubClass_06\r
  },\r
  {\r
    0x07,\r
    L"Simple Communications Controllers",\r
    PCISubClass_07\r
  },\r
  {\r
    0x08,\r
    L"Base System Peripherals",\r
    PCISubClass_08\r
  },\r
  {\r
    0x09,\r
    L"Input Devices",\r
    PCISubClass_09\r
  },\r
  {\r
    0x0a,\r
    L"Docking Stations",\r
    PCISubClass_0a\r
  },\r
  {\r
    0x0b,\r
    L"Processors",\r
    PCISubClass_0b\r
  },\r
  {\r
    0x0c,\r
    L"Serial Bus Controllers",\r
    PCISubClass_0c\r
  },\r
  {\r
    0x0d,\r
    L"Wireless Controllers",\r
    PCISubClass_0d\r
  },\r
  {\r
    0x0e,\r
    L"Intelligent IO Controllers",\r
    PCISubClass_0e\r
  },\r
  {\r
    0x0f,\r
    L"Satellite Communications Controllers",\r
    PCISubClass_0f\r
  },\r
  {\r
    0x10,\r
    L"Encryption/Decryption Controllers",\r
    PCISubClass_10\r
  },\r
  {\r
    0x11,\r
    L"Data Acquisition & Signal Processing Controllers",\r
    PCISubClass_11\r
  },\r
  {\r
    0x12,\r
    L"Processing Accelerators",\r
    PCISubClass_12\r
  },\r
  {\r
    0x13,\r
    L"Non-Essential Instrumentation",\r
    PCISubClass_13\r
  },\r
  {\r
    0xff,\r
    L"Device does not fit in any defined classes",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
//\r
// Subclass strings entries\r
//\r
PCI_CLASS_ENTRY PCIBlankEntry[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_00[] = {\r
  {\r
    0x00,\r
    L"All devices other than VGA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"VGA-compatible devices",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_01[] = {\r
  {\r
    0x00,\r
    L"SCSI",\r
    PCIPIFClass_0100\r
  },\r
  {\r
    0x01,\r
    L"IDE controller",\r
    PCIPIFClass_0101\r
  },\r
  {\r
    0x02,\r
    L"Floppy disk controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"IPI controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"RAID controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x05,\r
    L"ATA controller with ADMA interface",\r
    PCIPIFClass_0105\r
  },\r
  {\r
    0x06,\r
    L"Serial ATA controller",\r
    PCIPIFClass_0106\r
  },\r
  {\r
    0x07,\r
    L"Serial Attached SCSI (SAS) controller ",\r
    PCIPIFClass_0107\r
  },\r
  {\r
    0x08,\r
    L"Non-volatile memory subsystem",\r
    PCIPIFClass_0108\r
  },\r
  {\r
    0x09,\r
    L"Universal Flash Storage (UFS) controller ",\r
    PCIPIFClass_0109\r
  },\r
  {\r
    0x80,\r
    L"Other mass storage controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_02[] = {\r
  {\r
    0x00,\r
    L"Ethernet controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Token ring controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"FDDI controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"ATM controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"ISDN controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x05,\r
    L"WorldFip controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x06,\r
    L"PICMG 2.14 Multi Computing",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x07,\r
    L"InfiniBand controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other network controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_03[] = {\r
  {\r
    0x00,\r
    L"VGA/8514 controller",\r
    PCIPIFClass_0300\r
  },\r
  {\r
    0x01,\r
    L"XGA controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"3D controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other display controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */PCIBlankEntry\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_04[] = {\r
  {\r
    0x00,\r
    L"Video device",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Audio device",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"Computer Telephony device",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"Mixed mode device",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other multimedia device",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_05[] = {\r
  {\r
    0x00,\r
    L"RAM memory controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Flash memory controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other memory controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_06[] = {\r
  {\r
    0x00,\r
    L"Host/PCI bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"PCI/ISA bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"PCI/EISA bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"PCI/Micro Channel bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"PCI/PCI bridge",\r
    PCIPIFClass_0604\r
  },\r
  {\r
    0x05,\r
    L"PCI/PCMCIA bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x06,\r
    L"NuBus bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x07,\r
    L"CardBus bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x08,\r
    L"RACEway bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x09,\r
    L"Semi-transparent PCI-to-PCI bridge",\r
    PCIPIFClass_0609\r
  },\r
  {\r
    0x0A,\r
    L"InfiniBand-to-PCI host bridge",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x0B,\r
    L"Advanced Switching to PCI host bridge",\r
    PCIPIFClass_060b\r
  },\r
  {\r
    0x80,\r
    L"Other bridge type",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_07[] = {\r
  {\r
    0x00,\r
    L"Serial controller",\r
    PCIPIFClass_0700\r
  },\r
  {\r
    0x01,\r
    L"Parallel port",\r
    PCIPIFClass_0701\r
  },\r
  {\r
    0x02,\r
    L"Multiport serial controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"Modem",\r
    PCIPIFClass_0703\r
  },\r
  {\r
    0x04,\r
    L"GPIB (IEEE 488.1/2) controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x05,\r
    L"Smart Card",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other communication device",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_08[] = {\r
  {\r
    0x00,\r
    L"PIC",\r
    PCIPIFClass_0800\r
  },\r
  {\r
    0x01,\r
    L"DMA controller",\r
    PCIPIFClass_0801\r
  },\r
  {\r
    0x02,\r
    L"System timer",\r
    PCIPIFClass_0802\r
  },\r
  {\r
    0x03,\r
    L"RTC controller",\r
    PCIPIFClass_0803\r
  },\r
  {\r
    0x04,\r
    L"Generic PCI Hot-Plug controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x05,\r
    L"SD Host controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x06,\r
    L"IOMMU",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x07,\r
    L"Root Complex Event Collector",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other system peripheral",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_09[] = {\r
  {\r
    0x00,\r
    L"Keyboard controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Digitizer (pen)",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"Mouse controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"Scanner controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"Gameport controller",\r
    PCIPIFClass_0904\r
  },\r
  {\r
    0x80,\r
    L"Other input controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_0a[] = {\r
  {\r
    0x00,\r
    L"Generic docking station",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other type of docking station",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_0b[] = {\r
  {\r
    0x00,\r
    L"386",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"486",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"Pentium",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x10,\r
    L"Alpha",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x20,\r
    L"PowerPC",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x30,\r
    L"MIPS",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x40,\r
    L"Co-processor",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other processor",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
  {\r
    0x00,\r
    L"IEEE 1394",\r
    PCIPIFClass_0c00\r
  },\r
  {\r
    0x01,\r
    L"ACCESS.bus",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"SSA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"USB",\r
    PCIPIFClass_0c03\r
  },\r
  {\r
    0x04,\r
    L"Fibre Channel",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x05,\r
    L"System Management Bus",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x06,\r
    L"InfiniBand",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x07,\r
    L"IPMI",\r
    PCIPIFClass_0c07\r
  },\r
  {\r
    0x08,\r
    L"SERCOS Interface Standard (IEC 61491)",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x09,\r
    L"CANbus",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other bus type",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_0d[] = {\r
  {\r
    0x00,\r
    L"iRDA compatible controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"",\r
    PCIPIFClass_0d01\r
  },\r
  {\r
    0x10,\r
    L"RF controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x11,\r
    L"Bluetooth",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x12,\r
    L"Broadband",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x20,\r
    L"Ethernet (802.11a - 5 GHz)",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x21,\r
    L"Ethernet (802.11b - 2.4 GHz)",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other type of wireless controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_0e[] = {\r
  {\r
    0x00,\r
    L"I2O Architecture",\r
    PCIPIFClass_0e00\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
  {\r
    0x01,\r
    L"TV",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"Audio",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"Voice",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"Data",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other satellite communication controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_10[] = {\r
  {\r
    0x00,\r
    L"Network & computing Encrypt/Decrypt",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Entertainment Encrypt/Decrypt",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other Encrypt/Decrypt",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_11[] = {\r
  {\r
    0x00,\r
    L"DPIO modules",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Performance Counters",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x10,\r
    L"Communications synchronization plus time and frequency test/measurement ",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x20,\r
    L"Management card",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Other DAQ & SP controllers",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_12[] = {\r
  {\r
    0x00,\r
    L"Processing Accelerator",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCISubClass_13[] = {\r
  {\r
    0x00,\r
    L"Non-Essential Instrumentation Function",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
//\r
// Programming Interface entries\r
//\r
PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r
  {\r
    0x00,\r
    L"SCSI controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x11,\r
    L"SCSI storage device SOP using PQI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x12,\r
    L"SCSI controller SOP using PQI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x13,\r
    L"SCSI storage device and controller SOP using PQI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x21,\r
    L"SCSI storage device SOP using NVMe",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"OM-primary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"PI-primary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"OM/PI-primary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x05,\r
    L"OM-primary, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x06,\r
    L"PI-primary, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x07,\r
    L"OM/PI-primary, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x08,\r
    L"OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x09,\r
    L"OM-primary, PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x0a,\r
    L"PI-primary, PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x0b,\r
    L"OM/PI-primary, PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x0c,\r
    L"OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x0d,\r
    L"OM-primary, OM/PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x0e,\r
    L"PI-primary, OM/PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x0f,\r
    L"OM/PI-primary, OM/PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Master",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x81,\r
    L"Master, OM-primary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x82,\r
    L"Master, PI-primary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x83,\r
    L"Master, OM/PI-primary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x84,\r
    L"Master, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x85,\r
    L"Master, OM-primary, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x86,\r
    L"Master, PI-primary, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x87,\r
    L"Master, OM/PI-primary, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x88,\r
    L"Master, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x89,\r
    L"Master, OM-primary, PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x8a,\r
    L"Master, PI-primary, PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x8b,\r
    L"Master, OM/PI-primary, PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x8c,\r
    L"Master, OM-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x8d,\r
    L"Master, OM-primary, OM/PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x8e,\r
    L"Master, PI-primary, OM/PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x8f,\r
    L"Master, OM/PI-primary, OM/PI-secondary",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r
  {\r
    0x20,\r
    L"Single stepping",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x30,\r
    L"Continuous operation",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"AHCI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"Serial Storage Bus",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Obsolete",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"NVMHCI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"NVM Express",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"UFSHCI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
  {\r
    0x00,\r
    L"VGA compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"8514 compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0604[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Subtractive decode",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r
  {\r
    0x40,\r
    L"Primary PCI bus side facing the system host processor",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"Secondary PCI bus side facing the system host processor",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r
  {\r
    0x00,\r
    L"Custom",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"ASI-SIG Defined Portal",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
  {\r
    0x00,\r
    L"Generic XT-compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"16450-compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"16550-compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"16650-compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"16750-compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x05,\r
    L"16850-compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x06,\r
    L"16950-compatible",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0701[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Bi-directional",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"ECP 1.X-compliant",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"IEEE 1284",\r
    PCIBlankEntry\r
  },\r
  {\r
    0xfe,\r
    L"IEEE 1284 target (not a controller)",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0703[] = {\r
  {\r
    0x00,\r
    L"Generic",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Hayes-compatible 16450",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"Hayes-compatible 16550",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x03,\r
    L"Hayes-compatible 16650",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x04,\r
    L"Hayes-compatible 16750",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0800[] = {\r
  {\r
    0x00,\r
    L"Generic 8259",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"ISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"EISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x10,\r
    L"IO APIC",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x20,\r
    L"IO(x) APIC interrupt controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0801[] = {\r
  {\r
    0x00,\r
    L"Generic 8237",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"ISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"EISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0802[] = {\r
  {\r
    0x00,\r
    L"Generic 8254",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"ISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"EISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0803[] = {\r
  {\r
    0x00,\r
    L"Generic",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"ISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"EISA",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0904[] = {\r
  {\r
    0x00,\r
    L"Generic",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x10,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
  {\r
    0x00,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x10,\r
    L"Using 1394 OpenHCI spec",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
  {\r
    0x00,\r
    L"UHCI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x10,\r
    L"OHCI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x20,\r
    L"EHCI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x30,\r
    L"xHCI",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x80,\r
    L"No specific programming interface",\r
    PCIBlankEntry\r
  },\r
  {\r
    0xfe,\r
    L"(Not Host Controller)",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r
  {\r
    0x00,\r
    L"SMIC",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"Keyboard Controller Style",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x02,\r
    L"Block Transfer",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r
  {\r
    0x00,\r
    L"Consumer IR controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x10,\r
    L"UWB Radio controller",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {\r
  {\r
    0x00,\r
    L"Message FIFO at offset 40h",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x01,\r
    L"",\r
    PCIBlankEntry\r
  },\r
  {\r
    0x00,\r
    NULL,\r
    /* null string ends the list */NULL\r
  }\r
};\r
\r
\r
/**\r
  Generates printable Unicode strings that represent PCI device class,\r
  subclass and programmed I/F based on a value passed to the function.\r
\r
  @param[in] ClassCode      Value representing the PCI "Class Code" register read from a\r
                 PCI device. The encodings are:\r
                     bits 23:16 - Base Class Code\r
                     bits 15:8  - Sub-Class Code\r
                     bits  7:0  - Programming Interface\r
  @param[in, out] ClassStrings   Pointer of PCI_CLASS_STRINGS structure, which contains\r
                 printable class strings corresponding to ClassCode. The\r
                 caller must not modify the strings that are pointed by\r
                 the fields in ClassStrings.\r
**/\r
VOID\r
PciGetClassStrings (\r
  IN      UINT32               ClassCode,\r
  IN OUT  PCI_CLASS_STRINGS    *ClassStrings\r
  )\r
{\r
  INTN            Index;\r
  UINT8           Code;\r
  PCI_CLASS_ENTRY *CurrentClass;\r
\r
  //\r
  // Assume no strings found\r
  //\r
  ClassStrings->BaseClass = L"UNDEFINED";\r
  ClassStrings->SubClass  = L"UNDEFINED";\r
  ClassStrings->PIFClass  = L"UNDEFINED";\r
\r
  CurrentClass = gClassStringList;\r
  Code = (UINT8) (ClassCode >> 16);\r
  Index = 0;\r
\r
  //\r
  // Go through all entries of the base class, until the entry with a matching\r
  // base class code is found. If reaches an entry with a null description\r
  // text, the last entry is met, which means no text for the base class was\r
  // found, so no more action is needed.\r
  //\r
  while (Code != CurrentClass[Index].Code) {\r
    if (NULL == CurrentClass[Index].DescText) {\r
      return ;\r
    }\r
\r
    Index++;\r
  }\r
  //\r
  // A base class was found. Assign description, and check if this class has\r
  // sub-class defined. If sub-class defined, no more action is needed,\r
  // otherwise, continue to find description for the sub-class code.\r
  //\r
  ClassStrings->BaseClass = CurrentClass[Index].DescText;\r
  if (NULL == CurrentClass[Index].LowerLevelClass) {\r
    return ;\r
  }\r
  //\r
  // find Subclass entry\r
  //\r
  CurrentClass  = CurrentClass[Index].LowerLevelClass;\r
  Code          = (UINT8) (ClassCode >> 8);\r
  Index         = 0;\r
\r
  //\r
  // Go through all entries of the sub-class, until the entry with a matching\r
  // sub-class code is found. If reaches an entry with a null description\r
  // text, the last entry is met, which means no text for the sub-class was\r
  // found, so no more action is needed.\r
  //\r
  while (Code != CurrentClass[Index].Code) {\r
    if (NULL == CurrentClass[Index].DescText) {\r
      return ;\r
    }\r
\r
    Index++;\r
  }\r
  //\r
  // A class was found for the sub-class code. Assign description, and check if\r
  // this sub-class has programming interface defined. If no, no more action is\r
  // needed, otherwise, continue to find description for the programming\r
  // interface.\r
  //\r
  ClassStrings->SubClass = CurrentClass[Index].DescText;\r
  if (NULL == CurrentClass[Index].LowerLevelClass) {\r
    return ;\r
  }\r
  //\r
  // Find programming interface entry\r
  //\r
  CurrentClass  = CurrentClass[Index].LowerLevelClass;\r
  Code          = (UINT8) ClassCode;\r
  Index         = 0;\r
\r
  //\r
  // Go through all entries of the I/F entries, until the entry with a\r
  // matching I/F code is found. If reaches an entry with a null description\r
  // text, the last entry is met, which means no text was found, so no more\r
  // action is needed.\r
  //\r
  while (Code != CurrentClass[Index].Code) {\r
    if (NULL == CurrentClass[Index].DescText) {\r
      return ;\r
    }\r
\r
    Index++;\r
  }\r
  //\r
  // A class was found for the I/F code. Assign description, done!\r
  //\r
  ClassStrings->PIFClass = CurrentClass[Index].DescText;\r
  return ;\r
}\r
\r
/**\r
  Print strings that represent PCI device class, subclass and programmed I/F.\r
\r
  @param[in] ClassCodePtr   Points to the memory which stores register Class Code in PCI\r
                            configuration space.\r
  @param[in] IncludePIF     If the printed string should include the programming I/F part\r
**/\r
VOID\r
PciPrintClassCode (\r
  IN      UINT8               *ClassCodePtr,\r
  IN      BOOLEAN             IncludePIF\r
  )\r
{\r
  UINT32            ClassCode;\r
  PCI_CLASS_STRINGS ClassStrings;\r
\r
  ClassCode = 0;\r
  ClassCode |= (UINT32)ClassCodePtr[0];\r
  ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r
  ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r
\r
  //\r
  // Get name from class code\r
  //\r
  PciGetClassStrings (ClassCode, &ClassStrings);\r
\r
  if (IncludePIF) {\r
    //\r
    // Print base class, sub class, and programming inferface name\r
    //\r
    ShellPrintEx (-1, -1, L"%s - %s - %s",\r
      ClassStrings.BaseClass,\r
      ClassStrings.SubClass,\r
      ClassStrings.PIFClass\r
     );\r
\r
  } else {\r
    //\r
    // Only print base class and sub class name\r
    //\r
    ShellPrintEx (-1, -1, L"%s - %s",\r
      ClassStrings.BaseClass,\r
      ClassStrings.SubClass\r
    );\r
  }\r
}\r
\r
/**\r
  This function finds out the protocol which is in charge of the given\r
  segment, and its bus range covers the current bus number. It lookes\r
  each instances of RootBridgeIoProtocol handle, until the one meets the\r
  criteria is found.\r
\r
  @param[in] HandleBuf       Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
  @param[in] HandleCount     Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
  @param[in] Segment         Segment number of device we are dealing with.\r
  @param[in] Bus             Bus number of device we are dealing with.\r
  @param[out] IoDev          Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS             The command completed successfully.\r
  @retval EFI_INVALID_PARAMETER   Invalid parameter.\r
\r
**/\r
EFI_STATUS\r
PciFindProtocolInterface (\r
  IN  EFI_HANDLE                            *HandleBuf,\r
  IN  UINTN                                 HandleCount,\r
  IN  UINT16                                Segment,\r
  IN  UINT16                                Bus,\r
  OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev\r
  );\r
\r
/**\r
  This function gets the protocol interface from the given handle, and\r
  obtains its address space descriptors.\r
\r
  @param[in] Handle          The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
  @param[out] IoDev          Handle used to access configuration space of PCI device.\r
  @param[out] Descriptors    Points to the address space descriptors.\r
\r
  @retval EFI_SUCCESS     The command completed successfully\r
**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
  IN  EFI_HANDLE                            Handle,\r
  OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev,\r
  OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     **Descriptors\r
  );\r
\r
/**\r
  This function get the next bus range of given address space descriptors.\r
  It also moves the pointer backward a node, to get prepared to be called\r
  again.\r
\r
  @param[in, out] Descriptors Points to current position of a serial of address space\r
                              descriptors.\r
  @param[out] MinBus          The lower range of bus number.\r
  @param[out] MaxBus          The upper range of bus number.\r
  @param[out] IsEnd           Meet end of the serial of descriptors.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciGetNextBusRange (\r
  IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  **Descriptors,\r
  OUT    UINT16                             *MinBus,\r
  OUT    UINT16                             *MaxBus,\r
  OUT    BOOLEAN                            *IsEnd\r
  );\r
\r
/**\r
  Explain the data in PCI configuration space. The part which is common for\r
  PCI device and bridge is interpreted in this function. It calls other\r
  functions to interpret data unique for device or bridge.\r
\r
  @param[in] ConfigSpace     Data in PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
  @param[in] EnhancedDump    The print format for the dump data.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainData (\r
  IN PCI_CONFIG_SPACE                       *ConfigSpace,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev,\r
  IN CONST UINT16                           EnhancedDump\r
  );\r
\r
/**\r
  Explain the device specific part of data in PCI configuration space.\r
\r
  @param[in] Device          Data in PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
  IN PCI_DEVICE_HEADER                      *Device,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev\r
  );\r
\r
/**\r
  Explain the bridge specific part of data in PCI configuration space.\r
\r
  @param[in] Bridge          Bridge specific data region in PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
  IN  PCI_BRIDGE_HEADER                     *Bridge,\r
  IN  UINT64                                Address,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *IoDev\r
  );\r
\r
/**\r
  Explain the Base Address Register(Bar) in PCI configuration space.\r
\r
  @param[in] Bar              Points to the Base Address Register intended to interpret.\r
  @param[in] Command          Points to the register Command.\r
  @param[in] Address          Address used to access configuration space of this PCI device.\r
  @param[in] IoDev            Handle used to access configuration space of PCI device.\r
  @param[in, out] Index       The Index.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainBar (\r
  IN UINT32                                 *Bar,\r
  IN UINT16                                 *Command,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev,\r
  IN OUT UINTN                              *Index\r
  );\r
\r
/**\r
  Explain the cardbus specific part of data in PCI configuration space.\r
\r
  @param[in] CardBus         CardBus specific region of PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
  IN PCI_CARDBUS_HEADER                     *CardBus,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev\r
  );\r
\r
/**\r
  Explain each meaningful bit of register Status. The definition of Status is\r
  slightly different depending on the PCI header type.\r
\r
  @param[in] Status          Points to the content of register Status.\r
  @param[in] MainStatus      Indicates if this register is main status(not secondary\r
                             status).\r
  @param[in] HeaderType      Header type of this PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainStatus (\r
  IN UINT16                                 *Status,\r
  IN BOOLEAN                                MainStatus,\r
  IN PCI_HEADER_TYPE                        HeaderType\r
  );\r
\r
/**\r
  Explain each meaningful bit of register Command.\r
\r
  @param[in] Command         Points to the content of register Command.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainCommand (\r
  IN UINT16                                 *Command\r
  );\r
\r
/**\r
  Explain each meaningful bit of register Bridge Control.\r
\r
  @param[in] BridgeControl   Points to the content of register Bridge Control.\r
  @param[in] HeaderType      The headertype.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
  IN UINT16                                 *BridgeControl,\r
  IN PCI_HEADER_TYPE                        HeaderType\r
  );\r
\r
/**\r
  Print each capability structure.\r
\r
  @param[in] IoDev            The pointer to the deivce.\r
  @param[in] Address          The address to start at.\r
  @param[in] CapPtr           The offset from the address.\r
  @param[in] EnhancedDump     The print format for the dump data.\r
\r
  @retval EFI_SUCCESS         The operation was successful.\r
**/\r
EFI_STATUS\r
PciExplainCapabilityStruct (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,\r
  IN UINT64                                   Address,\r
  IN  UINT8                                   CapPtr,\r
  IN CONST UINT16                            EnhancedDump\r
  );\r
\r
/**\r
  Display Pcie device structure.\r
\r
  @param[in] IoDev            The pointer to the root pci protocol.\r
  @param[in] Address          The Address to start at.\r
  @param[in] CapabilityPtr    The offset from the address to start.\r
  @param[in] EnhancedDump     The print format for the dump data.\r
  \r
  @retval EFI_SUCCESS           The command completed successfully.\r
  @retval @retval EFI_SUCCESS   Pci express extend space IO is not suppoted.   \r
**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,\r
  IN  UINT64                                  Address,\r
  IN  UINT8                                   CapabilityPtr,\r
  IN CONST UINT16                            EnhancedDump\r
  );\r
\r
/**\r
  Print out information of the capability information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device capability information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device control information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device link information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device link control information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device link status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device slot information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device slot control information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device slot status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device root information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device root capability information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
/**\r
  Print out information of the device root status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  );\r
\r
typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STRUCTURE *PciExpressCap);\r
\r
typedef enum {\r
  FieldWidthUINT8,\r
  FieldWidthUINT16,\r
  FieldWidthUINT32\r
} PCIE_CAPREG_FIELD_WIDTH;\r
\r
typedef enum {\r
  PcieExplainTypeCommon,\r
  PcieExplainTypeDevice,\r
  PcieExplainTypeLink,\r
  PcieExplainTypeSlot,\r
  PcieExplainTypeRoot,\r
  PcieExplainTypeMax\r
} PCIE_EXPLAIN_TYPE;\r
\r
typedef struct\r
{\r
  UINT16                  Token;\r
  UINTN                   Offset;\r
  PCIE_CAPREG_FIELD_WIDTH Width;\r
  PCIE_EXPLAIN_FUNCTION   Func;\r
  PCIE_EXPLAIN_TYPE       Type;\r
} PCIE_EXPLAIN_STRUCT;\r
\r
PCIE_EXPLAIN_STRUCT PcieExplainList[] = {\r
  {\r
    STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),\r
    0x00,\r
    FieldWidthUINT8,\r
    NULL,\r
    PcieExplainTypeCommon\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),\r
    0x01,\r
    FieldWidthUINT8,\r
    NULL,\r
    PcieExplainTypeCommon\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_CAP_REGISTER),\r
    0x02,\r
    FieldWidthUINT16,\r
    ExplainPcieCapReg,\r
    PcieExplainTypeCommon\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_DEVICE_CAP),\r
    0x04,\r
    FieldWidthUINT32,\r
    ExplainPcieDeviceCap,\r
    PcieExplainTypeDevice\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),\r
    0x08,\r
    FieldWidthUINT16,\r
    ExplainPcieDeviceControl,\r
    PcieExplainTypeDevice\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),\r
    0x0a,\r
    FieldWidthUINT16,\r
    ExplainPcieDeviceStatus,\r
    PcieExplainTypeDevice\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),\r
    0x0c,\r
    FieldWidthUINT32,\r
    ExplainPcieLinkCap,\r
    PcieExplainTypeLink\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_LINK_CONTROL),\r
    0x10,\r
    FieldWidthUINT16,\r
    ExplainPcieLinkControl,\r
    PcieExplainTypeLink\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_LINK_STATUS),\r
    0x12,\r
    FieldWidthUINT16,\r
    ExplainPcieLinkStatus,\r
    PcieExplainTypeLink\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),\r
    0x14,\r
    FieldWidthUINT32,\r
    ExplainPcieSlotCap,\r
    PcieExplainTypeSlot\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),\r
    0x18,\r
    FieldWidthUINT16,\r
    ExplainPcieSlotControl,\r
    PcieExplainTypeSlot\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_SLOT_STATUS),\r
    0x1a,\r
    FieldWidthUINT16,\r
    ExplainPcieSlotStatus,\r
    PcieExplainTypeSlot\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),\r
    0x1c,\r
    FieldWidthUINT16,\r
    ExplainPcieRootControl,\r
    PcieExplainTypeRoot\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_RSVDP),\r
    0x1e,\r
    FieldWidthUINT16,\r
    ExplainPcieRootCap,\r
    PcieExplainTypeRoot\r
  },\r
  {\r
    STRING_TOKEN (STR_PCIEX_ROOT_STATUS),\r
    0x20,\r
    FieldWidthUINT32,\r
    ExplainPcieRootStatus,\r
    PcieExplainTypeRoot\r
  },\r
  {\r
    0,\r
    0,\r
    (PCIE_CAPREG_FIELD_WIDTH)0,\r
    NULL,\r
    PcieExplainTypeMax\r
  }\r
};\r
\r
//\r
// Global Variables\r
//\r
PCI_CONFIG_SPACE  *mConfigSpace = NULL;\r
STATIC CONST SHELL_PARAM_ITEM ParamList[] = {\r
  {L"-s", TypeValue},\r
  {L"-i", TypeFlag},\r
  {L"-_e", TypeValue},\r
  {NULL, TypeMax}\r
  };\r
\r
CHAR16 *DevicePortTypeTable[] = {\r
  L"PCI Express Endpoint",\r
  L"Legacy PCI Express Endpoint",\r
  L"Unknown Type",\r
  L"Unknonw Type",\r
  L"Root Port of PCI Express Root Complex",\r
  L"Upstream Port of PCI Express Switch",\r
  L"Downstream Port of PCI Express Switch",\r
  L"PCI Express to PCI/PCI-X Bridge",\r
  L"PCI/PCI-X to PCI Express Bridge",\r
  L"Root Complex Integrated Endpoint",\r
  L"Root Complex Event Collector"\r
};\r
\r
CHAR16 *L0sLatencyStrTable[] = {\r
  L"Less than 64ns",\r
  L"64ns to less than 128ns",\r
  L"128ns to less than 256ns",\r
  L"256ns to less than 512ns",\r
  L"512ns to less than 1us",\r
  L"1us to less than 2us",\r
  L"2us-4us",\r
  L"More than 4us"\r
};\r
\r
CHAR16 *L1LatencyStrTable[] = {\r
  L"Less than 1us",\r
  L"1us to less than 2us",\r
  L"2us to less than 4us",\r
  L"4us to less than 8us",\r
  L"8us to less than 16us",\r
  L"16us to less than 32us",\r
  L"32us-64us",\r
  L"More than 64us"\r
};\r
\r
CHAR16 *ASPMCtrlStrTable[] = {\r
  L"Disabled",\r
  L"L0s Entry Enabled",\r
  L"L1 Entry Enabled",\r
  L"L0s and L1 Entry Enabled"\r
};\r
\r
CHAR16 *SlotPwrLmtScaleTable[] = {\r
  L"1.0x",\r
  L"0.1x",\r
  L"0.01x",\r
  L"0.001x"\r
};\r
\r
CHAR16 *IndicatorTable[] = {\r
  L"Reserved",\r
  L"On",\r
  L"Blink",\r
  L"Off"\r
};\r
\r
\r
/**\r
  Function for 'pci' command.\r
\r
  @param[in] ImageHandle  Handle to the Image (NULL if Internal).\r
  @param[in] SystemTable  Pointer to the System Table (NULL if Internal).\r
**/\r
SHELL_STATUS\r
EFIAPI\r
ShellCommandRunPci (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  UINT16                            Segment;\r
  UINT16                            Bus;\r
  UINT16                            Device;\r
  UINT16                            Func;\r
  UINT64                            Address;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL   *IoDev;\r
  EFI_STATUS                        Status;\r
  PCI_COMMON_HEADER                 PciHeader;\r
  PCI_CONFIG_SPACE                  ConfigSpace;\r
  UINTN                             ScreenCount;\r
  UINTN                             TempColumn;\r
  UINTN                             ScreenSize;\r
  BOOLEAN                           ExplainData;\r
  UINTN                             Index;\r
  UINTN                             SizeOfHeader;\r
  BOOLEAN                           PrintTitle;\r
  UINTN                             HandleBufSize;\r
  EFI_HANDLE                        *HandleBuf;\r
  UINTN                             HandleCount;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
  UINT16                            MinBus;\r
  UINT16                            MaxBus;\r
  BOOLEAN                           IsEnd;\r
  LIST_ENTRY                        *Package;\r
  CHAR16                            *ProblemParam;\r
  SHELL_STATUS                      ShellStatus;\r
  CONST CHAR16                      *Temp;\r
  UINT64                            RetVal;\r
  UINT16                            EnhancedDump;\r
\r
  ShellStatus         = SHELL_SUCCESS;\r
  Status              = EFI_SUCCESS;\r
  Address             = 0;\r
  IoDev               = NULL;\r
  HandleBuf           = NULL;\r
  Package             = NULL;\r
\r
  //\r
  // initialize the shell lib (we must be in non-auto-init...)\r
  //\r
  Status = ShellInitialize();\r
  ASSERT_EFI_ERROR(Status);\r
\r
  Status = CommandInit();\r
  ASSERT_EFI_ERROR(Status);\r
\r
  //\r
  // parse the command line\r
  //\r
  Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
  if (EFI_ERROR(Status)) {\r
    if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);  \r
      FreePool(ProblemParam);\r
      ShellStatus = SHELL_INVALID_PARAMETER;\r
    } else {\r
      ASSERT(FALSE);\r
    }\r
  } else {\r
\r
    if (ShellCommandLineGetCount(Package) == 2) {\r
      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");  \r
      ShellStatus = SHELL_INVALID_PARAMETER;\r
      goto Done;\r
    }\r
\r
    if (ShellCommandLineGetCount(Package) > 4) {\r
      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");  \r
      ShellStatus = SHELL_INVALID_PARAMETER;\r
      goto Done;\r
    }\r
    if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle,  L"pci", L"-s");  \r
      ShellStatus = SHELL_INVALID_PARAMETER;\r
      goto Done;\r
    }\r
    //\r
    // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and\r
    // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough\r
    // space for handles and call it again.\r
    //\r
    HandleBufSize = sizeof (EFI_HANDLE);\r
    HandleBuf     = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
    if (HandleBuf == NULL) {\r
      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");  \r
      ShellStatus = SHELL_OUT_OF_RESOURCES;\r
      goto Done;\r
    }\r
\r
    Status = gBS->LocateHandle (\r
                  ByProtocol,\r
                  &gEfiPciRootBridgeIoProtocolGuid,\r
                  NULL,\r
                  &HandleBufSize,\r
                  HandleBuf\r
                 );\r
\r
    if (Status == EFI_BUFFER_TOO_SMALL) {\r
      HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
      if (HandleBuf == NULL) {\r
        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");  \r
        ShellStatus = SHELL_OUT_OF_RESOURCES;\r
        goto Done;\r
      }\r
\r
      Status = gBS->LocateHandle (\r
                    ByProtocol,\r
                    &gEfiPciRootBridgeIoProtocolGuid,\r
                    NULL,\r
                    &HandleBufSize,\r
                    HandleBuf\r
                   );\r
    }\r
\r
    if (EFI_ERROR (Status)) {\r
      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");  \r
      ShellStatus = SHELL_NOT_FOUND;\r
      goto Done;\r
    }\r
\r
    HandleCount = HandleBufSize / sizeof (EFI_HANDLE);\r
    //\r
    // Argument Count == 1(no other argument): enumerate all pci functions\r
    //\r
    if (ShellCommandLineGetCount(Package) == 1) {\r
      gST->ConOut->QueryMode (\r
                    gST->ConOut,\r
                    gST->ConOut->Mode->Mode,\r
                    &TempColumn,\r
                    &ScreenSize\r
                   );\r
\r
      ScreenCount = 0;\r
      ScreenSize -= 4;\r
      if ((ScreenSize & 1) == 1) {\r
        ScreenSize -= 1;\r
      }\r
\r
      PrintTitle = TRUE;\r
\r
      //\r
      // For each handle, which decides a segment and a bus number range,\r
      // enumerate all devices on it.\r
      //\r
      for (Index = 0; Index < HandleCount; Index++) {\r
        Status = PciGetProtocolAndResource (\r
                  HandleBuf[Index],\r
                  &IoDev,\r
                  &Descriptors\r
                 );\r
        if (EFI_ERROR (Status)) {\r
          ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");  \r
          ShellStatus = SHELL_NOT_FOUND;\r
          goto Done;\r
        }\r
        //\r
        // No document say it's impossible for a RootBridgeIo protocol handle\r
        // to have more than one address space descriptors, so find out every\r
        // bus range and for each of them do device enumeration.\r
        //\r
        while (TRUE) {\r
          Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
\r
          if (EFI_ERROR (Status)) {\r
            ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");  \r
            ShellStatus = SHELL_NOT_FOUND;\r
            goto Done;\r
          }\r
\r
          if (IsEnd) {\r
            break;\r
          }\r
\r
          for (Bus = MinBus; Bus <= MaxBus; Bus++) {\r
            //\r
            // For each devices, enumerate all functions it contains\r
            //\r
            for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
              //\r
              // For each function, read its configuration space and print summary\r
              //\r
              for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
                if (ShellGetExecutionBreakFlag ()) {\r
                  ShellStatus = SHELL_ABORTED;\r
                  goto Done;\r
                }\r
                Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
                IoDev->Pci.Read (\r
                            IoDev,\r
                            EfiPciWidthUint16,\r
                            Address,\r
                            1,\r
                            &PciHeader.VendorId\r
                           );\r
\r
                //\r
                // If VendorId = 0xffff, there does not exist a device at this\r
                // location. For each device, if there is any function on it,\r
                // there must be 1 function at Function 0. So if Func = 0, there\r
                // will be no more functions in the same device, so we can break\r
                // loop to deal with the next device.\r
                //\r
                if (PciHeader.VendorId == 0xffff && Func == 0) {\r
                  break;\r
                }\r
\r
                if (PciHeader.VendorId != 0xffff) {\r
\r
                  if (PrintTitle) {\r
                    ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);\r
                    PrintTitle = FALSE;\r
                  }\r
\r
                  IoDev->Pci.Read (\r
                              IoDev,\r
                              EfiPciWidthUint32,\r
                              Address,\r
                              sizeof (PciHeader) / sizeof (UINT32),\r
                              &PciHeader\r
                             );\r
\r
                  ShellPrintHiiEx(\r
                    -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,\r
                    IoDev->SegmentNumber,\r
                    Bus,\r
                    Device,\r
                    Func\r
                   );\r
\r
                  PciPrintClassCode (PciHeader.ClassCode, FALSE);\r
                  ShellPrintHiiEx(\r
                    -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,\r
                    PciHeader.VendorId,\r
                    PciHeader.DeviceId,\r
                    PciHeader.ClassCode[0]\r
                   );\r
\r
                  ScreenCount += 2;\r
                  if (ScreenCount >= ScreenSize && ScreenSize != 0) {\r
                    //\r
                    // If ScreenSize == 0 we have the console redirected so don't\r
                    //  block updates\r
                    //\r
                    ScreenCount = 0;\r
                  }\r
                  //\r
                  // If this is not a multi-function device, we can leave the loop\r
                  // to deal with the next device.\r
                  //\r
                  if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {\r
                    break;\r
                  }\r
                }\r
              }\r
            }\r
          }\r
          //\r
          // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,\r
          // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all\r
          // devices on all bus, we can leave loop.\r
          //\r
          if (Descriptors == NULL) {\r
            break;\r
          }\r
        }\r
      }\r
\r
      Status = EFI_SUCCESS;\r
      goto Done;\r
    }\r
\r
    ExplainData                   = FALSE;\r
    Segment                       = 0;\r
    Bus                           = 0;\r
    Device                        = 0;\r
    Func                          = 0;\r
    if (ShellCommandLineGetFlag(Package, L"-i")) {\r
      ExplainData = TRUE;\r
    }\r
\r
    Temp = ShellCommandLineGetValue(Package, L"-s");\r
    if (Temp != NULL) {\r
      //\r
      // Input converted to hexadecimal number.\r
      //\r
      if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
        Segment = (UINT16) RetVal;\r
      } else {\r
        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
        ShellStatus = SHELL_INVALID_PARAMETER;\r
        goto Done;\r
      }\r
    }\r
\r
    //\r
    // The first Argument(except "-i") is assumed to be Bus number, second\r
    // to be Device number, and third to be Func number.\r
    //\r
    Temp = ShellCommandLineGetRawValue(Package, 1);\r
    if (Temp != NULL) {\r
      //\r
      // Input converted to hexadecimal number.\r
      //\r
      if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
        Bus = (UINT16) RetVal;\r
      } else {\r
        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
        ShellStatus = SHELL_INVALID_PARAMETER;\r
        goto Done;\r
      }\r
\r
      if (Bus > MAX_BUS_NUMBER) {\r
        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);  \r
        ShellStatus = SHELL_INVALID_PARAMETER;\r
        goto Done;\r
      }\r
    }\r
    Temp = ShellCommandLineGetRawValue(Package, 2);\r
    if (Temp != NULL) {\r
      //\r
      // Input converted to hexadecimal number.\r
      //\r
      if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
        Device = (UINT16) RetVal;\r
      } else {\r
        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
        ShellStatus = SHELL_INVALID_PARAMETER;\r
        goto Done;\r
      }\r
\r
      if (Device > MAX_DEVICE_NUMBER){\r
        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);  \r
        ShellStatus = SHELL_INVALID_PARAMETER;\r
        goto Done;\r
      }\r
    }\r
\r
    Temp = ShellCommandLineGetRawValue(Package, 3);\r
    if (Temp != NULL) {\r
      //\r
      // Input converted to hexadecimal number.\r
      //\r
      if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
        Func = (UINT16) RetVal;\r
      } else {\r
        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
        ShellStatus = SHELL_INVALID_PARAMETER;\r
        goto Done;\r
      }\r
\r
      if (Func > MAX_FUNCTION_NUMBER){\r
        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);  \r
        ShellStatus = SHELL_INVALID_PARAMETER;\r
        goto Done;\r
      }\r
    }\r
\r
    //\r
    // Find the protocol interface who's in charge of current segment, and its\r
    // bus range covers the current bus\r
    //\r
    Status = PciFindProtocolInterface (\r
              HandleBuf,\r
              HandleCount,\r
              Segment,\r
              Bus,\r
              &IoDev\r
             );\r
\r
    if (EFI_ERROR (Status)) {\r
      ShellPrintHiiEx(\r
        -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci",  \r
        Segment,\r
        Bus\r
       );\r
      ShellStatus = SHELL_NOT_FOUND;\r
      goto Done;\r
    }\r
\r
    Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);\r
    Status = IoDev->Pci.Read (\r
                          IoDev,\r
                          EfiPciWidthUint8,\r
                          Address,\r
                          sizeof (ConfigSpace),\r
                          &ConfigSpace\r
                         );\r
\r
    if (EFI_ERROR (Status)) {\r
      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");  \r
      ShellStatus = SHELL_ACCESS_DENIED;\r
      goto Done;\r
    }\r
\r
    mConfigSpace = &ConfigSpace;\r
    ShellPrintHiiEx(\r
      -1,\r
      -1,\r
      NULL,\r
      STRING_TOKEN (STR_PCI_INFO),\r
      gShellDebug1HiiHandle,\r
      Segment,\r
      Bus,\r
      Device,\r
      Func,\r
      Segment,\r
      Bus,\r
      Device,\r
      Func\r
     );\r
\r
    //\r
    // Dump standard header of configuration space\r
    //\r
    SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);\r
\r
    DumpHex (2, 0, SizeOfHeader, &ConfigSpace);\r
    ShellPrintEx(-1,-1, L"\r\n");\r
\r
    //\r
    // Dump device dependent Part of configuration space\r
    //\r
    DumpHex (\r
      2,\r
      SizeOfHeader,\r
      sizeof (ConfigSpace) - SizeOfHeader,\r
      ConfigSpace.Data\r
     );\r
\r
    //\r
    // If "-i" appears in command line, interpret data in configuration space\r
    //\r
    if (ExplainData) {\r
      EnhancedDump = 0;\r
      if (ShellCommandLineGetFlag(Package, L"-_e")) {\r
        EnhancedDump = 0xFFFF;\r
        Temp = ShellCommandLineGetValue(Package, L"-_e");\r
        if (Temp != NULL) {\r
          EnhancedDump = (UINT16) ShellHexStrToUintn (Temp);\r
        }\r
      }\r
      Status = PciExplainData (&ConfigSpace, Address, IoDev, EnhancedDump);\r
    }\r
  }\r
Done:\r
  if (HandleBuf != NULL) {\r
    FreePool (HandleBuf);\r
  }\r
  if (Package != NULL) {\r
    ShellCommandLineFreeVarList (Package);\r
  }\r
  mConfigSpace = NULL;\r
  return ShellStatus;\r
}\r
\r
/**\r
  This function finds out the protocol which is in charge of the given\r
  segment, and its bus range covers the current bus number. It lookes\r
  each instances of RootBridgeIoProtocol handle, until the one meets the\r
  criteria is found.\r
\r
  @param[in] HandleBuf       Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
  @param[in] HandleCount     Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.\r
  @param[in] Segment         Segment number of device we are dealing with.\r
  @param[in] Bus             Bus number of device we are dealing with.\r
  @param[out] IoDev          Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS             The command completed successfully.\r
  @retval EFI_INVALID_PARAMETER   Invalid parameter.\r
\r
**/\r
EFI_STATUS\r
PciFindProtocolInterface (\r
  IN  EFI_HANDLE                            *HandleBuf,\r
  IN  UINTN                                 HandleCount,\r
  IN  UINT16                                Segment,\r
  IN  UINT16                                Bus,\r
  OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev\r
  )\r
{\r
  UINTN                             Index;\r
  EFI_STATUS                        Status;\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
  UINT16                            MinBus;\r
  UINT16                            MaxBus;\r
  BOOLEAN                           IsEnd;\r
\r
  //\r
  // Go through all handles, until the one meets the criteria is found\r
  //\r
  for (Index = 0; Index < HandleCount; Index++) {\r
    Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    //\r
    // When Descriptors == NULL, the Configuration() is not implemented,\r
    // so we only check the Segment number\r
    //\r
    if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {\r
      return EFI_SUCCESS;\r
    }\r
\r
    if ((*IoDev)->SegmentNumber != Segment) {\r
      continue;\r
    }\r
\r
    while (TRUE) {\r
      Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
\r
      if (IsEnd) {\r
        break;\r
      }\r
\r
      if (MinBus <= Bus && MaxBus >= Bus) {\r
        return EFI_SUCCESS;\r
      }\r
    }\r
  }\r
\r
  return EFI_NOT_FOUND;\r
}\r
\r
/**\r
  This function gets the protocol interface from the given handle, and\r
  obtains its address space descriptors.\r
\r
  @param[in] Handle          The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.\r
  @param[out] IoDev          Handle used to access configuration space of PCI device.\r
  @param[out] Descriptors    Points to the address space descriptors.\r
\r
  @retval EFI_SUCCESS     The command completed successfully\r
**/\r
EFI_STATUS\r
PciGetProtocolAndResource (\r
  IN  EFI_HANDLE                            Handle,\r
  OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       **IoDev,\r
  OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     **Descriptors\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Get inferface from protocol\r
  //\r
  Status = gBS->HandleProtocol (\r
                Handle,\r
                &gEfiPciRootBridgeIoProtocolGuid,\r
                (VOID**)IoDev\r
               );\r
\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  //\r
  // Call Configuration() to get address space descriptors\r
  //\r
  Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);\r
  if (Status == EFI_UNSUPPORTED) {\r
    *Descriptors = NULL;\r
    return EFI_SUCCESS;\r
\r
  } else {\r
    return Status;\r
  }\r
}\r
\r
/**\r
  This function get the next bus range of given address space descriptors.\r
  It also moves the pointer backward a node, to get prepared to be called\r
  again.\r
\r
  @param[in, out] Descriptors Points to current position of a serial of address space\r
                              descriptors.\r
  @param[out] MinBus          The lower range of bus number.\r
  @param[out] MaxBus          The upper range of bus number.\r
  @param[out] IsEnd           Meet end of the serial of descriptors.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciGetNextBusRange (\r
  IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR  **Descriptors,\r
  OUT    UINT16                             *MinBus,\r
  OUT    UINT16                             *MaxBus,\r
  OUT    BOOLEAN                            *IsEnd\r
  )\r
{\r
  *IsEnd = FALSE;\r
\r
  //\r
  // When *Descriptors is NULL, Configuration() is not implemented, so assume\r
  // range is 0~PCI_MAX_BUS\r
  //\r
  if ((*Descriptors) == NULL) {\r
    *MinBus = 0;\r
    *MaxBus = PCI_MAX_BUS;\r
    return EFI_SUCCESS;\r
  }\r
  //\r
  // *Descriptors points to one or more address space descriptors, which\r
  // ends with a end tagged descriptor. Examine each of the descriptors,\r
  // if a bus typed one is found and its bus range covers bus, this handle\r
  // is the handle we are looking for.\r
  //\r
\r
  while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
    if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
      *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;\r
      *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;\r
      (*Descriptors)++;\r
      return (EFI_SUCCESS);\r
    }\r
\r
    (*Descriptors)++;\r
  }\r
\r
  if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {\r
    *IsEnd = TRUE;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Explain the data in PCI configuration space. The part which is common for\r
  PCI device and bridge is interpreted in this function. It calls other\r
  functions to interpret data unique for device or bridge.\r
\r
  @param[in] ConfigSpace     Data in PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
  @param[in] EnhancedDump    The print format for the dump data.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainData (\r
  IN PCI_CONFIG_SPACE                       *ConfigSpace,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev,\r
  IN CONST UINT16                           EnhancedDump\r
  )\r
{\r
  PCI_COMMON_HEADER *Common;\r
  PCI_HEADER_TYPE   HeaderType;\r
  EFI_STATUS        Status;\r
  UINT8             CapPtr;\r
\r
  Common = &(ConfigSpace->Common);\r
\r
  ShellPrintEx (-1, -1, L"\r\n");\r
\r
  //\r
  // Print Vendor Id and Device Id\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,\r
    INDEX_OF (&(Common->VendorId)),\r
    Common->VendorId,\r
    INDEX_OF (&(Common->DeviceId)),\r
    Common->DeviceId\r
   );\r
\r
  //\r
  // Print register Command\r
  //\r
  PciExplainCommand (&(Common->Command));\r
\r
  //\r
  // Print register Status\r
  //\r
  PciExplainStatus (&(Common->Status), TRUE, PciUndefined);\r
\r
  //\r
  // Print register Revision ID\r
  //\r
  ShellPrintEx(-1, -1, L"\r\n");\r
  ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,\r
    INDEX_OF (&(Common->RevisionId)),\r
    Common->RevisionId\r
   );\r
\r
  //\r
  // Print register BIST\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));\r
  if ((Common->Bist & PCI_BIT_7) != 0) {\r
    ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);\r
  }\r
  //\r
  // Print register Cache Line Size\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Common->CacheLineSize)),\r
    Common->CacheLineSize\r
   );\r
\r
  //\r
  // Print register Latency Timer\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_LATENCY_TIMER),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Common->PrimaryLatencyTimer)),\r
    Common->PrimaryLatencyTimer\r
   );\r
\r
  //\r
  // Print register Header Type\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_HEADER_TYPE),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Common->HeaderType)),\r
    Common->HeaderType\r
   );\r
\r
  if ((Common->HeaderType & PCI_BIT_7) != 0) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);\r
  }\r
\r
  HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);\r
  switch (HeaderType) {\r
  case PciDevice:\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);\r
    break;\r
\r
  case PciP2pBridge:\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);\r
    break;\r
\r
  case PciCardBusBridge:\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);\r
    break;\r
\r
  default:\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);\r
    HeaderType = PciUndefined;\r
  }\r
\r
  //\r
  // Print register Class Code\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);\r
  PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);\r
  ShellPrintEx (-1, -1, L"\r\n");\r
\r
  if (ShellGetExecutionBreakFlag()) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  //\r
  // Interpret remaining part of PCI configuration header depending on\r
  // HeaderType\r
  //\r
  CapPtr  = 0;\r
  Status  = EFI_SUCCESS;\r
  switch (HeaderType) {\r
  case PciDevice:\r
    Status = PciExplainDeviceData (\r
              &(ConfigSpace->NonCommon.Device),\r
              Address,\r
              IoDev\r
             );\r
    CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;\r
    break;\r
\r
  case PciP2pBridge:\r
    Status = PciExplainBridgeData (\r
              &(ConfigSpace->NonCommon.Bridge),\r
              Address,\r
              IoDev\r
             );\r
    CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;\r
    break;\r
\r
  case PciCardBusBridge:\r
    Status = PciExplainCardBusData (\r
              &(ConfigSpace->NonCommon.CardBus),\r
              Address,\r
              IoDev\r
             );\r
    CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;\r
    break;\r
  case PciUndefined:\r
  default:\r
    break;\r
  }\r
  //\r
  // If Status bit4 is 1, dump or explain capability structure\r
  //\r
  if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {\r
    PciExplainCapabilityStruct (IoDev, Address, CapPtr, EnhancedDump);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Explain the device specific part of data in PCI configuration space.\r
\r
  @param[in] Device          Data in PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainDeviceData (\r
  IN PCI_DEVICE_HEADER                      *Device,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev\r
  )\r
{\r
  UINTN       Index;\r
  BOOLEAN     BarExist;\r
  EFI_STATUS  Status;\r
  UINTN       BarCount;\r
\r
  //\r
  // Print Base Address Registers(Bar). When Bar = 0, this Bar does not\r
  // exist. If these no Bar for this function, print "none", otherwise\r
  // list detail information about this Bar.\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));\r
\r
  BarExist  = FALSE;\r
  BarCount  = sizeof (Device->Bar) / sizeof (Device->Bar[0]);\r
  for (Index = 0; Index < BarCount; Index++) {\r
    if (Device->Bar[Index] == 0) {\r
      continue;\r
    }\r
\r
    if (!BarExist) {\r
      BarExist = TRUE;\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);\r
      ShellPrintEx (-1, -1, L"  --------------------------------------------------------------------------");\r
    }\r
\r
    Status = PciExplainBar (\r
              &(Device->Bar[Index]),\r
              &(mConfigSpace->Common.Command),\r
              Address,\r
              IoDev,\r
              &Index\r
             );\r
\r
    if (EFI_ERROR (Status)) {\r
      break;\r
    }\r
  }\r
\r
  if (!BarExist) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
\r
  } else {\r
    ShellPrintEx (-1, -1, L"\r\n  --------------------------------------------------------------------------");\r
  }\r
\r
  //\r
  // Print register Expansion ROM Base Address\r
  //\r
  if ((Device->ROMBar & PCI_BIT_0) == 0) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),\r
      gShellDebug1HiiHandle,\r
      INDEX_OF (&(Device->ROMBar)),\r
      Device->ROMBar\r
     );\r
  }\r
  //\r
  // Print register Cardbus CIS ptr\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_CARDBUS_CIS),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->CardBusCISPtr)),\r
    Device->CardBusCISPtr\r
   );\r
\r
  //\r
  // Print register Sub-vendor ID and subsystem ID\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->SubVendorId)),\r
    Device->SubVendorId\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->SubSystemId)),\r
    Device->SubSystemId\r
   );\r
\r
  //\r
  // Print register Capabilities Ptr\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->CapabilitiesPtr)),\r
    Device->CapabilitiesPtr\r
   );\r
\r
  //\r
  // Print register Interrupt Line and interrupt pin\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->InterruptLine)),\r
    Device->InterruptLine\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->InterruptPin)),\r
    Device->InterruptPin\r
   );\r
\r
  //\r
  // Print register Min_Gnt and Max_Lat\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MIN_GNT),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->MinGnt)),\r
    Device->MinGnt\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MAX_LAT),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Device->MaxLat)),\r
    Device->MaxLat\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Explain the bridge specific part of data in PCI configuration space.\r
\r
  @param[in] Bridge          Bridge specific data region in PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainBridgeData (\r
  IN  PCI_BRIDGE_HEADER                     *Bridge,\r
  IN  UINT64                                Address,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL       *IoDev\r
  )\r
{\r
  UINTN       Index;\r
  BOOLEAN     BarExist;\r
  UINTN       BarCount;\r
  UINT32      IoAddress32;\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Print Base Address Registers. When Bar = 0, this Bar does not\r
  // exist. If these no Bar for this function, print "none", otherwise\r
  // list detail information about this Bar.\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));\r
\r
  BarExist  = FALSE;\r
  BarCount  = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);\r
\r
  for (Index = 0; Index < BarCount; Index++) {\r
    if (Bridge->Bar[Index] == 0) {\r
      continue;\r
    }\r
\r
    if (!BarExist) {\r
      BarExist = TRUE;\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);\r
      ShellPrintEx (-1, -1, L"  --------------------------------------------------------------------------");\r
    }\r
\r
    Status = PciExplainBar (\r
              &(Bridge->Bar[Index]),\r
              &(mConfigSpace->Common.Command),\r
              Address,\r
              IoDev,\r
              &Index\r
             );\r
\r
    if (EFI_ERROR (Status)) {\r
      break;\r
    }\r
  }\r
\r
  if (!BarExist) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);\r
  } else {\r
    ShellPrintEx (-1, -1, L"\r\n  --------------------------------------------------------------------------");\r
  }\r
\r
  //\r
  // Expansion register ROM Base Address\r
  //\r
  if ((Bridge->ROMBar & PCI_BIT_0) == 0) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),\r
      gShellDebug1HiiHandle,\r
      INDEX_OF (&(Bridge->ROMBar)),\r
      Bridge->ROMBar\r
     );\r
  }\r
  //\r
  // Print Bus Numbers(Primary, Secondary, and Subordinate\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_BUS_NUMBERS),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->PrimaryBus)),\r
    INDEX_OF (&(Bridge->SecondaryBus)),\r
    INDEX_OF (&(Bridge->SubordinateBus))\r
   );\r
\r
  ShellPrintEx (-1, -1, L"               ------------------------------------------------------\r\n");\r
\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);\r
\r
  //\r
  // Print register Secondary Latency Timer\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->SecondaryLatencyTimer)),\r
    Bridge->SecondaryLatencyTimer\r
   );\r
\r
  //\r
  // Print register Secondary Status\r
  //\r
  PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);\r
\r
  //\r
  // Print I/O and memory ranges this bridge forwards. There are 3 resource\r
  // types: I/O, memory, and pre-fetchable memory. For each resource type,\r
  // base and limit address are listed.\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);\r
  ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
  //\r
  // IO Base & Limit\r
  //\r
  IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);\r
  IoAddress32 &= 0xfffff000;\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_TWO_VARS),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->IoBase)),\r
    IoAddress32\r
   );\r
\r
  IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);\r
  IoAddress32 |= 0x00000fff;\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);\r
\r
  //\r
  // Memory Base & Limit\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MEMORY),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->MemoryBase)),\r
    (Bridge->MemoryBase << 16) & 0xfff00000\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_ONE_VAR),\r
    gShellDebug1HiiHandle,\r
    (Bridge->MemoryLimit << 16) | 0x000fffff\r
   );\r
\r
  //\r
  // Pre-fetch-able Memory Base & Limit\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_PREFETCHABLE),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->PrefetchableMemBase)),\r
    Bridge->PrefetchableBaseUpper,\r
    (Bridge->PrefetchableMemBase << 16) & 0xfff00000\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_TWO_VARS_2),\r
    gShellDebug1HiiHandle,\r
    Bridge->PrefetchableLimitUpper,\r
    (Bridge->PrefetchableMemLimit << 16) | 0x000fffff\r
   );\r
\r
  //\r
  // Print register Capabilities Pointer\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->CapabilitiesPtr)),\r
    Bridge->CapabilitiesPtr\r
   );\r
\r
  //\r
  // Print register Bridge Control\r
  //\r
  PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);\r
\r
  //\r
  // Print register Interrupt Line & PIN\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->InterruptLine)),\r
    Bridge->InterruptLine\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(Bridge->InterruptPin)),\r
    Bridge->InterruptPin\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Explain the Base Address Register(Bar) in PCI configuration space.\r
\r
  @param[in] Bar              Points to the Base Address Register intended to interpret.\r
  @param[in] Command          Points to the register Command.\r
  @param[in] Address          Address used to access configuration space of this PCI device.\r
  @param[in] IoDev            Handle used to access configuration space of PCI device.\r
  @param[in, out] Index       The Index.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainBar (\r
  IN UINT32                                 *Bar,\r
  IN UINT16                                 *Command,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev,\r
  IN OUT UINTN                              *Index\r
  )\r
{\r
  UINT16  OldCommand;\r
  UINT16  NewCommand;\r
  UINT64  Bar64;\r
  UINT32  OldBar32;\r
  UINT32  NewBar32;\r
  UINT64  OldBar64;\r
  UINT64  NewBar64;\r
  BOOLEAN IsMem;\r
  BOOLEAN IsBar32;\r
  UINT64  RegAddress;\r
\r
  IsBar32   = TRUE;\r
  Bar64     = 0;\r
  NewBar32  = 0;\r
  NewBar64  = 0;\r
\r
  //\r
  // According the bar type, list detail about this bar, for example: 32 or\r
  // 64 bits; pre-fetchable or not.\r
  //\r
  if ((*Bar & PCI_BIT_0) == 0) {\r
    //\r
    // This bar is of memory type\r
    //\r
    IsMem = TRUE;\r
\r
    if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);\r
\r
    } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {\r
      Bar64 = 0x0;\r
      CopyMem (&Bar64, Bar, sizeof (UINT64));\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);\r
      IsBar32 = FALSE;\r
      *Index += 1;\r
\r
    } else {\r
      //\r
      // Reserved\r
      //\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);\r
    }\r
\r
    if ((*Bar & PCI_BIT_3) == 0) {\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);\r
\r
    } else {\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);\r
    }\r
\r
  } else {\r
    //\r
    // This bar is of io type\r
    //\r
    IsMem = FALSE;\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);\r
    ShellPrintEx (-1, -1, L"I/O                               ");\r
  }\r
\r
  //\r
  // Get BAR length(or the amount of resource this bar demands for). To get\r
  // Bar length, first we should temporarily disable I/O and memory access\r
  // of this function(by set bits in the register Command), then write all\r
  // "1"s to this bar. The bar value read back is the amount of resource\r
  // this bar demands for.\r
  //\r
  //\r
  // Disable io & mem access\r
  //\r
  OldCommand  = *Command;\r
  NewCommand  = (UINT16) (OldCommand & 0xfffc);\r
  RegAddress  = Address | INDEX_OF (Command);\r
  IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);\r
\r
  RegAddress = Address | INDEX_OF (Bar);\r
\r
  //\r
  // Read after write the BAR to get the size\r
  //\r
  if (IsBar32) {\r
    OldBar32  = *Bar;\r
    NewBar32  = 0xffffffff;\r
\r
    IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
    IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);\r
    IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);\r
\r
    if (IsMem) {\r
      NewBar32  = NewBar32 & 0xfffffff0;\r
      NewBar32  = (~NewBar32) + 1;\r
\r
    } else {\r
      NewBar32  = NewBar32 & 0xfffffffc;\r
      NewBar32  = (~NewBar32) + 1;\r
      NewBar32  = NewBar32 & 0x0000ffff;\r
    }\r
  } else {\r
\r
    OldBar64 = 0x0;\r
    CopyMem (&OldBar64, Bar, sizeof (UINT64));\r
    NewBar64 = 0xffffffffffffffffULL;\r
\r
    IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
    IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);\r
    IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);\r
\r
    if (IsMem) {\r
      NewBar64  = NewBar64 & 0xfffffffffffffff0ULL;\r
      NewBar64  = (~NewBar64) + 1;\r
\r
    } else {\r
      NewBar64  = NewBar64 & 0xfffffffffffffffcULL;\r
      NewBar64  = (~NewBar64) + 1;\r
      NewBar64  = NewBar64 & 0x000000000000ffff;\r
    }\r
  }\r
  //\r
  // Enable io & mem access\r
  //\r
  RegAddress = Address | INDEX_OF (Command);\r
  IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);\r
\r
  if (IsMem) {\r
    if (IsBar32) {\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);\r
\r
    } else {\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);\r
      ShellPrintEx (-1, -1, L"  ");\r
      ShellPrintHiiEx(-1, -1, NULL,\r
        STRING_TOKEN (STR_PCI2_RSHIFT),\r
        gShellDebug1HiiHandle,\r
        (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)\r
       );\r
      ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));\r
\r
    }\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Explain the cardbus specific part of data in PCI configuration space.\r
\r
  @param[in] CardBus         CardBus specific region of PCI configuration space.\r
  @param[in] Address         Address used to access configuration space of this PCI device.\r
  @param[in] IoDev           Handle used to access configuration space of PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainCardBusData (\r
  IN PCI_CARDBUS_HEADER                     *CardBus,\r
  IN UINT64                                 Address,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *IoDev\r
  )\r
{\r
  BOOLEAN           Io32Bit;\r
  PCI_CARDBUS_DATA  *CardBusData;\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->CardBusSocketReg)),\r
    CardBus->CardBusSocketReg\r
   );\r
\r
  //\r
  // Print Secondary Status\r
  //\r
  PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);\r
\r
  //\r
  // Print Bus Numbers(Primary bus number, CardBus bus number, and\r
  // Subordinate bus number\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->PciBusNumber)),\r
    INDEX_OF (&(CardBus->CardBusBusNumber)),\r
    INDEX_OF (&(CardBus->SubordinateBusNumber))\r
   );\r
\r
  ShellPrintEx (-1, -1, L"               ------------------------------------------------------\r\n");\r
\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);\r
\r
  //\r
  // Print CardBus Latency Timer\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->CardBusLatencyTimer)),\r
    CardBus->CardBusLatencyTimer\r
   );\r
\r
  //\r
  // Print Memory/Io ranges this cardbus bridge forwards\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);\r
  ShellPrintEx (-1, -1, L"----------------------------------------------------------------------\r\n");\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MEM_3),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->MemoryBase0)),\r
    CardBus->BridgeControl & PCI_BIT_8 ? L"    Prefetchable" : L"Non-Prefetchable",\r
    CardBus->MemoryBase0 & 0xfffff000,\r
    CardBus->MemoryLimit0 | 0x00000fff\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MEM_3),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->MemoryBase1)),\r
    CardBus->BridgeControl & PCI_BIT_9 ? L"    Prefetchable" : L"Non-Prefetchable",\r
    CardBus->MemoryBase1 & 0xfffff000,\r
    CardBus->MemoryLimit1 | 0x00000fff\r
   );\r
\r
  Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_IO_2),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->IoBase0)),\r
    Io32Bit ? L"          32 bit" : L"          16 bit",\r
    CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
    (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
   );\r
\r
  Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_IO_2),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->IoBase1)),\r
    Io32Bit ? L"          32 bit" : L"          16 bit",\r
    CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),\r
    (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003\r
   );\r
\r
  //\r
  // Print register Interrupt Line & PIN\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBus->InterruptLine)),\r
    CardBus->InterruptLine,\r
    INDEX_OF (&(CardBus->InterruptPin)),\r
    CardBus->InterruptPin\r
   );\r
\r
  //\r
  // Print register Bridge Control\r
  //\r
  PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);\r
\r
  //\r
  // Print some registers in data region of PCI configuration space for cardbus\r
  // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base\r
  // Address.\r
  //\r
  CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBusData->SubVendorId)),\r
    CardBusData->SubVendorId,\r
    INDEX_OF (&(CardBusData->SubSystemId)),\r
    CardBusData->SubSystemId\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_OPTIONAL),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (&(CardBusData->LegacyBase)),\r
    CardBusData->LegacyBase\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Explain each meaningful bit of register Status. The definition of Status is\r
  slightly different depending on the PCI header type.\r
\r
  @param[in] Status          Points to the content of register Status.\r
  @param[in] MainStatus      Indicates if this register is main status(not secondary\r
                             status).\r
  @param[in] HeaderType      Header type of this PCI device.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainStatus (\r
  IN UINT16                                 *Status,\r
  IN BOOLEAN                                MainStatus,\r
  IN PCI_HEADER_TYPE                        HeaderType\r
  )\r
{\r
  if (MainStatus) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);\r
  }\r
\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);\r
\r
  //\r
  // Bit 5 is meaningless for CardBus Bridge\r
  //\r
  if (HeaderType == PciCardBusBridge) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);\r
  }\r
\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);\r
\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);\r
  //\r
  // Bit 9 and bit 10 together decides the DEVSEL timing\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);\r
  if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);\r
\r
  } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);\r
\r
  } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);\r
  }\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),\r
    gShellDebug1HiiHandle,\r
    (*Status & PCI_BIT_11) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),\r
    gShellDebug1HiiHandle,\r
    (*Status & PCI_BIT_12) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),\r
    gShellDebug1HiiHandle,\r
    (*Status & PCI_BIT_13) != 0\r
   );\r
\r
  if (MainStatus) {\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),\r
      gShellDebug1HiiHandle,\r
      (*Status & PCI_BIT_14) != 0\r
     );\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),\r
      gShellDebug1HiiHandle,\r
      (*Status & PCI_BIT_14) != 0\r
     );\r
  }\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_DETECTED_ERROR),\r
    gShellDebug1HiiHandle,\r
    (*Status & PCI_BIT_15) != 0\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Explain each meaningful bit of register Command.\r
\r
  @param[in] Command         Points to the content of register Command.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainCommand (\r
  IN UINT16                                 *Command\r
  )\r
{\r
  //\r
  // Print the binary value of register Command\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);\r
\r
  //\r
  // Explain register Command bit by bit\r
  //\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_0) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MEMORY_SPACE),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_1) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_2) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_3) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_4) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_5) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_ASSERT_PERR),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_6) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_7) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SERR_DRIVER),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_8) != 0\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_FAST_BACK_2),\r
    gShellDebug1HiiHandle,\r
    (*Command & PCI_BIT_9) != 0\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Explain each meaningful bit of register Bridge Control.\r
\r
  @param[in] BridgeControl   Points to the content of register Bridge Control.\r
  @param[in] HeaderType      The headertype.\r
\r
  @retval EFI_SUCCESS     The command completed successfully.\r
**/\r
EFI_STATUS\r
PciExplainBridgeControl (\r
  IN UINT16                                 *BridgeControl,\r
  IN PCI_HEADER_TYPE                        HeaderType\r
  )\r
{\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),\r
    gShellDebug1HiiHandle,\r
    INDEX_OF (BridgeControl),\r
    *BridgeControl\r
   );\r
\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_PARITY_ERROR),\r
    gShellDebug1HiiHandle,\r
    (*BridgeControl & PCI_BIT_0) != 0\r
   );\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_SERR_ENABLE),\r
    gShellDebug1HiiHandle,\r
    (*BridgeControl & PCI_BIT_1) != 0\r
   );\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_ISA_ENABLE),\r
    gShellDebug1HiiHandle,\r
    (*BridgeControl & PCI_BIT_2) != 0\r
   );\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_VGA_ENABLE),\r
    gShellDebug1HiiHandle,\r
    (*BridgeControl & PCI_BIT_3) != 0\r
   );\r
  ShellPrintHiiEx(-1, -1, NULL,\r
    STRING_TOKEN (STR_PCI2_MASTER_ABORT),\r
    gShellDebug1HiiHandle,\r
    (*BridgeControl & PCI_BIT_5) != 0\r
   );\r
\r
  //\r
  // Register Bridge Control has some slight differences between P2P bridge\r
  // and Cardbus bridge from bit 6 to bit 11.\r
  //\r
  if (HeaderType == PciP2pBridge) {\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_6) != 0\r
     );\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_FAST_ENABLE),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_7) != 0\r
     );\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"\r
     );\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"\r
     );\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_10) != 0\r
     );\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_11) != 0\r
     );\r
\r
  } else {\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_CARDBUS_RESET),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_6) != 0\r
     );\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_IREQ_ENABLE),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_7) != 0\r
     );\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),\r
      gShellDebug1HiiHandle,\r
      (*BridgeControl & PCI_BIT_10) != 0\r
     );\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print each capability structure.\r
\r
  @param[in] IoDev            The pointer to the deivce.\r
  @param[in] Address          The address to start at.\r
  @param[in] CapPtr           The offset from the address.\r
  @param[in] EnhancedDump     The print format for the dump data.\r
\r
  @retval EFI_SUCCESS     The operation was successful.\r
**/\r
EFI_STATUS\r
PciExplainCapabilityStruct (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,\r
  IN UINT64                                   Address,\r
  IN  UINT8                                   CapPtr,\r
  IN CONST UINT16                            EnhancedDump\r
  )\r
{\r
  UINT8   CapabilityPtr;\r
  UINT16  CapabilityEntry;\r
  UINT8   CapabilityID;\r
  UINT64  RegAddress;\r
\r
  CapabilityPtr = CapPtr;\r
\r
  //\r
  // Go through the Capability list\r
  //\r
  while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
    RegAddress = Address + CapabilityPtr;\r
    IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);\r
\r
    CapabilityID = (UINT8) CapabilityEntry;\r
\r
    //\r
    // Explain PciExpress data\r
    //\r
    if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {\r
      PciExplainPciExpress (IoDev, Address, CapabilityPtr, EnhancedDump);\r
      return EFI_SUCCESS;\r
    }\r
    //\r
    // Explain other capabilities here\r
    //\r
    CapabilityPtr = (UINT8) (CapabilityEntry >> 8);\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the capability information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieCapReg;\r
  CHAR16 *DevicePortType;\r
\r
  PcieCapReg = PciExpressCap->PcieCapReg;\r
  ShellPrintEx (-1, -1,\r
    L"  Capability Version(3:0):          %E0x%04x%N\r\n",\r
    PCIE_CAP_VERSION (PcieCapReg)\r
   );\r
  if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {\r
    DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];\r
  } else {\r
    DevicePortType = L"Unknown Type";\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Device/PortType(7:4):             %E%s%N\r\n",\r
    DevicePortType\r
   );\r
  //\r
  // 'Slot Implemented' is only valid for:\r
  // a) Root Port of PCI Express Root Complex, or\r
  // b) Downstream Port of PCI Express Switch\r
  //\r
  if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||\r
      PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {\r
    ShellPrintEx (-1, -1,\r
      L"  Slot Implemented(8):              %E%d%N\r\n",\r
      PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)\r
     );\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Interrupt Message Number(13:9):   %E0x%05x%N\r\n",\r
    PCIE_CAP_INT_MSG_NUM (PcieCapReg)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device capability information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieCapReg;\r
  UINT32 PcieDeviceCap;\r
  UINT8  DevicePortType;\r
  UINT8  L0sLatency;\r
  UINT8  L1Latency;\r
\r
  PcieCapReg     = PciExpressCap->PcieCapReg;\r
  PcieDeviceCap  = PciExpressCap->PcieDeviceCap;\r
  DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);\r
  ShellPrintEx (-1, -1, L"  Max_Payload_Size Supported(2:0):          ");\r
  if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {\r
    ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));\r
  } else {\r
    ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Phantom Functions Supported(4:3):         %E%d%N\r\n",\r
    PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Extended Tag Field Supported(5):          %E%d-bit Tag field supported%N\r\n",\r
    PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5\r
   );\r
  //\r
  // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint\r
  //\r
  if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
    L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);\r
    L1Latency  = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);\r
    ShellPrintEx (-1, -1, L"  Endpoint L0s Acceptable Latency(8:6):     ");\r
    if (L0sLatency < 4) {\r
      ShellPrintEx (-1, -1, L"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency + 6));\r
    } else {\r
      if (L0sLatency < 7) {\r
        ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L0sLatency - 3));\r
      } else {\r
        ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
      }\r
    }\r
    ShellPrintEx (-1, -1, L"  Endpoint L1 Acceptable Latency(11:9):     ");\r
    if (L1Latency < 7) {\r
      ShellPrintEx (-1, -1, L"%EMaximum of %d us%N\r\n", 1 << (L1Latency + 1));\r
    } else {\r
      ShellPrintEx (-1, -1, L"%ENo limit%N\r\n");\r
    }\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Role-based Error Reporting(15):           %E%d%N\r\n",\r
    PCIE_CAP_ERR_REPORTING (PcieDeviceCap)\r
   );\r
  //\r
  // Only valid for Upstream Port:\r
  // a) Captured Slot Power Limit Value\r
  // b) Captured Slot Power Scale\r
  //\r
  if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {\r
    ShellPrintEx (-1, -1,\r
      L"  Captured Slot Power Limit Value(25:18):   %E0x%02x%N\r\n",\r
      PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)\r
     );\r
    ShellPrintEx (-1, -1,\r
      L"  Captured Slot Power Limit Scale(27:26):   %E%s%N\r\n",\r
      SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]\r
     );\r
  }\r
  //\r
  // Function Level Reset Capability is only valid for Endpoint\r
  //\r
  if (IS_PCIE_ENDPOINT (DevicePortType)) {\r
    ShellPrintEx (-1, -1,\r
      L"  Function Level Reset Capability(28):      %E%d%N\r\n",\r
      PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)\r
     );\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device control information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieCapReg;\r
  UINT16 PcieDeviceControl;\r
\r
  PcieCapReg        = PciExpressCap->PcieCapReg;\r
  PcieDeviceControl = PciExpressCap->DeviceControl;\r
  ShellPrintEx (-1, -1,\r
    L"  Correctable Error Reporting Enable(0):    %E%d%N\r\n",\r
    PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Non-Fatal Error Reporting Enable(1):      %E%d%N\r\n",\r
    PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Fatal Error Reporting Enable(2):          %E%d%N\r\n",\r
    PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Unsupported Request Reporting Enable(3):  %E%d%N\r\n",\r
    PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Enable Relaxed Ordering(4):               %E%d%N\r\n",\r
    PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1, L"  Max_Payload_Size(7:5):                    ");\r
  if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {\r
    ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));\r
  } else {\r
    ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Extended Tag Field Enable(8):             %E%d%N\r\n",\r
    PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Phantom Functions Enable(9):              %E%d%N\r\n",\r
    PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Auxiliary (AUX) Power PM Enable(10):      %E%d%N\r\n",\r
    PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Enable No Snoop(11):                      %E%d%N\r\n",\r
    PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)\r
   );\r
  ShellPrintEx (-1, -1, L"  Max_Read_Request_Size(14:12):             ");\r
  if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {\r
    ShellPrintEx (-1, -1, L"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));\r
  } else {\r
    ShellPrintEx (-1, -1, L"%EUnknown%N\r\n");\r
  }\r
  //\r
  // Read operation is only valid for PCI Express to PCI/PCI-X Bridges\r
  //\r
  if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {\r
    ShellPrintEx (-1, -1,\r
      L"  Bridge Configuration Retry Enable(15):  %E%d%N\r\n",\r
      PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)\r
     );\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieDeviceStatus;\r
\r
  PcieDeviceStatus = PciExpressCap->DeviceStatus;\r
  ShellPrintEx (-1, -1,\r
    L"  Correctable Error Detected(0):            %E%d%N\r\n",\r
    PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Non-Fatal Error Detected(1):              %E%d%N\r\n",\r
    PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Fatal Error Detected(2):                  %E%d%N\r\n",\r
    PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Unsupported Request Detected(3):          %E%d%N\r\n",\r
    PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  AUX Power Detected(4):                    %E%d%N\r\n",\r
    PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Transactions Pending(5):                  %E%d%N\r\n",\r
    PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device link information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT32 PcieLinkCap;\r
  CHAR16 *MaxLinkSpeed;\r
  CHAR16 *AspmValue;\r
\r
  PcieLinkCap = PciExpressCap->LinkCap;\r
  switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {\r
    case 1:\r
      MaxLinkSpeed = L"2.5 GT/s";\r
      break;\r
    case 2:\r
      MaxLinkSpeed = L"5.0 GT/s";\r
      break;\r
    case 3:\r
      MaxLinkSpeed = L"8.0 GT/s";\r
      break;\r
    default:\r
      MaxLinkSpeed = L"Unknown";\r
      break;\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Maximum Link Speed(3:0):                            %E%s%N\r\n",\r
    MaxLinkSpeed\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Maximum Link Width(9:4):                            %Ex%d%N\r\n",\r
    PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)\r
   );\r
  switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {\r
    case 0:\r
      AspmValue = L"Not";\r
      break;\r
    case 1:\r
      AspmValue = L"L0s";\r
      break;\r
    case 2:\r
      AspmValue = L"L1";\r
      break;\r
    case 3:\r
      AspmValue = L"L0s and L1";\r
      break;\r
    default:\r
      AspmValue = L"Reserved";\r
      break;\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Active State Power Management Support(11:10):       %E%s Supported%N\r\n",\r
    AspmValue\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  L0s Exit Latency(14:12):                            %E%s%N\r\n",\r
    L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  L1 Exit Latency(17:15):                             %E%s%N\r\n",\r
    L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Clock Power Management(18):                         %E%d%N\r\n",\r
    PCIE_CAP_CLOCK_PM (PcieLinkCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Surprise Down Error Reporting Capable(19):          %E%d%N\r\n",\r
    PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Data Link Layer Link Active Reporting Capable(20):  %E%d%N\r\n",\r
    PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Link Bandwidth Notification Capability(21):         %E%d%N\r\n",\r
    PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Port Number(31:24):                                 %E0x%02x%N\r\n",\r
    PCIE_CAP_PORT_NUMBER (PcieLinkCap)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device link control information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieLinkControl;\r
  UINT8  DevicePortType;\r
\r
  PcieLinkControl = PciExpressCap->LinkControl;\r
  DevicePortType  = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);\r
  ShellPrintEx (-1, -1,\r
    L"  Active State Power Management Control(1:0):         %E%s%N\r\n",\r
    ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]\r
   );\r
  //\r
  // RCB is not applicable to switches\r
  //\r
  if (!IS_PCIE_SWITCH(DevicePortType)) {\r
    ShellPrintEx (-1, -1,\r
      L"  Read Completion Boundary (RCB)(3):                  %E%d byte%N\r\n",\r
      1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)\r
     );\r
  }\r
  //\r
  // Link Disable is reserved on\r
  // a) Endpoints\r
  // b) PCI Express to PCI/PCI-X bridges\r
  // c) Upstream Ports of Switches\r
  //\r
  if (!IS_PCIE_ENDPOINT (DevicePortType) &&\r
      DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&\r
      DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {\r
    ShellPrintEx (-1, -1,\r
      L"  Link Disable(4):                                    %E%d%N\r\n",\r
      PCIE_CAP_LINK_DISABLE (PcieLinkControl)\r
     );\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Common Clock Configuration(6):                      %E%d%N\r\n",\r
    PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Extended Synch(7):                                  %E%d%N\r\n",\r
    PCIE_CAP_EXT_SYNC (PcieLinkControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Enable Clock Power Management(8):                   %E%d%N\r\n",\r
    PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Hardware Autonomous Width Disable(9):               %E%d%N\r\n",\r
    PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Link Bandwidth Management Interrupt Enable(10):     %E%d%N\r\n",\r
    PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Link Autonomous Bandwidth Interrupt Enable(11):     %E%d%N\r\n",\r
    PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device link status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieLinkStatus;\r
  CHAR16 *CurLinkSpeed;\r
\r
  PcieLinkStatus = PciExpressCap->LinkStatus;\r
  switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {\r
    case 1:\r
      CurLinkSpeed = L"2.5 GT/s";\r
      break;\r
    case 2:\r
      CurLinkSpeed = L"5.0 GT/s";\r
      break;\r
    case 3:\r
      CurLinkSpeed = L"8.0 GT/s";\r
      break;\r
    default:\r
      CurLinkSpeed = L"Reserved";\r
      break;\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Current Link Speed(3:0):                            %E%s%N\r\n",\r
    CurLinkSpeed\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Negotiated Link Width(9:4):                         %Ex%d%N\r\n",\r
    PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Link Training(11):                                  %E%d%N\r\n",\r
    PCIE_CAP_LINK_TRAINING (PcieLinkStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Slot Clock Configuration(12):                       %E%d%N\r\n",\r
    PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Data Link Layer Link Active(13):                    %E%d%N\r\n",\r
    PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Link Bandwidth Management Status(14):               %E%d%N\r\n",\r
    PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Link Autonomous Bandwidth Status(15):               %E%d%N\r\n",\r
    PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device slot information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT32 PcieSlotCap;\r
\r
  PcieSlotCap = PciExpressCap->SlotCap;\r
\r
  ShellPrintEx (-1, -1,\r
    L"  Attention Button Present(0):                        %E%d%N\r\n",\r
    PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Power Controller Present(1):                        %E%d%N\r\n",\r
    PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  MRL Sensor Present(2):                              %E%d%N\r\n",\r
    PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Attention Indicator Present(3):                     %E%d%N\r\n",\r
    PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Power Indicator Present(4):                         %E%d%N\r\n",\r
    PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Hot-Plug Surprise(5):                               %E%d%N\r\n",\r
    PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Hot-Plug Capable(6):                                %E%d%N\r\n",\r
    PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Slot Power Limit Value(14:7):                       %E0x%02x%N\r\n",\r
    PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Slot Power Limit Scale(16:15):                      %E%s%N\r\n",\r
    SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Electromechanical Interlock Present(17):            %E%d%N\r\n",\r
    PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  No Command Completed Support(18):                   %E%d%N\r\n",\r
    PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Physical Slot Number(31:19):                        %E%d%N\r\n",\r
    PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device slot control information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieSlotControl;\r
\r
  PcieSlotControl = PciExpressCap->SlotControl;\r
  ShellPrintEx (-1, -1,\r
    L"  Attention Button Pressed Enable(0):                 %E%d%N\r\n",\r
    PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Power Fault Detected Enable(1):                     %E%d%N\r\n",\r
    PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  MRL Sensor Changed Enable(2):                       %E%d%N\r\n",\r
    PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Presence Detect Changed Enable(3):                  %E%d%N\r\n",\r
    PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Command Completed Interrupt Enable(4):              %E%d%N\r\n",\r
    PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Hot-Plug Interrupt Enable(5):                       %E%d%N\r\n",\r
    PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Attention Indicator Control(7:6):                   %E%s%N\r\n",\r
    IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Power Indicator Control(9:8):                       %E%s%N\r\n",\r
    IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]\r
   );\r
  ShellPrintEx (-1, -1, L"  Power Controller Control(10):                       %EPower ");\r
  if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {\r
    ShellPrintEx (-1, -1, L"Off%N\r\n");\r
  } else {\r
    ShellPrintEx (-1, -1, L"On%N\r\n");\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Electromechanical Interlock Control(11):            %E%d%N\r\n",\r
    PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Data Link Layer State Changed Enable(12):           %E%d%N\r\n",\r
    PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device slot status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieSlotStatus;\r
\r
  PcieSlotStatus = PciExpressCap->SlotStatus;\r
\r
  ShellPrintEx (-1, -1,\r
    L"  Attention Button Pressed(0):           %E%d%N\r\n",\r
    PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Power Fault Detected(1):               %E%d%N\r\n",\r
    PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  MRL Sensor Changed(2):                 %E%d%N\r\n",\r
    PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Presence Detect Changed(3):            %E%d%N\r\n",\r
    PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  Command Completed(4):                  %E%d%N\r\n",\r
    PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)\r
   );\r
  ShellPrintEx (-1, -1, L"  MRL Sensor State(5):                   %EMRL ");\r
  if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {\r
    ShellPrintEx (-1, -1, L" Opened%N\r\n");\r
  } else {\r
    ShellPrintEx (-1, -1, L" Closed%N\r\n");\r
  }\r
  ShellPrintEx (-1, -1, L"  Presence Detect State(6):              ");\r
  if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {\r
    ShellPrintEx (-1, -1, L"%ECard Present in slot%N\r\n");\r
  } else {\r
    ShellPrintEx (-1, -1, L"%ESlot Empty%N\r\n");\r
  }\r
  ShellPrintEx (-1, -1, L"  Electromechanical Interlock Status(7): %EElectromechanical Interlock ");\r
  if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {\r
    ShellPrintEx (-1, -1, L"Engaged%N\r\n");\r
  } else {\r
    ShellPrintEx (-1, -1, L"Disengaged%N\r\n");\r
  }\r
  ShellPrintEx (-1, -1,\r
    L"  Data Link Layer State Changed(8):      %E%d%N\r\n",\r
    PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device root information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieRootControl;\r
\r
  PcieRootControl = PciExpressCap->RootControl;\r
\r
  ShellPrintEx (-1, -1,\r
    L"  System Error on Correctable Error Enable(0):  %E%d%N\r\n",\r
    PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  System Error on Non-Fatal Error Enable(1):    %E%d%N\r\n",\r
    PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  System Error on Fatal Error Enable(2):        %E%d%N\r\n",\r
    PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  PME Interrupt Enable(3):                      %E%d%N\r\n",\r
    PCIE_CAP_PME_INT_ENABLE (PcieRootControl)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  CRS Software Visibility Enable(4):            %E%d%N\r\n",\r
    PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device root capability information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT16 PcieRootCap;\r
\r
  PcieRootCap = PciExpressCap->RsvdP;\r
\r
  ShellPrintEx (-1, -1,\r
    L"  CRS Software Visibility(0):                   %E%d%N\r\n",\r
    PCIE_CAP_CRS_SW_VIS (PcieRootCap)\r
   );\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Print out information of the device root status information.\r
\r
  @param[in] PciExpressCap  The pointer to the structure about the device.\r
\r
  @retval EFI_SUCCESS   The operation was successful.\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
  )\r
{\r
  UINT32 PcieRootStatus;\r
\r
  PcieRootStatus = PciExpressCap->RootStatus;\r
\r
  ShellPrintEx (-1, -1,\r
    L"  PME Requester ID(15:0):                       %E0x%04x%N\r\n",\r
    PCIE_CAP_PME_REQ_ID (PcieRootStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  PME Status(16):                               %E%d%N\r\n",\r
    PCIE_CAP_PME_STATUS (PcieRootStatus)\r
   );\r
  ShellPrintEx (-1, -1,\r
    L"  PME Pending(17):                              %E%d%N\r\n",\r
    PCIE_CAP_PME_PENDING (PcieRootStatus)\r
   );\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Function to interpret and print out the link control structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityLinkControl (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL), \r
    gShellDebug1HiiHandle, \r
    Header->RootComplexLinkCapabilities,\r
    Header->RootComplexLinkControl,\r
    Header->RootComplexLinkStatus\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the power budgeting structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityPowerBudgeting (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_POWER), \r
    gShellDebug1HiiHandle, \r
    Header->DataSelect,\r
    Header->Data,\r
    Header->PowerBudgetCapability\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the ACS structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityAcs (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED  *Header;\r
  UINT16                                                VectorSize;\r
  UINT16                                                LoopCounter;\r
\r
  Header      = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED*)HeaderAddress;\r
  VectorSize  = 0;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_ACS), \r
    gShellDebug1HiiHandle, \r
    Header->AcsCapability,\r
    Header->AcsControl\r
    ); \r
  if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header)) {\r
    VectorSize = PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header);\r
    if (VectorSize == 0) {\r
      VectorSize = 256;\r
    }\r
    for (LoopCounter = 0 ; LoopCounter * 8 < VectorSize ; LoopCounter++) {\r
      ShellPrintHiiEx(\r
        -1, -1, NULL, \r
        STRING_TOKEN (STR_PCI_EXT_CAP_ACS2), \r
        gShellDebug1HiiHandle, \r
        LoopCounter + 1,\r
        Header->EgressControlVectorArray[LoopCounter]\r
        ); \r
    }\r
  }\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED) + (VectorSize / 8) - 1,\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the latency tolerance reporting structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_LAT), \r
    gShellDebug1HiiHandle, \r
    Header->MaxSnoopLatency,\r
    Header->MaxNoSnoopLatency\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the serial number structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilitySerialNumber (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_SN), \r
    gShellDebug1HiiHandle, \r
    Header->SerialNumber\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the RCRB structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityRcrb (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_RCRB), \r
    gShellDebug1HiiHandle, \r
    Header->VendorId,\r
    Header->DeviceId,\r
    Header->RcrbCapabilities,\r
    Header->RcrbControl\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the vendor specific structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityVendorSpecific (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_VEN), \r
    gShellDebug1HiiHandle, \r
    Header->VendorSpecificHeader\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the Event Collector Endpoint Association structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityECEA (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_ECEA), \r
    gShellDebug1HiiHandle, \r
    Header->AssociationBitmap\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the ARI structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityAri (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_ARI), \r
    gShellDebug1HiiHandle, \r
    Header->AriCapability,\r
    Header->AriControl\r
    ); \r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the DPA structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION *Header;\r
  UINT8                                                            LinkCount;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_DPA), \r
    gShellDebug1HiiHandle, \r
    Header->DpaCapability,\r
    Header->DpaLatencyIndicator,\r
    Header->DpaStatus,\r
    Header->DpaControl\r
    ); \r
  for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header) + 1 ; LinkCount++) {\r
    ShellPrintHiiEx(\r
      -1, -1, NULL, \r
      STRING_TOKEN (STR_PCI_EXT_CAP_DPA2), \r
      gShellDebug1HiiHandle, \r
      LinkCount+1,\r
      Header->DpaPowerAllocationArray[LinkCount]\r
      );\r
  }\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the link declaration structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityLinkDeclaration (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION  *Header;\r
  UINT8                                                     LinkCount;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR), \r
    gShellDebug1HiiHandle, \r
    Header->ElementSelfDescription\r
    );\r
\r
  for (LinkCount = 0 ; LinkCount < PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header) ; LinkCount++) {\r
    ShellPrintHiiEx(\r
      -1, -1, NULL, \r
      STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2), \r
      gShellDebug1HiiHandle, \r
      LinkCount+1,\r
      Header->LinkEntry[LinkCount]\r
      );\r
  }\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header)-1)*sizeof(UINT32),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the Advanced Error Reporting structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityAer (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_AER), \r
    gShellDebug1HiiHandle, \r
    Header->UncorrectableErrorStatus,\r
    Header->UncorrectableErrorMask,\r
    Header->UncorrectableErrorSeverity,\r
    Header->CorrectableErrorStatus,\r
    Header->CorrectableErrorMask,\r
    Header->AdvancedErrorCapabilitiesAndControl,\r
    Header->HeaderLog[0],\r
    Header->HeaderLog[1],\r
    Header->HeaderLog[2],\r
    Header->HeaderLog[3],\r
    Header->RootErrorCommand,\r
    Header->RootErrorStatus,\r
    Header->ErrorSourceIdentification,\r
    Header->CorrectableErrorSourceIdentification,\r
    Header->TlpPrefixLog[0],\r
    Header->TlpPrefixLog[1],\r
    Header->TlpPrefixLog[2],\r
    Header->TlpPrefixLog[3]\r
    );\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING),\r
    (VOID *) (HeaderAddress)\r
    );\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the multicast structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
  @param[in] PciExpressCapPtr     The address of the PCIe capabilities structure.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityMulticast (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
  IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
    gShellDebug1HiiHandle, \r
    Header->MultiCastCapability,\r
    Header->MulticastControl,\r
    Header->McBaseAddress,\r
    Header->McReceiveAddress,\r
    Header->McBlockAll,\r
    Header->McBlockUntranslated,\r
    Header->McOverlayBar\r
    );\r
\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
    (VOID *) (HeaderAddress)\r
    );\r
\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the virtual channel and multi virtual channel structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityVirtualChannel (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY  *Header;\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC          *CapabilityItem;\r
  UINT32                                                              ItemCount;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
    gShellDebug1HiiHandle, \r
    Header->ExtendedVcCount,\r
    Header->PortVcCapability1,\r
    Header->PortVcCapability2,\r
    Header->VcArbTableOffset,\r
    Header->PortVcControl,\r
    Header->PortVcStatus\r
    );\r
  for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
    CapabilityItem = &Header->Capability[ItemCount];\r
    ShellPrintHiiEx(\r
      -1, -1, NULL, \r
      STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
      gShellDebug1HiiHandle, \r
      ItemCount+1,\r
      CapabilityItem->VcResourceCapability,\r
      CapabilityItem->PortArbTableOffset,\r
      CapabilityItem->VcResourceControl,\r
      CapabilityItem->VcResourceStatus\r
      );\r
  }\r
\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r
    (VOID *) (HeaderAddress)\r
    );\r
\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the resizeable bar structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityResizeableBar (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR        *Header;\r
  UINT32                                                       ItemCount;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
\r
  for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
    ShellPrintHiiEx(\r
      -1, -1, NULL, \r
      STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
      gShellDebug1HiiHandle, \r
      ItemCount+1,\r
      Header->Capability[ItemCount].ResizableBarCapability,\r
      Header->Capability[ItemCount].ResizableBarControl\r
      );\r
  }\r
\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
    (VOID *) (HeaderAddress)\r
    );\r
\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the TPH structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilityTph (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
    gShellDebug1HiiHandle, \r
    Header->TphRequesterCapability,\r
    Header->TphRequesterControl\r
    );\r
  DumpHex (\r
    8,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
    GET_TPH_TABLE_SIZE(Header),\r
    (VOID *)Header->TphStTable\r
    );\r
\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
    (VOID *) (HeaderAddress)\r
    );\r
\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Function to interpret and print out the secondary PCIe capability structure\r
\r
  @param[in] HeaderAddress        The Address of this capability header.\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
  @param[in] PciExpressCapPtr     The address of the PCIe capabilities structure.\r
**/\r
EFI_STATUS\r
PrintInterpretedExtendedCompatibilitySecondary (\r
  IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
  IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
  IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
  )\r
{\r
  CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
  Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
\r
  ShellPrintHiiEx(\r
    -1, -1, NULL, \r
    STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
    gShellDebug1HiiHandle, \r
    Header->LinkControl3,\r
    Header->LaneErrorStatus\r
    );\r
  DumpHex (\r
    8,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
    PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
    (VOID *)Header->EqualizationControl\r
    );\r
\r
  DumpHex (\r
    4,\r
    EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
    sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
    (VOID *) (HeaderAddress)\r
    );\r
\r
  return (EFI_SUCCESS);\r
}\r
\r
/**\r
  Display Pcie extended capability details\r
\r
  @param[in] HeadersBaseAddress   The address of all the extended capability headers.\r
  @param[in] HeaderAddress        The address of this capability header.\r
  @param[in] PciExpressCapPtr     The address of the PCIe capabilities structure.\r
**/\r
EFI_STATUS\r
PrintPciExtendedCapabilityDetails(\r
  IN CONST PCI_EXP_EXT_HDR    *HeadersBaseAddress, \r
  IN CONST PCI_EXP_EXT_HDR    *HeaderAddress,\r
  IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
  )\r
{\r
  switch (HeaderAddress->CapabilityId){\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
      return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
      return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
      return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
      return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
      return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
      return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
      return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
      return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
      return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
      return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
      return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
      return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
      return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
      //\r
      // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
      //\r
      return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
      return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
      return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
    case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
      return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
    default:\r
      ShellPrintEx (-1, -1,\r
        L"Unknown PCIe extended capability ID (%04xh).  No interpretation available.\r\n",\r
        HeaderAddress->CapabilityId\r
        );\r
      return EFI_SUCCESS;\r
  };\r
\r
}\r
\r
/**\r
  Display Pcie device structure.\r
\r
  @param[in] IoDev          The pointer to the root pci protocol.\r
  @param[in] Address        The Address to start at.\r
  @param[in] CapabilityPtr  The offset from the address to start.\r
  @param[in] EnhancedDump   The print format for the dump data.\r
  \r
**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *IoDev,\r
  IN  UINT64                                  Address,\r
  IN  UINT8                                   CapabilityPtr,\r
  IN CONST UINT16                            EnhancedDump\r
  )\r
{\r
\r
  PCIE_CAP_STRUCTURE  PciExpressCap;\r
  EFI_STATUS          Status;\r
  UINT64              CapRegAddress;\r
  UINT8               Bus;\r
  UINT8               Dev;\r
  UINT8               Func;\r
  UINT8               *ExRegBuffer;\r
  UINTN               ExtendRegSize;\r
  UINT64              Pciex_Address;\r
  UINT8               DevicePortType;\r
  UINTN               Index;\r
  UINT8               *RegAddr;\r
  UINTN               RegValue;\r
  PCI_EXP_EXT_HDR     *ExtHdr;\r
\r
  CapRegAddress = Address + CapabilityPtr;\r
  IoDev->Pci.Read (\r
              IoDev,\r
              EfiPciWidthUint32,\r
              CapRegAddress,\r
              sizeof (PciExpressCap) / sizeof (UINT32),\r
              &PciExpressCap\r
             );\r
\r
  DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);\r
\r
  ShellPrintEx (-1, -1, L"\r\nPci Express device capability structure:\r\n");\r
\r
  for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {\r
    if (ShellGetExecutionBreakFlag()) {\r
      goto Done;\r
    }\r
    RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;\r
    switch (PcieExplainList[Index].Width) {\r
      case FieldWidthUINT8:\r
        RegValue = *(UINT8 *) RegAddr;\r
        break;\r
      case FieldWidthUINT16:\r
        RegValue = *(UINT16 *) RegAddr;\r
        break;\r
      case FieldWidthUINT32:\r
        RegValue = *(UINT32 *) RegAddr;\r
        break;\r
      default:\r
        RegValue = 0;\r
        break;\r
    }\r
    ShellPrintHiiEx(-1, -1, NULL,\r
      PcieExplainList[Index].Token,\r
      gShellDebug1HiiHandle,\r
      PcieExplainList[Index].Offset,\r
      RegValue\r
     );\r
    if (PcieExplainList[Index].Func == NULL) {\r
      continue;\r
    }\r
    switch (PcieExplainList[Index].Type) {\r
      case PcieExplainTypeLink:\r
        //\r
        // Link registers should not be used by\r
        // a) Root Complex Integrated Endpoint\r
        // b) Root Complex Event Collector\r
        //\r
        if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||\r
            DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {\r
          continue;\r
        }\r
        break;\r
      case PcieExplainTypeSlot:\r
        //\r
        // Slot registers are only valid for\r
        // a) Root Port of PCI Express Root Complex\r
        // b) Downstream Port of PCI Express Switch\r
        // and when SlotImplemented bit is set in PCIE cap register.\r
        //\r
        if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&\r
             DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||\r
            !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {\r
          continue;\r
        }\r
        break;\r
      case PcieExplainTypeRoot:\r
        //\r
        // Root registers are only valid for\r
        // Root Port of PCI Express Root Complex\r
        //\r
        if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {\r
          continue;\r
        }\r
        break;\r
      default:\r
        break;\r
    }\r
    PcieExplainList[Index].Func (&PciExpressCap);\r
  }\r
\r
  Bus           = (UINT8) (RShiftU64 (Address, 24));\r
  Dev           = (UINT8) (RShiftU64 (Address, 16));\r
  Func          = (UINT8) (RShiftU64 (Address, 8));\r
\r
  Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
\r
  ExtendRegSize = 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET;\r
\r
  ExRegBuffer   = (UINT8 *) AllocateZeroPool (ExtendRegSize);\r
\r
  //\r
  // PciRootBridgeIo protocol should support pci express extend space IO\r
  // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)\r
  //\r
  Status = IoDev->Pci.Read (\r
                        IoDev,\r
                        EfiPciWidthUint32,\r
                        Pciex_Address,\r
                        (ExtendRegSize) / sizeof (UINT32),\r
                        (VOID *) (ExRegBuffer)\r
                       );\r
  if (EFI_ERROR (Status) || ExRegBuffer == NULL) {\r
    SHELL_FREE_NON_NULL(ExRegBuffer);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  if (EnhancedDump == 0) {\r
    //\r
    // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)\r
    //\r
    ShellPrintEx (-1, -1, L"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");\r
\r
    DumpHex (\r
      2,\r
      EFI_PCIE_CAPABILITY_BASE_OFFSET,\r
      ExtendRegSize,\r
      (VOID *) (ExRegBuffer)\r
      );\r
  } else {\r
    ExtHdr = (PCI_EXP_EXT_HDR*)ExRegBuffer;\r
    while (ExtHdr->CapabilityId != 0 && ExtHdr->CapabilityVersion != 0) {\r
      //\r
      // Process this item\r
      //\r
      if (EnhancedDump == 0xFFFF || EnhancedDump == ExtHdr->CapabilityId) {\r
        //\r
        // Print this item\r
        //\r
        PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR*)ExRegBuffer, ExtHdr, &PciExpressCap);\r
      }\r
\r
      //\r
      // Advance to the next item if it exists\r
      //\r
      if (ExtHdr->NextCapabilityOffset != 0) {\r
        ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);\r
      } else {\r
        break;\r
      }\r
    }\r
  }\r
  SHELL_FREE_NON_NULL(ExRegBuffer);\r
\r
Done:\r
  return EFI_SUCCESS;\r
}\r