[mirror_edk2.git] / SourceLevelDebugPkg / Library / DebugCommunicationLibUsb3 / DebugCommunicationLibUsb3Internal.h

/** @file\r
  Debug Port Library implementation based on usb3 debug port.\r
\r
  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__\r
#define __USB3_DEBUG_PORT_LIB_INTERNAL__\r
\r
#include <Uefi.h>\r
#include <Base.h>\r
#include <IndustryStandard/Usb.h>\r
#include <Library/IoLib.h>\r
#include <IndustryStandard/Pci.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/DebugCommunicationLib.h>\r
#include <Library/PciLib.h>\r
\r
//\r
// USB Debug GUID value\r
//\r
#define USB3_DBG_GUID \\r
    { \\r
      0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \\r
    }\r
\r
//\r
// The state machine of usb debug port\r
//\r
#define USB3DBG_NO_DBG_CAB    0   // The XHCI host controller does not support debug capability\r
#define USB3DBG_DBG_CAB       1   // The XHCI host controller supports debug capability\r
#define USB3DBG_ENABLED       2   // The XHCI debug device is enabled\r
#define USB3DBG_NOT_ENABLED   4   // The XHCI debug device is not enabled\r
\r
#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08\r
\r
//\r
// MaxPacketSize for DbC Endpoint Descriptor IN and OUT\r
//\r
#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE    0x400\r
\r
#define XHCI_DEBUG_DEVICE_VENDOR_ID   0x0525\r
#define XHCI_DEBUG_DEVICE_PRODUCT_ID  0x127A\r
#define XHCI_DEBUG_DEVICE_PROTOCOL    0xFF\r
#define XHCI_DEBUG_DEVICE_REVISION    0x00\r
\r
#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
\r
#define PCI_CAPABILITY_ID_DEBUG_PORT  0x0A\r
#define XHC_HCCPARAMS_OFFSET          0x10\r
#define XHC_CAPABILITY_ID_MASK        0xFF\r
#define XHC_NEXT_CAPABILITY_MASK      0xFF00\r
\r
#define XHC_HCSPARAMS1_OFFSET         0x4    // Structural Parameters 1\r
#define XHC_USBCMD_OFFSET             0x0    // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET             0x4    // USB Status Register Offset\r
#define XHC_PORTSC_OFFSET             0x400  // Port Status and Control Register Offset\r
\r
#define XHC_USBCMD_RUN                BIT0  // Run/Stop\r
#define XHC_USBCMD_RESET              BIT1  // Host Controller Reset\r
\r
#define XHC_USBSTS_HALT               BIT0\r
\r
//\r
// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
//\r
#define DATA_TRANSFER_WRITE_TIMEOUT      0\r
#define DATA_TRANSFER_READ_TIMEOUT       50000\r
#define DATA_TRANSFER_POLL_TIMEOUT       1000\r
#define XHC_DEBUG_PORT_1_MILLISECOND     1000\r
//\r
// XHCI port power off/on delay\r
//\r
#define XHC_DEBUG_PORT_ON_OFF_DELAY    100000\r
\r
//\r
// USB debug device string descritpor (header size + unicode string length)\r
//\r
#define STRING0_DESC_LEN      4\r
#define MANU_DESC_LEN         12\r
#define PRODUCT_DESC_LEN      40\r
#define SERIAL_DESC_LEN       4\r
\r
//\r
// Debug Capability Register Offset\r
//\r
#define XHC_DC_DCID                  0x0\r
#define XHC_DC_DCDB                  0x4\r
#define XHC_DC_DCERSTSZ              0x8\r
#define XHC_DC_DCERSTBA              0x10\r
#define XHC_DC_DCERDP                0x18\r
#define XHC_DC_DCCTRL                0x20\r
#define XHC_DC_DCST                  0x24\r
#define XHC_DC_DCPORTSC              0x28\r
#define XHC_DC_DCCP                  0x30\r
#define XHC_DC_DCDDI1                0x38\r
#define XHC_DC_DCDDI2                0x3C\r
\r
#define TRB_TYPE_LINK                6\r
\r
#define ERST_NUMBER                  0x01\r
#define TR_RING_TRB_NUMBER           0x100\r
#define EVENT_RING_TRB_NUMBER        0x200\r
\r
#define ED_BULK_OUT                  2\r
#define ED_BULK_IN                   6\r
\r
#define XHC_LOW_32BIT(Addr64)          ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
#define XHC_HIGH_32BIT(Addr64)         ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
#define XHC_BIT_IS_SET(Data, Bit)      ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
\r
//\r
// Endpoint Type (EP Type).\r
//\r
#define ED_NOT_VALID                          0\r
#define ED_ISOCH_OUT                          1\r
#define ED_BULK_OUT                           2\r
#define ED_INTERRUPT_OUT                      3\r
#define ED_CONTROL_BIDIR                      4\r
#define ED_ISOCH_IN                           5\r
#define ED_BULK_IN                            6\r
#define ED_INTERRUPT_IN                       7\r
\r
//\r
// 6.4.5 TRB Completion Codes\r
//\r
#define TRB_COMPLETION_INVALID                0\r
#define TRB_COMPLETION_SUCCESS                1\r
#define TRB_COMPLETION_DATA_BUFFER_ERROR      2\r
#define TRB_COMPLETION_BABBLE_ERROR           3\r
#define TRB_COMPLETION_USB_TRANSACTION_ERROR  4\r
#define TRB_COMPLETION_TRB_ERROR              5\r
#define TRB_COMPLETION_STALL_ERROR            6\r
#define TRB_COMPLETION_SHORT_PACKET           13\r
\r
//\r
// 6.4.6 TRB Types\r
//\r
#define TRB_TYPE_NORMAL                       1\r
#define TRB_TYPE_SETUP_STAGE                  2\r
#define TRB_TYPE_DATA_STAGE                   3\r
#define TRB_TYPE_STATUS_STAGE                 4\r
#define TRB_TYPE_ISOCH                        5\r
#define TRB_TYPE_LINK                         6\r
#define TRB_TYPE_EVENT_DATA                   7\r
#define TRB_TYPE_NO_OP                        8\r
#define TRB_TYPE_EN_SLOT                      9\r
#define TRB_TYPE_DIS_SLOT                     10\r
#define TRB_TYPE_ADDRESS_DEV                  11\r
#define TRB_TYPE_CON_ENDPOINT                 12\r
#define TRB_TYPE_EVALU_CONTXT                 13\r
#define TRB_TYPE_RESET_ENDPOINT               14\r
#define TRB_TYPE_STOP_ENDPOINT                15\r
#define TRB_TYPE_SET_TR_DEQUE                 16\r
#define TRB_TYPE_RESET_DEV                    17\r
#define TRB_TYPE_GET_PORT_BANW                21\r
#define TRB_TYPE_FORCE_HEADER                 22\r
#define TRB_TYPE_NO_OP_COMMAND                23\r
#define TRB_TYPE_TRANS_EVENT                  32\r
#define TRB_TYPE_COMMAND_COMPLT_EVENT         33\r
#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT     34\r
#define TRB_TYPE_HOST_CONTROLLER_EVENT        37\r
#define TRB_TYPE_DEVICE_NOTIFI_EVENT          38\r
#define TRB_TYPE_MFINDEX_WRAP_EVENT           39\r
\r
//\r
// Convert millisecond to microsecond.\r
//\r
#define XHC_1_MILLISECOND                     (1000)\r
#define XHC_POLL_DELAY                        (1000)\r
#define XHC_GENERIC_TIMEOUT                   (10 * 1000)\r
\r
#define EFI_USB_SPEED_FULL                    0x0000  ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
#define EFI_USB_SPEED_LOW                     0x0001  ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
#define EFI_USB_SPEED_HIGH                    0x0002  ///< 480 Mb/s, USB 2.0 EHCI HC.\r
#define EFI_USB_SPEED_SUPER                   0x0003  ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
\r
//\r
// Transfer types, used in URB to identify the transfer type\r
//\r
#define XHC_CTRL_TRANSFER                     0x01\r
#define XHC_BULK_TRANSFER                     0x02\r
#define XHC_INT_TRANSFER_SYNC                 0x04\r
#define XHC_INT_TRANSFER_ASYNC                0x08\r
#define XHC_INT_ONLY_TRANSFER_ASYNC           0x10\r
\r
//\r
// USB Transfer Results\r
//\r
#define EFI_USB_NOERROR             0x00\r
#define EFI_USB_ERR_NOTEXECUTE      0x01\r
#define EFI_USB_ERR_STALL           0x02\r
#define EFI_USB_ERR_BUFFER          0x04\r
#define EFI_USB_ERR_BABBLE          0x08\r
#define EFI_USB_ERR_NAK             0x10\r
#define EFI_USB_ERR_CRC             0x20\r
#define EFI_USB_ERR_TIMEOUT         0x40\r
#define EFI_USB_ERR_BITSTUFF        0x80\r
#define EFI_USB_ERR_SYSTEM          0x100\r
\r
#pragma pack(1)\r
\r
//\r
// 7.6.9 OUT/IN EP Context: 64 bytes\r
// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
//\r
typedef struct _ENDPOINT_CONTEXT_64 {\r
  UINT32                  EPState:3;\r
  UINT32                  RsvdZ1:5;\r
  UINT32                  Mult:2;         // set to 0\r
  UINT32                  MaxPStreams:5;  // set to 0\r
  UINT32                  LSA:1;          // set to 0\r
  UINT32                  Interval:8;     // set to 0\r
  UINT32                  RsvdZ2:8;\r
\r
  UINT32                  RsvdZ3:1;\r
  UINT32                  CErr:2;\r
  UINT32                  EPType:3;\r
  UINT32                  RsvdZ4:1;\r
  UINT32                  HID:1;          // set to 0\r
  UINT32                  MaxBurstSize:8;\r
  UINT32                  MaxPacketSize:16;\r
\r
  UINT32                  PtrLo;\r
\r
  UINT32                  PtrHi;\r
\r
  UINT32                  AverageTRBLength:16;\r
  UINT32                  MaxESITPayload:16;  // set to 0\r
\r
  UINT32                  RsvdZ5;             // Reserved\r
  UINT32                  RsvdZ6;\r
  UINT32                  RsvdZ7;\r
  \r
  UINT32                  RsvdZ8;\r
  UINT32                  RsvdZ9;\r
  UINT32                  RsvdZ10;\r
  UINT32                  RsvdZ11;\r
  \r
  UINT32                  RsvdZ12;\r
  UINT32                  RsvdZ13;\r
  UINT32                  RsvdZ14;\r
  UINT32                  RsvdZ15;\r
} ENDPOINT_CONTEXT_64;\r
\r
//\r
// 6.4.1.1 Normal TRB: 16 bytes\r
// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
// Rings, and to define the Data stage information for Control Transfer Rings.\r
//\r
typedef struct _TRANSFER_TRB_NORMAL {\r
  UINT32                  TRBPtrLo;\r
\r
  UINT32                  TRBPtrHi;\r
\r
  UINT32                  Length:17;\r
  UINT32                  TDSize:5;\r
  UINT32                  IntTarget:10;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  ENT:1;\r
  UINT32                  ISP:1;\r
  UINT32                  NS:1;\r
  UINT32                  CH:1;\r
  UINT32                  IOC:1;\r
  UINT32                  IDT:1;\r
  UINT32                  RsvdZ1:2;\r
  UINT32                  BEI:1;\r
  UINT32                  Type:6;\r
  UINT32                  RsvdZ2:16;\r
} TRANSFER_TRB_NORMAL;\r
\r
//\r
// 6.4.2.1 Transfer Event TRB: 16 bytes\r
// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
// for more information on the use and operation of Transfer Events.\r
//\r
typedef struct _EVT_TRB_TRANSFER {\r
  UINT32                  TRBPtrLo;\r
\r
  UINT32                  TRBPtrHi;\r
\r
  UINT32                  Length:24;\r
  UINT32                  Completecode:8;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  RsvdZ1:1;\r
  UINT32                  ED:1;\r
  UINT32                  RsvdZ2:7;\r
  UINT32                  Type:6;\r
  UINT32                  EndpointId:5;\r
  UINT32                  RsvdZ3:3;\r
  UINT32                  SlotId:8;\r
} EVT_TRB_TRANSFER;\r
\r
//\r
// 6.4.4.1 Link TRB: 16 bytes\r
// A Link TRB provides support for non-contiguous TRB Rings.\r
//\r
typedef struct _LINK_TRB {\r
  UINT32                  PtrLo;\r
\r
  UINT32                  PtrHi;\r
\r
  UINT32                  RsvdZ1:22;\r
  UINT32                  InterTarget:10;\r
\r
  UINT32                  CycleBit:1;\r
  UINT32                  TC:1;\r
  UINT32                  RsvdZ2:2;\r
  UINT32                  CH:1;\r
  UINT32                  IOC:1;\r
  UINT32                  RsvdZ3:4;\r
  UINT32                  Type:6;\r
  UINT32                  RsvdZ4:16;\r
} LINK_TRB;\r
\r
//\r
// TRB Template: 16 bytes\r
//\r
typedef struct _TRB_TEMPLATE {\r
  UINT32                    Parameter1;\r
\r
  UINT32                    Parameter2;\r
\r
  UINT32                    Status;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ1:9;\r
  UINT32                    Type:6;\r
  UINT32                    Control:16;\r
} TRB_TEMPLATE;\r
\r
//\r
// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
//\r
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
  UINT32                  PtrLo;\r
  UINT32                  PtrHi;\r
  UINT32                  RingTrbSize:16;\r
  UINT32                  RsvdZ1:16;\r
  UINT32                  RsvdZ2;\r
} EVENT_RING_SEG_TABLE_ENTRY;\r
\r
//\r
// Size: 40 bytes\r
//\r
typedef struct _EVENT_RING {\r
  EFI_PHYSICAL_ADDRESS      ERSTBase;\r
  EFI_PHYSICAL_ADDRESS      EventRingSeg0;\r
  UINT32                    TrbNumber;\r
  EFI_PHYSICAL_ADDRESS      EventRingEnqueue;\r
  EFI_PHYSICAL_ADDRESS      EventRingDequeue;\r
  UINT32                    EventRingCCS;\r
} EVENT_RING;\r
\r
// Size: 32 bytes\r
typedef struct _TRANSFER_RING {\r
  EFI_PHYSICAL_ADDRESS      RingSeg0;\r
  UINT32                    TrbNumber;\r
  EFI_PHYSICAL_ADDRESS      RingEnqueue;\r
  EFI_PHYSICAL_ADDRESS      RingDequeue;\r
  UINT32                    RingPCS;\r
} TRANSFER_RING;\r
\r
//\r
// Size: 64 bytes\r
//\r
typedef struct _DBC_INFO_CONTEXT {\r
  UINT64        String0DescAddress;\r
  UINT64        ManufacturerStrDescAddress;\r
  UINT64        ProductStrDescAddress;\r
  UINT64        SerialNumberStrDescAddress;\r
  UINT64        String0Length:8;\r
  UINT64        ManufacturerStrLength:8;\r
  UINT64        ProductStrLength:8;\r
  UINT64        SerialNumberStrLength:8;\r
  UINT64        RsvdZ1:32;\r
  UINT64        RsvdZ2;\r
  UINT64        RsvdZ3;\r
  UINT64        RsvdZ4;  \r
} DBC_INFO_CONTEXT;\r
\r
//\r
// Debug Capability Context Data Structure: 192 bytes\r
//\r
typedef struct _XHC_DC_CONTEXT {\r
  DBC_INFO_CONTEXT      DbcInfoContext;\r
  ENDPOINT_CONTEXT_64   EpOutContext;\r
  ENDPOINT_CONTEXT_64   EpInContext;\r
} XHC_DC_CONTEXT;\r
\r
//\r
// Size: 16 bytes\r
//\r
typedef union _TRB {\r
  TRB_TEMPLATE                TrbTemplate;\r
  TRANSFER_TRB_NORMAL         TrbNormal;\r
} TRB;\r
\r
///\r
/// USB data transfer direction\r
///\r
typedef enum {\r
  EfiUsbDataIn,\r
  EfiUsbDataOut,\r
  EfiUsbNoData\r
} EFI_USB_DATA_DIRECTION;\r
\r
//\r
// URB (Usb Request Block) contains information for all kinds of\r
// usb requests.\r
//\r
typedef struct _URB {\r
  //\r
  // Transfer data buffer\r
  //\r
  EFI_PHYSICAL_ADDRESS            Data;\r
  UINT32                          DataLen;\r
\r
  //\r
  // Execute result\r
  //\r
  UINT32                          Result;\r
  //\r
  // Completed data length\r
  //\r
  UINT32                          Completed;\r
  //\r
  // Tranfer Ring info\r
  //\r
  EFI_PHYSICAL_ADDRESS            Ring;\r
  EFI_PHYSICAL_ADDRESS            Trb;\r
  BOOLEAN                         Finished;\r
  EFI_USB_DATA_DIRECTION          Direction;\r
} URB;\r
\r
typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
  UINT8                                   Initialized;\r
\r
  //\r
  // The flag indicates debug device is ready\r
  //\r
  BOOLEAN                                 DebugSupport;\r
  \r
  //\r
  // The flag indicates debug device is ready\r
  //\r
  BOOLEAN                                 Ready;\r
\r
  //\r
  // The flag indicates if USB 3.0 ports has been turn off/on power\r
  //  \r
  BOOLEAN                                 ChangePortPower;\r
\r
  //\r
  // XHCI MMIO Base address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    XhciMmioBase;\r
\r
  //\r
  // XHCI OP RegisterBase address\r
  //  \r
  EFI_PHYSICAL_ADDRESS                    XhciOpRegister;\r
  \r
  //\r
  // XHCI Debug Register Base Address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    DebugCapabilityBase;\r
  \r
  //\r
  // XHCI Debug Capability offset\r
  //\r
  UINT64                                  DebugCapabilityOffset;  \r
  \r
  //\r
  // XHCI Debug Context Address\r
  //\r
  EFI_PHYSICAL_ADDRESS                    DebugCapabilityContext;\r
  \r
  //\r
  // Transfer Ring\r
  //\r
  TRANSFER_RING                           TransferRingOut;\r
  TRANSFER_RING                           TransferRingIn;\r
\r
  //\r
  // EventRing\r
  //\r
  EVENT_RING                              EventRing;\r
  \r
  //\r
  // URB - Read\r
  //\r
  URB                                     UrbOut;\r
\r
  //\r
  // URB - Write\r
  //\r
  URB                                     UrbIn;\r
\r
  //\r
  // The available data length in the following data buffer.\r
  //\r
  UINT8                                   DataCount;\r
  //\r
  // The data buffer address for data read and poll.\r
  //\r
  EFI_PHYSICAL_ADDRESS                    Data;\r
} USB3_DEBUG_PORT_HANDLE;\r
\r
#pragma pack()\r
\r
/**\r
  Read XHCI debug register.\r
\r
 @param  Handle        Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadDebugReg (\r
  IN  USB3_DEBUG_PORT_HANDLE    *Handle,\r
  IN  UINT32                      Offset\r
  );\r
\r
/**\r
  Set one bit of the debug register while keeping other bits.\r
\r
  @param  Handle       Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetDebugRegBit (\r
  IN USB3_DEBUG_PORT_HANDLE  *Handle,\r
  IN UINT32                   Offset,\r
  IN UINT32                   Bit\r
  );\r
  \r
/**\r
  Write the data to the debug register.\r
\r
  @param  Handle       Debug port handle.\r
  @param  Offset       The offset of the debug register.\r
  @param  Data         The data to write.\r
\r
**/  \r
VOID\r
XhcWriteDebugReg (\r
  IN USB3_DEBUG_PORT_HANDLE     *Handle,\r
  IN UINT32                     Offset,\r
  IN UINT32                     Data\r
  );\r
\r
/**\r
  Discover the USB3 debug device.\r
  \r
  @param  Handle                Debug port handle.\r
  \r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
  @retval RETURN_DEVICE_ERROR   The serial device could not be initialized.\r
\r
**/\r
RETURN_STATUS\r
DiscoverUsb3DebugPort(\r
  USB3_DEBUG_PORT_HANDLE  *Handle\r
  );\r
  \r
/**\r
  Initialize the Serial Device hardware.\r
  \r
  @param  Handle            Debug port handle.\r
\r
  @retval RETURN_SUCCESS    The serial device was initialized successfully.\r
  @retval !RETURN_SUCCESS   Error.\r
\r
**/\r
RETURN_STATUS\r
InitializeUsb3DebugPort (\r
  USB3_DEBUG_PORT_HANDLE  *Handle\r
  );\r
\r
/**\r
  Return XHCI MMIO base address.\r
\r
**/\r
EFI_PHYSICAL_ADDRESS\r
GetXhciBaseAddress (\r
  VOID\r
  );\r
\r
/**\r
  Verifies if the bit positions specified by a mask are set in a register.\r
\r
  @param[in, out] Register    UNITN register\r
  @param[in]      BitMask     32-bit mask\r
\r
  @return  BOOLEAN  - TRUE  if all bits specified by the mask are enabled.\r
                    - FALSE even if one of the bits specified by the mask \r
                            is not enabled.\r
**/\r
BOOLEAN\r
XhcIsBitSet(\r
  UINTN   Register, \r
  UINT32  BitMask\r
  );\r
\r
/**\r
  Sets bits as per the enabled bit positions in the mask.\r
\r
  @param[in, out] Register    UINTN register\r
  @param[in]      BitMask     32-bit mask\r
**/\r
VOID\r
XhcSetR32Bit(\r
  UINTN   Register, \r
  UINT32  BitMask\r
  );\r
\r
/**\r
  Clears bits as per the enabled bit positions in the mask.\r
\r
  @param[in, out] Register    UINTN register\r
  @param[in]      BitMask     32-bit mask\r
**/\r
VOID\r
XhcClearR32Bit(\r
  IN OUT  UINTN  Register, \r
  IN      UINT32 BitMask\r
  );\r
\r
/**\r
  Initialize USB3 debug port.\r
  \r
  This method invokes various internal functions to facilitate\r
  detection and initialization of USB3 debug port.\r
\r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
USB3Initialize (\r
  VOID\r
  );\r
\r
/**\r
  Return command register value in XHCI controller.\r
\r
**/\r
UINT16\r
GetXhciPciCommand (\r
  VOID\r
  );\r
\r
/**\r
  Allocate aligned memory for XHC's usage.\r
\r
  @param  BufferSize      The size, in bytes, of the Buffer.\r
  \r
  @return A pointer to the allocated buffer or NULL if allocation fails.\r
\r
**/\r
VOID*\r
AllocateAlignBuffer (\r
  IN UINTN                    BufferSize\r
  );\r
\r
/**\r
  The real function to initialize USB3 debug port.\r
  \r
  This method invokes various internal functions to facilitate\r
  detection and initialization of USB3 debug port.\r
\r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
USB3InitializeReal (\r
  VOID\r
  );\r
\r
/**\r
  Submits bulk transfer to a bulk endpoint of a USB device.\r
\r
  @param  Handle                The instance of debug device.\r
  @param  Direction             The direction of data transfer.\r
  @param  Data                  Array of pointers to the buffers of data to transmit\r
                                from or receive into.\r
  @param  DataLength            The lenght of the data buffer.\r
  @param  Timeout               Indicates the maximum time, in millisecond, which\r
                                the transfer is allowed to complete.\r
\r
  @retval EFI_SUCCESS           The transfer was completed successfully.\r
  @retval EFI_OUT_OF_RESOURCES  The transfer failed due to lack of resource.\r
  @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
  @retval EFI_TIMEOUT           The transfer failed due to timeout.\r
  @retval EFI_DEVICE_ERROR      The transfer failed due to host controller error.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcDataTransfer (\r
  IN     USB3_DEBUG_PORT_HANDLE              *Handle,\r
  IN     EFI_USB_DATA_DIRECTION              Direction,\r
  IN OUT VOID                                *Data,\r
  IN OUT UINTN                               *DataLength,\r
  IN     UINTN                               Timeout\r
  );\r
\r
#endif //__SERIAL_PORT_LIB_USB__\r
Commit	Line	Data
2cb6eabe EL	1	/** @file\r
	2	Debug Port Library implementation based on usb3 debug port.\r
	3	\r
1f279e7a	4	Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
2cb6eabe EL	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php.\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef __USB3_DEBUG_PORT_LIB_INTERNAL__\r
	16	#define __USB3_DEBUG_PORT_LIB_INTERNAL__\r
	17	\r
	18	#include <Uefi.h>\r
	19	#include <Base.h>\r
	20	#include <IndustryStandard/Usb.h>\r
	21	#include <Library/IoLib.h>\r
	22	#include <IndustryStandard/Pci.h>\r
	23	#include <Library/PcdLib.h>\r
	24	#include <Library/UefiLib.h>\r
	25	#include <Library/UefiBootServicesTableLib.h>\r
	26	#include <Library/MemoryAllocationLib.h>\r
	27	#include <Library/DebugLib.h>\r
	28	#include <Library/BaseMemoryLib.h>\r
	29	#include <Library/BaseLib.h>\r
	30	#include <Library/TimerLib.h>\r
	31	#include <Library/DebugCommunicationLib.h>\r
	32	#include <Library/PciLib.h>\r
2cb6eabe EL	33	\r
	34	//\r
	35	// USB Debug GUID value\r
	36	//\r
	37	#define USB3_DBG_GUID \\r
	38	{ \\r
	39	0xb2a56f4d, 0x9177, 0x4fc8, { 0xa6, 0x77, 0xdd, 0x96, 0x3e, 0xb4, 0xcb, 0x1b } \\r
	40	}\r
	41	\r
	42	//\r
	43	// The state machine of usb debug port\r
	44	//\r
	45	#define USB3DBG_NO_DBG_CAB 0 // The XHCI host controller does not support debug capability\r
	46	#define USB3DBG_DBG_CAB 1 // The XHCI host controller supports debug capability\r
	47	#define USB3DBG_ENABLED 2 // The XHCI debug device is enabled\r
	48	#define USB3DBG_NOT_ENABLED 4 // The XHCI debug device is not enabled\r
	49	\r
5d6507a1 EL	50	#define USB3_DEBUG_PORT_WRITE_MAX_PACKET_SIZE 0x08\r
	51	\r
	52	//\r
	53	// MaxPacketSize for DbC Endpoint Descriptor IN and OUT\r
	54	//\r
	55	#define XHCI_DEBUG_DEVICE_MAX_PACKET_SIZE 0x400\r
2cb6eabe EL	56	\r
	57	#define XHCI_DEBUG_DEVICE_VENDOR_ID 0x0525\r
	58	#define XHCI_DEBUG_DEVICE_PRODUCT_ID 0x127A\r
	59	#define XHCI_DEBUG_DEVICE_PROTOCOL 0xFF\r
	60	#define XHCI_DEBUG_DEVICE_REVISION 0x00\r
	61	\r
	62	#define XHCI_BASE_ADDRESS_64_BIT_MASK 0xFFFFFFFFFFFF0000ULL\r
	63	#define XHCI_BASE_ADDRESS_32_BIT_MASK 0xFFFF0000\r
	64	\r
	65	#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A\r
	66	#define XHC_HCCPARAMS_OFFSET 0x10\r
	67	#define XHC_CAPABILITY_ID_MASK 0xFF\r
	68	#define XHC_NEXT_CAPABILITY_MASK 0xFF00\r
	69	\r
	70	#define XHC_HCSPARAMS1_OFFSET 0x4 // Structural Parameters 1\r
	71	#define XHC_USBCMD_OFFSET 0x0 // USB Command Register Offset\r
	72	#define XHC_USBSTS_OFFSET 0x4 // USB Status Register Offset\r
	73	#define XHC_PORTSC_OFFSET 0x400 // Port Status and Control Register Offset\r
	74	\r
	75	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	76	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	77	\r
	78	#define XHC_USBSTS_HALT BIT0\r
	79	\r
2cb6eabe EL	80	//\r
	81	// Indicate the timeout when data is transferred in microsecond. 0 means infinite timeout.\r
	82	//\r
	83	#define DATA_TRANSFER_WRITE_TIMEOUT 0\r
	84	#define DATA_TRANSFER_READ_TIMEOUT 50000\r
	85	#define DATA_TRANSFER_POLL_TIMEOUT 1000\r
08021523	86	#define XHC_DEBUG_PORT_1_MILLISECOND 1000\r
2cb6eabe EL	87	//\r
	88	// XHCI port power off/on delay\r
	89	//\r
	90	#define XHC_DEBUG_PORT_ON_OFF_DELAY 100000\r
	91	\r
	92	//\r
	93	// USB debug device string descritpor (header size + unicode string length)\r
	94	//\r
	95	#define STRING0_DESC_LEN 4\r
	96	#define MANU_DESC_LEN 12\r
	97	#define PRODUCT_DESC_LEN 40\r
	98	#define SERIAL_DESC_LEN 4\r
	99	\r
	100	//\r
	101	// Debug Capability Register Offset\r
	102	//\r
	103	#define XHC_DC_DCID 0x0\r
	104	#define XHC_DC_DCDB 0x4\r
	105	#define XHC_DC_DCERSTSZ 0x8\r
	106	#define XHC_DC_DCERSTBA 0x10\r
	107	#define XHC_DC_DCERDP 0x18\r
	108	#define XHC_DC_DCCTRL 0x20\r
	109	#define XHC_DC_DCST 0x24\r
	110	#define XHC_DC_DCPORTSC 0x28\r
	111	#define XHC_DC_DCCP 0x30\r
	112	#define XHC_DC_DCDDI1 0x38\r
	113	#define XHC_DC_DCDDI2 0x3C\r
	114	\r
	115	#define TRB_TYPE_LINK 6\r
	116	\r
	117	#define ERST_NUMBER 0x01\r
	118	#define TR_RING_TRB_NUMBER 0x100\r
	119	#define EVENT_RING_TRB_NUMBER 0x200\r
	120	\r
	121	#define ED_BULK_OUT 2\r
	122	#define ED_BULK_IN 6\r
	123	\r
	124	#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0xFFFFFFFF))\r
	125	#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINT64)(UINTN)(Addr64), 32) & 0xFFFFFFFF))\r
	126	#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
	127	\r
	128	//\r
	129	// Endpoint Type (EP Type).\r
	130	//\r
	131	#define ED_NOT_VALID 0\r
	132	#define ED_ISOCH_OUT 1\r
	133	#define ED_BULK_OUT 2\r
	134	#define ED_INTERRUPT_OUT 3\r
	135	#define ED_CONTROL_BIDIR 4\r
	136	#define ED_ISOCH_IN 5\r
	137	#define ED_BULK_IN 6\r
	138	#define ED_INTERRUPT_IN 7\r
	139	\r
	140	//\r
	141	// 6.4.5 TRB Completion Codes\r
	142	//\r
	143	#define TRB_COMPLETION_INVALID 0\r
	144	#define TRB_COMPLETION_SUCCESS 1\r
	145	#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
	146	#define TRB_COMPLETION_BABBLE_ERROR 3\r
	147	#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
	148	#define TRB_COMPLETION_TRB_ERROR 5\r
	149	#define TRB_COMPLETION_STALL_ERROR 6\r
	150	#define TRB_COMPLETION_SHORT_PACKET 13\r
151	\r
152	//\r
153	// 6.4.6 TRB Types\r
154	//\r
155	#define TRB_TYPE_NORMAL 1\r
156	#define TRB_TYPE_SETUP_STAGE 2\r
157	#define TRB_TYPE_DATA_STAGE 3\r
158	#define TRB_TYPE_STATUS_STAGE 4\r
159	#define TRB_TYPE_ISOCH 5\r
160	#define TRB_TYPE_LINK 6\r
161	#define TRB_TYPE_EVENT_DATA 7\r
162	#define TRB_TYPE_NO_OP 8\r
163	#define TRB_TYPE_EN_SLOT 9\r
164	#define TRB_TYPE_DIS_SLOT 10\r
165	#define TRB_TYPE_ADDRESS_DEV 11\r
166	#define TRB_TYPE_CON_ENDPOINT 12\r
167	#define TRB_TYPE_EVALU_CONTXT 13\r
168	#define TRB_TYPE_RESET_ENDPOINT 14\r
169	#define TRB_TYPE_STOP_ENDPOINT 15\r
170	#define TRB_TYPE_SET_TR_DEQUE 16\r
171	#define TRB_TYPE_RESET_DEV 17\r
172	#define TRB_TYPE_GET_PORT_BANW 21\r
173	#define TRB_TYPE_FORCE_HEADER 22\r
174	#define TRB_TYPE_NO_OP_COMMAND 23\r
175	#define TRB_TYPE_TRANS_EVENT 32\r
176	#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
177	#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
178	#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
179	#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
180	#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
181	\r
182	//\r
183	// Convert millisecond to microsecond.\r
184	//\r
185	#define XHC_1_MILLISECOND (1000)\r
186	#define XHC_POLL_DELAY (1000)\r
187	#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
188	\r
189	#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
190	#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
191	#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
192	#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
193	\r
194	//\r
195	// Transfer types, used in URB to identify the transfer type\r
196	//\r
197	#define XHC_CTRL_TRANSFER 0x01\r
198	#define XHC_BULK_TRANSFER 0x02\r
199	#define XHC_INT_TRANSFER_SYNC 0x04\r
200	#define XHC_INT_TRANSFER_ASYNC 0x08\r
201	#define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r
202	\r
203	//\r
204	// USB Transfer Results\r
205	//\r
206	#define EFI_USB_NOERROR 0x00\r
207	#define EFI_USB_ERR_NOTEXECUTE 0x01\r
208	#define EFI_USB_ERR_STALL 0x02\r
209	#define EFI_USB_ERR_BUFFER 0x04\r
210	#define EFI_USB_ERR_BABBLE 0x08\r
211	#define EFI_USB_ERR_NAK 0x10\r
212	#define EFI_USB_ERR_CRC 0x20\r
213	#define EFI_USB_ERR_TIMEOUT 0x40\r
214	#define EFI_USB_ERR_BITSTUFF 0x80\r
215	#define EFI_USB_ERR_SYSTEM 0x100\r
216	\r
217	#pragma pack(1)\r
218	\r
219	//\r
220	// 7.6.9 OUT/IN EP Context: 64 bytes\r
221	// 7.6.9.2 When used by the DbC it is always a 64 byte data structure\r
222	//\r
223	typedef struct _ENDPOINT_CONTEXT_64 {\r
224	UINT32 EPState:3;\r
225	UINT32 RsvdZ1:5;\r
226	UINT32 Mult:2; // set to 0\r
227	UINT32 MaxPStreams:5; // set to 0\r
228	UINT32 LSA:1; // set to 0\r
229	UINT32 Interval:8; // set to 0\r
230	UINT32 RsvdZ2:8;\r
231	\r
232	UINT32 RsvdZ3:1;\r
233	UINT32 CErr:2;\r
234	UINT32 EPType:3;\r
235	UINT32 RsvdZ4:1;\r
236	UINT32 HID:1; // set to 0\r
237	UINT32 MaxBurstSize:8;\r
238	UINT32 MaxPacketSize:16;\r
239	\r
240	UINT32 PtrLo;\r
241	\r
242	UINT32 PtrHi;\r
243	\r
244	UINT32 AverageTRBLength:16;\r
245	UINT32 MaxESITPayload:16; // set to 0\r
246	\r
247	UINT32 RsvdZ5; // Reserved\r
248	UINT32 RsvdZ6;\r
249	UINT32 RsvdZ7;\r
250	\r
251	UINT32 RsvdZ8;\r
252	UINT32 RsvdZ9;\r
253	UINT32 RsvdZ10;\r
254	UINT32 RsvdZ11;\r
255	\r
256	UINT32 RsvdZ12;\r
257	UINT32 RsvdZ13;\r
258	UINT32 RsvdZ14;\r
259	UINT32 RsvdZ15;\r
260	} ENDPOINT_CONTEXT_64;\r
261	\r
262	//\r
263	// 6.4.1.1 Normal TRB: 16 bytes\r
264	// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
265	// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
266	// Rings, and to define the Data stage information for Control Transfer Rings.\r
267	//\r
268	typedef struct _TRANSFER_TRB_NORMAL {\r
269	UINT32 TRBPtrLo;\r
270	\r
271	UINT32 TRBPtrHi;\r
272	\r
273	UINT32 Length:17;\r
274	UINT32 TDSize:5;\r
275	UINT32 IntTarget:10;\r
276	\r
277	UINT32 CycleBit:1;\r
278	UINT32 ENT:1;\r
279	UINT32 ISP:1;\r
280	UINT32 NS:1;\r
281	UINT32 CH:1;\r
282	UINT32 IOC:1;\r
283	UINT32 IDT:1;\r
284	UINT32 RsvdZ1:2;\r
285	UINT32 BEI:1;\r
286	UINT32 Type:6;\r
287	UINT32 RsvdZ2:16;\r
288	} TRANSFER_TRB_NORMAL;\r
289	\r
290	//\r
291	// 6.4.2.1 Transfer Event TRB: 16 bytes\r
292	// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
293	// for more information on the use and operation of Transfer Events.\r
294	//\r
295	typedef struct _EVT_TRB_TRANSFER {\r
296	UINT32 TRBPtrLo;\r
297	\r
298	UINT32 TRBPtrHi;\r
299	\r
300	UINT32 Length:24;\r
301	UINT32 Completecode:8;\r
302	\r
303	UINT32 CycleBit:1;\r
304	UINT32 RsvdZ1:1;\r
305	UINT32 ED:1;\r
306	UINT32 RsvdZ2:7;\r
307	UINT32 Type:6;\r
308	UINT32 EndpointId:5;\r
309	UINT32 RsvdZ3:3;\r
310	UINT32 SlotId:8;\r
311	} EVT_TRB_TRANSFER;\r
312	\r
313	//\r
314	// 6.4.4.1 Link TRB: 16 bytes\r
315	// A Link TRB provides support for non-contiguous TRB Rings.\r
316	//\r
317	typedef struct _LINK_TRB {\r
318	UINT32 PtrLo;\r
319	\r
320	UINT32 PtrHi;\r
321	\r
322	UINT32 RsvdZ1:22;\r
323	UINT32 InterTarget:10;\r
324	\r
325	UINT32 CycleBit:1;\r
326	UINT32 TC:1;\r
327	UINT32 RsvdZ2:2;\r
328	UINT32 CH:1;\r
329	UINT32 IOC:1;\r
330	UINT32 RsvdZ3:4;\r
331	UINT32 Type:6;\r
332	UINT32 RsvdZ4:16;\r
333	} LINK_TRB;\r
334	\r
335	//\r
336	// TRB Template: 16 bytes\r
337	//\r
338	typedef struct _TRB_TEMPLATE {\r
339	UINT32 Parameter1;\r
340	\r
341	UINT32 Parameter2;\r
342	\r
343	UINT32 Status;\r
344	\r
345	UINT32 CycleBit:1;\r
346	UINT32 RsvdZ1:9;\r
347	UINT32 Type:6;\r
348	UINT32 Control:16;\r
349	} TRB_TEMPLATE;\r
350	\r
351	//\r
352	// Refer to XHCI 6.5 Event Ring Segment Table: 16 bytes\r
353	//\r
354	typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
355	UINT32 PtrLo;\r
356	UINT32 PtrHi;\r
357	UINT32 RingTrbSize:16;\r
358	UINT32 RsvdZ1:16;\r
359	UINT32 RsvdZ2;\r
360	} EVENT_RING_SEG_TABLE_ENTRY;\r
361	\r
362	//\r
363	// Size: 40 bytes\r
364	//\r
365	typedef struct _EVENT_RING {\r
366	EFI_PHYSICAL_ADDRESS ERSTBase;\r
367	EFI_PHYSICAL_ADDRESS EventRingSeg0;\r
368	UINT32 TrbNumber;\r
369	EFI_PHYSICAL_ADDRESS EventRingEnqueue;\r
370	EFI_PHYSICAL_ADDRESS EventRingDequeue;\r
371	UINT32 EventRingCCS;\r
372	} EVENT_RING;\r
373	\r
374	// Size: 32 bytes\r
375	typedef struct _TRANSFER_RING {\r
376	EFI_PHYSICAL_ADDRESS RingSeg0;\r
377	UINT32 TrbNumber;\r
378	EFI_PHYSICAL_ADDRESS RingEnqueue;\r
379	EFI_PHYSICAL_ADDRESS RingDequeue;\r
380	UINT32 RingPCS;\r
381	} TRANSFER_RING;\r
382	\r
383	//\r
384	// Size: 64 bytes\r
385	//\r
386	typedef struct _DBC_INFO_CONTEXT {\r
387	UINT64 String0DescAddress;\r
388	UINT64 ManufacturerStrDescAddress;\r
389	UINT64 ProductStrDescAddress;\r
390	UINT64 SerialNumberStrDescAddress;\r
391	UINT64 String0Length:8;\r
392	UINT64 ManufacturerStrLength:8;\r
393	UINT64 ProductStrLength:8;\r
394	UINT64 SerialNumberStrLength:8;\r
395	UINT64 RsvdZ1:32;\r
396	UINT64 RsvdZ2;\r
397	UINT64 RsvdZ3;\r
398	UINT64 RsvdZ4; \r
399	} DBC_INFO_CONTEXT;\r
400	\r
401	//\r
402	// Debug Capability Context Data Structure: 192 bytes\r
403	//\r
404	typedef struct _XHC_DC_CONTEXT {\r
405	DBC_INFO_CONTEXT DbcInfoContext;\r
406	ENDPOINT_CONTEXT_64 EpOutContext;\r
407	ENDPOINT_CONTEXT_64 EpInContext;\r
408	} XHC_DC_CONTEXT;\r
409	\r
410	//\r
411	// Size: 16 bytes\r
412	//\r
413	typedef union _TRB {\r
414	TRB_TEMPLATE TrbTemplate;\r
415	TRANSFER_TRB_NORMAL TrbNormal;\r
416	} TRB;\r
417	\r
418	///\r
419	/// USB data transfer direction\r
420	///\r
421	typedef enum {\r
422	EfiUsbDataIn,\r
423	EfiUsbDataOut,\r
424	EfiUsbNoData\r
425	} EFI_USB_DATA_DIRECTION;\r
426	\r
427	//\r
428	// URB (Usb Request Block) contains information for all kinds of\r
429	// usb requests.\r
430	//\r
431	typedef struct _URB {\r
432	//\r
433	// Transfer data buffer\r
434	//\r
435	EFI_PHYSICAL_ADDRESS Data;\r
436	UINT32 DataLen;\r
437	\r
438	//\r
439	// Execute result\r
440	//\r
441	UINT32 Result;\r
442	//\r
443	// Completed data length\r
444	//\r
445	UINT32 Completed;\r
446	//\r
447	// Tranfer Ring info\r
448	//\r
449	EFI_PHYSICAL_ADDRESS Ring;\r
450	EFI_PHYSICAL_ADDRESS Trb;\r
451	BOOLEAN Finished;\r
452	EFI_USB_DATA_DIRECTION Direction;\r
453	} URB;\r
454	\r
455	typedef struct _USB3_DEBUG_PORT_INSTANCE {\r
456	UINT8 Initialized;\r
457	\r
458	//\r
1f279e7a	459	// The flag indicates debug device is ready\r
2cb6eabe EL	460	//\r
	461	BOOLEAN DebugSupport;\r
	462	\r
	463	//\r
	464	// The flag indicates debug device is ready\r
	465	//\r
	466	BOOLEAN Ready;\r
	467	\r
	468	//\r
	469	// The flag indicates if USB 3.0 ports has been turn off/on power\r
	470	// \r
	471	BOOLEAN ChangePortPower;\r
	472	\r
	473	//\r
	474	// XHCI MMIO Base address\r
	475	//\r
	476	EFI_PHYSICAL_ADDRESS XhciMmioBase;\r
	477	\r
	478	//\r
	479	// XHCI OP RegisterBase address\r
	480	// \r
	481	EFI_PHYSICAL_ADDRESS XhciOpRegister;\r
	482	\r
	483	//\r
	484	// XHCI Debug Register Base Address\r
	485	//\r
	486	EFI_PHYSICAL_ADDRESS DebugCapabilityBase;\r
	487	\r
	488	//\r
	489	// XHCI Debug Capability offset\r
	490	//\r
	491	UINT64 DebugCapabilityOffset; \r
	492	\r
	493	//\r
	494	// XHCI Debug Context Address\r
	495	//\r
	496	EFI_PHYSICAL_ADDRESS DebugCapabilityContext;\r
	497	\r
	498	//\r
	499	// Transfer Ring\r
	500	//\r
	501	TRANSFER_RING TransferRingOut;\r
	502	TRANSFER_RING TransferRingIn;\r
	503	\r
	504	//\r
	505	// EventRing\r
	506	//\r
	507	EVENT_RING EventRing;\r
	508	\r
	509	//\r
	510	// URB - Read\r
	511	//\r
	512	URB UrbOut;\r
	513	\r
	514	//\r
	515	// URB - Write\r
	516	//\r
	517	URB UrbIn;\r
	518	\r
	519	//\r
	520	// The available data length in the following data buffer.\r
	521	//\r
	522	UINT8 DataCount;\r
	523	//\r
5d6507a1	524	// The data buffer address for data read and poll.\r
2cb6eabe	525	//\r
5d6507a1	526	EFI_PHYSICAL_ADDRESS Data;\r
2cb6eabe EL	527	} USB3_DEBUG_PORT_HANDLE;\r
	528	\r
	529	#pragma pack()\r
	530	\r
	531	/**\r
	532	Read XHCI debug register.\r
	533	\r
	534	@param Handle Debug port handle.\r
	535	@param Offset The offset of the debug register.\r
	536	\r
	537	@return The register content read\r
	538	\r
	539	**/\r
	540	UINT32\r
	541	XhcReadDebugReg (\r
	542	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
	543	IN UINT32 Offset\r
	544	);\r
	545	\r
	546	/**\r
	547	Set one bit of the debug register while keeping other bits.\r
	548	\r
	549	@param Handle Debug port handle.\r
	550	@param Offset The offset of the debug register.\r
	551	@param Bit The bit mask of the register to set.\r
	552	\r
	553	**/\r
	554	VOID\r
	555	XhcSetDebugRegBit (\r
	556	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
	557	IN UINT32 Offset,\r
	558	IN UINT32 Bit\r
	559	);\r
	560	\r
	561	/**\r
	562	Write the data to the debug register.\r
	563	\r
	564	@param Handle Debug port handle.\r
	565	@param Offset The offset of the debug register.\r
	566	@param Data The data to write.\r
	567	\r
	568	**/ \r
	569	VOID\r
	570	XhcWriteDebugReg (\r
	571	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
	572	IN UINT32 Offset,\r
	573	IN UINT32 Data\r
	574	);\r
	575	\r
	576	/**\r
	577	Discover the USB3 debug device.\r
	578	\r
	579	@param Handle Debug port handle.\r
	580	\r
	581	@retval RETURN_SUCCESS The serial device was initialized.\r
	582	@retval RETURN_DEVICE_ERROR The serial device could not be initialized.\r
	583	\r
	584	**/\r
	585	RETURN_STATUS\r
	586	DiscoverUsb3DebugPort(\r
	587	USB3_DEBUG_PORT_HANDLE *Handle\r
	588	);\r
	589	\r
	590	/**\r
591	Initialize the Serial Device hardware.\r
592	\r
593	@param Handle Debug port handle.\r
594	\r
595	@retval RETURN_SUCCESS The serial device was initialized successfully.\r
596	@retval !RETURN_SUCCESS Error.\r
597	\r
598	**/\r
599	RETURN_STATUS\r
600	InitializeUsb3DebugPort (\r
601	USB3_DEBUG_PORT_HANDLE *Handle\r
602	);\r
603	\r
604	/**\r
605	Return XHCI MMIO base address.\r
606	\r
607	**/\r
608	EFI_PHYSICAL_ADDRESS\r
609	GetXhciBaseAddress (\r
610	VOID\r
611	);\r
612	\r
613	/**\r
614	Verifies if the bit positions specified by a mask are set in a register.\r
615	\r
616	@param[in, out] Register UNITN register\r
617	@param[in] BitMask 32-bit mask\r
618	\r
619	@return BOOLEAN - TRUE if all bits specified by the mask are enabled.\r
620	- FALSE even if one of the bits specified by the mask \r
621	is not enabled.\r
622	**/\r
623	BOOLEAN\r
624	XhcIsBitSet(\r
625	UINTN Register, \r
626	UINT32 BitMask\r
627	);\r
628	\r
629	/**\r
630	Sets bits as per the enabled bit positions in the mask.\r
631	\r
632	@param[in, out] Register UINTN register\r
633	@param[in] BitMask 32-bit mask\r
634	**/\r
635	VOID\r
636	XhcSetR32Bit(\r
637	UINTN Register, \r
638	UINT32 BitMask\r
639	);\r
640	\r
641	/**\r
642	Clears bits as per the enabled bit positions in the mask.\r
643	\r
644	@param[in, out] Register UINTN register\r
645	@param[in] BitMask 32-bit mask\r
646	**/\r
647	VOID\r
648	XhcClearR32Bit(\r
649	IN OUT UINTN Register, \r
650	IN UINT32 BitMask\r
651	);\r
652	\r
653	/**\r
654	Initialize USB3 debug port.\r
655	\r
656	This method invokes various internal functions to facilitate\r
657	detection and initialization of USB3 debug port.\r
658	\r
659	@retval RETURN_SUCCESS The serial device was initialized.\r
660	**/\r
661	RETURN_STATUS\r
662	EFIAPI\r
663	USB3Initialize (\r
664	VOID\r
665	);\r
666	\r
667	/**\r
668	Return command register value in XHCI controller.\r
669	\r
670	**/\r
671	UINT16\r
672	GetXhciPciCommand (\r
673	VOID\r
674	);\r
675	\r
676	/**\r
677	Allocate aligned memory for XHC's usage.\r
678	\r
679	@param BufferSize The size, in bytes, of the Buffer.\r
680	\r
681	@return A pointer to the allocated buffer or NULL if allocation fails.\r
682	\r
683	**/\r
684	VOID*\r
685	AllocateAlignBuffer (\r
686	IN UINTN BufferSize\r
687	);\r
688	\r
689	/**\r
690	The real function to initialize USB3 debug port.\r
691	\r
692	This method invokes various internal functions to facilitate\r
693	detection and initialization of USB3 debug port.\r
694	\r
695	@retval RETURN_SUCCESS The serial device was initialized.\r
696	**/\r
697	RETURN_STATUS\r
698	EFIAPI\r
699	USB3InitializeReal (\r
700	VOID\r
701	);\r
702	\r
703	/**\r
704	Submits bulk transfer to a bulk endpoint of a USB device.\r
705	\r
706	@param Handle The instance of debug device.\r
707	@param Direction The direction of data transfer.\r
708	@param Data Array of pointers to the buffers of data to transmit\r
709	from or receive into.\r
710	@param DataLength The lenght of the data buffer.\r
711	@param Timeout Indicates the maximum time, in millisecond, which\r
712	the transfer is allowed to complete.\r
713	\r
714	@retval EFI_SUCCESS The transfer was completed successfully.\r
715	@retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r
716	@retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
717	@retval EFI_TIMEOUT The transfer failed due to timeout.\r
718	@retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r
719	\r
720	**/\r
721	EFI_STATUS\r
722	EFIAPI\r
723	XhcDataTransfer (\r
724	IN USB3_DEBUG_PORT_HANDLE *Handle,\r
725	IN EFI_USB_DATA_DIRECTION Direction,\r
726	IN OUT VOID *Data,\r
727	IN OUT UINTN *DataLength,\r
728	IN UINTN Timeout\r
729	);\r
730	\r
2cb6eabe	731	#endif //__SERIAL_PORT_LIB_USB__\r