[mirror_edk2.git] / StandaloneMmPkg / Library / StandaloneMmCoreEntryPoint / AArch64 / CreateHobList.c

/** @file\r
  Creates HOB during Standalone MM Foundation entry point\r
  on ARM platforms.\r
\r
Copyright (c) 2017 - 2018, ARM Ltd. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php.\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#include <PiMm.h>\r
\r
#include <PiPei.h>\r
#include <Guid/MmramMemoryReserve.h>\r
#include <Guid/MpInformation.h>\r
\r
#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>\r
#include <Library/ArmMmuLib.h>\r
#include <Library/ArmSvcLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/SerialPortLib.h>\r
\r
#include <IndustryStandard/ArmStdSmc.h>\r
\r
extern EFI_HOB_HANDOFF_INFO_TABLE*\r
HobConstructor (\r
  IN VOID   *EfiMemoryBegin,\r
  IN UINTN  EfiMemoryLength,\r
  IN VOID   *EfiFreeMemoryBottom,\r
  IN VOID   *EfiFreeMemoryTop\r
  );\r
\r
// GUID to identify HOB with whereabouts of communication buffer with Normal\r
// World\r
extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;\r
\r
// GUID to identify HOB where the entry point of the CPU driver will be\r
// populated to allow this entry point driver to invoke it upon receipt of an\r
// event\r
extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;\r
\r
/**\r
  Use the boot information passed by privileged firmware to populate a HOB list\r
  suitable for consumption by the MM Core and drivers.\r
\r
  @param  PayloadBootInfo    Boot information passed by privileged firmware\r
\r
**/\r
VOID *\r
CreateHobListFromBootInfo (\r
  IN  OUT  PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,\r
  IN       EFI_SECURE_PARTITION_BOOT_INFO     *PayloadBootInfo\r
)\r
{\r
  EFI_HOB_HANDOFF_INFO_TABLE      *HobStart;\r
  EFI_RESOURCE_ATTRIBUTE_TYPE     Attributes;\r
  UINT32                          Index;\r
  UINT32                          BufferSize;\r
  UINT32                          Flags;\r
  EFI_MMRAM_HOB_DESCRIPTOR_BLOCK  *MmramRangesHob;\r
  EFI_MMRAM_DESCRIPTOR            *MmramRanges;\r
  EFI_MMRAM_DESCRIPTOR            *NsCommBufMmramRange;\r
  MP_INFORMATION_HOB_DATA         *MpInformationHobData;\r
  EFI_PROCESSOR_INFORMATION       *ProcInfoBuffer;\r
  EFI_SECURE_PARTITION_CPU_INFO   *CpuInfo;\r
  ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;\r
\r
  // Create a hoblist with a PHIT and EOH\r
  HobStart = HobConstructor (\r
               (VOID *) PayloadBootInfo->SpMemBase,\r
               (UINTN)  PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,\r
               (VOID *) PayloadBootInfo->SpHeapBase,\r
               (VOID *) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)\r
               );\r
\r
  // Check that the Hoblist starts at the bottom of the Heap\r
  ASSERT (HobStart == (VOID *) PayloadBootInfo->SpHeapBase);\r
\r
  // Build a Boot Firmware Volume HOB\r
  BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);\r
\r
  // Build a resource descriptor Hob that describes the available physical\r
  // memory range\r
  Attributes = (\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
    EFI_RESOURCE_ATTRIBUTE_TESTED |\r
    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
  );\r
\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
    Attributes,\r
    (UINTN) PayloadBootInfo->SpMemBase,\r
    PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase\r
    );\r
\r
  // Find the size of the GUIDed HOB with MP information\r
  BufferSize = sizeof (MP_INFORMATION_HOB_DATA);\r
  BufferSize += sizeof (EFI_PROCESSOR_INFORMATION) * PayloadBootInfo->NumCpus;\r
\r
  // Create a Guided MP information HOB to enable the ARM TF CPU driver to\r
  // perform per-cpu allocations.\r
  MpInformationHobData = BuildGuidHob (&gMpInformationHobGuid, BufferSize);\r
\r
  // Populate the MP information HOB with the topology information passed by\r
  // privileged firmware\r
  MpInformationHobData->NumberOfProcessors = PayloadBootInfo->NumCpus;\r
  MpInformationHobData->NumberOfEnabledProcessors = PayloadBootInfo->NumCpus;\r
  ProcInfoBuffer = MpInformationHobData->ProcessorInfoBuffer;\r
  CpuInfo = PayloadBootInfo->CpuInfo;\r
\r
  for (Index = 0; Index < PayloadBootInfo->NumCpus; Index++) {\r
    ProcInfoBuffer[Index].ProcessorId      = CpuInfo[Index].Mpidr;\r
    ProcInfoBuffer[Index].Location.Package = GET_CLUSTER_ID(CpuInfo[Index].Mpidr);\r
    ProcInfoBuffer[Index].Location.Core    = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
    ProcInfoBuffer[Index].Location.Thread  = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
\r
    Flags = PROCESSOR_ENABLED_BIT | PROCESSOR_HEALTH_STATUS_BIT;\r
    if (CpuInfo[Index].Flags & CPU_INFO_FLAG_PRIMARY_CPU) {\r
      Flags |= PROCESSOR_AS_BSP_BIT;\r
    }\r
    ProcInfoBuffer[Index].StatusFlag = Flags;\r
  }\r
\r
  // Create a Guided HOB to tell the ARM TF CPU driver the location and length\r
  // of the communication buffer shared with the Normal world.\r
  NsCommBufMmramRange = (EFI_MMRAM_DESCRIPTOR *) BuildGuidHob (\r
                                                   &gEfiStandaloneMmNonSecureBufferGuid,\r
                                                   sizeof (EFI_MMRAM_DESCRIPTOR)\r
                                                   );\r
  NsCommBufMmramRange->PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
  NsCommBufMmramRange->CpuStart      = PayloadBootInfo->SpNsCommBufBase;\r
  NsCommBufMmramRange->PhysicalSize  = PayloadBootInfo->SpNsCommBufSize;\r
  NsCommBufMmramRange->RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Create a Guided HOB to enable the ARM TF CPU driver to share its entry\r
  // point and populate it with the address of the shared buffer\r
  CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *) BuildGuidHob (\r
                                                                  &gEfiArmTfCpuDriverEpDescriptorGuid,\r
                                                                  sizeof (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)\r
                                                                  );\r
\r
  *CpuDriverEntryPoint = NULL;\r
  CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr = CpuDriverEntryPoint;\r
\r
  // Find the size of the GUIDed HOB with SRAM ranges\r
  BufferSize = sizeof (EFI_MMRAM_HOB_DESCRIPTOR_BLOCK);\r
  BufferSize += PayloadBootInfo->NumSpMemRegions * sizeof (EFI_MMRAM_DESCRIPTOR);\r
\r
  // Create a GUIDed HOB with SRAM ranges\r
  MmramRangesHob = BuildGuidHob (&gEfiMmPeiMmramMemoryReserveGuid, BufferSize);\r
\r
  // Fill up the number of MMRAM memory regions\r
  MmramRangesHob->NumberOfMmReservedRegions = PayloadBootInfo->NumSpMemRegions;\r
  // Fill up the MMRAM ranges\r
  MmramRanges = &MmramRangesHob->Descriptor[0];\r
\r
  // Base and size of memory occupied by the Standalone MM image\r
  MmramRanges[0].PhysicalStart = PayloadBootInfo->SpImageBase;\r
  MmramRanges[0].CpuStart      = PayloadBootInfo->SpImageBase;\r
  MmramRanges[0].PhysicalSize  = PayloadBootInfo->SpImageSize;\r
  MmramRanges[0].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of buffer shared with privileged Secure world software\r
  MmramRanges[1].PhysicalStart = PayloadBootInfo->SpSharedBufBase;\r
  MmramRanges[1].CpuStart      = PayloadBootInfo->SpSharedBufBase;\r
  MmramRanges[1].PhysicalSize  = PayloadBootInfo->SpPcpuSharedBufSize * PayloadBootInfo->NumCpus;\r
  MmramRanges[1].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of buffer used for synchronous communication with Normal\r
  // world software\r
  MmramRanges[2].PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
  MmramRanges[2].CpuStart      = PayloadBootInfo->SpNsCommBufBase;\r
  MmramRanges[2].PhysicalSize  = PayloadBootInfo->SpNsCommBufSize;\r
  MmramRanges[2].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of memory allocated for stacks for all cpus\r
  MmramRanges[3].PhysicalStart = PayloadBootInfo->SpStackBase;\r
  MmramRanges[3].CpuStart      = PayloadBootInfo->SpStackBase;\r
  MmramRanges[3].PhysicalSize  = PayloadBootInfo->SpPcpuStackSize * PayloadBootInfo->NumCpus;\r
  MmramRanges[3].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of heap memory shared by all cpus\r
  MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) HobStart;\r
  MmramRanges[4].CpuStart      = (EFI_PHYSICAL_ADDRESS) HobStart;\r
  MmramRanges[4].PhysicalSize  = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) HobStart;\r
  MmramRanges[4].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;\r
\r
  // Base and size of heap memory shared by all cpus\r
  MmramRanges[5].PhysicalStart = HobStart->EfiFreeMemoryBottom;\r
  MmramRanges[5].CpuStart      = HobStart->EfiFreeMemoryBottom;\r
  MmramRanges[5].PhysicalSize  = HobStart->EfiFreeMemoryTop - HobStart->EfiFreeMemoryBottom;\r
  MmramRanges[5].RegionState   = EFI_CACHEABLE;\r
\r
  return HobStart;\r
}\r
Commit	Line	Data
184558d0 SV	1	/** @file\r
	2	Creates HOB during Standalone MM Foundation entry point\r
	3	on ARM platforms.\r
	4	\r
	5	Copyright (c) 2017 - 2018, ARM Ltd. All rights reserved.<BR>\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php.\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	\r
	17	#include <PiMm.h>\r
	18	\r
	19	#include <PiPei.h>\r
	20	#include <Guid/MmramMemoryReserve.h>\r
	21	#include <Guid/MpInformation.h>\r
	22	\r
	23	#include <Library/AArch64/StandaloneMmCoreEntryPoint.h>\r
	24	#include <Library/ArmMmuLib.h>\r
	25	#include <Library/ArmSvcLib.h>\r
	26	#include <Library/DebugLib.h>\r
	27	#include <Library/HobLib.h>\r
	28	#include <Library/BaseLib.h>\r
	29	#include <Library/BaseMemoryLib.h>\r
	30	#include <Library/SerialPortLib.h>\r
	31	\r
	32	#include <IndustryStandard/ArmStdSmc.h>\r
	33	\r
	34	extern EFI_HOB_HANDOFF_INFO_TABLE*\r
	35	HobConstructor (\r
	36	IN VOID *EfiMemoryBegin,\r
	37	IN UINTN EfiMemoryLength,\r
	38	IN VOID *EfiFreeMemoryBottom,\r
	39	IN VOID *EfiFreeMemoryTop\r
	40	);\r
	41	\r
	42	// GUID to identify HOB with whereabouts of communication buffer with Normal\r
	43	// World\r
	44	extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;\r
	45	\r
	46	// GUID to identify HOB where the entry point of the CPU driver will be\r
	47	// populated to allow this entry point driver to invoke it upon receipt of an\r
	48	// event\r
	49	extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;\r
	50	\r
	51	/**\r
	52	Use the boot information passed by privileged firmware to populate a HOB list\r
	53	suitable for consumption by the MM Core and drivers.\r
	54	\r
	55	@param PayloadBootInfo Boot information passed by privileged firmware\r
	56	\r
	57	**/\r
	58	VOID *\r
	59	CreateHobListFromBootInfo (\r
	60	IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,\r
	61	IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo\r
	62	)\r
	63	{\r
	64	EFI_HOB_HANDOFF_INFO_TABLE *HobStart;\r
65	EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;\r
66	UINT32 Index;\r
67	UINT32 BufferSize;\r
68	UINT32 Flags;\r
69	EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;\r
70	EFI_MMRAM_DESCRIPTOR *MmramRanges;\r
71	EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;\r
72	MP_INFORMATION_HOB_DATA *MpInformationHobData;\r
73	EFI_PROCESSOR_INFORMATION *ProcInfoBuffer;\r
74	EFI_SECURE_PARTITION_CPU_INFO *CpuInfo;\r
75	ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;\r
76	\r
77	// Create a hoblist with a PHIT and EOH\r
78	HobStart = HobConstructor (\r
79	(VOID *) PayloadBootInfo->SpMemBase,\r
80	(UINTN) PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase,\r
81	(VOID *) PayloadBootInfo->SpHeapBase,\r
82	(VOID *) (PayloadBootInfo->SpHeapBase + PayloadBootInfo->SpHeapSize)\r
83	);\r
84	\r
85	// Check that the Hoblist starts at the bottom of the Heap\r
86	ASSERT (HobStart == (VOID *) PayloadBootInfo->SpHeapBase);\r
87	\r
88	// Build a Boot Firmware Volume HOB\r
89	BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);\r
90	\r
91	// Build a resource descriptor Hob that describes the available physical\r
92	// memory range\r
93	Attributes = (\r
94	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
95	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
96	EFI_RESOURCE_ATTRIBUTE_TESTED \|\r
97	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
98	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
99	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
100	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
101	);\r
102	\r
103	BuildResourceDescriptorHob (\r
104	EFI_RESOURCE_SYSTEM_MEMORY,\r
105	Attributes,\r
106	(UINTN) PayloadBootInfo->SpMemBase,\r
107	PayloadBootInfo->SpMemLimit - PayloadBootInfo->SpMemBase\r
108	);\r
109	\r
110	// Find the size of the GUIDed HOB with MP information\r
111	BufferSize = sizeof (MP_INFORMATION_HOB_DATA);\r
112	BufferSize += sizeof (EFI_PROCESSOR_INFORMATION) * PayloadBootInfo->NumCpus;\r
113	\r
114	// Create a Guided MP information HOB to enable the ARM TF CPU driver to\r
115	// perform per-cpu allocations.\r
116	MpInformationHobData = BuildGuidHob (&gMpInformationHobGuid, BufferSize);\r
117	\r
118	// Populate the MP information HOB with the topology information passed by\r
119	// privileged firmware\r
120	MpInformationHobData->NumberOfProcessors = PayloadBootInfo->NumCpus;\r
121	MpInformationHobData->NumberOfEnabledProcessors = PayloadBootInfo->NumCpus;\r
122	ProcInfoBuffer = MpInformationHobData->ProcessorInfoBuffer;\r
123	CpuInfo = PayloadBootInfo->CpuInfo;\r
124	\r
125	for (Index = 0; Index < PayloadBootInfo->NumCpus; Index++) {\r
126	ProcInfoBuffer[Index].ProcessorId = CpuInfo[Index].Mpidr;\r
127	ProcInfoBuffer[Index].Location.Package = GET_CLUSTER_ID(CpuInfo[Index].Mpidr);\r
128	ProcInfoBuffer[Index].Location.Core = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
129	ProcInfoBuffer[Index].Location.Thread = GET_CORE_ID(CpuInfo[Index].Mpidr);\r
130	\r
131	Flags = PROCESSOR_ENABLED_BIT \| PROCESSOR_HEALTH_STATUS_BIT;\r
132	if (CpuInfo[Index].Flags & CPU_INFO_FLAG_PRIMARY_CPU) {\r
133	Flags \|= PROCESSOR_AS_BSP_BIT;\r
134	}\r
135	ProcInfoBuffer[Index].StatusFlag = Flags;\r
136	}\r
137	\r
138	// Create a Guided HOB to tell the ARM TF CPU driver the location and length\r
139	// of the communication buffer shared with the Normal world.\r
140	NsCommBufMmramRange = (EFI_MMRAM_DESCRIPTOR *) BuildGuidHob (\r
141	&gEfiStandaloneMmNonSecureBufferGuid,\r
142	sizeof (EFI_MMRAM_DESCRIPTOR)\r
143	);\r
144	NsCommBufMmramRange->PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
145	NsCommBufMmramRange->CpuStart = PayloadBootInfo->SpNsCommBufBase;\r
146	NsCommBufMmramRange->PhysicalSize = PayloadBootInfo->SpNsCommBufSize;\r
147	NsCommBufMmramRange->RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
148	\r
149	// Create a Guided HOB to enable the ARM TF CPU driver to share its entry\r
150	// point and populate it with the address of the shared buffer\r
151	CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *) BuildGuidHob (\r
152	&gEfiArmTfCpuDriverEpDescriptorGuid,\r
153	sizeof (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)\r
154	);\r
155	\r
156	*CpuDriverEntryPoint = NULL;\r
157	CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr = CpuDriverEntryPoint;\r
158	\r
159	// Find the size of the GUIDed HOB with SRAM ranges\r
160	BufferSize = sizeof (EFI_MMRAM_HOB_DESCRIPTOR_BLOCK);\r
161	BufferSize += PayloadBootInfo->NumSpMemRegions * sizeof (EFI_MMRAM_DESCRIPTOR);\r
162	\r
163	// Create a GUIDed HOB with SRAM ranges\r
164	MmramRangesHob = BuildGuidHob (&gEfiMmPeiMmramMemoryReserveGuid, BufferSize);\r
165	\r
166	// Fill up the number of MMRAM memory regions\r
167	MmramRangesHob->NumberOfMmReservedRegions = PayloadBootInfo->NumSpMemRegions;\r
168	// Fill up the MMRAM ranges\r
169	MmramRanges = &MmramRangesHob->Descriptor[0];\r
170	\r
171	// Base and size of memory occupied by the Standalone MM image\r
172	MmramRanges[0].PhysicalStart = PayloadBootInfo->SpImageBase;\r
173	MmramRanges[0].CpuStart = PayloadBootInfo->SpImageBase;\r
174	MmramRanges[0].PhysicalSize = PayloadBootInfo->SpImageSize;\r
175	MmramRanges[0].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
176	\r
177	// Base and size of buffer shared with privileged Secure world software\r
178	MmramRanges[1].PhysicalStart = PayloadBootInfo->SpSharedBufBase;\r
179	MmramRanges[1].CpuStart = PayloadBootInfo->SpSharedBufBase;\r
180	MmramRanges[1].PhysicalSize = PayloadBootInfo->SpPcpuSharedBufSize * PayloadBootInfo->NumCpus;\r
181	MmramRanges[1].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
182	\r
183	// Base and size of buffer used for synchronous communication with Normal\r
184	// world software\r
185	MmramRanges[2].PhysicalStart = PayloadBootInfo->SpNsCommBufBase;\r
186	MmramRanges[2].CpuStart = PayloadBootInfo->SpNsCommBufBase;\r
187	MmramRanges[2].PhysicalSize = PayloadBootInfo->SpNsCommBufSize;\r
188	MmramRanges[2].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
189	\r
190	// Base and size of memory allocated for stacks for all cpus\r
191	MmramRanges[3].PhysicalStart = PayloadBootInfo->SpStackBase;\r
192	MmramRanges[3].CpuStart = PayloadBootInfo->SpStackBase;\r
193	MmramRanges[3].PhysicalSize = PayloadBootInfo->SpPcpuStackSize * PayloadBootInfo->NumCpus;\r
194	MmramRanges[3].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
195	\r
196	// Base and size of heap memory shared by all cpus\r
197	MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) HobStart;\r
198	MmramRanges[4].CpuStart = (EFI_PHYSICAL_ADDRESS) HobStart;\r
199	MmramRanges[4].PhysicalSize = HobStart->EfiFreeMemoryBottom - (EFI_PHYSICAL_ADDRESS) HobStart;\r
200	MmramRanges[4].RegionState = EFI_CACHEABLE \| EFI_ALLOCATED;\r
201	\r
202	// Base and size of heap memory shared by all cpus\r
203	MmramRanges[5].PhysicalStart = HobStart->EfiFreeMemoryBottom;\r
204	MmramRanges[5].CpuStart = HobStart->EfiFreeMemoryBottom;\r
205	MmramRanges[5].PhysicalSize = HobStart->EfiFreeMemoryTop - HobStart->EfiFreeMemoryBottom;\r
206	MmramRanges[5].RegionState = EFI_CACHEABLE;\r
207	\r
208	return HobStart;\r
209	}\r