[mirror_edk2.git] / Tools / CodeTools / TianoTools / PeCoffLoader / Ipf / PeCoffLoaderEx.c

/*++\r
\r
Copyright (c) 2004, Intel Corporation                                                         \r
All rights reserved. This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
\r
    PeCoffLoaderEx.c\r
\r
Abstract:\r
\r
    Fixes Intel Itanium(TM) specific relocation types\r
\r
\r
Revision History\r
\r
--*/\r
\r
#include <Common/UefiBaseTypes.h>\r
#include <Common/EfiImage.h>\r
#include <Library/PeCoffLib.h>\r
\r
\r
\r
\r
\r
#define EXT_IMM64(Value, Address, Size, InstPos, ValPos)  \\r
    Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)\r
\r
#define INS_IMM64(Value, Address, Size, InstPos, ValPos)  \\r
    *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \\r
          ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)\r
\r
#define IMM64_IMM7B_INST_WORD_X         3  \r
#define IMM64_IMM7B_SIZE_X              7  \r
#define IMM64_IMM7B_INST_WORD_POS_X     4  \r
#define IMM64_IMM7B_VAL_POS_X           0  \r
\r
#define IMM64_IMM9D_INST_WORD_X         3  \r
#define IMM64_IMM9D_SIZE_X              9  \r
#define IMM64_IMM9D_INST_WORD_POS_X     18  \r
#define IMM64_IMM9D_VAL_POS_X           7  \r
\r
#define IMM64_IMM5C_INST_WORD_X         3  \r
#define IMM64_IMM5C_SIZE_X              5  \r
#define IMM64_IMM5C_INST_WORD_POS_X     13  \r
#define IMM64_IMM5C_VAL_POS_X           16  \r
\r
#define IMM64_IC_INST_WORD_X            3  \r
#define IMM64_IC_SIZE_X                 1  \r
#define IMM64_IC_INST_WORD_POS_X        12  \r
#define IMM64_IC_VAL_POS_X              21  \r
\r
#define IMM64_IMM41a_INST_WORD_X        1  \r
#define IMM64_IMM41a_SIZE_X             10  \r
#define IMM64_IMM41a_INST_WORD_POS_X    14  \r
#define IMM64_IMM41a_VAL_POS_X          22  \r
\r
#define IMM64_IMM41b_INST_WORD_X        1  \r
#define IMM64_IMM41b_SIZE_X             8  \r
#define IMM64_IMM41b_INST_WORD_POS_X    24  \r
#define IMM64_IMM41b_VAL_POS_X          32  \r
\r
#define IMM64_IMM41c_INST_WORD_X        2  \r
#define IMM64_IMM41c_SIZE_X             23  \r
#define IMM64_IMM41c_INST_WORD_POS_X    0  \r
#define IMM64_IMM41c_VAL_POS_X          40  \r
\r
#define IMM64_SIGN_INST_WORD_X          3  \r
#define IMM64_SIGN_SIZE_X               1  \r
#define IMM64_SIGN_INST_WORD_POS_X      27  \r
#define IMM64_SIGN_VAL_POS_X            63  \r
\r
RETURN_STATUS\r
PeCoffLoaderRelocateImageEx (\r
  IN UINT16      *Reloc,\r
  IN OUT CHAR8   *Fixup, \r
  IN OUT CHAR8   **FixupData,\r
  IN UINT64      Adjust\r
  )\r
/*++\r
\r
Routine Description:\r
\r
  Performs an Itanium-based specific relocation fixup\r
\r
Arguments:\r
\r
  Reloc      - Pointer to the relocation record\r
\r
  Fixup      - Pointer to the address to fix up\r
\r
  FixupData  - Pointer to a buffer to log the fixups\r
\r
  Adjust     - The offset to adjust the fixup\r
\r
Returns:\r
\r
  Status code\r
\r
--*/\r
{\r
  UINT64      *F64;\r
  UINT64      FixupVal;\r
\r
  switch ((*Reloc) >> 12) {\r
\r
    case EFI_IMAGE_REL_BASED_DIR64:\r
      F64 = (UINT64 *) Fixup;\r
      *F64 = *F64 + (UINT64) Adjust;\r
      if (*FixupData != NULL) {\r
        *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));\r
        *(UINT64 *)(*FixupData) = *F64;\r
        *FixupData = *FixupData + sizeof(UINT64);\r
      }\r
      break;\r
\r
    case EFI_IMAGE_REL_BASED_IA64_IMM64:\r
\r
      //\r
      // Align it to bundle address before fixing up the\r
      // 64-bit immediate value of the movl instruction.\r
      //\r
\r
      Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));\r
      FixupVal = (UINT64)0;\r
                       \r
      // \r
      // Extract the lower 32 bits of IMM64 from bundle\r
      //\r
      EXT_IMM64(FixupVal,\r
                (UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,\r
                IMM64_IMM7B_SIZE_X,\r
                IMM64_IMM7B_INST_WORD_POS_X,\r
                IMM64_IMM7B_VAL_POS_X\r
                );\r
\r
      EXT_IMM64(FixupVal,\r
                (UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,\r
                IMM64_IMM9D_SIZE_X,\r
                IMM64_IMM9D_INST_WORD_POS_X,\r
                IMM64_IMM9D_VAL_POS_X\r
                );\r
\r
      EXT_IMM64(FixupVal,\r
                (UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,\r
                IMM64_IMM5C_SIZE_X,\r
                IMM64_IMM5C_INST_WORD_POS_X,\r
                IMM64_IMM5C_VAL_POS_X\r
                );\r
\r
      EXT_IMM64(FixupVal,\r
                (UINT32 *)Fixup + IMM64_IC_INST_WORD_X,\r
                IMM64_IC_SIZE_X,\r
                IMM64_IC_INST_WORD_POS_X,\r
                IMM64_IC_VAL_POS_X\r
                );\r
\r
      EXT_IMM64(FixupVal,\r
                (UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,\r
                IMM64_IMM41a_SIZE_X,\r
                IMM64_IMM41a_INST_WORD_POS_X,\r
                IMM64_IMM41a_VAL_POS_X\r
                );\r
                       \r
      // \r
      // Update 64-bit address\r
      //\r
      FixupVal += Adjust;\r
\r
      // \r
      // Insert IMM64 into bundle\r
      //\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),\r
                IMM64_IMM7B_SIZE_X,\r
                IMM64_IMM7B_INST_WORD_POS_X,\r
                IMM64_IMM7B_VAL_POS_X\r
                );\r
\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),\r
                IMM64_IMM9D_SIZE_X,\r
                IMM64_IMM9D_INST_WORD_POS_X,\r
                IMM64_IMM9D_VAL_POS_X\r
                );\r
\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),\r
                IMM64_IMM5C_SIZE_X,\r
                IMM64_IMM5C_INST_WORD_POS_X,\r
                IMM64_IMM5C_VAL_POS_X\r
                );\r
\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),\r
                IMM64_IC_SIZE_X,\r
                IMM64_IC_INST_WORD_POS_X,\r
                IMM64_IC_VAL_POS_X\r
                );\r
\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),\r
                IMM64_IMM41a_SIZE_X,\r
                IMM64_IMM41a_INST_WORD_POS_X,\r
                IMM64_IMM41a_VAL_POS_X\r
                );\r
\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),\r
                IMM64_IMM41b_SIZE_X,\r
                IMM64_IMM41b_INST_WORD_POS_X,\r
                IMM64_IMM41b_VAL_POS_X\r
                );\r
\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),\r
                IMM64_IMM41c_SIZE_X,\r
                IMM64_IMM41c_INST_WORD_POS_X,\r
                IMM64_IMM41c_VAL_POS_X\r
                );\r
\r
      INS_IMM64(FixupVal,\r
                ((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),\r
                IMM64_SIGN_SIZE_X,\r
                IMM64_SIGN_INST_WORD_POS_X,\r
                IMM64_SIGN_VAL_POS_X\r
                );\r
\r
      F64 = (UINT64 *) Fixup;\r
      if (*FixupData != NULL) {\r
        *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));\r
        *(UINT64 *)(*FixupData) = *F64;\r
        *FixupData = *FixupData + sizeof(UINT64);\r
      }\r
      break;\r
\r
    default:\r
      return RETURN_UNSUPPORTED;\r
  }\r
\r
  return RETURN_SUCCESS;\r
}\r
Commit	Line	Data
878ddf1f	1	/*++\r
	2	\r
	3	Copyright (c) 2004, Intel Corporation \r
	4	All rights reserved. This program and the accompanying materials \r
	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	\r
	14	PeCoffLoaderEx.c\r
	15	\r
	16	Abstract:\r
	17	\r
	18	Fixes Intel Itanium(TM) specific relocation types\r
	19	\r
	20	\r
	21	Revision History\r
	22	\r
	23	--*/\r
	24	\r
ce53a8c3	25	#include <Common/UefiBaseTypes.h>\r
ce53a8c3	26	#include <Common/EfiImage.h>\r
878ddf1f	27	#include <Library/PeCoffLib.h>\r
878ddf1f	28	\r
	29	\r
	30	\r
	31	\r
	32	\r
	33	#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \\r
	34	Value \|= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)\r
	35	\r
	36	#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \\r
	37	(UINT32)Address = ((UINT32)Address & ~(((1 << Size) - 1) << InstPos)) \| \\r
	38	((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)\r
	39	\r
	40	#define IMM64_IMM7B_INST_WORD_X 3 \r
	41	#define IMM64_IMM7B_SIZE_X 7 \r
	42	#define IMM64_IMM7B_INST_WORD_POS_X 4 \r
	43	#define IMM64_IMM7B_VAL_POS_X 0 \r
	44	\r
	45	#define IMM64_IMM9D_INST_WORD_X 3 \r
	46	#define IMM64_IMM9D_SIZE_X 9 \r
	47	#define IMM64_IMM9D_INST_WORD_POS_X 18 \r
	48	#define IMM64_IMM9D_VAL_POS_X 7 \r
	49	\r
	50	#define IMM64_IMM5C_INST_WORD_X 3 \r
	51	#define IMM64_IMM5C_SIZE_X 5 \r
	52	#define IMM64_IMM5C_INST_WORD_POS_X 13 \r
	53	#define IMM64_IMM5C_VAL_POS_X 16 \r
	54	\r
	55	#define IMM64_IC_INST_WORD_X 3 \r
	56	#define IMM64_IC_SIZE_X 1 \r
	57	#define IMM64_IC_INST_WORD_POS_X 12 \r
	58	#define IMM64_IC_VAL_POS_X 21 \r
	59	\r
	60	#define IMM64_IMM41a_INST_WORD_X 1 \r
	61	#define IMM64_IMM41a_SIZE_X 10 \r
	62	#define IMM64_IMM41a_INST_WORD_POS_X 14 \r
	63	#define IMM64_IMM41a_VAL_POS_X 22 \r
	64	\r
	65	#define IMM64_IMM41b_INST_WORD_X 1 \r
	66	#define IMM64_IMM41b_SIZE_X 8 \r
	67	#define IMM64_IMM41b_INST_WORD_POS_X 24 \r
	68	#define IMM64_IMM41b_VAL_POS_X 32 \r
	69	\r
	70	#define IMM64_IMM41c_INST_WORD_X 2 \r
	71	#define IMM64_IMM41c_SIZE_X 23 \r
	72	#define IMM64_IMM41c_INST_WORD_POS_X 0 \r
	73	#define IMM64_IMM41c_VAL_POS_X 40 \r
	74	\r
	75	#define IMM64_SIGN_INST_WORD_X 3 \r
	76	#define IMM64_SIGN_SIZE_X 1 \r
	77	#define IMM64_SIGN_INST_WORD_POS_X 27 \r
	78	#define IMM64_SIGN_VAL_POS_X 63 \r
	79	\r
	80	RETURN_STATUS\r
	81	PeCoffLoaderRelocateImageEx (\r
	82	IN UINT16 *Reloc,\r
	83	IN OUT CHAR8 *Fixup, \r
	84	IN OUT CHAR8 **FixupData,\r
	85	IN UINT64 Adjust\r
	86	)\r
	87	/*++\r
	88	\r
	89	Routine Description:\r
	90	\r
	91	Performs an Itanium-based specific relocation fixup\r
92	\r
93	Arguments:\r
94	\r
95	Reloc - Pointer to the relocation record\r
96	\r
97	Fixup - Pointer to the address to fix up\r
98	\r
99	FixupData - Pointer to a buffer to log the fixups\r
100	\r
101	Adjust - The offset to adjust the fixup\r
102	\r
103	Returns:\r
104	\r
105	Status code\r
106	\r
107	--*/\r
108	{\r
109	UINT64 *F64;\r
110	UINT64 FixupVal;\r
111	\r
112	switch ((*Reloc) >> 12) {\r
113	\r
114	case EFI_IMAGE_REL_BASED_DIR64:\r
115	F64 = (UINT64 *) Fixup;\r
116	F64 = F64 + (UINT64) Adjust;\r
117	if (*FixupData != NULL) {\r
118	FixupData = ALIGN_POINTER(FixupData, sizeof(UINT64));\r
119	(UINT64 )(FixupData) = F64;\r
120	FixupData = FixupData + sizeof(UINT64);\r
121	}\r
122	break;\r
123	\r
124	case EFI_IMAGE_REL_BASED_IA64_IMM64:\r
125	\r
126	//\r
127	// Align it to bundle address before fixing up the\r
128	// 64-bit immediate value of the movl instruction.\r
129	//\r
130	\r
131	Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));\r
132	FixupVal = (UINT64)0;\r
133	\r
134	// \r
135	// Extract the lower 32 bits of IMM64 from bundle\r
136	//\r
137	EXT_IMM64(FixupVal,\r
138	(UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,\r
139	IMM64_IMM7B_SIZE_X,\r
140	IMM64_IMM7B_INST_WORD_POS_X,\r
141	IMM64_IMM7B_VAL_POS_X\r
142	);\r
143	\r
144	EXT_IMM64(FixupVal,\r
145	(UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,\r
146	IMM64_IMM9D_SIZE_X,\r
147	IMM64_IMM9D_INST_WORD_POS_X,\r
148	IMM64_IMM9D_VAL_POS_X\r
149	);\r
150	\r
151	EXT_IMM64(FixupVal,\r
152	(UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,\r
153	IMM64_IMM5C_SIZE_X,\r
154	IMM64_IMM5C_INST_WORD_POS_X,\r
155	IMM64_IMM5C_VAL_POS_X\r
156	);\r
157	\r
158	EXT_IMM64(FixupVal,\r
159	(UINT32 *)Fixup + IMM64_IC_INST_WORD_X,\r
160	IMM64_IC_SIZE_X,\r
161	IMM64_IC_INST_WORD_POS_X,\r
162	IMM64_IC_VAL_POS_X\r
163	);\r
164	\r
165	EXT_IMM64(FixupVal,\r
166	(UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,\r
167	IMM64_IMM41a_SIZE_X,\r
168	IMM64_IMM41a_INST_WORD_POS_X,\r
169	IMM64_IMM41a_VAL_POS_X\r
170	);\r
171	\r
172	// \r
173	// Update 64-bit address\r
174	//\r
175	FixupVal += Adjust;\r
176	\r
177	// \r
178	// Insert IMM64 into bundle\r
179	//\r
180	INS_IMM64(FixupVal,\r
181	((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),\r
182	IMM64_IMM7B_SIZE_X,\r
183	IMM64_IMM7B_INST_WORD_POS_X,\r
184	IMM64_IMM7B_VAL_POS_X\r
185	);\r
186	\r
187	INS_IMM64(FixupVal,\r
188	((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),\r
189	IMM64_IMM9D_SIZE_X,\r
190	IMM64_IMM9D_INST_WORD_POS_X,\r
191	IMM64_IMM9D_VAL_POS_X\r
192	);\r
193	\r
194	INS_IMM64(FixupVal,\r
195	((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),\r
196	IMM64_IMM5C_SIZE_X,\r
197	IMM64_IMM5C_INST_WORD_POS_X,\r
198	IMM64_IMM5C_VAL_POS_X\r
199	);\r
200	\r
201	INS_IMM64(FixupVal,\r
202	((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),\r
203	IMM64_IC_SIZE_X,\r
204	IMM64_IC_INST_WORD_POS_X,\r
205	IMM64_IC_VAL_POS_X\r
206	);\r
207	\r
208	INS_IMM64(FixupVal,\r
209	((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),\r
210	IMM64_IMM41a_SIZE_X,\r
211	IMM64_IMM41a_INST_WORD_POS_X,\r
212	IMM64_IMM41a_VAL_POS_X\r
213	);\r
214	\r
215	INS_IMM64(FixupVal,\r
216	((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),\r
217	IMM64_IMM41b_SIZE_X,\r
218	IMM64_IMM41b_INST_WORD_POS_X,\r
219	IMM64_IMM41b_VAL_POS_X\r
220	);\r
221	\r
222	INS_IMM64(FixupVal,\r
223	((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),\r
224	IMM64_IMM41c_SIZE_X,\r
225	IMM64_IMM41c_INST_WORD_POS_X,\r
226	IMM64_IMM41c_VAL_POS_X\r
227	);\r
228	\r
229	INS_IMM64(FixupVal,\r
230	((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),\r
231	IMM64_SIGN_SIZE_X,\r
232	IMM64_SIGN_INST_WORD_POS_X,\r
233	IMM64_SIGN_VAL_POS_X\r
234	);\r
235	\r
236	F64 = (UINT64 *) Fixup;\r
237	if (*FixupData != NULL) {\r
238	FixupData = ALIGN_POINTER(FixupData, sizeof(UINT64));\r
239	(UINT64 )(FixupData) = F64;\r
240	FixupData = FixupData + sizeof(UINT64);\r
241	}\r
242	break;\r
243	\r
244	default:\r
245	return RETURN_UNSUPPORTED;\r
246	}\r
247	\r
248	return RETURN_SUCCESS;\r
249	}\r