[mirror_edk2.git] / Tools / Source / TianoTools / Include / Dxe / ArchProtocol / Cpu.h

/** @file\r
  CPU Architectural Protocol as defined in DXE CIS\r
\r
  This code abstracts the DXE core from processor implementation details.\r
\r
  Copyright (c) 2006, Intel Corporation                                                         \r
  All rights reserved. This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
  Module Name:  Cpu.h\r
\r
  @par Revision Reference:\r
  Version 0.91B.\r
\r
**/\r
\r
#ifndef __ARCH_PROTOCOL_CPU_H__\r
#define __ARCH_PROTOCOL_CPU_H__\r
\r
\r
#define EFI_CPU_ARCH_PROTOCOL_GUID \\r
  { 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r
\r
typedef struct _EFI_CPU_ARCH_PROTOCOL   EFI_CPU_ARCH_PROTOCOL;\r
\r
typedef enum {\r
  EfiCpuFlushTypeWriteBackInvalidate,\r
  EfiCpuFlushTypeWriteBack,\r
  EfiCpuFlushTypeInvalidate,\r
  EfiCpuMaxFlushType\r
} EFI_CPU_FLUSH_TYPE;\r
\r
typedef enum {\r
  EfiCpuInit,\r
  EfiCpuMaxInitType\r
} EFI_CPU_INIT_TYPE;\r
\r
/**\r
  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
  @param  InterruptType Defines the type of interrupt or exception that \r
  occurred on the processor.This parameter is processor architecture specific.\r
  \r
  @param  SystemContext A pointer to the processor context when \r
  the interrupt occurred on the processor.\r
\r
  @return None\r
\r
**/\r
typedef\r
VOID\r
(*EFI_CPU_INTERRUPT_HANDLER) (\r
  IN EFI_EXCEPTION_TYPE                 InterruptType,\r
  IN EFI_SYSTEM_CONTEXT                 SystemContext\r
  );\r
\r
/**\r
  This function flushes the range of addresses from Start to Start+Length \r
  from the processor's data cache. If Start is not aligned to a cache line \r
  boundary, then the bytes before Start to the preceding cache line boundary \r
  are also flushed. If Start+Length is not aligned to a cache line boundary, \r
  then the bytes past Start+Length to the end of the next cache line boundary \r
  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
  supported. If the data cache is fully coherent with all DMA operations, then \r
  this function can just return EFI_SUCCESS. If the processor does not support \r
  flushing a range of the data cache, then the entire data cache can be flushed.\r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  Start The beginning physical address to flush from the processor's data\r
  cache.\r
  @param  Length The number of bytes to flush from the processor's data cache. This\r
  function may flush more bytes than Length specifies depending upon\r
  the granularity of the flush operation that the processor supports.\r
  @param  FlushType Specifies the type of flush operation to perform.\r
\r
  @retval  EFI_SUCCESS The address range from Start to Start+Length was flushed from\r
  the processor's data cache.\r
  @retval  EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r
  by FlushType.\r
  @retval  EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r
  from the processor's data cache.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_FLUSH_DATA_CACHE) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN EFI_PHYSICAL_ADDRESS               Start,\r
  IN UINT64                             Length,\r
  IN EFI_CPU_FLUSH_TYPE                 FlushType\r
  );\r
\r
\r
/**\r
  This function enables interrupt processing by the processor. \r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
  @retval  EFI_SUCCESS Interrupts are enabled on the processor.\r
  @retval  EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_ENABLE_INTERRUPT) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This\r
  );\r
\r
\r
/**\r
  This function disables interrupt processing by the processor.\r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
  @retval  EFI_SUCCESS Interrupts are disabled on the processor.\r
  @retval  EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_DISABLE_INTERRUPT) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This\r
  );\r
\r
\r
/**\r
  This function retrieves the processor's current interrupt state a returns it in \r
  State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r
  are currently disabled, then FALSE is returned.\r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  State A pointer to the processor's current interrupt state. Set to TRUE if\r
  interrupts are enabled and FALSE if interrupts are disabled.\r
\r
  @retval  EFI_SUCCESS The processor's current interrupt state was returned in State.\r
  @retval  EFI_INVALID_PARAMETER State is NULL.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_GET_INTERRUPT_STATE) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  OUT BOOLEAN                           *State\r
  );\r
\r
\r
/**\r
  This function generates an INIT on the processor. If this function succeeds, then the\r
  processor will be reset, and control will not be returned to the caller. If InitType is \r
  not supported by this processor, or the processor cannot programmatically generate an \r
  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r
  occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  InitType The type of processor INIT to perform.\r
\r
  @retval  EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r
  @retval  EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r
  by this processor.\r
  @retval  EFI_DEVICE_ERROR The processor INIT failed.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_INIT) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN EFI_CPU_INIT_TYPE                  InitType\r
  );\r
\r
\r
/**\r
  This function registers and enables the handler specified by InterruptHandler for a processor \r
  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
  The installed handler is called once for each processor interrupt or exception.\r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
  are enabled and FALSE if interrupts are disabled.\r
  @param  InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
  when a processor interrupt occurs. If this parameter is NULL, then the handler\r
  will be uninstalled.\r
\r
  @retval  EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.\r
  @retval  EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was\r
  previously installed.\r
  @retval  EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
  previously installed.\r
  @retval  EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN EFI_EXCEPTION_TYPE                 InterruptType,\r
  IN EFI_CPU_INTERRUPT_HANDLER          InterruptHandler\r
  );\r
\r
\r
/**\r
  This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter\r
  must be between 0 and NumberOfTimers-1.\r
  @param  TimerValue Pointer to the returned timer value.\r
  @param  TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment\r
  of TimerValue.\r
\r
  @retval  EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.\r
  @retval  EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.\r
  @retval  EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r
  @retval  EFI_UNSUPPORTED The processor does not have any readable timers.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_GET_TIMER_VALUE) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN UINT32                             TimerIndex,\r
  OUT UINT64                            *TimerValue,\r
  OUT UINT64                            *TimerPeriod OPTIONAL\r
  );\r
\r
\r
/**\r
  This function modifies the attributes for the memory region specified by BaseAddress and\r
  Length from their current attributes to the attributes specified by Attributes.\r
\r
  @param  This The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  BaseAddress The physical address that is the start address of a memory region.\r
  @param  Length The size in bytes of the memory region.\r
  @param  Attributes The bit mask of attributes to set for the memory region.\r
\r
  @retval  EFI_SUCCESS The attributes were set for the memory region.\r
  @retval  EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
  BaseAddress and Length cannot be modified.\r
  @retval  EFI_INVALID_PARAMETER Length is zero.\r
  @retval  EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
  the memory resource range.\r
  @retval  EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
  resource range specified by BaseAddress and Length.\r
  The bit mask of attributes is not support for the memory resource\r
  range specified by BaseAddress and Length.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES) (\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN  EFI_PHYSICAL_ADDRESS              BaseAddress,\r
  IN  UINT64                            Length,\r
  IN  UINT64                            Attributes\r
  );\r
\r
\r
/**\r
  @par Protocol Description:\r
  The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
  Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
  vectors and exception vectors, reading internal processor timers, resetting the processor, and\r
  determining the processor frequency.\r
\r
  @param FlushDataCache\r
  Flushes a range of the processor's data cache. If the processor does \r
  not contain a data cache, or the data cache is fully coherent, then this \r
  function can just return EFI_SUCCESS. If the processor does not support \r
  flushing a range of addresses from the data cache, then the entire data \r
  cache must be flushed. \r
\r
  @param EnableInterrupt    Enables interrupt processing by the processor. \r
\r
  @param DisableInterrupt    Disables interrupt processing by the processor.\r
\r
  @param GetInterruptState  Retrieves the processor's current interrupt state.\r
\r
  @param Init\r
  Generates an INIT on the processor. If a processor cannot programmatically \r
  generate an INIT without help from external hardware, then this function \r
  returns EFI_UNSUPPORTED.\r
\r
  @param RegisterInterruptHandler\r
  Associates an interrupt service routine with one of the processor's interrupt \r
  vectors. This function is typically used by the EFI_TIMER_ARCH_PROTOCOL to \r
  hook the timer interrupt in a system. It can also be used by the debugger to \r
  hook exception vectors.\r
\r
  @param GetTimerValue    Returns the value of one of the processor's internal timers.\r
\r
  @param SetMemoryAttributes  Attempts to set the attributes of a memory region.\r
\r
  @param NumberOfTimers\r
  The number of timers that are available in a processor. The value in this \r
  field is a constant that must not be modified after the CPU Architectural \r
  Protocol is installed. All consumers must treat this as a read-only field.\r
\r
  @param DmaBufferAlignment\r
  The size, in bytes, of the alignment required for DMA buffer allocations. \r
  This is typically the size of the largest data cache line in the platform. \r
  The value in this field is a constant that must not be modified after the \r
  CPU Architectural Protocol is installed. All consumers must treat this as \r
  a read-only field.\r
\r
**/\r
struct _EFI_CPU_ARCH_PROTOCOL {\r
  EFI_CPU_FLUSH_DATA_CACHE            FlushDataCache;\r
  EFI_CPU_ENABLE_INTERRUPT            EnableInterrupt;\r
  EFI_CPU_DISABLE_INTERRUPT           DisableInterrupt;\r
  EFI_CPU_GET_INTERRUPT_STATE         GetInterruptState;\r
  EFI_CPU_INIT                        Init;\r
  EFI_CPU_REGISTER_INTERRUPT_HANDLER  RegisterInterruptHandler;\r
  EFI_CPU_GET_TIMER_VALUE             GetTimerValue;\r
  EFI_CPU_SET_MEMORY_ATTRIBUTES       SetMemoryAttributes;\r
  UINT32                              NumberOfTimers;\r
  UINT32                              DmaBufferAlignment;\r
};\r
\r
extern EFI_GUID gEfiCpuArchProtocolGuid;\r
\r
#endif\r
Commit	Line	Data
21b50a27	1	/** @file\r
	2	CPU Architectural Protocol as defined in DXE CIS\r
	3	\r
	4	This code abstracts the DXE core from processor implementation details.\r
	5	\r
	6	Copyright (c) 2006, Intel Corporation \r
	7	All rights reserved. This program and the accompanying materials \r
	8	are licensed and made available under the terms and conditions of the BSD License \r
	9	which accompanies this distribution. The full text of the license may be found at \r
	10	http://opensource.org/licenses/bsd-license.php \r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	14	\r
	15	Module Name: Cpu.h\r
	16	\r
	17	@par Revision Reference:\r
	18	Version 0.91B.\r
	19	\r
	20	**/\r
	21	\r
	22	#ifndef __ARCH_PROTOCOL_CPU_H__\r
	23	#define __ARCH_PROTOCOL_CPU_H__\r
	24	\r
	25	\r
	26	#define EFI_CPU_ARCH_PROTOCOL_GUID \\r
	27	{ 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r
	28	\r
	29	typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r
	30	\r
	31	typedef enum {\r
	32	EfiCpuFlushTypeWriteBackInvalidate,\r
	33	EfiCpuFlushTypeWriteBack,\r
	34	EfiCpuFlushTypeInvalidate,\r
	35	EfiCpuMaxFlushType\r
	36	} EFI_CPU_FLUSH_TYPE;\r
	37	\r
	38	typedef enum {\r
	39	EfiCpuInit,\r
	40	EfiCpuMaxInitType\r
	41	} EFI_CPU_INIT_TYPE;\r
	42	\r
	43	/**\r
	44	EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
	45	\r
	46	@param InterruptType Defines the type of interrupt or exception that \r
	47	occurred on the processor.This parameter is processor architecture specific.\r
	48	\r
	49	@param SystemContext A pointer to the processor context when \r
	50	the interrupt occurred on the processor.\r
	51	\r
	52	@return None\r
	53	\r
	54	**/\r
	55	typedef\r
	56	VOID\r
	57	(*EFI_CPU_INTERRUPT_HANDLER) (\r
	58	IN EFI_EXCEPTION_TYPE InterruptType,\r
	59	IN EFI_SYSTEM_CONTEXT SystemContext\r
	60	);\r
	61	\r
	62	/**\r
	63	This function flushes the range of addresses from Start to Start+Length \r
	64	from the processor's data cache. If Start is not aligned to a cache line \r
65	boundary, then the bytes before Start to the preceding cache line boundary \r
66	are also flushed. If Start+Length is not aligned to a cache line boundary, \r
67	then the bytes past Start+Length to the end of the next cache line boundary \r
68	are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r
69	supported. If the data cache is fully coherent with all DMA operations, then \r
70	this function can just return EFI_SUCCESS. If the processor does not support \r
71	flushing a range of the data cache, then the entire data cache can be flushed.\r
72	\r
73	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
74	@param Start The beginning physical address to flush from the processor's data\r
75	cache.\r
76	@param Length The number of bytes to flush from the processor's data cache. This\r
77	function may flush more bytes than Length specifies depending upon\r
78	the granularity of the flush operation that the processor supports.\r
79	@param FlushType Specifies the type of flush operation to perform.\r
80	\r
81	@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r
82	the processor's data cache.\r
83	@retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r
84	by FlushType.\r
85	@retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r
86	from the processor's data cache.\r
87	\r
88	**/\r
89	typedef\r
90	EFI_STATUS\r
91	(EFIAPI *EFI_CPU_FLUSH_DATA_CACHE) (\r
92	IN EFI_CPU_ARCH_PROTOCOL *This,\r
93	IN EFI_PHYSICAL_ADDRESS Start,\r
94	IN UINT64 Length,\r
95	IN EFI_CPU_FLUSH_TYPE FlushType\r
96	);\r
97	\r
98	\r
99	/**\r
100	This function enables interrupt processing by the processor. \r
101	\r
102	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
103	\r
104	@retval EFI_SUCCESS Interrupts are enabled on the processor.\r
105	@retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r
106	\r
107	**/\r
108	typedef\r
109	EFI_STATUS\r
110	(EFIAPI *EFI_CPU_ENABLE_INTERRUPT) (\r
111	IN EFI_CPU_ARCH_PROTOCOL *This\r
112	);\r
113	\r
114	\r
115	/**\r
116	This function disables interrupt processing by the processor.\r
117	\r
118	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
119	\r
120	@retval EFI_SUCCESS Interrupts are disabled on the processor.\r
121	@retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r
122	\r
123	**/\r
124	typedef\r
125	EFI_STATUS\r
126	(EFIAPI *EFI_CPU_DISABLE_INTERRUPT) (\r
127	IN EFI_CPU_ARCH_PROTOCOL *This\r
128	);\r
129	\r
130	\r
131	/**\r
132	This function retrieves the processor's current interrupt state a returns it in \r
133	State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r
134	are currently disabled, then FALSE is returned.\r
135	\r
136	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
137	@param State A pointer to the processor's current interrupt state. Set to TRUE if\r
138	interrupts are enabled and FALSE if interrupts are disabled.\r
139	\r
140	@retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r
141	@retval EFI_INVALID_PARAMETER State is NULL.\r
142	\r
143	**/\r
144	typedef\r
145	EFI_STATUS\r
146	(EFIAPI *EFI_CPU_GET_INTERRUPT_STATE) (\r
147	IN EFI_CPU_ARCH_PROTOCOL *This,\r
148	OUT BOOLEAN *State\r
149	);\r
150	\r
151	\r
152	/**\r
153	This function generates an INIT on the processor. If this function succeeds, then the\r
154	processor will be reset, and control will not be returned to the caller. If InitType is \r
155	not supported by this processor, or the processor cannot programmatically generate an \r
156	INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r
157	occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
158	\r
159	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
160	@param InitType The type of processor INIT to perform.\r
161	\r
162	@retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r
163	@retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r
164	by this processor.\r
165	@retval EFI_DEVICE_ERROR The processor INIT failed.\r
166	\r
167	**/\r
168	typedef\r
169	EFI_STATUS\r
170	(EFIAPI *EFI_CPU_INIT) (\r
171	IN EFI_CPU_ARCH_PROTOCOL *This,\r
172	IN EFI_CPU_INIT_TYPE InitType\r
173	);\r
174	\r
175	\r
176	/**\r
177	This function registers and enables the handler specified by InterruptHandler for a processor \r
178	interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
179	handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
180	The installed handler is called once for each processor interrupt or exception.\r
181	\r
182	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
183	@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
184	are enabled and FALSE if interrupts are disabled.\r
185	@param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
186	when a processor interrupt occurs. If this parameter is NULL, then the handler\r
187	will be uninstalled.\r
188	\r
189	@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.\r
190	@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was\r
191	previously installed.\r
192	@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
193	previously installed.\r
194	@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.\r
195	\r
196	**/\r
197	typedef\r
198	EFI_STATUS\r
199	(EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER) (\r
200	IN EFI_CPU_ARCH_PROTOCOL *This,\r
201	IN EFI_EXCEPTION_TYPE InterruptType,\r
202	IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
203	);\r
204	\r
205	\r
206	/**\r
207	This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r
208	\r
209	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
210	@param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter\r
211	must be between 0 and NumberOfTimers-1.\r
212	@param TimerValue Pointer to the returned timer value.\r
213	@param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment\r
214	of TimerValue.\r
215	\r
216	@retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.\r
217	@retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.\r
218	@retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r
219	@retval EFI_UNSUPPORTED The processor does not have any readable timers.\r
220	\r
221	**/\r
222	typedef\r
223	EFI_STATUS\r
224	(EFIAPI *EFI_CPU_GET_TIMER_VALUE) (\r
225	IN EFI_CPU_ARCH_PROTOCOL *This,\r
226	IN UINT32 TimerIndex,\r
227	OUT UINT64 *TimerValue,\r
228	OUT UINT64 *TimerPeriod OPTIONAL\r
229	);\r
230	\r
231	\r
232	/**\r
233	This function modifies the attributes for the memory region specified by BaseAddress and\r
234	Length from their current attributes to the attributes specified by Attributes.\r
235	\r
236	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
237	@param BaseAddress The physical address that is the start address of a memory region.\r
238	@param Length The size in bytes of the memory region.\r
239	@param Attributes The bit mask of attributes to set for the memory region.\r
240	\r
241	@retval EFI_SUCCESS The attributes were set for the memory region.\r
242	@retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
243	BaseAddress and Length cannot be modified.\r
244	@retval EFI_INVALID_PARAMETER Length is zero.\r
245	@retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
246	the memory resource range.\r
247	@retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
248	resource range specified by BaseAddress and Length.\r
249	The bit mask of attributes is not support for the memory resource\r
250	range specified by BaseAddress and Length.\r
251	\r
252	**/\r
253	typedef\r
254	EFI_STATUS\r
255	(EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES) (\r
256	IN EFI_CPU_ARCH_PROTOCOL *This,\r
257	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
258	IN UINT64 Length,\r
259	IN UINT64 Attributes\r
260	);\r
261	\r
262	\r
263	/**\r
264	@par Protocol Description:\r
265	The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
266	Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
267	vectors and exception vectors, reading internal processor timers, resetting the processor, and\r
268	determining the processor frequency.\r
269	\r
270	@param FlushDataCache\r
271	Flushes a range of the processor's data cache. If the processor does \r
272	not contain a data cache, or the data cache is fully coherent, then this \r
273	function can just return EFI_SUCCESS. If the processor does not support \r
274	flushing a range of addresses from the data cache, then the entire data \r
275	cache must be flushed. \r
276	\r
277	@param EnableInterrupt Enables interrupt processing by the processor. \r
278	\r
279	@param DisableInterrupt Disables interrupt processing by the processor.\r
280	\r
281	@param GetInterruptState Retrieves the processor's current interrupt state.\r
282	\r
283	@param Init\r
284	Generates an INIT on the processor. If a processor cannot programmatically \r
285	generate an INIT without help from external hardware, then this function \r
286	returns EFI_UNSUPPORTED.\r
287	\r
288	@param RegisterInterruptHandler\r
289	Associates an interrupt service routine with one of the processor's interrupt \r
290	vectors. This function is typically used by the EFI_TIMER_ARCH_PROTOCOL to \r
291	hook the timer interrupt in a system. It can also be used by the debugger to \r
292	hook exception vectors.\r
293	\r
294	@param GetTimerValue Returns the value of one of the processor's internal timers.\r
295	\r
296	@param SetMemoryAttributes Attempts to set the attributes of a memory region.\r
297	\r
298	@param NumberOfTimers\r
299	The number of timers that are available in a processor. The value in this \r
300	field is a constant that must not be modified after the CPU Architectural \r
301	Protocol is installed. All consumers must treat this as a read-only field.\r
302	\r
303	@param DmaBufferAlignment\r
304	The size, in bytes, of the alignment required for DMA buffer allocations. \r
305	This is typically the size of the largest data cache line in the platform. \r
306	The value in this field is a constant that must not be modified after the \r
307	CPU Architectural Protocol is installed. All consumers must treat this as \r
308	a read-only field.\r
309	\r
310	**/\r
311	struct _EFI_CPU_ARCH_PROTOCOL {\r
312	EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;\r
313	EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;\r
314	EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;\r
315	EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;\r
316	EFI_CPU_INIT Init;\r
317	EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;\r
318	EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r
319	EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r
320	UINT32 NumberOfTimers;\r
321	UINT32 DmaBufferAlignment;\r
322	};\r
323	\r
324	extern EFI_GUID gEfiCpuArchProtocolGuid;\r
325	\r
326	#endif\r