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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / UefiCpuPkg / Application / Cpuid / Cpuid.c
CommitLineData
25705752
MK		 1/** @file\r
2 UEFI Application to display CPUID leaf information.\r
3\r
516e3397 4 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
25705752
MK		 6\r
7**/\r
8\r
9#include <Uefi.h>\r
10#include <Library/BaseLib.h>\r
11#include <Library/UefiLib.h>\r
01acb06c 12#include <Register/Intel/Cpuid.h>\r
25705752
MK		 13\r
14///\r
15/// Macro used to display the value of a bit field in a register returned by CPUID.\r
16///\r
17#define PRINT_BIT_FIELD(Variable, FieldName) \\r
d2ba6f41 18 Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);\r
25705752
MK		 19\r
20///\r
21/// Macro used to display the value of a register returned by CPUID.\r
22///\r
23#define PRINT_VALUE(Variable, Description) \\r
24 Print (L"%5a%42a: %x\n", #Variable, #Description, Variable);\r
25\r
26///\r
27/// Structure for cache description lookup table\r
28///\r
29typedef struct {\r
053e878b
MK		 30 UINT8 CacheDescriptor;\r
31 CHAR8 *Type;\r
32 CHAR8 *Description;\r
25705752
MK		 33} CPUID_CACHE_INFO_DESCRIPTION;\r
34\r
35///\r
36/// Cache description lookup table\r
37///\r
38CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {\r
053e878b
MK		 39 { 0x00, "General", "Null descriptor, this byte contains no information" },\r
40 { 0x01, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },\r
41 { 0x02, "TLB", "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },\r
42 { 0x03, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },\r
43 { 0x04, "TLB", "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },\r
44 { 0x05, "TLB", "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },\r
45 { 0x06, "Cache", "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },\r
46 { 0x08, "Cache", "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
47 { 0x09, "Cache", "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },\r
48 { 0x0A, "Cache", "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },\r
49 { 0x0B, "TLB", "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },\r
50 { 0x0C, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
51 { 0x0D, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },\r
52 { 0x0E, "Cache", "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },\r
53 { 0x1D, "Cache", "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },\r
54 { 0x21, "Cache", "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },\r
55 { 0x22, "Cache", "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },\r
56 { 0x23, "Cache", "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
57 { 0x24, "Cache", "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },\r
58 { 0x25, "Cache", "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
59 { 0x29, "Cache", "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
60 { 0x2C, "Cache", "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
61 { 0x30, "Cache", "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
62 { 0x40, "Cache", "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },\r
63 { 0x41, "Cache", "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },\r
64 { 0x42, "Cache", "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },\r
65 { 0x43, "Cache", "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },\r
66 { 0x44, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },\r
67 { 0x45, "Cache", "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },\r
68 { 0x46, "Cache", "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },\r
69 { 0x47, "Cache", "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },\r
70 { 0x48, "Cache", "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },\r
71 { 0x49, "Cache", "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
72 { 0x4A, "Cache", "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },\r
73 { 0x4B, "Cache", "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },\r
74 { 0x4C, "Cache", "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },\r
75 { 0x4D, "Cache", "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },\r
76 { 0x4E, "Cache", "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },\r
77 { 0x4F, "TLB", "Instruction TLB: 4 KByte pages, 32 entries" },\r
78 { 0x50, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },\r
79 { 0x51, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },\r
80 { 0x52, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },\r
81 { 0x55, "TLB", "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },\r
82 { 0x56, "TLB", "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
83 { 0x57, "TLB", "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
84 { 0x59, "TLB", "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
85 { 0x5A, "TLB", "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
86 { 0x5B, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
87 { 0x5C, "TLB", "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
88 { 0x5D, "TLB", "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
89 { 0x60, "Cache", "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
90 { 0x61, "TLB", "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
91 { 0x63, "TLB", "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r
92 { 0x64, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r
93 { 0x66, "Cache", "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
94 { 0x67, "Cache", "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
95 { 0x68, "Cache", "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
96 { 0x6A, "Cache", "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },\r
97 { 0x6B, "Cache", "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },\r
98 { 0x6C, "Cache", "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },\r
99 { 0x6D, "Cache", "DTLB: 1 GByte pages, fully associative, 16 entries" },\r
100 { 0x70, "Cache", "Trace cache: 12 K-uop, 8-way set associative" },\r
101 { 0x71, "Cache", "Trace cache: 16 K-uop, 8-way set associative" },\r
102 { 0x72, "Cache", "Trace cache: 32 K-uop, 8-way set associative" },\r
103 { 0x76, "TLB", "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },\r
104 { 0x78, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },\r
105 { 0x79, "Cache", "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
106 { 0x7A, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
107 { 0x7B, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
108 { 0x7C, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
109 { 0x7D, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },\r
110 { 0x7F, "Cache", "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },\r
111 { 0x80, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },\r
112 { 0x82, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },\r
113 { 0x83, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },\r
114 { 0x84, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },\r
115 { 0x85, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },\r
116 { 0x86, "Cache", "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
117 { 0x87, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
118 { 0xA0, "DTLB", "DTLB: 4k pages, fully associative, 32 entries" },\r
119 { 0xB0, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
120 { 0xB1, "TLB", "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },\r
121 { 0xB2, "TLB", "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },\r
122 { 0xB3, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
123 { 0xB4, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },\r
124 { 0xB5, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },\r
125 { 0xB6, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },\r
126 { 0xBA, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },\r
127 { 0xC0, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },\r
128 { 0xC1, "STLB", "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
129 { 0xC2, "DTLB", "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
130 { 0xC3, "STLB", "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
131 { 0xC4, "DTLB", "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r
132 { 0xCA, "STLB", "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
133 { 0xD0, "Cache", "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
134 { 0xD1, "Cache", "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
135 { 0xD2, "Cache", "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },\r
136 { 0xD6, "Cache", "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
137 { 0xD7, "Cache", "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },\r
138 { 0xD8, "Cache", "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },\r
139 { 0xDC, "Cache", "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },\r
140 { 0xDD, "Cache", "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },\r
141 { 0xDE, "Cache", "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },\r
142 { 0xE2, "Cache", "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },\r
143 { 0xE3, "Cache", "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
144 { 0xE4, "Cache", "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },\r
145 { 0xEA, "Cache", "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },\r
146 { 0xEB, "Cache", "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },\r
147 { 0xEC, "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },\r
148 { 0xF0, "Prefetch", "64-Byte prefetching" },\r
149 { 0xF1, "Prefetch", "128-Byte prefetching" },\r
150 { 0xFE, "General", "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },\r
151 { 0xFF, "General", "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }\r
25705752
MK		 152};\r
153\r
154///\r
155/// The maximum supported CPUID leaf index starting from leaf 0x00000000.\r
156///\r
053e878b 157UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;\r
25705752
MK		 158\r
159///\r
160/// The maximum supported CPUID leaf index starting from leaf 0x80000000.\r
161///\r
162UINT32 gMaximumExtendedFunction = CPUID_EXTENDED_FUNCTION;\r
163\r
164/**\r
165 Display CPUID_SIGNATURE leaf.\r
166\r
167**/\r
168VOID\r
169CpuidSignature (\r
170 VOID\r
171 )\r
172{\r
053e878b
MK		 173 UINT32 Eax;\r
174 UINT32 Ebx;\r
175 UINT32 Ecx;\r
176 UINT32 Edx;\r
177 CHAR8 Signature[13];\r
25705752 178\r
25705752
MK		 179 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
180\r
181 Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);\r
182 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
183 PRINT_VALUE (Eax, MaximumLeaf);\r
184 *(UINT32 *)(Signature + 0) = Ebx;\r
185 *(UINT32 *)(Signature + 4) = Edx;\r
186 *(UINT32 *)(Signature + 8) = Ecx;\r
053e878b 187 Signature[12] = 0;\r
25705752
MK		 188 Print (L" Signature = %a\n", Signature);\r
189\r
190 gMaximumBasicFunction = Eax;\r
191}\r
192\r
193/**\r
194 Display CPUID_VERSION_INFO leaf.\r
195\r
196**/\r
197VOID\r
198CpuidVersionInfo (\r
199 VOID\r
200 )\r
201{\r
202 CPUID_VERSION_INFO_EAX Eax;\r
203 CPUID_VERSION_INFO_EBX Ebx;\r
204 CPUID_VERSION_INFO_ECX Ecx;\r
205 CPUID_VERSION_INFO_EDX Edx;\r
5a676df9
JF		 206 UINT32 DisplayFamily;\r
207 UINT32 DisplayModel;\r
25705752 208\r
321ef72c
JF		 209 if (CPUID_VERSION_INFO > gMaximumBasicFunction) {\r
210 return;\r
211 }\r
212\r
25705752
MK		 213 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
214\r
215 Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);\r
216 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
217\r
218 DisplayFamily = Eax.Bits.FamilyId;\r
219 if (Eax.Bits.FamilyId == 0x0F) {\r
220 DisplayFamily |= (Eax.Bits.ExtendedFamilyId << 4);\r
221 }\r
222\r
223 DisplayModel = Eax.Bits.Model;\r
053e878b 224 if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {\r
25705752
MK		 225 DisplayModel |= (Eax.Bits.ExtendedModelId << 4);\r
226 }\r
227\r
228 Print (L" Family = %x Model = %x Stepping = %x\n", DisplayFamily, DisplayModel, Eax.Bits.SteppingId);\r
229\r
230 PRINT_BIT_FIELD (Eax, SteppingId);\r
231 PRINT_BIT_FIELD (Eax, Model);\r
232 PRINT_BIT_FIELD (Eax, FamilyId);\r
233 PRINT_BIT_FIELD (Eax, ProcessorType);\r
234 PRINT_BIT_FIELD (Eax, ExtendedModelId);\r
235 PRINT_BIT_FIELD (Eax, ExtendedFamilyId);\r
236 PRINT_BIT_FIELD (Ebx, BrandIndex);\r
237 PRINT_BIT_FIELD (Ebx, CacheLineSize);\r
238 PRINT_BIT_FIELD (Ebx, MaximumAddressableIdsForLogicalProcessors);\r
239 PRINT_BIT_FIELD (Ebx, InitialLocalApicId);\r
240 PRINT_BIT_FIELD (Ecx, SSE3);\r
241 PRINT_BIT_FIELD (Ecx, PCLMULQDQ);\r
242 PRINT_BIT_FIELD (Ecx, DTES64);\r
243 PRINT_BIT_FIELD (Ecx, MONITOR);\r
244 PRINT_BIT_FIELD (Ecx, DS_CPL);\r
245 PRINT_BIT_FIELD (Ecx, VMX);\r
246 PRINT_BIT_FIELD (Ecx, SMX);\r
247 PRINT_BIT_FIELD (Ecx, TM2);\r
248 PRINT_BIT_FIELD (Ecx, SSSE3);\r
249 PRINT_BIT_FIELD (Ecx, CNXT_ID);\r
250 PRINT_BIT_FIELD (Ecx, SDBG);\r
251 PRINT_BIT_FIELD (Ecx, FMA);\r
252 PRINT_BIT_FIELD (Ecx, CMPXCHG16B);\r
253 PRINT_BIT_FIELD (Ecx, xTPR_Update_Control);\r
254 PRINT_BIT_FIELD (Ecx, PDCM);\r
255 PRINT_BIT_FIELD (Ecx, PCID);\r
256 PRINT_BIT_FIELD (Ecx, DCA);\r
257 PRINT_BIT_FIELD (Ecx, SSE4_1);\r
258 PRINT_BIT_FIELD (Ecx, SSE4_2);\r
259 PRINT_BIT_FIELD (Ecx, x2APIC);\r
260 PRINT_BIT_FIELD (Ecx, MOVBE);\r
261 PRINT_BIT_FIELD (Ecx, POPCNT);\r
262 PRINT_BIT_FIELD (Ecx, TSC_Deadline);\r
263 PRINT_BIT_FIELD (Ecx, AESNI);\r
264 PRINT_BIT_FIELD (Ecx, XSAVE);\r
265 PRINT_BIT_FIELD (Ecx, OSXSAVE);\r
266 PRINT_BIT_FIELD (Ecx, AVX);\r
267 PRINT_BIT_FIELD (Ecx, F16C);\r
268 PRINT_BIT_FIELD (Ecx, RDRAND);\r
269 PRINT_BIT_FIELD (Edx, FPU);\r
270 PRINT_BIT_FIELD (Edx, VME);\r
271 PRINT_BIT_FIELD (Edx, DE);\r
272 PRINT_BIT_FIELD (Edx, PSE);\r
273 PRINT_BIT_FIELD (Edx, TSC);\r
274 PRINT_BIT_FIELD (Edx, MSR);\r
275 PRINT_BIT_FIELD (Edx, PAE);\r
276 PRINT_BIT_FIELD (Edx, MCE);\r
277 PRINT_BIT_FIELD (Edx, CX8);\r
278 PRINT_BIT_FIELD (Edx, APIC);\r
279 PRINT_BIT_FIELD (Edx, SEP);\r
280 PRINT_BIT_FIELD (Edx, MTRR);\r
281 PRINT_BIT_FIELD (Edx, PGE);\r
282 PRINT_BIT_FIELD (Edx, MCA);\r
283 PRINT_BIT_FIELD (Edx, CMOV);\r
284 PRINT_BIT_FIELD (Edx, PAT);\r
285 PRINT_BIT_FIELD (Edx, PSE_36);\r
286 PRINT_BIT_FIELD (Edx, PSN);\r
287 PRINT_BIT_FIELD (Edx, CLFSH);\r
288 PRINT_BIT_FIELD (Edx, DS);\r
289 PRINT_BIT_FIELD (Edx, ACPI);\r
290 PRINT_BIT_FIELD (Edx, MMX);\r
291 PRINT_BIT_FIELD (Edx, FXSR);\r
292 PRINT_BIT_FIELD (Edx, SSE);\r
293 PRINT_BIT_FIELD (Edx, SSE2);\r
294 PRINT_BIT_FIELD (Edx, SS);\r
295 PRINT_BIT_FIELD (Edx, HTT);\r
296 PRINT_BIT_FIELD (Edx, TM);\r
297 PRINT_BIT_FIELD (Edx, PBE);\r
298}\r
299\r
300/**\r
301 Lookup a cache description string from the mCpuidCacheInfoDescription table.\r
302\r
303 @param[in] CacheDescriptor Cache descriptor value from CPUID_CACHE_INFO.\r
304\r
305**/\r
306CPUID_CACHE_INFO_DESCRIPTION *\r
307LookupCacheDescription (\r
308 UINT8 CacheDescriptor\r
309 )\r
310{\r
311 UINTN NumDescriptors;\r
312 UINTN Descriptor;\r
313\r
314 if (CacheDescriptor == 0x00) {\r
315 return NULL;\r
316 }\r
053e878b 317\r
25705752
MK		 318 NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);\r
319 for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {\r
320 if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {\r
321 return &mCpuidCacheInfoDescription[Descriptor];\r
322 }\r
323 }\r
053e878b 324\r
25705752
MK		 325 return NULL;\r
326}\r
327\r
328/**\r
329 Display CPUID_CACHE_INFO leaf for each supported cache descriptor.\r
330\r
331**/\r
332VOID\r
333CpuidCacheInfo (\r
334 VOID\r
335 )\r
336{\r
337 CPUID_CACHE_INFO_CACHE_TLB Eax;\r
338 CPUID_CACHE_INFO_CACHE_TLB Ebx;\r
339 CPUID_CACHE_INFO_CACHE_TLB Ecx;\r
340 CPUID_CACHE_INFO_CACHE_TLB Edx;\r
341 UINTN Index;\r
342 CPUID_CACHE_INFO_DESCRIPTION *CacheDescription;\r
343\r
344 if (CPUID_CACHE_INFO > gMaximumBasicFunction) {\r
345 return;\r
346 }\r
347\r
348 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
349\r
350 Print (L"CPUID_CACHE_INFO (Leaf %08x)\n", CPUID_CACHE_INFO);\r
351 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
352 if (Eax.Bits.NotValid == 0) {\r
353 //\r
354 // Process Eax.CacheDescriptor[1..3]. Ignore Eax.CacheDescriptor[0]\r
355 //\r
356 for (Index = 1; Index < 4; Index++) {\r
357 CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);\r
358 if (CacheDescription != NULL) {\r
053e878b
MK		 359 Print (\r
360 L" %-8a %a\n",\r
25705752
MK		 361 CacheDescription->Type,\r
362 CacheDescription->Description\r
363 );\r
364 }\r
365 }\r
366 }\r
053e878b 367\r
25705752
MK		 368 if (Ebx.Bits.NotValid == 0) {\r
369 //\r
370 // Process Ebx.CacheDescriptor[0..3]\r
371 //\r
372 for (Index = 0; Index < 4; Index++) {\r
373 CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);\r
374 if (CacheDescription != NULL) {\r
053e878b
MK		 375 Print (\r
376 L" %-8a %a\n",\r
25705752
MK		 377 CacheDescription->Type,\r
378 CacheDescription->Description\r
379 );\r
380 }\r
381 }\r
382 }\r
053e878b 383\r
25705752
MK		 384 if (Ecx.Bits.NotValid == 0) {\r
385 //\r
386 // Process Ecx.CacheDescriptor[0..3]\r
387 //\r
388 for (Index = 0; Index < 4; Index++) {\r
389 CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);\r
390 if (CacheDescription != NULL) {\r
053e878b
MK		 391 Print (\r
392 L" %-8a %a\n",\r
25705752
MK		 393 CacheDescription->Type,\r
394 CacheDescription->Description\r
395 );\r
396 }\r
397 }\r
398 }\r
053e878b 399\r
25705752
MK		 400 if (Edx.Bits.NotValid == 0) {\r
401 //\r
402 // Process Edx.CacheDescriptor[0..3]\r
403 //\r
404 for (Index = 0; Index < 4; Index++) {\r
405 CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);\r
406 if (CacheDescription != NULL) {\r
053e878b
MK		 407 Print (\r
408 L" %-8a %a\n",\r
25705752
MK		 409 CacheDescription->Type,\r
410 CacheDescription->Description\r
411 );\r
412 }\r
413 }\r
414 }\r
415}\r
416\r
417/**\r
418 Display CPUID_SERIAL_NUMBER leaf if it is supported.\r
419\r
420**/\r
421VOID\r
422CpuidSerialNumber (\r
423 VOID\r
424 )\r
425{\r
426 CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
427 UINT32 Ecx;\r
428 UINT32 Edx;\r
429\r
430 Print (L"CPUID_SERIAL_NUMBER (Leaf %08x)\n", CPUID_SERIAL_NUMBER);\r
431\r
432 if (CPUID_SERIAL_NUMBER > gMaximumBasicFunction) {\r
433 return;\r
434 }\r
435\r
436 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
437 if (VersionInfoEdx.Bits.PSN == 0) {\r
438 Print (L" Not Supported\n");\r
439 return;\r
440 }\r
441\r
442 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
443 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx, Edx);\r
444 Print (L" Processor Serial Number = %08x%08x%08x\n", 0, Edx, Ecx);\r
445}\r
446\r
447/**\r
448 Display CPUID_CACHE_PARAMS for all supported sub-leafs.\r
449\r
450**/\r
451VOID\r
452CpuidCacheParams (\r
453 VOID\r
454 )\r
455{\r
456 UINT32 CacheLevel;\r
457 CPUID_CACHE_PARAMS_EAX Eax;\r
458 CPUID_CACHE_PARAMS_EBX Ebx;\r
459 UINT32 Ecx;\r
460 CPUID_CACHE_PARAMS_EDX Edx;\r
461\r
462 if (CPUID_CACHE_PARAMS > gMaximumBasicFunction) {\r
463 return;\r
464 }\r
465\r
466 CacheLevel = 0;\r
467 do {\r
468 AsmCpuidEx (\r
053e878b
MK		 469 CPUID_CACHE_PARAMS,\r
470 CacheLevel,\r
471 &Eax.Uint32,\r
472 &Ebx.Uint32,\r
473 &Ecx,\r
474 &Edx.Uint32\r
25705752
MK		 475 );\r
476 if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {\r
477 Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);\r
478 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx, Edx.Uint32);\r
479 PRINT_BIT_FIELD (Eax, CacheType);\r
480 PRINT_BIT_FIELD (Eax, CacheLevel);\r
481 PRINT_BIT_FIELD (Eax, SelfInitializingCache);\r
482 PRINT_BIT_FIELD (Eax, FullyAssociativeCache);\r
483 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForLogicalProcessors);\r
484 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForProcessorCores);\r
485 PRINT_BIT_FIELD (Ebx, LineSize);\r
486 PRINT_BIT_FIELD (Ebx, LinePartitions);\r
487 PRINT_BIT_FIELD (Ebx, Ways);\r
053e878b 488 PRINT_VALUE (Ecx, NumberOfSets);\r
25705752
MK		 489 PRINT_BIT_FIELD (Edx, Invalidate);\r
490 PRINT_BIT_FIELD (Edx, CacheInclusiveness);\r
491 PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);\r
492 }\r
053e878b 493\r
25705752
MK		 494 CacheLevel++;\r
495 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
496}\r
497\r
498/**\r
499 Display CPUID_MONITOR_MWAIT leaf.\r
500\r
501**/\r
502VOID\r
503CpuidMonitorMwait (\r
504 VOID\r
505 )\r
506{\r
507 CPUID_MONITOR_MWAIT_EAX Eax;\r
508 CPUID_MONITOR_MWAIT_EBX Ebx;\r
509 CPUID_MONITOR_MWAIT_ECX Ecx;\r
510 CPUID_MONITOR_MWAIT_EDX Edx;\r
511\r
512 if (CPUID_MONITOR_MWAIT > gMaximumBasicFunction) {\r
513 return;\r
514 }\r
515\r
516 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
517\r
518 Print (L"CPUID_MONITOR_MWAIT (Leaf %08x)\n", CPUID_MONITOR_MWAIT);\r
519 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
520\r
521 PRINT_BIT_FIELD (Eax, SmallestMonitorLineSize);\r
522 PRINT_BIT_FIELD (Ebx, LargestMonitorLineSize);\r
523 PRINT_BIT_FIELD (Ecx, ExtensionsSupported);\r
524 PRINT_BIT_FIELD (Ecx, InterruptAsBreak);\r
525 PRINT_BIT_FIELD (Edx, C0States);\r
526 PRINT_BIT_FIELD (Edx, C1States);\r
527 PRINT_BIT_FIELD (Edx, C2States);\r
528 PRINT_BIT_FIELD (Edx, C3States);\r
529 PRINT_BIT_FIELD (Edx, C4States);\r
530 PRINT_BIT_FIELD (Edx, C5States);\r
531 PRINT_BIT_FIELD (Edx, C6States);\r
532 PRINT_BIT_FIELD (Edx, C7States);\r
533}\r
534\r
535/**\r
536 Display CPUID_THERMAL_POWER_MANAGEMENT leaf.\r
537\r
538**/\r
539VOID\r
540CpuidThermalPowerManagement (\r
541 VOID\r
542 )\r
543{\r
544 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r
545 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r
546 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r
547\r
548 if (CPUID_THERMAL_POWER_MANAGEMENT > gMaximumBasicFunction) {\r
549 return;\r
550 }\r
551\r
552 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
553\r
554 Print (L"CPUID_THERMAL_POWER_MANAGEMENT (Leaf %08x)\n", CPUID_THERMAL_POWER_MANAGEMENT);\r
555 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r
556\r
557 PRINT_BIT_FIELD (Eax, DigitalTemperatureSensor);\r
558 PRINT_BIT_FIELD (Eax, TurboBoostTechnology);\r
559 PRINT_BIT_FIELD (Eax, ARAT);\r
560 PRINT_BIT_FIELD (Eax, PLN);\r
561 PRINT_BIT_FIELD (Eax, ECMD);\r
562 PRINT_BIT_FIELD (Eax, PTM);\r
563 PRINT_BIT_FIELD (Eax, HWP);\r
564 PRINT_BIT_FIELD (Eax, HWP_Notification);\r
565 PRINT_BIT_FIELD (Eax, HWP_Activity_Window);\r
566 PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);\r
567 PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);\r
568 PRINT_BIT_FIELD (Eax, HDC);\r
56fbaecb
ED		 569 PRINT_BIT_FIELD (Eax, TurboBoostMaxTechnology30);\r
570 PRINT_BIT_FIELD (Eax, HWPCapabilities);\r
571 PRINT_BIT_FIELD (Eax, HWPPECIOverride);\r
572 PRINT_BIT_FIELD (Eax, FlexibleHWP);\r
573 PRINT_BIT_FIELD (Eax, FastAccessMode);\r
574 PRINT_BIT_FIELD (Eax, IgnoringIdleLogicalProcessorHWPRequest);\r
25705752
MK		 575 PRINT_BIT_FIELD (Ebx, InterruptThresholds);\r
576 PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);\r
577 PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);\r
578}\r
579\r
580/**\r
581 Display CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS for all supported sub-leafs.\r
582\r
583**/\r
584VOID\r
585CpuidStructuredExtendedFeatureFlags (\r
586 VOID\r
587 )\r
588{\r
589 UINT32 Eax;\r
590 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
591 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r
56fbaecb 592 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;\r
25705752
MK		 593 UINT32 SubLeaf;\r
594\r
595 if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {\r
596 return;\r
597 }\r
598\r
599 AsmCpuidEx (\r
600 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
601 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
053e878b
MK		 602 &Eax,\r
603 NULL,\r
604 NULL,\r
605 NULL\r
25705752
MK		 606 );\r
607 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
608 AsmCpuidEx (\r
609 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
610 SubLeaf,\r
053e878b
MK		 611 NULL,\r
612 &Ebx.Uint32,\r
613 &Ecx.Uint32,\r
614 &Edx.Uint32\r
25705752 615 );\r
053e878b 616 if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {\r
25705752 617 Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);\r
56fbaecb 618 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
25705752
MK		 619 PRINT_BIT_FIELD (Ebx, FSGSBASE);\r
620 PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);\r
f5a2d6f0 621 PRINT_BIT_FIELD (Ebx, SGX);\r
25705752
MK		 622 PRINT_BIT_FIELD (Ebx, BMI1);\r
623 PRINT_BIT_FIELD (Ebx, HLE);\r
624 PRINT_BIT_FIELD (Ebx, AVX2);\r
625 PRINT_BIT_FIELD (Ebx, FDP_EXCPTN_ONLY);\r
626 PRINT_BIT_FIELD (Ebx, SMEP);\r
627 PRINT_BIT_FIELD (Ebx, BMI2);\r
628 PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);\r
629 PRINT_BIT_FIELD (Ebx, INVPCID);\r
630 PRINT_BIT_FIELD (Ebx, RTM);\r
14806d7b 631 PRINT_BIT_FIELD (Ebx, RDT_M);\r
25705752
MK		 632 PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);\r
633 PRINT_BIT_FIELD (Ebx, MPX);\r
14806d7b 634 PRINT_BIT_FIELD (Ebx, RDT_A);\r
56fbaecb
ED		 635 PRINT_BIT_FIELD (Ebx, AVX512F);\r
636 PRINT_BIT_FIELD (Ebx, AVX512DQ);\r
25705752
MK		 637 PRINT_BIT_FIELD (Ebx, RDSEED);\r
638 PRINT_BIT_FIELD (Ebx, ADX);\r
639 PRINT_BIT_FIELD (Ebx, SMAP);\r
56fbaecb 640 PRINT_BIT_FIELD (Ebx, AVX512_IFMA);\r
25705752 641 PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);\r
14806d7b 642 PRINT_BIT_FIELD (Ebx, CLWB);\r
25705752 643 PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);\r
56fbaecb
ED		 644 PRINT_BIT_FIELD (Ebx, AVX512PF);\r
645 PRINT_BIT_FIELD (Ebx, AVX512ER);\r
646 PRINT_BIT_FIELD (Ebx, AVX512CD);\r
14806d7b 647 PRINT_BIT_FIELD (Ebx, SHA);\r
56fbaecb
ED		 648 PRINT_BIT_FIELD (Ebx, AVX512BW);\r
649 PRINT_BIT_FIELD (Ebx, AVX512VL);\r
650\r
25705752 651 PRINT_BIT_FIELD (Ecx, PREFETCHWT1);\r
56fbaecb 652 PRINT_BIT_FIELD (Ecx, AVX512_VBMI);\r
14806d7b 653 PRINT_BIT_FIELD (Ecx, UMIP);\r
25705752
MK		 654 PRINT_BIT_FIELD (Ecx, PKU);\r
655 PRINT_BIT_FIELD (Ecx, OSPKE);\r
56fbaecb 656 PRINT_BIT_FIELD (Ecx, AVX512_VPOPCNTDQ);\r
14806d7b
HW		 657 PRINT_BIT_FIELD (Ecx, MAWAU);\r
658 PRINT_BIT_FIELD (Ecx, RDPID);\r
659 PRINT_BIT_FIELD (Ecx, SGX_LC);\r
56fbaecb
ED		 660\r
661 PRINT_BIT_FIELD (Edx, AVX512_4VNNIW);\r
662 PRINT_BIT_FIELD (Edx, AVX512_4FMAPS);\r
663 PRINT_BIT_FIELD (Edx, EnumeratesSupportForIBRSAndIBPB);\r
664 PRINT_BIT_FIELD (Edx, EnumeratesSupportForSTIBP);\r
665 PRINT_BIT_FIELD (Edx, EnumeratesSupportForL1D_FLUSH);\r
666 PRINT_BIT_FIELD (Edx, EnumeratesSupportForCapability);\r
667 PRINT_BIT_FIELD (Edx, EnumeratesSupportForSSBD);\r
25705752 668 }\r
d93a10c0 669 }\r
25705752
MK		 670}\r
671\r
672/**\r
673 Display CPUID_DIRECT_CACHE_ACCESS_INFO leaf.\r
674\r
675**/\r
676VOID\r
677CpuidDirectCacheAccessInfo (\r
678 VOID\r
679 )\r
680{\r
681 UINT32 Eax;\r
682\r
683 if (CPUID_DIRECT_CACHE_ACCESS_INFO > gMaximumBasicFunction) {\r
684 return;\r
685 }\r
686\r
687 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
688 Print (L"CPUID_DIRECT_CACHE_ACCESS_INFO (Leaf %08x)\n", CPUID_DIRECT_CACHE_ACCESS_INFO);\r
689 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r
690}\r
691\r
692/**\r
693 Display CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING leaf.\r
694\r
695**/\r
696VOID\r
697CpuidArchitecturalPerformanceMonitoring (\r
698 VOID\r
699 )\r
700{\r
701 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r
702 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r
703 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r
704\r
705 if (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING > gMaximumBasicFunction) {\r
706 return;\r
707 }\r
708\r
709 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r
710 Print (L"CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (Leaf %08x)\n", CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING);\r
711 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, Edx.Uint32);\r
712 PRINT_BIT_FIELD (Eax, ArchPerfMonVerID);\r
713 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounters);\r
714 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounterWidth);\r
715 PRINT_BIT_FIELD (Eax, EbxBitVectorLength);\r
716 PRINT_BIT_FIELD (Ebx, UnhaltedCoreCycles);\r
717 PRINT_BIT_FIELD (Ebx, InstructionsRetired);\r
718 PRINT_BIT_FIELD (Ebx, UnhaltedReferenceCycles);\r
719 PRINT_BIT_FIELD (Ebx, LastLevelCacheReferences);\r
720 PRINT_BIT_FIELD (Ebx, LastLevelCacheMisses);\r
721 PRINT_BIT_FIELD (Ebx, BranchInstructionsRetired);\r
722 PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);\r
723 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);\r
724 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);\r
56fbaecb 725 PRINT_BIT_FIELD (Edx, AnyThreadDeprecation);\r
25705752
MK		 726}\r
727\r
728/**\r
729 Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.\r
730\r
501de814 731 @param[in] LeafFunction Leaf function index for CPUID_EXTENDED_TOPOLOGY.\r
d1904080 732\r
25705752
MK		 733**/\r
734VOID\r
735CpuidExtendedTopology (\r
053e878b 736 UINT32 LeafFunction\r
25705752
MK		 737 )\r
738{\r
739 CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
740 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r
741 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r
742 UINT32 Edx;\r
743 UINT32 LevelNumber;\r
744\r
079141eb
RN		 745 if (LeafFunction > gMaximumBasicFunction) {\r
746 return;\r
747 }\r
053e878b 748\r
079141eb 749 if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {\r
25705752
MK		 750 return;\r
751 }\r
752\r
753 LevelNumber = 0;\r
079141eb 754 for (LevelNumber = 0; ; LevelNumber++) {\r
25705752 755 AsmCpuidEx (\r
053e878b
MK		 756 LeafFunction,\r
757 LevelNumber,\r
758 &Eax.Uint32,\r
759 &Ebx.Uint32,\r
760 &Ecx.Uint32,\r
761 &Edx\r
25705752 762 );\r
079141eb
RN		 763 if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
764 break;\r
25705752 765 }\r
053e878b 766\r
079141eb
RN		 767 Print (\r
768 L"%a (Leaf %08x, Sub-Leaf %08x)\n",\r
769 LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",\r
053e878b
MK		 770 LeafFunction,\r
771 LevelNumber\r
079141eb
RN		 772 );\r
773 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);\r
774 PRINT_BIT_FIELD (Eax, ApicIdShift);\r
775 PRINT_BIT_FIELD (Ebx, LogicalProcessors);\r
776 PRINT_BIT_FIELD (Ecx, LevelNumber);\r
777 PRINT_BIT_FIELD (Ecx, LevelType);\r
053e878b 778 PRINT_VALUE (Edx, x2APIC_ID);\r
079141eb 779 }\r
25705752
MK		 780}\r
781\r
782/**\r
783 Display CPUID_EXTENDED_STATE sub-leaf.\r
784\r
785**/\r
786VOID\r
787CpuidExtendedStateSubLeaf (\r
788 VOID\r
789 )\r
790{\r
791 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r
792 UINT32 Ebx;\r
793 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r
794 UINT32 Edx;\r
795\r
796 AsmCpuidEx (\r
053e878b
MK		 797 CPUID_EXTENDED_STATE,\r
798 CPUID_EXTENDED_STATE_SUB_LEAF,\r
799 &Eax.Uint32,\r
800 &Ebx,\r
801 &Ecx.Uint32,\r
802 &Edx\r
25705752
MK		 803 );\r
804 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);\r
805 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);\r
806 PRINT_BIT_FIELD (Eax, XSAVEOPT);\r
807 PRINT_BIT_FIELD (Eax, XSAVEC);\r
808 PRINT_BIT_FIELD (Eax, XGETBV);\r
809 PRINT_BIT_FIELD (Eax, XSAVES);\r
053e878b 810 PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r
25705752 811 PRINT_BIT_FIELD (Ecx, XCR0);\r
56fbaecb 812 PRINT_BIT_FIELD (Ecx, HWPState);\r
25705752
MK		 813 PRINT_BIT_FIELD (Ecx, PT);\r
814 PRINT_BIT_FIELD (Ecx, XCR0_1);\r
053e878b 815 PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);\r
25705752
MK		 816}\r
817\r
818/**\r
819 Display CPUID_EXTENDED_STATE size and offset information sub-leaf.\r
820\r
821**/\r
822VOID\r
823CpuidExtendedStateSizeOffset (\r
824 VOID\r
825 )\r
826{\r
827 UINT32 Eax;\r
828 UINT32 Ebx;\r
829 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r
830 UINT32 Edx;\r
831 UINT32 SubLeaf;\r
832\r
833 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
834 AsmCpuidEx (\r
053e878b
MK		 835 CPUID_EXTENDED_STATE,\r
836 SubLeaf,\r
837 &Eax,\r
838 &Ebx,\r
839 &Ecx.Uint32,\r
840 &Edx\r
25705752
MK		 841 );\r
842 if (Edx != 0) {\r
843 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);\r
844 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);\r
053e878b
MK		 845 PRINT_VALUE (Eax, FeatureSaveStateSize);\r
846 PRINT_VALUE (Ebx, FeatureSaveStateOffset);\r
25705752
MK		 847 PRINT_BIT_FIELD (Ecx, XSS);\r
848 PRINT_BIT_FIELD (Ecx, Compacted);\r
849 }\r
850 }\r
851}\r
852\r
853/**\r
854 Display CPUID_EXTENDED_STATE main leaf and sub-leafs.\r
855\r
856**/\r
857VOID\r
858CpuidExtendedStateMainLeaf (\r
859 VOID\r
860 )\r
861{\r
862 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r
863 UINT32 Ebx;\r
864 UINT32 Ecx;\r
865 UINT32 Edx;\r
866\r
867 if (CPUID_EXTENDED_STATE > gMaximumBasicFunction) {\r
868 return;\r
869 }\r
870\r
871 AsmCpuidEx (\r
053e878b
MK		 872 CPUID_EXTENDED_STATE,\r
873 CPUID_EXTENDED_STATE_MAIN_LEAF,\r
874 &Eax.Uint32,\r
875 &Ebx,\r
876 &Ecx,\r
877 &Edx\r
25705752
MK		 878 );\r
879 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);\r
880 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);\r
881 PRINT_BIT_FIELD (Eax, x87);\r
882 PRINT_BIT_FIELD (Eax, SSE);\r
883 PRINT_BIT_FIELD (Eax, AVX);\r
884 PRINT_BIT_FIELD (Eax, MPX);\r
885 PRINT_BIT_FIELD (Eax, AVX_512);\r
886 PRINT_BIT_FIELD (Eax, IA32_XSS);\r
887 PRINT_BIT_FIELD (Eax, PKRU);\r
56fbaecb 888 PRINT_BIT_FIELD (Eax, IA32_XSS_2);\r
053e878b
MK		 889 PRINT_VALUE (Ebx, EnabledSaveStateSize);\r
890 PRINT_VALUE (Ecx, SupportedSaveStateSize);\r
891 PRINT_VALUE (Edx, XCR0_Supported_32_63);\r
25705752
MK		 892\r
893 CpuidExtendedStateSubLeaf ();\r
894 CpuidExtendedStateSizeOffset ();\r
895}\r
896\r
897/**\r
14806d7b 898 Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.\r
25705752
MK		 899\r
900**/\r
901VOID\r
14806d7b 902CpuidIntelRdtMonitoringEnumerationSubLeaf (\r
25705752
MK		 903 VOID\r
904 )\r
905{\r
053e878b
MK		 906 UINT32 Ebx;\r
907 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
25705752 908\r
14806d7b 909 if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
25705752
MK		 910 return;\r
911 }\r
912\r
913 AsmCpuidEx (\r
053e878b
MK		 914 CPUID_INTEL_RDT_MONITORING,\r
915 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
916 NULL,\r
917 &Ebx,\r
918 NULL,\r
919 &Edx.Uint32\r
25705752 920 );\r
14806d7b 921 Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);\r
25705752 922 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
053e878b 923 PRINT_VALUE (Ebx, Maximum_RMID_Range);\r
14806d7b 924 PRINT_BIT_FIELD (Edx, L3CacheRDT_M);\r
25705752
MK		 925}\r
926\r
927/**\r
14806d7b 928 Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.\r
25705752
MK		 929\r
930**/\r
931VOID\r
14806d7b 932CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (\r
25705752
MK		 933 VOID\r
934 )\r
935{\r
053e878b
MK		 936 UINT32 Ebx;\r
937 UINT32 Ecx;\r
938 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r
25705752 939\r
14806d7b 940 if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
25705752
MK		 941 return;\r
942 }\r
943\r
944 AsmCpuidEx (\r
053e878b
MK		 945 CPUID_INTEL_RDT_MONITORING,\r
946 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
947 NULL,\r
948 &Ebx,\r
949 &Ecx,\r
950 &Edx.Uint32\r
25705752 951 );\r
14806d7b 952 Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);\r
25705752 953 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
053e878b
MK		 954 PRINT_VALUE (Ebx, OccupancyConversionFactor);\r
955 PRINT_VALUE (Ecx, Maximum_RMID_Range);\r
25705752 956 PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r
14806d7b
HW		 957 PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);\r
958 PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);\r
25705752
MK		 959}\r
960\r
56fbaecb
ED		 961/**\r
962 Display CPUID_INTEL_RDT_ALLOCATION memory bandwidth allocation technology enumeration\r
963 sub-leaf.\r
964\r
965**/\r
966VOID\r
967CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (\r
968 VOID\r
969 )\r
970{\r
971 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;\r
972 UINT32 Ebx;\r
973 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;\r
974 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;\r
975\r
976 AsmCpuidEx (\r
053e878b
MK		 977 CPUID_INTEL_RDT_ALLOCATION,\r
978 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r
979 &Eax.Uint32,\r
980 &Ebx,\r
981 &Ecx.Uint32,\r
982 &Edx.Uint32\r
56fbaecb
ED		 983 );\r
984 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);\r
985 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
986 PRINT_BIT_FIELD (Eax, MaximumMBAThrottling);\r
053e878b 987 PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
56fbaecb
ED		 988 PRINT_BIT_FIELD (Ecx, Liner);\r
989 PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
990}\r
991\r
25705752 992/**\r
14806d7b
HW		 993 Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration\r
994 sub-leaf.\r
25705752
MK		 995\r
996**/\r
997VOID\r
14806d7b 998CpuidIntelRdtAllocationL3CacheSubLeaf (\r
25705752
MK		 999 VOID\r
1000 )\r
1001{\r
14806d7b 1002 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r
25705752 1003 UINT32 Ebx;\r
14806d7b
HW		 1004 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r
1005 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r
25705752
MK		 1006\r
1007 AsmCpuidEx (\r
053e878b
MK		 1008 CPUID_INTEL_RDT_ALLOCATION,\r
1009 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
1010 &Eax.Uint32,\r
1011 &Ebx,\r
1012 &Ecx.Uint32,\r
1013 &Edx.Uint32\r
25705752 1014 );\r
14806d7b 1015 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);\r
25705752
MK		 1016 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
1017 PRINT_BIT_FIELD (Eax, CapacityLength);\r
053e878b 1018 PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
25705752
MK		 1019 PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);\r
1020 PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
1021}\r
1022\r
1023/**\r
14806d7b
HW		 1024 Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration\r
1025 sub-leaf.\r
25705752
MK		 1026\r
1027**/\r
1028VOID\r
14806d7b 1029CpuidIntelRdtAllocationL2CacheSubLeaf (\r
25705752
MK		 1030 VOID\r
1031 )\r
1032{\r
14806d7b
HW		 1033 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r
1034 UINT32 Ebx;\r
1035 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r
1036\r
1037 AsmCpuidEx (\r
053e878b
MK		 1038 CPUID_INTEL_RDT_ALLOCATION,\r
1039 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
1040 &Eax.Uint32,\r
1041 &Ebx,\r
1042 NULL,\r
1043 &Edx.Uint32\r
14806d7b
HW		 1044 );\r
1045 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);\r
1046 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
1047 PRINT_BIT_FIELD (Eax, CapacityLength);\r
053e878b 1048 PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
14806d7b
HW		 1049 PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
1050}\r
1051\r
1052/**\r
1053 Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.\r
1054\r
1055**/\r
1056VOID\r
1057CpuidIntelRdtAllocationMainLeaf (\r
1058 VOID\r
1059 )\r
1060{\r
1061 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r
25705752 1062\r
14806d7b 1063 if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {\r
25705752
MK		 1064 return;\r
1065 }\r
1066\r
1067 AsmCpuidEx (\r
053e878b
MK		 1068 CPUID_INTEL_RDT_ALLOCATION,\r
1069 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
1070 NULL,\r
1071 &Ebx.Uint32,\r
1072 NULL,\r
1073 NULL\r
25705752 1074 );\r
14806d7b 1075 Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);\r
25705752 1076 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r
14806d7b
HW		 1077 PRINT_BIT_FIELD (Ebx, L3CacheAllocation);\r
1078 PRINT_BIT_FIELD (Ebx, L2CacheAllocation);\r
56fbaecb
ED		 1079 PRINT_BIT_FIELD (Ebx, MemoryBandwidth);\r
1080 CpuidIntelRdtAllocationMemoryBandwidthSubLeaf ();\r
14806d7b
HW		 1081 CpuidIntelRdtAllocationL3CacheSubLeaf ();\r
1082 CpuidIntelRdtAllocationL2CacheSubLeaf ();\r
25705752
MK		 1083}\r
1084\r
f5a2d6f0
JF		 1085/**\r
1086 Display Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
1087\r
1088**/\r
1089VOID\r
1090CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (\r
1091 VOID\r
1092 )\r
1093{\r
1094 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r
1095 UINT32 Ebx;\r
1096 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r
1097\r
1098 AsmCpuidEx (\r
053e878b
MK		 1099 CPUID_INTEL_SGX,\r
1100 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
1101 &Eax.Uint32,\r
1102 &Ebx,\r
1103 NULL,\r
1104 &Edx.Uint32\r
f5a2d6f0
JF		 1105 );\r
1106 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);\r
1107 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
1108 PRINT_BIT_FIELD (Eax, SGX1);\r
1109 PRINT_BIT_FIELD (Eax, SGX2);\r
56fbaecb
ED		 1110 PRINT_BIT_FIELD (Eax, ENCLV);\r
1111 PRINT_BIT_FIELD (Eax, ENCLS);\r
f5a2d6f0
JF		 1112 PRINT_BIT_FIELD (Edx, MaxEnclaveSize_Not64);\r
1113 PRINT_BIT_FIELD (Edx, MaxEnclaveSize_64);\r
1114}\r
1115\r
1116/**\r
1117 Display Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
1118\r
1119**/\r
1120VOID\r
1121CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (\r
1122 VOID\r
1123 )\r
1124{\r
053e878b
MK		 1125 UINT32 Eax;\r
1126 UINT32 Ebx;\r
1127 UINT32 Ecx;\r
1128 UINT32 Edx;\r
f5a2d6f0
JF		 1129\r
1130 AsmCpuidEx (\r
053e878b
MK		 1131 CPUID_INTEL_SGX,\r
1132 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
1133 &Eax,\r
1134 &Ebx,\r
1135 &Ecx,\r
1136 &Edx\r
f5a2d6f0
JF		 1137 );\r
1138 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);\r
1139 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
1140}\r
1141\r
1142/**\r
1143 Display Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
1144\r
1145**/\r
1146VOID\r
1147CpuidEnumerationOfIntelSgxResourcesSubLeaf (\r
1148 VOID\r
1149 )\r
1150{\r
1151 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r
1152 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r
1153 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r
1154 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r
1155 UINT32 SubLeaf;\r
7367cc6c 1156\r
f5a2d6f0
JF		 1157 SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r
1158 do {\r
1159 AsmCpuidEx (\r
053e878b
MK		 1160 CPUID_INTEL_SGX,\r
1161 SubLeaf,\r
1162 &Eax.Uint32,\r
1163 &Ebx.Uint32,\r
1164 &Ecx.Uint32,\r
1165 &Edx.Uint32\r
f5a2d6f0
JF		 1166 );\r
1167 if (Eax.Bits.SubLeafType == 0x1) {\r
1168 Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);\r
1169 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1170 PRINT_BIT_FIELD (Eax, SubLeafType);\r
1171 PRINT_BIT_FIELD (Eax, LowAddressOfEpcSection);\r
1172 PRINT_BIT_FIELD (Ebx, HighAddressOfEpcSection);\r
1173 PRINT_BIT_FIELD (Ecx, EpcSection);\r
1174 PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);\r
1175 PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);\r
1176 }\r
053e878b 1177\r
f5a2d6f0
JF		 1178 SubLeaf++;\r
1179 } while (Eax.Bits.SubLeafType == 0x1);\r
1180}\r
1181\r
1182/**\r
1183 Display Intel SGX Resource Enumeration.\r
1184\r
1185**/\r
1186VOID\r
1187CpuidEnumerationOfIntelSgx (\r
1188 VOID\r
1189 )\r
1190{\r
1191 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
1192\r
1193 if (CPUID_INTEL_SGX > gMaximumBasicFunction) {\r
1194 return;\r
1195 }\r
1196\r
1197 AsmCpuidEx (\r
1198 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
1199 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
053e878b
MK		 1200 NULL,\r
1201 &Ebx.Uint32,\r
1202 NULL,\r
1203 NULL\r
f5a2d6f0
JF		 1204 );\r
1205 if (Ebx.Bits.SGX != 1) {\r
1206 //\r
1207 // Only if CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor has support\r
1208 // for Intel SGX.\r
1209 //\r
1210 return;\r
1211 }\r
7367cc6c 1212\r
f5a2d6f0
JF		 1213 CpuidEnumerationOfIntelSgxCapabilities0SubLeaf ();\r
1214 CpuidEnumerationOfIntelSgxCapabilities1SubLeaf ();\r
1215 CpuidEnumerationOfIntelSgxResourcesSubLeaf ();\r
1216}\r
1217\r
25705752
MK		 1218/**\r
1219 Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.\r
1220\r
1221 @param[in] MaximumSubLeaf Maximum sub-leaf index for CPUID_INTEL_PROCESSOR_TRACE.\r
1222\r
1223**/\r
1224VOID\r
1225CpuidIntelProcessorTraceSubLeaf (\r
1226 UINT32 MaximumSubLeaf\r
1227 )\r
1228{\r
1229 UINT32 SubLeaf;\r
1230 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r
1231 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r
1232\r
1233 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
1234 AsmCpuidEx (\r
053e878b
MK		 1235 CPUID_INTEL_PROCESSOR_TRACE,\r
1236 SubLeaf,\r
1237 &Eax.Uint32,\r
1238 &Ebx.Uint32,\r
1239 NULL,\r
1240 NULL\r
25705752
MK		 1241 );\r
1242 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);\r
1243 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);\r
1244 PRINT_BIT_FIELD (Eax, ConfigurableAddressRanges);\r
1245 PRINT_BIT_FIELD (Eax, MtcPeriodEncodings);\r
1246 PRINT_BIT_FIELD (Ebx, CycleThresholdEncodings);\r
1247 PRINT_BIT_FIELD (Ebx, PsbFrequencyEncodings);\r
1248 }\r
1249}\r
1250\r
1251/**\r
1252 Display CPUID_INTEL_PROCESSOR_TRACE main leaf and sub-leafs.\r
1253\r
1254**/\r
1255VOID\r
1256CpuidIntelProcessorTraceMainLeaf (\r
1257 VOID\r
1258 )\r
1259{\r
1260 UINT32 Eax;\r
1261 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r
1262 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r
1263\r
1264 if (CPUID_INTEL_PROCESSOR_TRACE > gMaximumBasicFunction) {\r
1265 return;\r
1266 }\r
1267\r
1268 AsmCpuidEx (\r
053e878b
MK		 1269 CPUID_INTEL_PROCESSOR_TRACE,\r
1270 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
1271 &Eax,\r
1272 &Ebx.Uint32,\r
1273 &Ecx.Uint32,\r
1274 NULL\r
25705752
MK		 1275 );\r
1276 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);\r
1277 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
053e878b 1278 PRINT_VALUE (Eax, MaximumSubLeaf);\r
25705752
MK		 1279 PRINT_BIT_FIELD (Ebx, Cr3Filter);\r
1280 PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
1281 PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
1282 PRINT_BIT_FIELD (Ebx, Mtc);\r
14806d7b
HW		 1283 PRINT_BIT_FIELD (Ebx, PTWrite);\r
1284 PRINT_BIT_FIELD (Ebx, PowerEventTrace);\r
25705752
MK		 1285 PRINT_BIT_FIELD (Ecx, RTIT);\r
1286 PRINT_BIT_FIELD (Ecx, ToPA);\r
1287 PRINT_BIT_FIELD (Ecx, SingleRangeOutput);\r
1288 PRINT_BIT_FIELD (Ecx, TraceTransportSubsystem);\r
1289 PRINT_BIT_FIELD (Ecx, LIP);\r
1290\r
1291 CpuidIntelProcessorTraceSubLeaf (Eax);\r
1292}\r
1293\r
1294/**\r
1295 Display CPUID_TIME_STAMP_COUNTER leaf.\r
1296\r
1297**/\r
1298VOID\r
1299CpuidTimeStampCounter (\r
1300 VOID\r
1301 )\r
1302{\r
1303 UINT32 Eax;\r
1304 UINT32 Ebx;\r
14806d7b 1305 UINT32 Ecx;\r
25705752
MK		 1306\r
1307 if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {\r
1308 return;\r
1309 }\r
1310\r
14806d7b 1311 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
25705752 1312 Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);\r
14806d7b 1313 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);\r
25705752
MK		 1314}\r
1315\r
1316/**\r
1317 Display CPUID_PROCESSOR_FREQUENCY leaf.\r
1318\r
1319**/\r
1320VOID\r
1321CpuidProcessorFrequency (\r
1322 VOID\r
1323 )\r
1324{\r
1325 CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r
1326 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r
1327 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r
1328\r
1329 if (CPUID_PROCESSOR_FREQUENCY > gMaximumBasicFunction) {\r
1330 return;\r
1331 }\r
1332\r
1333 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
1334 Print (L"CPUID_PROCESSOR_FREQUENCY (Leaf %08x)\n", CPUID_PROCESSOR_FREQUENCY);\r
1335 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r
1336 PRINT_BIT_FIELD (Eax, ProcessorBaseFrequency);\r
1337 PRINT_BIT_FIELD (Ebx, MaximumFrequency);\r
1338 PRINT_BIT_FIELD (Ecx, BusFrequency);\r
1339}\r
1340\r
1341/**\r
1342 Display CPUID_SOC_VENDOR sub-leafs that contain the SoC Vendor Brand String.\r
1343 Also display these sub-leafs as a single SoC Vendor Brand String.\r
1344\r
1345**/\r
1346VOID\r
1347CpuidSocVendorBrandString (\r
1348 VOID\r
1349 )\r
1350{\r
1351 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
1352 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
1353 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
1354 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
1355 //\r
1356 // Array to store brand string from 3 brand string leafs with\r
1357 // 4 32-bit brand string values per leaf and an extra value to\r
1358 // null terminate the string.\r
1359 //\r
053e878b 1360 UINT32 BrandString[3 * 4 + 1];\r
25705752
MK		 1361\r
1362 AsmCpuidEx (\r
053e878b
MK		 1363 CPUID_SOC_VENDOR,\r
1364 CPUID_SOC_VENDOR_BRAND_STRING1,\r
1365 &Eax.Uint32,\r
1366 &Ebx.Uint32,\r
1367 &Ecx.Uint32,\r
1368 &Edx.Uint32\r
25705752
MK		 1369 );\r
1370 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);\r
1371 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1372 BrandString[0] = Eax.Uint32;\r
1373 BrandString[1] = Ebx.Uint32;\r
1374 BrandString[2] = Ecx.Uint32;\r
1375 BrandString[3] = Edx.Uint32;\r
1376\r
1377 AsmCpuidEx (\r
053e878b
MK		 1378 CPUID_SOC_VENDOR,\r
1379 CPUID_SOC_VENDOR_BRAND_STRING2,\r
1380 &Eax.Uint32,\r
1381 &Ebx.Uint32,\r
1382 &Ecx.Uint32,\r
1383 &Edx.Uint32\r
25705752
MK		 1384 );\r
1385 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);\r
1386 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1387 BrandString[4] = Eax.Uint32;\r
1388 BrandString[5] = Ebx.Uint32;\r
1389 BrandString[6] = Ecx.Uint32;\r
1390 BrandString[7] = Edx.Uint32;\r
1391\r
1392 AsmCpuidEx (\r
053e878b
MK		 1393 CPUID_SOC_VENDOR,\r
1394 CPUID_SOC_VENDOR_BRAND_STRING3,\r
1395 &Eax.Uint32,\r
1396 &Ebx.Uint32,\r
1397 &Ecx.Uint32,\r
1398 &Edx.Uint32\r
25705752
MK		 1399 );\r
1400 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);\r
1401 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1402 BrandString[8] = Eax.Uint32;\r
1403 BrandString[9] = Ebx.Uint32;\r
1404 BrandString[10] = Ecx.Uint32;\r
1405 BrandString[11] = Edx.Uint32;\r
1406\r
1407 BrandString[12] = 0;\r
1408\r
1409 Print (L"Vendor Brand String = %a\n", (CHAR8 *)BrandString);\r
1410}\r
1411\r
1412/**\r
1413 Display CPUID_SOC_VENDOR main leaf and sub-leafs.\r
1414\r
1415**/\r
1416VOID\r
1417CpuidSocVendor (\r
1418 VOID\r
1419 )\r
1420{\r
1421 UINT32 Eax;\r
1422 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r
1423 UINT32 Ecx;\r
1424 UINT32 Edx;\r
1425\r
1426 if (CPUID_SOC_VENDOR > gMaximumBasicFunction) {\r
1427 return;\r
1428 }\r
1429\r
1430 AsmCpuidEx (\r
053e878b
MK		 1431 CPUID_SOC_VENDOR,\r
1432 CPUID_SOC_VENDOR_MAIN_LEAF,\r
1433 &Eax,\r
1434 &Ebx.Uint32,\r
1435 &Ecx,\r
1436 &Edx\r
25705752
MK		 1437 );\r
1438 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);\r
1439 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);\r
1440 if (Eax < 3) {\r
1441 Print (L" Not Supported\n");\r
1442 return;\r
1443 }\r
053e878b
MK		 1444\r
1445 PRINT_VALUE (Eax, MaxSOCID_Index);\r
25705752
MK		 1446 PRINT_BIT_FIELD (Ebx, SocVendorId);\r
1447 PRINT_BIT_FIELD (Ebx, IsVendorScheme);\r
053e878b
MK		 1448 PRINT_VALUE (Ecx, ProjectID);\r
1449 PRINT_VALUE (Edx, SteppingID);\r
25705752
MK		 1450 CpuidSocVendorBrandString ();\r
1451}\r
1452\r
56fbaecb
ED		 1453/**\r
1454 Display CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS main leaf and sub-leafs.\r
1455\r
1456**/\r
1457VOID\r
1458CpuidDeterministicAddressTranslationParameters (\r
1459 VOID\r
1460 )\r
1461{\r
1462 UINT32 Eax;\r
1463 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;\r
1464 UINT32 Ecx;\r
1465 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;\r
1466\r
1467 if (CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS > gMaximumBasicFunction) {\r
1468 return;\r
1469 }\r
1470\r
1471 AsmCpuidEx (\r
1472 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,\r
1473 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,\r
053e878b
MK		 1474 &Eax,\r
1475 &Ebx.Uint32,\r
1476 &Ecx,\r
1477 &Edx.Uint32\r
56fbaecb
ED		 1478 );\r
1479 Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);\r
1480 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);\r
1481\r
053e878b 1482 PRINT_VALUE (Eax, MaxID_Index);\r
56fbaecb
ED		 1483 PRINT_BIT_FIELD (Ebx, Page4K);\r
1484 PRINT_BIT_FIELD (Ebx, Page2M);\r
1485 PRINT_BIT_FIELD (Ebx, Page4M);\r
1486 PRINT_BIT_FIELD (Ebx, Page1G);\r
1487 PRINT_BIT_FIELD (Ebx, Partitioning);\r
1488 PRINT_BIT_FIELD (Ebx, Way);\r
1489\r
053e878b 1490 PRINT_VALUE (Ecx, NumberOfSets);\r
56fbaecb
ED		 1491\r
1492 PRINT_BIT_FIELD (Edx, TranslationCacheType);\r
1493 PRINT_BIT_FIELD (Edx, TranslationCacheLevel);\r
1494 PRINT_BIT_FIELD (Edx, FullyAssociative);\r
1495 PRINT_BIT_FIELD (Edx, MaximumNum);\r
1496}\r
1497\r
25705752
MK		 1498/**\r
1499 Display CPUID_EXTENDED_FUNCTION leaf.\r
1500\r
1501**/\r
1502VOID\r
1503CpuidExtendedFunction (\r
1504 VOID\r
1505 )\r
1506{\r
1507 UINT32 Eax;\r
1508\r
1509 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
1510 Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);\r
1511 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r
053e878b 1512 PRINT_VALUE (Eax, MaximumExtendedFunction);\r
25705752
MK		 1513\r
1514 gMaximumExtendedFunction = Eax;\r
1515}\r
1516\r
1517/**\r
1518 Display CPUID_EXTENDED_CPU_SIG leaf.\r
1519\r
1520**/\r
1521VOID\r
1522CpuidExtendedCpuSig (\r
1523 VOID\r
1524 )\r
1525{\r
1526 UINT32 Eax;\r
1527 CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r
1528 CPUID_EXTENDED_CPU_SIG_EDX Edx;\r
1529\r
1530 if (CPUID_EXTENDED_CPU_SIG > gMaximumExtendedFunction) {\r
1531 return;\r
1532 }\r
1533\r
1534 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
1535 Print (L"CPUID_EXTENDED_CPU_SIG (Leaf %08x)\n", CPUID_EXTENDED_CPU_SIG);\r
1536 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, Ecx.Uint32, Edx.Uint32);\r
1537 PRINT_BIT_FIELD (Ecx, LAHF_SAHF);\r
1538 PRINT_BIT_FIELD (Ecx, LZCNT);\r
1539 PRINT_BIT_FIELD (Ecx, PREFETCHW);\r
1540 PRINT_BIT_FIELD (Edx, SYSCALL_SYSRET);\r
1541 PRINT_BIT_FIELD (Edx, NX);\r
1542 PRINT_BIT_FIELD (Edx, Page1GB);\r
1543 PRINT_BIT_FIELD (Edx, RDTSCP);\r
1544 PRINT_BIT_FIELD (Edx, LM);\r
1545}\r
1546\r
1547/**\r
1548 Display CPUID_BRAND_STRING1, CPUID_BRAND_STRING2 and CPUID_BRAND_STRING3\r
1549 leafs. Also display these three leafs as a single brand string.\r
1550\r
1551**/\r
1552VOID\r
1553CpuidProcessorBrandString (\r
1554 VOID\r
1555 )\r
1556{\r
1557 CPUID_BRAND_STRING_DATA Eax;\r
1558 CPUID_BRAND_STRING_DATA Ebx;\r
1559 CPUID_BRAND_STRING_DATA Ecx;\r
1560 CPUID_BRAND_STRING_DATA Edx;\r
1561 //\r
1562 // Array to store brand string from 3 brand string leafs with\r
1563 // 4 32-bit brand string values per leaf and an extra value to\r
1564 // null terminate the string.\r
1565 //\r
053e878b 1566 UINT32 BrandString[3 * 4 + 1];\r
25705752
MK		 1567\r
1568 if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {\r
1569 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1570 Print (L"CPUID_BRAND_STRING1 (Leaf %08x)\n", CPUID_BRAND_STRING1);\r
1571 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1572 BrandString[0] = Eax.Uint32;\r
1573 BrandString[1] = Ebx.Uint32;\r
1574 BrandString[2] = Ecx.Uint32;\r
1575 BrandString[3] = Edx.Uint32;\r
1576 }\r
1577\r
1578 if (CPUID_BRAND_STRING2 <= gMaximumExtendedFunction) {\r
1579 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1580 Print (L"CPUID_BRAND_STRING2 (Leaf %08x)\n", CPUID_BRAND_STRING2);\r
1581 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1582 BrandString[4] = Eax.Uint32;\r
1583 BrandString[5] = Ebx.Uint32;\r
1584 BrandString[6] = Ecx.Uint32;\r
1585 BrandString[7] = Edx.Uint32;\r
1586 }\r
1587\r
1588 if (CPUID_BRAND_STRING3 <= gMaximumExtendedFunction) {\r
1589 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1590 Print (L"CPUID_BRAND_STRING3 (Leaf %08x)\n", CPUID_BRAND_STRING3);\r
1591 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1592 BrandString[8] = Eax.Uint32;\r
1593 BrandString[9] = Ebx.Uint32;\r
1594 BrandString[10] = Ecx.Uint32;\r
1595 BrandString[11] = Edx.Uint32;\r
1596 }\r
1597\r
1598 BrandString[12] = 0;\r
1599\r
1600 Print (L"Brand String = %a\n", (CHAR8 *)BrandString);\r
1601}\r
1602\r
1603/**\r
1604 Display CPUID_EXTENDED_CACHE_INFO leaf.\r
1605\r
1606**/\r
1607VOID\r
1608CpuidExtendedCacheInfo (\r
1609 VOID\r
1610 )\r
1611{\r
1612 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r
1613\r
1614 if (CPUID_EXTENDED_CACHE_INFO > gMaximumExtendedFunction) {\r
1615 return;\r
1616 }\r
1617\r
1618 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
1619 Print (L"CPUID_EXTENDED_CACHE_INFO (Leaf %08x)\n", CPUID_EXTENDED_CACHE_INFO);\r
1620 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx.Uint32, 0);\r
1621 PRINT_BIT_FIELD (Ecx, CacheLineSize);\r
1622 PRINT_BIT_FIELD (Ecx, L2Associativity);\r
1623 PRINT_BIT_FIELD (Ecx, CacheSize);\r
1624}\r
1625\r
1626/**\r
1627 Display CPUID_EXTENDED_TIME_STAMP_COUNTER leaf.\r
1628\r
1629**/\r
1630VOID\r
1631CpuidExtendedTimeStampCounter (\r
1632 VOID\r
1633 )\r
1634{\r
1635 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r
1636\r
1637 if (CPUID_EXTENDED_TIME_STAMP_COUNTER > gMaximumExtendedFunction) {\r
1638 return;\r
1639 }\r
1640\r
1641 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r
1642 Print (L"CPUID_EXTENDED_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_EXTENDED_TIME_STAMP_COUNTER);\r
1643 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, 0, Edx.Uint32);\r
1644 PRINT_BIT_FIELD (Edx, InvariantTsc);\r
1645}\r
1646\r
1647/**\r
1648 Display CPUID_VIR_PHY_ADDRESS_SIZE leaf.\r
1649\r
1650**/\r
1651VOID\r
1652CpuidVirPhyAddressSize (\r
1653 VOID\r
1654 )\r
1655{\r
1656 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r
1657\r
1658 if (CPUID_VIR_PHY_ADDRESS_SIZE > gMaximumExtendedFunction) {\r
1659 return;\r
1660 }\r
1661\r
1662 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r
1663 Print (L"CPUID_VIR_PHY_ADDRESS_SIZE (Leaf %08x)\n", CPUID_VIR_PHY_ADDRESS_SIZE);\r
1664 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, 0, 0, 0);\r
1665 PRINT_BIT_FIELD (Eax, PhysicalAddressBits);\r
1666 PRINT_BIT_FIELD (Eax, LinearAddressBits);\r
1667}\r
1668\r
1669/**\r
1670 The user Entry Point for Application. The user code starts with this function\r
1671 as the real entry point for the application.\r
1672\r
1673 @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
1674 @param[in] SystemTable A pointer to the EFI System Table.\r
1675\r
1676 @retval EFI_SUCCESS The entry point is executed successfully.\r
1677 @retval other Some error occurs when executing this entry point.\r
1678\r
1679**/\r
1680EFI_STATUS\r
1681EFIAPI\r
1682UefiMain (\r
1683 IN EFI_HANDLE ImageHandle,\r
1684 IN EFI_SYSTEM_TABLE *SystemTable\r
1685 )\r
1686{\r
1687 Print (L"UEFI CPUID Version 0.5\n");\r
1688\r
1689 CpuidSignature ();\r
1690 CpuidVersionInfo ();\r
1691 CpuidCacheInfo ();\r
1692 CpuidSerialNumber ();\r
053e878b 1693 CpuidCacheParams ();\r
25705752
MK		 1694 CpuidMonitorMwait ();\r
1695 CpuidThermalPowerManagement ();\r
1696 CpuidStructuredExtendedFeatureFlags ();\r
053e878b 1697 CpuidDirectCacheAccessInfo ();\r
25705752 1698 CpuidArchitecturalPerformanceMonitoring ();\r
079141eb 1699 CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);\r
25705752 1700 CpuidExtendedStateMainLeaf ();\r
14806d7b
HW		 1701 CpuidIntelRdtMonitoringEnumerationSubLeaf ();\r
1702 CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();\r
1703 CpuidIntelRdtAllocationMainLeaf ();\r
f5a2d6f0 1704 CpuidEnumerationOfIntelSgx ();\r
25705752
MK		 1705 CpuidIntelProcessorTraceMainLeaf ();\r
1706 CpuidTimeStampCounter ();\r
1707 CpuidProcessorFrequency ();\r
1708 CpuidSocVendor ();\r
56fbaecb 1709 CpuidDeterministicAddressTranslationParameters ();\r
079141eb 1710 CpuidExtendedTopology (CPUID_V2_EXTENDED_TOPOLOGY);\r
25705752
MK		 1711 CpuidExtendedFunction ();\r
1712 CpuidExtendedCpuSig ();\r
1713 CpuidProcessorBrandString ();\r
1714 CpuidExtendedCacheInfo ();\r
1715 CpuidExtendedTimeStampCounter ();\r
1716 CpuidVirPhyAddressSize ();\r
1717\r
1718 return EFI_SUCCESS;\r
1719}\r
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