UefiCpuPkg/Application/Cpuid: Remove unnecessary code check
[mirror_edk2.git] / UefiCpuPkg / Application / Cpuid / Cpuid.c
CommitLineData
25705752
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1/** @file\r
2 UEFI Application to display CPUID leaf information.\r
3\r
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include <Uefi.h>\r
16#include <Library/BaseLib.h>\r
17#include <Library/UefiLib.h>\r
18#include <Register/Cpuid.h>\r
19\r
20///\r
21/// Macro used to display the value of a bit field in a register returned by CPUID.\r
22///\r
23#define PRINT_BIT_FIELD(Variable, FieldName) \\r
d2ba6f41 24 Print (L"%5a%42a: %x\n", #Variable, #FieldName, Variable.Bits.FieldName);\r
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25\r
26///\r
27/// Macro used to display the value of a register returned by CPUID.\r
28///\r
29#define PRINT_VALUE(Variable, Description) \\r
30 Print (L"%5a%42a: %x\n", #Variable, #Description, Variable);\r
31\r
32///\r
33/// Structure for cache description lookup table\r
34///\r
35typedef struct {\r
36 UINT8 CacheDescriptor;\r
37 CHAR8 *Type;\r
38 CHAR8 *Description;\r
39} CPUID_CACHE_INFO_DESCRIPTION;\r
40\r
41///\r
42/// Cache description lookup table\r
43///\r
44CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {\r
45 { 0x00 , "General" , "Null descriptor, this byte contains no information" },\r
46 { 0x01 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },\r
47 { 0x02 , "TLB" , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },\r
48 { 0x03 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },\r
49 { 0x04 , "TLB" , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },\r
50 { 0x05 , "TLB" , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },\r
51 { 0x06 , "Cache" , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },\r
52 { 0x08 , "Cache" , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
53 { 0x09 , "Cache" , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },\r
54 { 0x0A , "Cache" , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },\r
55 { 0x0B , "TLB" , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },\r
56 { 0x0C , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
57 { 0x0D , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },\r
58 { 0x0E , "Cache" , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },\r
59 { 0x1D , "Cache" , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },\r
60 { 0x21 , "Cache" , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },\r
61 { 0x22 , "Cache" , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },\r
62 { 0x23 , "Cache" , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
63 { 0x24 , "Cache" , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },\r
64 { 0x25 , "Cache" , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
65 { 0x29 , "Cache" , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
66 { 0x2C , "Cache" , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
67 { 0x30 , "Cache" , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
68 { 0x40 , "Cache" , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },\r
69 { 0x41 , "Cache" , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },\r
70 { 0x42 , "Cache" , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },\r
71 { 0x43 , "Cache" , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },\r
72 { 0x44 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },\r
73 { 0x45 , "Cache" , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },\r
74 { 0x46 , "Cache" , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },\r
75 { 0x47 , "Cache" , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },\r
76 { 0x48 , "Cache" , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },\r
77 { 0x49 , "Cache" , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
78 { 0x4A , "Cache" , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },\r
79 { 0x4B , "Cache" , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },\r
80 { 0x4C , "Cache" , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },\r
81 { 0x4D , "Cache" , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },\r
82 { 0x4E , "Cache" , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },\r
83 { 0x4F , "TLB" , "Instruction TLB: 4 KByte pages, 32 entries" },\r
84 { 0x50 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },\r
85 { 0x51 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },\r
86 { 0x52 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },\r
87 { 0x55 , "TLB" , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },\r
88 { 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
89 { 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
90 { 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
91 { 0x5A , "TLB" , "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
92 { 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
93 { 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
94 { 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
95 { 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
96 { 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
97 { 0x63 , "TLB" , "Data TLB: 1 GByte pages, 4-way set associative, 4 entries" },\r
98 { 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
99 { 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
100 { 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
101 { 0x6A , "Cache" , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },\r
102 { 0x6B , "Cache" , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },\r
103 { 0x6C , "Cache" , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },\r
104 { 0x6D , "Cache" , "DTLB: 1 GByte pages, fully associative, 16 entries" },\r
105 { 0x70 , "Cache" , "Trace cache: 12 K-uop, 8-way set associative" },\r
106 { 0x71 , "Cache" , "Trace cache: 16 K-uop, 8-way set associative" },\r
107 { 0x72 , "Cache" , "Trace cache: 32 K-uop, 8-way set associative" },\r
108 { 0x76 , "TLB" , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },\r
109 { 0x78 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },\r
110 { 0x79 , "Cache" , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
111 { 0x7A , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
112 { 0x7B , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
113 { 0x7C , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
114 { 0x7D , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },\r
115 { 0x7F , "Cache" , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },\r
116 { 0x80 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },\r
117 { 0x82 , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },\r
118 { 0x83 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },\r
119 { 0x84 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },\r
120 { 0x85 , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },\r
121 { 0x86 , "Cache" , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
122 { 0x87 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
123 { 0xA0 , "DTLB" , "DTLB: 4k pages, fully associative, 32 entries" },\r
124 { 0xB0 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
125 { 0xB1 , "TLB" , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },\r
126 { 0xB2 , "TLB" , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },\r
127 { 0xB3 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
128 { 0xB4 , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },\r
129 { 0xB5 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },\r
130 { 0xB6 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },\r
131 { 0xBA , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },\r
132 { 0xC0 , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },\r
133 { 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
134 { 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
135 { 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
136 { 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
137 { 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
138 { 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
139 { 0xD2 , "Cache" , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },\r
140 { 0xD6 , "Cache" , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
141 { 0xD7 , "Cache" , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },\r
142 { 0xD8 , "Cache" , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },\r
143 { 0xDC , "Cache" , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },\r
144 { 0xDD , "Cache" , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },\r
145 { 0xDE , "Cache" , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },\r
146 { 0xE2 , "Cache" , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },\r
147 { 0xE3 , "Cache" , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
148 { 0xE4 , "Cache" , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },\r
149 { 0xEA , "Cache" , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },\r
150 { 0xEB , "Cache" , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },\r
151 { 0xEC , "Cache" , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },\r
152 { 0xF0 , "Prefetch" , "64-Byte prefetching" },\r
153 { 0xF1 , "Prefetch" , "128-Byte prefetching" },\r
154 { 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }\r
155};\r
156\r
157///\r
158/// The maximum supported CPUID leaf index starting from leaf 0x00000000.\r
159///\r
160UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;\r
161\r
162///\r
163/// The maximum supported CPUID leaf index starting from leaf 0x80000000.\r
164///\r
165UINT32 gMaximumExtendedFunction = CPUID_EXTENDED_FUNCTION;\r
166\r
167/**\r
168 Display CPUID_SIGNATURE leaf.\r
169\r
170**/\r
171VOID\r
172CpuidSignature (\r
173 VOID\r
174 )\r
175{\r
176 UINT32 Eax;\r
177 UINT32 Ebx;\r
178 UINT32 Ecx;\r
179 UINT32 Edx;\r
180 CHAR8 Signature[13];\r
181\r
182 if (CPUID_SIGNATURE > gMaximumBasicFunction) {\r
183 return;\r
184 }\r
185\r
186 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
187\r
188 Print (L"CPUID_SIGNATURE (Leaf %08x)\n", CPUID_SIGNATURE);\r
189 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
190 PRINT_VALUE (Eax, MaximumLeaf);\r
191 *(UINT32 *)(Signature + 0) = Ebx;\r
192 *(UINT32 *)(Signature + 4) = Edx;\r
193 *(UINT32 *)(Signature + 8) = Ecx;\r
194 Signature [12] = 0;\r
195 Print (L" Signature = %a\n", Signature);\r
196\r
197 gMaximumBasicFunction = Eax;\r
198}\r
199\r
200/**\r
201 Display CPUID_VERSION_INFO leaf.\r
202\r
203**/\r
204VOID\r
205CpuidVersionInfo (\r
206 VOID\r
207 )\r
208{\r
209 CPUID_VERSION_INFO_EAX Eax;\r
210 CPUID_VERSION_INFO_EBX Ebx;\r
211 CPUID_VERSION_INFO_ECX Ecx;\r
212 CPUID_VERSION_INFO_EDX Edx;\r
213 UINTN DisplayFamily;\r
214 UINTN DisplayModel;\r
215\r
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216 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
217\r
218 Print (L"CPUID_VERSION_INFO (Leaf %08x)\n", CPUID_VERSION_INFO);\r
219 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
220\r
221 DisplayFamily = Eax.Bits.FamilyId;\r
222 if (Eax.Bits.FamilyId == 0x0F) {\r
223 DisplayFamily |= (Eax.Bits.ExtendedFamilyId << 4);\r
224 }\r
225\r
226 DisplayModel = Eax.Bits.Model;\r
227 if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {\r
228 DisplayModel |= (Eax.Bits.ExtendedModelId << 4);\r
229 }\r
230\r
231 Print (L" Family = %x Model = %x Stepping = %x\n", DisplayFamily, DisplayModel, Eax.Bits.SteppingId);\r
232\r
233 PRINT_BIT_FIELD (Eax, SteppingId);\r
234 PRINT_BIT_FIELD (Eax, Model);\r
235 PRINT_BIT_FIELD (Eax, FamilyId);\r
236 PRINT_BIT_FIELD (Eax, ProcessorType);\r
237 PRINT_BIT_FIELD (Eax, ExtendedModelId);\r
238 PRINT_BIT_FIELD (Eax, ExtendedFamilyId);\r
239 PRINT_BIT_FIELD (Ebx, BrandIndex);\r
240 PRINT_BIT_FIELD (Ebx, CacheLineSize);\r
241 PRINT_BIT_FIELD (Ebx, MaximumAddressableIdsForLogicalProcessors);\r
242 PRINT_BIT_FIELD (Ebx, InitialLocalApicId);\r
243 PRINT_BIT_FIELD (Ecx, SSE3);\r
244 PRINT_BIT_FIELD (Ecx, PCLMULQDQ);\r
245 PRINT_BIT_FIELD (Ecx, DTES64);\r
246 PRINT_BIT_FIELD (Ecx, MONITOR);\r
247 PRINT_BIT_FIELD (Ecx, DS_CPL);\r
248 PRINT_BIT_FIELD (Ecx, VMX);\r
249 PRINT_BIT_FIELD (Ecx, SMX);\r
250 PRINT_BIT_FIELD (Ecx, TM2);\r
251 PRINT_BIT_FIELD (Ecx, SSSE3);\r
252 PRINT_BIT_FIELD (Ecx, CNXT_ID);\r
253 PRINT_BIT_FIELD (Ecx, SDBG);\r
254 PRINT_BIT_FIELD (Ecx, FMA);\r
255 PRINT_BIT_FIELD (Ecx, CMPXCHG16B);\r
256 PRINT_BIT_FIELD (Ecx, xTPR_Update_Control);\r
257 PRINT_BIT_FIELD (Ecx, PDCM);\r
258 PRINT_BIT_FIELD (Ecx, PCID);\r
259 PRINT_BIT_FIELD (Ecx, DCA);\r
260 PRINT_BIT_FIELD (Ecx, SSE4_1);\r
261 PRINT_BIT_FIELD (Ecx, SSE4_2);\r
262 PRINT_BIT_FIELD (Ecx, x2APIC);\r
263 PRINT_BIT_FIELD (Ecx, MOVBE);\r
264 PRINT_BIT_FIELD (Ecx, POPCNT);\r
265 PRINT_BIT_FIELD (Ecx, TSC_Deadline);\r
266 PRINT_BIT_FIELD (Ecx, AESNI);\r
267 PRINT_BIT_FIELD (Ecx, XSAVE);\r
268 PRINT_BIT_FIELD (Ecx, OSXSAVE);\r
269 PRINT_BIT_FIELD (Ecx, AVX);\r
270 PRINT_BIT_FIELD (Ecx, F16C);\r
271 PRINT_BIT_FIELD (Ecx, RDRAND);\r
272 PRINT_BIT_FIELD (Edx, FPU);\r
273 PRINT_BIT_FIELD (Edx, VME);\r
274 PRINT_BIT_FIELD (Edx, DE);\r
275 PRINT_BIT_FIELD (Edx, PSE);\r
276 PRINT_BIT_FIELD (Edx, TSC);\r
277 PRINT_BIT_FIELD (Edx, MSR);\r
278 PRINT_BIT_FIELD (Edx, PAE);\r
279 PRINT_BIT_FIELD (Edx, MCE);\r
280 PRINT_BIT_FIELD (Edx, CX8);\r
281 PRINT_BIT_FIELD (Edx, APIC);\r
282 PRINT_BIT_FIELD (Edx, SEP);\r
283 PRINT_BIT_FIELD (Edx, MTRR);\r
284 PRINT_BIT_FIELD (Edx, PGE);\r
285 PRINT_BIT_FIELD (Edx, MCA);\r
286 PRINT_BIT_FIELD (Edx, CMOV);\r
287 PRINT_BIT_FIELD (Edx, PAT);\r
288 PRINT_BIT_FIELD (Edx, PSE_36);\r
289 PRINT_BIT_FIELD (Edx, PSN);\r
290 PRINT_BIT_FIELD (Edx, CLFSH);\r
291 PRINT_BIT_FIELD (Edx, DS);\r
292 PRINT_BIT_FIELD (Edx, ACPI);\r
293 PRINT_BIT_FIELD (Edx, MMX);\r
294 PRINT_BIT_FIELD (Edx, FXSR);\r
295 PRINT_BIT_FIELD (Edx, SSE);\r
296 PRINT_BIT_FIELD (Edx, SSE2);\r
297 PRINT_BIT_FIELD (Edx, SS);\r
298 PRINT_BIT_FIELD (Edx, HTT);\r
299 PRINT_BIT_FIELD (Edx, TM);\r
300 PRINT_BIT_FIELD (Edx, PBE);\r
301}\r
302\r
303/**\r
304 Lookup a cache description string from the mCpuidCacheInfoDescription table.\r
305\r
306 @param[in] CacheDescriptor Cache descriptor value from CPUID_CACHE_INFO.\r
307\r
308**/\r
309CPUID_CACHE_INFO_DESCRIPTION *\r
310LookupCacheDescription (\r
311 UINT8 CacheDescriptor\r
312 )\r
313{\r
314 UINTN NumDescriptors;\r
315 UINTN Descriptor;\r
316\r
317 if (CacheDescriptor == 0x00) {\r
318 return NULL;\r
319 }\r
320 NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);\r
321 for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {\r
322 if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {\r
323 return &mCpuidCacheInfoDescription[Descriptor];\r
324 }\r
325 }\r
326 return NULL;\r
327}\r
328\r
329/**\r
330 Display CPUID_CACHE_INFO leaf for each supported cache descriptor.\r
331\r
332**/\r
333VOID\r
334CpuidCacheInfo (\r
335 VOID\r
336 )\r
337{\r
338 CPUID_CACHE_INFO_CACHE_TLB Eax;\r
339 CPUID_CACHE_INFO_CACHE_TLB Ebx;\r
340 CPUID_CACHE_INFO_CACHE_TLB Ecx;\r
341 CPUID_CACHE_INFO_CACHE_TLB Edx;\r
342 UINTN Index;\r
343 CPUID_CACHE_INFO_DESCRIPTION *CacheDescription;\r
344\r
345 if (CPUID_CACHE_INFO > gMaximumBasicFunction) {\r
346 return;\r
347 }\r
348\r
349 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
350\r
351 Print (L"CPUID_CACHE_INFO (Leaf %08x)\n", CPUID_CACHE_INFO);\r
352 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
353 if (Eax.Bits.NotValid == 0) {\r
354 //\r
355 // Process Eax.CacheDescriptor[1..3]. Ignore Eax.CacheDescriptor[0]\r
356 //\r
357 for (Index = 1; Index < 4; Index++) {\r
358 CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);\r
359 if (CacheDescription != NULL) {\r
360 Print (L" %-8a %a\n",\r
361 CacheDescription->Type,\r
362 CacheDescription->Description\r
363 );\r
364 }\r
365 }\r
366 }\r
367 if (Ebx.Bits.NotValid == 0) {\r
368 //\r
369 // Process Ebx.CacheDescriptor[0..3]\r
370 //\r
371 for (Index = 0; Index < 4; Index++) {\r
372 CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);\r
373 if (CacheDescription != NULL) {\r
374 Print (L" %-8a %a\n",\r
375 CacheDescription->Type,\r
376 CacheDescription->Description\r
377 );\r
378 }\r
379 }\r
380 }\r
381 if (Ecx.Bits.NotValid == 0) {\r
382 //\r
383 // Process Ecx.CacheDescriptor[0..3]\r
384 //\r
385 for (Index = 0; Index < 4; Index++) {\r
386 CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);\r
387 if (CacheDescription != NULL) {\r
388 Print (L" %-8a %a\n",\r
389 CacheDescription->Type,\r
390 CacheDescription->Description\r
391 );\r
392 }\r
393 }\r
394 }\r
395 if (Edx.Bits.NotValid == 0) {\r
396 //\r
397 // Process Edx.CacheDescriptor[0..3]\r
398 //\r
399 for (Index = 0; Index < 4; Index++) {\r
400 CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);\r
401 if (CacheDescription != NULL) {\r
402 Print (L" %-8a %a\n",\r
403 CacheDescription->Type,\r
404 CacheDescription->Description\r
405 );\r
406 }\r
407 }\r
408 }\r
409}\r
410\r
411/**\r
412 Display CPUID_SERIAL_NUMBER leaf if it is supported.\r
413\r
414**/\r
415VOID\r
416CpuidSerialNumber (\r
417 VOID\r
418 )\r
419{\r
420 CPUID_VERSION_INFO_EDX VersionInfoEdx;\r
421 UINT32 Ecx;\r
422 UINT32 Edx;\r
423\r
424 Print (L"CPUID_SERIAL_NUMBER (Leaf %08x)\n", CPUID_SERIAL_NUMBER);\r
425\r
426 if (CPUID_SERIAL_NUMBER > gMaximumBasicFunction) {\r
427 return;\r
428 }\r
429\r
430 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);\r
431 if (VersionInfoEdx.Bits.PSN == 0) {\r
432 Print (L" Not Supported\n");\r
433 return;\r
434 }\r
435\r
436 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
437 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx, Edx);\r
438 Print (L" Processor Serial Number = %08x%08x%08x\n", 0, Edx, Ecx);\r
439}\r
440\r
441/**\r
442 Display CPUID_CACHE_PARAMS for all supported sub-leafs.\r
443\r
444**/\r
445VOID\r
446CpuidCacheParams (\r
447 VOID\r
448 )\r
449{\r
450 UINT32 CacheLevel;\r
451 CPUID_CACHE_PARAMS_EAX Eax;\r
452 CPUID_CACHE_PARAMS_EBX Ebx;\r
453 UINT32 Ecx;\r
454 CPUID_CACHE_PARAMS_EDX Edx;\r
455\r
456 if (CPUID_CACHE_PARAMS > gMaximumBasicFunction) {\r
457 return;\r
458 }\r
459\r
460 CacheLevel = 0;\r
461 do {\r
462 AsmCpuidEx (\r
463 CPUID_CACHE_PARAMS, CacheLevel,\r
464 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
465 );\r
466 if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {\r
467 Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);\r
468 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx, Edx.Uint32);\r
469 PRINT_BIT_FIELD (Eax, CacheType);\r
470 PRINT_BIT_FIELD (Eax, CacheLevel);\r
471 PRINT_BIT_FIELD (Eax, SelfInitializingCache);\r
472 PRINT_BIT_FIELD (Eax, FullyAssociativeCache);\r
473 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForLogicalProcessors);\r
474 PRINT_BIT_FIELD (Eax, MaximumAddressableIdsForProcessorCores);\r
475 PRINT_BIT_FIELD (Ebx, LineSize);\r
476 PRINT_BIT_FIELD (Ebx, LinePartitions);\r
477 PRINT_BIT_FIELD (Ebx, Ways);\r
478 PRINT_VALUE (Ecx, NumberOfSets);\r
479 PRINT_BIT_FIELD (Edx, Invalidate);\r
480 PRINT_BIT_FIELD (Edx, CacheInclusiveness);\r
481 PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);\r
482 }\r
483 CacheLevel++;\r
484 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
485}\r
486\r
487/**\r
488 Display CPUID_MONITOR_MWAIT leaf.\r
489\r
490**/\r
491VOID\r
492CpuidMonitorMwait (\r
493 VOID\r
494 )\r
495{\r
496 CPUID_MONITOR_MWAIT_EAX Eax;\r
497 CPUID_MONITOR_MWAIT_EBX Ebx;\r
498 CPUID_MONITOR_MWAIT_ECX Ecx;\r
499 CPUID_MONITOR_MWAIT_EDX Edx;\r
500\r
501 if (CPUID_MONITOR_MWAIT > gMaximumBasicFunction) {\r
502 return;\r
503 }\r
504\r
505 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
506\r
507 Print (L"CPUID_MONITOR_MWAIT (Leaf %08x)\n", CPUID_MONITOR_MWAIT);\r
508 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
509\r
510 PRINT_BIT_FIELD (Eax, SmallestMonitorLineSize);\r
511 PRINT_BIT_FIELD (Ebx, LargestMonitorLineSize);\r
512 PRINT_BIT_FIELD (Ecx, ExtensionsSupported);\r
513 PRINT_BIT_FIELD (Ecx, InterruptAsBreak);\r
514 PRINT_BIT_FIELD (Edx, C0States);\r
515 PRINT_BIT_FIELD (Edx, C1States);\r
516 PRINT_BIT_FIELD (Edx, C2States);\r
517 PRINT_BIT_FIELD (Edx, C3States);\r
518 PRINT_BIT_FIELD (Edx, C4States);\r
519 PRINT_BIT_FIELD (Edx, C5States);\r
520 PRINT_BIT_FIELD (Edx, C6States);\r
521 PRINT_BIT_FIELD (Edx, C7States);\r
522}\r
523\r
524/**\r
525 Display CPUID_THERMAL_POWER_MANAGEMENT leaf.\r
526\r
527**/\r
528VOID\r
529CpuidThermalPowerManagement (\r
530 VOID\r
531 )\r
532{\r
533 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r
534 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r
535 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r
536\r
537 if (CPUID_THERMAL_POWER_MANAGEMENT > gMaximumBasicFunction) {\r
538 return;\r
539 }\r
540\r
541 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
542\r
543 Print (L"CPUID_THERMAL_POWER_MANAGEMENT (Leaf %08x)\n", CPUID_THERMAL_POWER_MANAGEMENT);\r
544 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r
545\r
546 PRINT_BIT_FIELD (Eax, DigitalTemperatureSensor);\r
547 PRINT_BIT_FIELD (Eax, TurboBoostTechnology);\r
548 PRINT_BIT_FIELD (Eax, ARAT);\r
549 PRINT_BIT_FIELD (Eax, PLN);\r
550 PRINT_BIT_FIELD (Eax, ECMD);\r
551 PRINT_BIT_FIELD (Eax, PTM);\r
552 PRINT_BIT_FIELD (Eax, HWP);\r
553 PRINT_BIT_FIELD (Eax, HWP_Notification);\r
554 PRINT_BIT_FIELD (Eax, HWP_Activity_Window);\r
555 PRINT_BIT_FIELD (Eax, HWP_Energy_Performance_Preference);\r
556 PRINT_BIT_FIELD (Eax, HWP_Package_Level_Request);\r
557 PRINT_BIT_FIELD (Eax, HDC);\r
558 PRINT_BIT_FIELD (Ebx, InterruptThresholds);\r
559 PRINT_BIT_FIELD (Ecx, HardwareCoordinationFeedback);\r
560 PRINT_BIT_FIELD (Ecx, PerformanceEnergyBias);\r
561}\r
562\r
563/**\r
564 Display CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS for all supported sub-leafs.\r
565\r
566**/\r
567VOID\r
568CpuidStructuredExtendedFeatureFlags (\r
569 VOID\r
570 )\r
571{\r
572 UINT32 Eax;\r
573 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
574 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r
575 UINT32 SubLeaf;\r
576\r
577 if (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS > gMaximumBasicFunction) {\r
578 return;\r
579 }\r
580\r
581 AsmCpuidEx (\r
582 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
583 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
584 &Eax, NULL, NULL, NULL\r
585 );\r
586 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
587 AsmCpuidEx (\r
588 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
589 SubLeaf,\r
590 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r
591 );\r
592 if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0) {\r
593 Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);\r
594 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
595 PRINT_BIT_FIELD (Ebx, FSGSBASE);\r
596 PRINT_BIT_FIELD (Ebx, IA32_TSC_ADJUST);\r
597 PRINT_BIT_FIELD (Ebx, BMI1);\r
598 PRINT_BIT_FIELD (Ebx, HLE);\r
599 PRINT_BIT_FIELD (Ebx, AVX2);\r
600 PRINT_BIT_FIELD (Ebx, FDP_EXCPTN_ONLY);\r
601 PRINT_BIT_FIELD (Ebx, SMEP);\r
602 PRINT_BIT_FIELD (Ebx, BMI2);\r
603 PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);\r
604 PRINT_BIT_FIELD (Ebx, INVPCID);\r
605 PRINT_BIT_FIELD (Ebx, RTM);\r
606 PRINT_BIT_FIELD (Ebx, PQM);\r
607 PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);\r
608 PRINT_BIT_FIELD (Ebx, MPX);\r
609 PRINT_BIT_FIELD (Ebx, PQE);\r
610 PRINT_BIT_FIELD (Ebx, RDSEED);\r
611 PRINT_BIT_FIELD (Ebx, ADX);\r
612 PRINT_BIT_FIELD (Ebx, SMAP);\r
613 PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);\r
614 PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);\r
615 PRINT_BIT_FIELD (Ecx, PREFETCHWT1);\r
616 PRINT_BIT_FIELD (Ecx, PKU);\r
617 PRINT_BIT_FIELD (Ecx, OSPKE);\r
618 }\r
619 SubLeaf++;\r
620 } while (SubLeaf <= Eax);\r
621}\r
622\r
623/**\r
624 Display CPUID_DIRECT_CACHE_ACCESS_INFO leaf.\r
625\r
626**/\r
627VOID\r
628CpuidDirectCacheAccessInfo (\r
629 VOID\r
630 )\r
631{\r
632 UINT32 Eax;\r
633\r
634 if (CPUID_DIRECT_CACHE_ACCESS_INFO > gMaximumBasicFunction) {\r
635 return;\r
636 }\r
637\r
638 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
639 Print (L"CPUID_DIRECT_CACHE_ACCESS_INFO (Leaf %08x)\n", CPUID_DIRECT_CACHE_ACCESS_INFO);\r
640 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r
641}\r
642\r
643/**\r
644 Display CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING leaf.\r
645\r
646**/\r
647VOID\r
648CpuidArchitecturalPerformanceMonitoring (\r
649 VOID\r
650 )\r
651{\r
652 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r
653 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r
654 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r
655\r
656 if (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING > gMaximumBasicFunction) {\r
657 return;\r
658 }\r
659\r
660 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r
661 Print (L"CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (Leaf %08x)\n", CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING);\r
662 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, Edx.Uint32);\r
663 PRINT_BIT_FIELD (Eax, ArchPerfMonVerID);\r
664 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounters);\r
665 PRINT_BIT_FIELD (Eax, PerformanceMonitorCounterWidth);\r
666 PRINT_BIT_FIELD (Eax, EbxBitVectorLength);\r
667 PRINT_BIT_FIELD (Ebx, UnhaltedCoreCycles);\r
668 PRINT_BIT_FIELD (Ebx, InstructionsRetired);\r
669 PRINT_BIT_FIELD (Ebx, UnhaltedReferenceCycles);\r
670 PRINT_BIT_FIELD (Ebx, LastLevelCacheReferences);\r
671 PRINT_BIT_FIELD (Ebx, LastLevelCacheMisses);\r
672 PRINT_BIT_FIELD (Ebx, BranchInstructionsRetired);\r
673 PRINT_BIT_FIELD (Ebx, AllBranchMispredictRetired);\r
674 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounters);\r
675 PRINT_BIT_FIELD (Edx, FixedFunctionPerformanceCounterWidth);\r
676}\r
677\r
678/**\r
679 Display CPUID_EXTENDED_TOPOLOGY leafs for all supported levels.\r
680\r
681**/\r
682VOID\r
683CpuidExtendedTopology (\r
684 VOID\r
685 )\r
686{\r
687 CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
688 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r
689 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r
690 UINT32 Edx;\r
691 UINT32 LevelNumber;\r
692\r
693 if (CPUID_EXTENDED_TOPOLOGY > gMaximumBasicFunction) {\r
694 return;\r
695 }\r
696\r
697 LevelNumber = 0;\r
698 do {\r
699 AsmCpuidEx (\r
700 CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r
701 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
702 );\r
703 if (Eax.Bits.ApicIdShift != 0) {\r
704 Print (L"CPUID_EXTENDED_TOPOLOGY (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_TOPOLOGY, LevelNumber);\r
705 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);\r
706 PRINT_BIT_FIELD (Eax, ApicIdShift);\r
707 PRINT_BIT_FIELD (Ebx, LogicalProcessors);\r
708 PRINT_BIT_FIELD (Ecx, LevelNumber);\r
709 PRINT_BIT_FIELD (Ecx, LevelType);\r
710 PRINT_VALUE (Edx, x2APIC_ID);\r
711 }\r
712 LevelNumber++;\r
713 } while (Eax.Bits.ApicIdShift != 0);\r
714}\r
715\r
716/**\r
717 Display CPUID_EXTENDED_STATE sub-leaf.\r
718\r
719**/\r
720VOID\r
721CpuidExtendedStateSubLeaf (\r
722 VOID\r
723 )\r
724{\r
725 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r
726 UINT32 Ebx;\r
727 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r
728 UINT32 Edx;\r
729\r
730 AsmCpuidEx (\r
731 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
732 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
733 );\r
734 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);\r
735 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);\r
736 PRINT_BIT_FIELD (Eax, XSAVEOPT);\r
737 PRINT_BIT_FIELD (Eax, XSAVEC);\r
738 PRINT_BIT_FIELD (Eax, XGETBV);\r
739 PRINT_BIT_FIELD (Eax, XSAVES);\r
740 PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r
741 PRINT_BIT_FIELD (Ecx, XCR0);\r
742 PRINT_BIT_FIELD (Ecx, PT);\r
743 PRINT_BIT_FIELD (Ecx, XCR0_1);\r
744 PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);\r
745}\r
746\r
747/**\r
748 Display CPUID_EXTENDED_STATE size and offset information sub-leaf.\r
749\r
750**/\r
751VOID\r
752CpuidExtendedStateSizeOffset (\r
753 VOID\r
754 )\r
755{\r
756 UINT32 Eax;\r
757 UINT32 Ebx;\r
758 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r
759 UINT32 Edx;\r
760 UINT32 SubLeaf;\r
761\r
762 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
763 AsmCpuidEx (\r
764 CPUID_EXTENDED_STATE, SubLeaf,\r
765 &Eax, &Ebx, &Ecx.Uint32, &Edx\r
766 );\r
767 if (Edx != 0) {\r
768 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);\r
769 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);\r
770 PRINT_VALUE (Eax, FeatureSaveStateSize);\r
771 PRINT_VALUE (Ebx, FeatureSaveStateOffset);\r
772 PRINT_BIT_FIELD (Ecx, XSS);\r
773 PRINT_BIT_FIELD (Ecx, Compacted);\r
774 }\r
775 }\r
776}\r
777\r
778/**\r
779 Display CPUID_EXTENDED_STATE main leaf and sub-leafs.\r
780\r
781**/\r
782VOID\r
783CpuidExtendedStateMainLeaf (\r
784 VOID\r
785 )\r
786{\r
787 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r
788 UINT32 Ebx;\r
789 UINT32 Ecx;\r
790 UINT32 Edx;\r
791\r
792 if (CPUID_EXTENDED_STATE > gMaximumBasicFunction) {\r
793 return;\r
794 }\r
795\r
796 AsmCpuidEx (\r
797 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
798 &Eax.Uint32, &Ebx, &Ecx, &Edx\r
799 );\r
800 Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);\r
801 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);\r
802 PRINT_BIT_FIELD (Eax, x87);\r
803 PRINT_BIT_FIELD (Eax, SSE);\r
804 PRINT_BIT_FIELD (Eax, AVX);\r
805 PRINT_BIT_FIELD (Eax, MPX);\r
806 PRINT_BIT_FIELD (Eax, AVX_512);\r
807 PRINT_BIT_FIELD (Eax, IA32_XSS);\r
808 PRINT_BIT_FIELD (Eax, PKRU);\r
809 PRINT_VALUE (Ebx, EnabledSaveStateSize);\r
810 PRINT_VALUE (Ecx, SupportedSaveStateSize);\r
811 PRINT_VALUE (Edx, XCR0_Supported_32_63);\r
812\r
813 CpuidExtendedStateSubLeaf ();\r
814 CpuidExtendedStateSizeOffset ();\r
815}\r
816\r
817/**\r
818 Display CPUID_PLATFORM_QOS_MONITORING enumeration sub-leaf.\r
819\r
820**/\r
821VOID\r
822CpuidPlatformQosMonitoringEnumerationSubLeaf (\r
823 VOID\r
824 )\r
825{\r
826 UINT32 Ebx;\r
827 CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
828\r
829 if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {\r
830 return;\r
831 }\r
832\r
833 AsmCpuidEx (\r
834 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
835 NULL, &Ebx, NULL, &Edx.Uint32\r
836 );\r
837 Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF);\r
838 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
839 PRINT_VALUE (Ebx, Maximum_RMID_Range);\r
840 PRINT_BIT_FIELD (Edx, L3CacheQosEnforcement);\r
841}\r
842\r
843/**\r
844 Display CPUID_PLATFORM_QOS_MONITORING capability sub-leaf.\r
845\r
846**/\r
847VOID\r
848CpuidPlatformQosMonitoringCapabilitySubLeaf (\r
849 VOID\r
850 )\r
851{\r
852 UINT32 Ebx;\r
853 UINT32 Ecx;\r
854 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;\r
855\r
856 if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {\r
857 return;\r
858 }\r
859\r
860 AsmCpuidEx (\r
861 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
862 NULL, &Ebx, &Ecx, &Edx.Uint32\r
863 );\r
864 Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF);\r
865 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
866 PRINT_VALUE (Ebx, OccupancyConversionFactor);\r
867 PRINT_VALUE (Ecx, Maximum_RMID_Range);\r
868 PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r
869}\r
870\r
871/**\r
872 Display CPUID_PLATFORM_QOS_ENFORCEMENT sub-leaf.\r
873\r
874**/\r
875VOID\r
876CpuidPlatformQosEnforcementResidSubLeaf (\r
877 VOID\r
878 )\r
879{\r
880 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
881 UINT32 Ebx;\r
882 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
883 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
884\r
885 AsmCpuidEx (\r
886 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
887 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
888 );\r
889 Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF);\r
890 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
891 PRINT_BIT_FIELD (Eax, CapacityLength);\r
892 PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
893 PRINT_BIT_FIELD (Ecx, CosUpdatesInfrequent);\r
894 PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);\r
895 PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
896}\r
897\r
898/**\r
899 Display CPUID_PLATFORM_QOS_ENFORCEMENT main leaf and sub-leaf.\r
900\r
901**/\r
902VOID\r
903CpuidPlatformQosEnforcementMainLeaf (\r
904 VOID\r
905 )\r
906{\r
907 CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;\r
908\r
909 if (CPUID_PLATFORM_QOS_ENFORCEMENT > gMaximumBasicFunction) {\r
910 return;\r
911 }\r
912\r
913 AsmCpuidEx (\r
914 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
915 NULL, &Ebx.Uint32, NULL, NULL\r
916 );\r
917 Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF);\r
918 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r
919 PRINT_BIT_FIELD (Ebx, L3CacheQosEnforcement);\r
920\r
921 CpuidPlatformQosEnforcementResidSubLeaf ();\r
922}\r
923\r
924/**\r
925 Display CPUID_INTEL_PROCESSOR_TRACE sub-leafs.\r
926\r
927 @param[in] MaximumSubLeaf Maximum sub-leaf index for CPUID_INTEL_PROCESSOR_TRACE.\r
928\r
929**/\r
930VOID\r
931CpuidIntelProcessorTraceSubLeaf (\r
932 UINT32 MaximumSubLeaf\r
933 )\r
934{\r
935 UINT32 SubLeaf;\r
936 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r
937 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r
938\r
939 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
940 AsmCpuidEx (\r
941 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
942 &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
943 );\r
944 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);\r
945 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);\r
946 PRINT_BIT_FIELD (Eax, ConfigurableAddressRanges);\r
947 PRINT_BIT_FIELD (Eax, MtcPeriodEncodings);\r
948 PRINT_BIT_FIELD (Ebx, CycleThresholdEncodings);\r
949 PRINT_BIT_FIELD (Ebx, PsbFrequencyEncodings);\r
950 }\r
951}\r
952\r
953/**\r
954 Display CPUID_INTEL_PROCESSOR_TRACE main leaf and sub-leafs.\r
955\r
956**/\r
957VOID\r
958CpuidIntelProcessorTraceMainLeaf (\r
959 VOID\r
960 )\r
961{\r
962 UINT32 Eax;\r
963 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r
964 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r
965\r
966 if (CPUID_INTEL_PROCESSOR_TRACE > gMaximumBasicFunction) {\r
967 return;\r
968 }\r
969\r
970 AsmCpuidEx (\r
971 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
972 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
973 );\r
974 Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);\r
975 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
976 PRINT_VALUE (Eax, MaximumSubLeaf);\r
977 PRINT_BIT_FIELD (Ebx, Cr3Filter);\r
978 PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
979 PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
980 PRINT_BIT_FIELD (Ebx, Mtc);\r
981 PRINT_BIT_FIELD (Ecx, RTIT);\r
982 PRINT_BIT_FIELD (Ecx, ToPA);\r
983 PRINT_BIT_FIELD (Ecx, SingleRangeOutput);\r
984 PRINT_BIT_FIELD (Ecx, TraceTransportSubsystem);\r
985 PRINT_BIT_FIELD (Ecx, LIP);\r
986\r
987 CpuidIntelProcessorTraceSubLeaf (Eax);\r
988}\r
989\r
990/**\r
991 Display CPUID_TIME_STAMP_COUNTER leaf.\r
992\r
993**/\r
994VOID\r
995CpuidTimeStampCounter (\r
996 VOID\r
997 )\r
998{\r
999 UINT32 Eax;\r
1000 UINT32 Ebx;\r
1001\r
1002 if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {\r
1003 return;\r
1004 }\r
1005\r
1006 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
1007 Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);\r
1008 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, 0, 0);\r
1009}\r
1010\r
1011/**\r
1012 Display CPUID_PROCESSOR_FREQUENCY leaf.\r
1013\r
1014**/\r
1015VOID\r
1016CpuidProcessorFrequency (\r
1017 VOID\r
1018 )\r
1019{\r
1020 CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r
1021 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r
1022 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r
1023\r
1024 if (CPUID_PROCESSOR_FREQUENCY > gMaximumBasicFunction) {\r
1025 return;\r
1026 }\r
1027\r
1028 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
1029 Print (L"CPUID_PROCESSOR_FREQUENCY (Leaf %08x)\n", CPUID_PROCESSOR_FREQUENCY);\r
1030 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, 0);\r
1031 PRINT_BIT_FIELD (Eax, ProcessorBaseFrequency);\r
1032 PRINT_BIT_FIELD (Ebx, MaximumFrequency);\r
1033 PRINT_BIT_FIELD (Ecx, BusFrequency);\r
1034}\r
1035\r
1036/**\r
1037 Display CPUID_SOC_VENDOR sub-leafs that contain the SoC Vendor Brand String.\r
1038 Also display these sub-leafs as a single SoC Vendor Brand String.\r
1039\r
1040**/\r
1041VOID\r
1042CpuidSocVendorBrandString (\r
1043 VOID\r
1044 )\r
1045{\r
1046 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
1047 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
1048 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
1049 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
1050 //\r
1051 // Array to store brand string from 3 brand string leafs with\r
1052 // 4 32-bit brand string values per leaf and an extra value to\r
1053 // null terminate the string.\r
1054 //\r
1055 UINT32 BrandString[3 * 4 + 1];\r
1056\r
1057 AsmCpuidEx (\r
1058 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
1059 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
1060 );\r
1061 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);\r
1062 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1063 BrandString[0] = Eax.Uint32;\r
1064 BrandString[1] = Ebx.Uint32;\r
1065 BrandString[2] = Ecx.Uint32;\r
1066 BrandString[3] = Edx.Uint32;\r
1067\r
1068 AsmCpuidEx (\r
1069 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
1070 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
1071 );\r
1072 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);\r
1073 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1074 BrandString[4] = Eax.Uint32;\r
1075 BrandString[5] = Ebx.Uint32;\r
1076 BrandString[6] = Ecx.Uint32;\r
1077 BrandString[7] = Edx.Uint32;\r
1078\r
1079 AsmCpuidEx (\r
1080 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
1081 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
1082 );\r
1083 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);\r
1084 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1085 BrandString[8] = Eax.Uint32;\r
1086 BrandString[9] = Ebx.Uint32;\r
1087 BrandString[10] = Ecx.Uint32;\r
1088 BrandString[11] = Edx.Uint32;\r
1089\r
1090 BrandString[12] = 0;\r
1091\r
1092 Print (L"Vendor Brand String = %a\n", (CHAR8 *)BrandString);\r
1093}\r
1094\r
1095/**\r
1096 Display CPUID_SOC_VENDOR main leaf and sub-leafs.\r
1097\r
1098**/\r
1099VOID\r
1100CpuidSocVendor (\r
1101 VOID\r
1102 )\r
1103{\r
1104 UINT32 Eax;\r
1105 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r
1106 UINT32 Ecx;\r
1107 UINT32 Edx;\r
1108\r
1109 if (CPUID_SOC_VENDOR > gMaximumBasicFunction) {\r
1110 return;\r
1111 }\r
1112\r
1113 AsmCpuidEx (\r
1114 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
1115 &Eax, &Ebx.Uint32, &Ecx, &Edx\r
1116 );\r
1117 Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);\r
1118 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);\r
1119 if (Eax < 3) {\r
1120 Print (L" Not Supported\n");\r
1121 return;\r
1122 }\r
1123 PRINT_VALUE (Eax, MaxSOCID_Index);\r
1124 PRINT_BIT_FIELD (Ebx, SocVendorId);\r
1125 PRINT_BIT_FIELD (Ebx, IsVendorScheme);\r
1126 PRINT_VALUE (Ecx, ProjectID);\r
1127 PRINT_VALUE (Edx, SteppingID);\r
1128 CpuidSocVendorBrandString ();\r
1129}\r
1130\r
1131/**\r
1132 Display CPUID_EXTENDED_FUNCTION leaf.\r
1133\r
1134**/\r
1135VOID\r
1136CpuidExtendedFunction (\r
1137 VOID\r
1138 )\r
1139{\r
1140 UINT32 Eax;\r
1141\r
1142 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
1143 Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);\r
1144 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);\r
1145 PRINT_VALUE (Eax, MaximumExtendedFunction);\r
1146\r
1147 gMaximumExtendedFunction = Eax;\r
1148}\r
1149\r
1150/**\r
1151 Display CPUID_EXTENDED_CPU_SIG leaf.\r
1152\r
1153**/\r
1154VOID\r
1155CpuidExtendedCpuSig (\r
1156 VOID\r
1157 )\r
1158{\r
1159 UINT32 Eax;\r
1160 CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r
1161 CPUID_EXTENDED_CPU_SIG_EDX Edx;\r
1162\r
1163 if (CPUID_EXTENDED_CPU_SIG > gMaximumExtendedFunction) {\r
1164 return;\r
1165 }\r
1166\r
1167 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
1168 Print (L"CPUID_EXTENDED_CPU_SIG (Leaf %08x)\n", CPUID_EXTENDED_CPU_SIG);\r
1169 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, Ecx.Uint32, Edx.Uint32);\r
1170 PRINT_BIT_FIELD (Ecx, LAHF_SAHF);\r
1171 PRINT_BIT_FIELD (Ecx, LZCNT);\r
1172 PRINT_BIT_FIELD (Ecx, PREFETCHW);\r
1173 PRINT_BIT_FIELD (Edx, SYSCALL_SYSRET);\r
1174 PRINT_BIT_FIELD (Edx, NX);\r
1175 PRINT_BIT_FIELD (Edx, Page1GB);\r
1176 PRINT_BIT_FIELD (Edx, RDTSCP);\r
1177 PRINT_BIT_FIELD (Edx, LM);\r
1178}\r
1179\r
1180/**\r
1181 Display CPUID_BRAND_STRING1, CPUID_BRAND_STRING2 and CPUID_BRAND_STRING3\r
1182 leafs. Also display these three leafs as a single brand string.\r
1183\r
1184**/\r
1185VOID\r
1186CpuidProcessorBrandString (\r
1187 VOID\r
1188 )\r
1189{\r
1190 CPUID_BRAND_STRING_DATA Eax;\r
1191 CPUID_BRAND_STRING_DATA Ebx;\r
1192 CPUID_BRAND_STRING_DATA Ecx;\r
1193 CPUID_BRAND_STRING_DATA Edx;\r
1194 //\r
1195 // Array to store brand string from 3 brand string leafs with\r
1196 // 4 32-bit brand string values per leaf and an extra value to\r
1197 // null terminate the string.\r
1198 //\r
1199 UINT32 BrandString[3 * 4 + 1];\r
1200\r
1201 if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {\r
1202 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1203 Print (L"CPUID_BRAND_STRING1 (Leaf %08x)\n", CPUID_BRAND_STRING1);\r
1204 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1205 BrandString[0] = Eax.Uint32;\r
1206 BrandString[1] = Ebx.Uint32;\r
1207 BrandString[2] = Ecx.Uint32;\r
1208 BrandString[3] = Edx.Uint32;\r
1209 }\r
1210\r
1211 if (CPUID_BRAND_STRING2 <= gMaximumExtendedFunction) {\r
1212 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1213 Print (L"CPUID_BRAND_STRING2 (Leaf %08x)\n", CPUID_BRAND_STRING2);\r
1214 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1215 BrandString[4] = Eax.Uint32;\r
1216 BrandString[5] = Ebx.Uint32;\r
1217 BrandString[6] = Ecx.Uint32;\r
1218 BrandString[7] = Edx.Uint32;\r
1219 }\r
1220\r
1221 if (CPUID_BRAND_STRING3 <= gMaximumExtendedFunction) {\r
1222 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
1223 Print (L"CPUID_BRAND_STRING3 (Leaf %08x)\n", CPUID_BRAND_STRING3);\r
1224 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
1225 BrandString[8] = Eax.Uint32;\r
1226 BrandString[9] = Ebx.Uint32;\r
1227 BrandString[10] = Ecx.Uint32;\r
1228 BrandString[11] = Edx.Uint32;\r
1229 }\r
1230\r
1231 BrandString[12] = 0;\r
1232\r
1233 Print (L"Brand String = %a\n", (CHAR8 *)BrandString);\r
1234}\r
1235\r
1236/**\r
1237 Display CPUID_EXTENDED_CACHE_INFO leaf.\r
1238\r
1239**/\r
1240VOID\r
1241CpuidExtendedCacheInfo (\r
1242 VOID\r
1243 )\r
1244{\r
1245 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r
1246\r
1247 if (CPUID_EXTENDED_CACHE_INFO > gMaximumExtendedFunction) {\r
1248 return;\r
1249 }\r
1250\r
1251 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
1252 Print (L"CPUID_EXTENDED_CACHE_INFO (Leaf %08x)\n", CPUID_EXTENDED_CACHE_INFO);\r
1253 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, Ecx.Uint32, 0);\r
1254 PRINT_BIT_FIELD (Ecx, CacheLineSize);\r
1255 PRINT_BIT_FIELD (Ecx, L2Associativity);\r
1256 PRINT_BIT_FIELD (Ecx, CacheSize);\r
1257}\r
1258\r
1259/**\r
1260 Display CPUID_EXTENDED_TIME_STAMP_COUNTER leaf.\r
1261\r
1262**/\r
1263VOID\r
1264CpuidExtendedTimeStampCounter (\r
1265 VOID\r
1266 )\r
1267{\r
1268 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r
1269\r
1270 if (CPUID_EXTENDED_TIME_STAMP_COUNTER > gMaximumExtendedFunction) {\r
1271 return;\r
1272 }\r
1273\r
1274 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r
1275 Print (L"CPUID_EXTENDED_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_EXTENDED_TIME_STAMP_COUNTER);\r
1276 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, 0, 0, Edx.Uint32);\r
1277 PRINT_BIT_FIELD (Edx, InvariantTsc);\r
1278}\r
1279\r
1280/**\r
1281 Display CPUID_VIR_PHY_ADDRESS_SIZE leaf.\r
1282\r
1283**/\r
1284VOID\r
1285CpuidVirPhyAddressSize (\r
1286 VOID\r
1287 )\r
1288{\r
1289 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r
1290\r
1291 if (CPUID_VIR_PHY_ADDRESS_SIZE > gMaximumExtendedFunction) {\r
1292 return;\r
1293 }\r
1294\r
1295 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r
1296 Print (L"CPUID_VIR_PHY_ADDRESS_SIZE (Leaf %08x)\n", CPUID_VIR_PHY_ADDRESS_SIZE);\r
1297 Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, 0, 0, 0);\r
1298 PRINT_BIT_FIELD (Eax, PhysicalAddressBits);\r
1299 PRINT_BIT_FIELD (Eax, LinearAddressBits);\r
1300}\r
1301\r
1302/**\r
1303 The user Entry Point for Application. The user code starts with this function\r
1304 as the real entry point for the application.\r
1305\r
1306 @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
1307 @param[in] SystemTable A pointer to the EFI System Table.\r
1308\r
1309 @retval EFI_SUCCESS The entry point is executed successfully.\r
1310 @retval other Some error occurs when executing this entry point.\r
1311\r
1312**/\r
1313EFI_STATUS\r
1314EFIAPI\r
1315UefiMain (\r
1316 IN EFI_HANDLE ImageHandle,\r
1317 IN EFI_SYSTEM_TABLE *SystemTable\r
1318 )\r
1319{\r
1320 Print (L"UEFI CPUID Version 0.5\n");\r
1321\r
1322 CpuidSignature ();\r
1323 CpuidVersionInfo ();\r
1324 CpuidCacheInfo ();\r
1325 CpuidSerialNumber ();\r
1326 CpuidCacheParams();\r
1327 CpuidMonitorMwait ();\r
1328 CpuidThermalPowerManagement ();\r
1329 CpuidStructuredExtendedFeatureFlags ();\r
1330 CpuidDirectCacheAccessInfo();\r
1331 CpuidArchitecturalPerformanceMonitoring ();\r
1332 CpuidExtendedTopology ();\r
1333 CpuidExtendedStateMainLeaf ();\r
1334 CpuidPlatformQosMonitoringEnumerationSubLeaf ();\r
1335 CpuidPlatformQosMonitoringCapabilitySubLeaf ();\r
1336 CpuidPlatformQosEnforcementMainLeaf ();\r
1337 CpuidIntelProcessorTraceMainLeaf ();\r
1338 CpuidTimeStampCounter ();\r
1339 CpuidProcessorFrequency ();\r
1340 CpuidSocVendor ();\r
1341 CpuidExtendedFunction ();\r
1342 CpuidExtendedCpuSig ();\r
1343 CpuidProcessorBrandString ();\r
1344 CpuidExtendedCacheInfo ();\r
1345 CpuidExtendedTimeStampCounter ();\r
1346 CpuidVirPhyAddressSize ();\r
1347\r
1348 return EFI_SUCCESS;\r
1349}\r