UefiCpuPkg/CpuDxe: Enable protection for newly added page table
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.c
CommitLineData
a47463f2 1/** @file\r
7fadaacd 2 CPU DXE Module to produce CPU ARCH Protocol.\r
a47463f2 3\r
22292ed3 4 Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc 5 This program and the accompanying materials\r
a47463f2 6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "CpuDxe.h"\r
6022e28c 16#include "CpuMp.h"\r
22292ed3
JY
17#include "CpuPageTable.h"\r
18\r
19#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)\r
20#define MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)\r
a47463f2 21\r
22//\r
23// Global Variables\r
24//\r
a47463f2 25BOOLEAN InterruptState = FALSE;\r
26EFI_HANDLE mCpuHandle = NULL;\r
27BOOLEAN mIsFlushingGCD;\r
147fd35c 28BOOLEAN mIsAllocatingPageTable = FALSE;\r
c894f83f
ED
29UINT64 mValidMtrrAddressMask;\r
30UINT64 mValidMtrrBitsMask;\r
7537f8c0 31UINT64 mTimerPeriod = 0;\r
a47463f2 32\r
33FIXED_MTRR mFixedMtrrTable[] = {\r
34 {\r
b1bd0d74 35 MSR_IA32_MTRR_FIX64K_00000,\r
a47463f2 36 0,\r
37 0x10000\r
38 },\r
39 {\r
b1bd0d74 40 MSR_IA32_MTRR_FIX16K_80000,\r
a47463f2 41 0x80000,\r
42 0x4000\r
43 },\r
44 {\r
b1bd0d74 45 MSR_IA32_MTRR_FIX16K_A0000,\r
a47463f2 46 0xA0000,\r
47 0x4000\r
48 },\r
49 {\r
b1bd0d74 50 MSR_IA32_MTRR_FIX4K_C0000,\r
a47463f2 51 0xC0000,\r
52 0x1000\r
53 },\r
54 {\r
b1bd0d74 55 MSR_IA32_MTRR_FIX4K_C8000,\r
a47463f2 56 0xC8000,\r
57 0x1000\r
58 },\r
59 {\r
b1bd0d74 60 MSR_IA32_MTRR_FIX4K_D0000,\r
a47463f2 61 0xD0000,\r
62 0x1000\r
63 },\r
64 {\r
b1bd0d74 65 MSR_IA32_MTRR_FIX4K_D8000,\r
a47463f2 66 0xD8000,\r
67 0x1000\r
68 },\r
69 {\r
b1bd0d74 70 MSR_IA32_MTRR_FIX4K_E0000,\r
a47463f2 71 0xE0000,\r
72 0x1000\r
73 },\r
74 {\r
b1bd0d74 75 MSR_IA32_MTRR_FIX4K_E8000,\r
a47463f2 76 0xE8000,\r
77 0x1000\r
78 },\r
79 {\r
b1bd0d74 80 MSR_IA32_MTRR_FIX4K_F0000,\r
a47463f2 81 0xF0000,\r
82 0x1000\r
83 },\r
84 {\r
b1bd0d74 85 MSR_IA32_MTRR_FIX4K_F8000,\r
a47463f2 86 0xF8000,\r
87 0x1000\r
88 },\r
89};\r
90\r
91\r
92EFI_CPU_ARCH_PROTOCOL gCpu = {\r
93 CpuFlushCpuDataCache,\r
94 CpuEnableInterrupt,\r
95 CpuDisableInterrupt,\r
96 CpuGetInterruptState,\r
97 CpuInit,\r
98 CpuRegisterInterruptHandler,\r
99 CpuGetTimerValue,\r
100 CpuSetMemoryAttributes,\r
101 1, // NumberOfTimers\r
102 4 // DmaBufferAlignment\r
103};\r
104\r
a47463f2 105//\r
106// CPU Arch Protocol Functions\r
107//\r
108\r
a47463f2 109/**\r
110 Flush CPU data cache. If the instruction cache is fully coherent\r
111 with all DMA operations then function can just return EFI_SUCCESS.\r
112\r
113 @param This Protocol instance structure\r
114 @param Start Physical address to start flushing from.\r
115 @param Length Number of bytes to flush. Round up to chipset\r
116 granularity.\r
117 @param FlushType Specifies the type of flush operation to perform.\r
118\r
119 @retval EFI_SUCCESS If cache was flushed\r
120 @retval EFI_UNSUPPORTED If flush type is not supported.\r
121 @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
122\r
123**/\r
124EFI_STATUS\r
125EFIAPI\r
126CpuFlushCpuDataCache (\r
127 IN EFI_CPU_ARCH_PROTOCOL *This,\r
128 IN EFI_PHYSICAL_ADDRESS Start,\r
129 IN UINT64 Length,\r
130 IN EFI_CPU_FLUSH_TYPE FlushType\r
131 )\r
132{\r
133 if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r
134 AsmWbinvd ();\r
135 return EFI_SUCCESS;\r
136 } else if (FlushType == EfiCpuFlushTypeInvalidate) {\r
137 AsmInvd ();\r
138 return EFI_SUCCESS;\r
139 } else {\r
140 return EFI_UNSUPPORTED;\r
141 }\r
142}\r
143\r
144\r
145/**\r
146 Enables CPU interrupts.\r
147\r
148 @param This Protocol instance structure\r
149\r
150 @retval EFI_SUCCESS If interrupts were enabled in the CPU\r
151 @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
152\r
153**/\r
154EFI_STATUS\r
155EFIAPI\r
156CpuEnableInterrupt (\r
157 IN EFI_CPU_ARCH_PROTOCOL *This\r
158 )\r
159{\r
160 EnableInterrupts ();\r
161\r
162 InterruptState = TRUE;\r
163 return EFI_SUCCESS;\r
164}\r
165\r
166\r
167/**\r
168 Disables CPU interrupts.\r
169\r
170 @param This Protocol instance structure\r
171\r
172 @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
173 @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
174\r
175**/\r
176EFI_STATUS\r
177EFIAPI\r
178CpuDisableInterrupt (\r
179 IN EFI_CPU_ARCH_PROTOCOL *This\r
180 )\r
181{\r
182 DisableInterrupts ();\r
183\r
184 InterruptState = FALSE;\r
185 return EFI_SUCCESS;\r
186}\r
187\r
188\r
189/**\r
190 Return the state of interrupts.\r
191\r
192 @param This Protocol instance structure\r
193 @param State Pointer to the CPU's current interrupt state\r
194\r
195 @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
196 @retval EFI_INVALID_PARAMETER State is NULL.\r
197\r
198**/\r
199EFI_STATUS\r
200EFIAPI\r
201CpuGetInterruptState (\r
202 IN EFI_CPU_ARCH_PROTOCOL *This,\r
203 OUT BOOLEAN *State\r
204 )\r
205{\r
206 if (State == NULL) {\r
207 return EFI_INVALID_PARAMETER;\r
208 }\r
209\r
210 *State = InterruptState;\r
211 return EFI_SUCCESS;\r
212}\r
213\r
214\r
215/**\r
216 Generates an INIT to the CPU.\r
217\r
218 @param This Protocol instance structure\r
219 @param InitType Type of CPU INIT to perform\r
220\r
221 @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
222 seen.\r
223 @retval EFI_DEVICE_ERROR If CPU INIT failed.\r
224 @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
225\r
226**/\r
227EFI_STATUS\r
228EFIAPI\r
229CpuInit (\r
230 IN EFI_CPU_ARCH_PROTOCOL *This,\r
231 IN EFI_CPU_INIT_TYPE InitType\r
232 )\r
233{\r
234 return EFI_UNSUPPORTED;\r
235}\r
236\r
237\r
238/**\r
239 Registers a function to be called from the CPU interrupt handler.\r
240\r
241 @param This Protocol instance structure\r
242 @param InterruptType Defines which interrupt to hook. IA-32\r
243 valid range is 0x00 through 0xFF\r
244 @param InterruptHandler A pointer to a function of type\r
245 EFI_CPU_INTERRUPT_HANDLER that is called\r
246 when a processor interrupt occurs. A null\r
247 pointer is an error condition.\r
248\r
249 @retval EFI_SUCCESS If handler installed or uninstalled.\r
250 @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
251 for InterruptType was previously installed.\r
252 @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
253 InterruptType was not previously installed.\r
254 @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
255 is not supported.\r
256\r
257**/\r
258EFI_STATUS\r
259EFIAPI\r
260CpuRegisterInterruptHandler (\r
261 IN EFI_CPU_ARCH_PROTOCOL *This,\r
262 IN EFI_EXCEPTION_TYPE InterruptType,\r
263 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
264 )\r
265{\r
e41aad15 266 return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);\r
a47463f2 267}\r
268\r
269\r
270/**\r
271 Returns a timer value from one of the CPU's internal timers. There is no\r
272 inherent time interval between ticks but is a function of the CPU frequency.\r
273\r
274 @param This - Protocol instance structure.\r
275 @param TimerIndex - Specifies which CPU timer is requested.\r
276 @param TimerValue - Pointer to the returned timer value.\r
277 @param TimerPeriod - A pointer to the amount of time that passes\r
278 in femtoseconds (10-15) for each increment\r
279 of TimerValue. If TimerValue does not\r
280 increment at a predictable rate, then 0 is\r
281 returned. The amount of time that has\r
282 passed between two calls to GetTimerValue()\r
283 can be calculated with the formula\r
284 (TimerValue2 - TimerValue1) * TimerPeriod.\r
285 This parameter is optional and may be NULL.\r
286\r
287 @retval EFI_SUCCESS - If the CPU timer count was returned.\r
288 @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
289 @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
290 @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
291\r
292**/\r
293EFI_STATUS\r
294EFIAPI\r
295CpuGetTimerValue (\r
296 IN EFI_CPU_ARCH_PROTOCOL *This,\r
297 IN UINT32 TimerIndex,\r
298 OUT UINT64 *TimerValue,\r
299 OUT UINT64 *TimerPeriod OPTIONAL\r
300 )\r
301{\r
7537f8c0
JF
302 UINT64 BeginValue;\r
303 UINT64 EndValue;\r
304\r
a47463f2 305 if (TimerValue == NULL) {\r
306 return EFI_INVALID_PARAMETER;\r
307 }\r
308\r
309 if (TimerIndex != 0) {\r
310 return EFI_INVALID_PARAMETER;\r
311 }\r
312\r
313 *TimerValue = AsmReadTsc ();\r
314\r
315 if (TimerPeriod != NULL) {\r
7537f8c0
JF
316 if (mTimerPeriod == 0) {\r
317 //\r
318 // Read time stamp counter before and after delay of 100 microseconds\r
319 //\r
320 BeginValue = AsmReadTsc ();\r
321 MicroSecondDelay (100);\r
322 EndValue = AsmReadTsc ();\r
a47463f2 323 //\r
7537f8c0 324 // Calculate the actual frequency\r
a47463f2 325 //\r
7537f8c0
JF
326 mTimerPeriod = DivU64x64Remainder (\r
327 MultU64x32 (\r
328 1000 * 1000 * 1000,\r
329 100\r
330 ),\r
331 EndValue - BeginValue,\r
332 NULL\r
333 );\r
334 }\r
335 *TimerPeriod = mTimerPeriod;\r
a47463f2 336 }\r
337\r
338 return EFI_SUCCESS;\r
339}\r
340\r
0b9f0dd6
JF
341/**\r
342 A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to\r
343 EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.\r
344\r
345 @param[in] Buffer Pointer to an MTRR_SETTINGS object, to be passed to\r
346 MtrrSetAllMtrrs().\r
347**/\r
348VOID\r
349EFIAPI\r
350SetMtrrsFromBuffer (\r
351 IN VOID *Buffer\r
352 )\r
353{\r
354 MtrrSetAllMtrrs (Buffer);\r
355}\r
a47463f2 356\r
357/**\r
4ec21e8b 358 Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.\r
359\r
360 This function modifies the attributes for the memory region specified by BaseAddress and\r
361 Length from their current attributes to the attributes specified by Attributes.\r
362\r
363 @param This The EFI_CPU_ARCH_PROTOCOL instance.\r
364 @param BaseAddress The physical address that is the start address of a memory region.\r
365 @param Length The size in bytes of the memory region.\r
366 @param Attributes The bit mask of attributes to set for the memory region.\r
367\r
368 @retval EFI_SUCCESS The attributes were set for the memory region.\r
369 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
370 BaseAddress and Length cannot be modified.\r
371 @retval EFI_INVALID_PARAMETER Length is zero.\r
372 Attributes specified an illegal combination of attributes that\r
373 cannot be set together.\r
374 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
375 the memory resource range.\r
376 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
377 resource range specified by BaseAddress and Length.\r
378 The bit mask of attributes is not support for the memory resource\r
379 range specified by BaseAddress and Length.\r
a47463f2 380\r
381**/\r
382EFI_STATUS\r
383EFIAPI\r
384CpuSetMemoryAttributes (\r
385 IN EFI_CPU_ARCH_PROTOCOL *This,\r
386 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
387 IN UINT64 Length,\r
388 IN UINT64 Attributes\r
389 )\r
390{\r
391 RETURN_STATUS Status;\r
392 MTRR_MEMORY_CACHE_TYPE CacheType;\r
94941c88
LE
393 EFI_STATUS MpStatus;\r
394 EFI_MP_SERVICES_PROTOCOL *MpService;\r
395 MTRR_SETTINGS MtrrSettings;\r
22292ed3
JY
396 UINT64 CacheAttributes;\r
397 UINT64 MemoryAttributes;\r
398 MTRR_MEMORY_CACHE_TYPE CurrentCacheType;\r
947a573a 399\r
a47463f2 400 //\r
401 // If this function is called because GCD SetMemorySpaceAttributes () is called\r
402 // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory\r
403 // map with MTRR values. So there is no need to modify MTRRs, just return immediately\r
404 // to avoid unnecessary computing.\r
405 //\r
406 if (mIsFlushingGCD) {\r
af9bce40 407 DEBUG((DEBUG_INFO, " Flushing GCD\n"));\r
79aca636
SEHM
408 return EFI_SUCCESS;\r
409 }\r
a47463f2 410\r
147fd35c
JW
411 //\r
412 // During memory attributes updating, new pages may be allocated to setup\r
413 // smaller granularity of page table. Page allocation action might then cause\r
414 // another calling of CpuSetMemoryAttributes() recursively, due to memory\r
415 // protection policy configured (such as PcdDxeNxMemoryProtectionPolicy).\r
416 // Since this driver will always protect memory used as page table by itself,\r
417 // there's no need to apply protection policy requested from memory service.\r
418 // So it's safe to just return EFI_SUCCESS if this time of calling is caused\r
419 // by page table memory allocation.\r
420 //\r
421 if (mIsAllocatingPageTable) {\r
422 DEBUG((DEBUG_VERBOSE, " Allocating page table memory\n"));\r
423 return EFI_SUCCESS;\r
424 }\r
a47463f2 425\r
22292ed3
JY
426 CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;\r
427 MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;\r
a47463f2 428\r
22292ed3
JY
429 if (Attributes != (CacheAttributes | MemoryAttributes)) {\r
430 return EFI_INVALID_PARAMETER;\r
431 }\r
a47463f2 432\r
22292ed3
JY
433 if (CacheAttributes != 0) {\r
434 if (!IsMtrrSupported ()) {\r
435 return EFI_UNSUPPORTED;\r
436 }\r
a47463f2 437\r
22292ed3
JY
438 switch (CacheAttributes) {\r
439 case EFI_MEMORY_UC:\r
440 CacheType = CacheUncacheable;\r
441 break;\r
a47463f2 442\r
22292ed3
JY
443 case EFI_MEMORY_WC:\r
444 CacheType = CacheWriteCombining;\r
445 break;\r
4ec21e8b 446\r
22292ed3
JY
447 case EFI_MEMORY_WT:\r
448 CacheType = CacheWriteThrough;\r
449 break;\r
a47463f2 450\r
22292ed3
JY
451 case EFI_MEMORY_WP:\r
452 CacheType = CacheWriteProtected;\r
453 break;\r
454\r
455 case EFI_MEMORY_WB:\r
456 CacheType = CacheWriteBack;\r
457 break;\r
458\r
459 default:\r
460 return EFI_INVALID_PARAMETER;\r
461 }\r
462 CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);\r
463 if (CurrentCacheType != CacheType) {\r
464 //\r
465 // call MTRR libary function\r
466 //\r
467 Status = MtrrSetMemoryAttribute (\r
468 BaseAddress,\r
469 Length,\r
470 CacheType\r
471 );\r
472\r
473 if (!RETURN_ERROR (Status)) {\r
474 MpStatus = gBS->LocateProtocol (\r
475 &gEfiMpServiceProtocolGuid,\r
476 NULL,\r
477 (VOID **)&MpService\r
478 );\r
479 //\r
480 // Synchronize the update with all APs\r
481 //\r
482 if (!EFI_ERROR (MpStatus)) {\r
483 MtrrGetAllMtrrs (&MtrrSettings);\r
484 MpStatus = MpService->StartupAllAPs (\r
485 MpService, // This\r
486 SetMtrrsFromBuffer, // Procedure\r
487 FALSE, // SingleThread\r
488 NULL, // WaitEvent\r
489 0, // TimeoutInMicrosecsond\r
490 &MtrrSettings, // ProcedureArgument\r
491 NULL // FailedCpuList\r
492 );\r
493 ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);\r
494 }\r
495 }\r
496 if (EFI_ERROR(Status)) {\r
497 return Status;\r
498 }\r
94941c88
LE
499 }\r
500 }\r
22292ed3
JY
501\r
502 //\r
503 // Set memory attribute by page table\r
504 //\r
147fd35c 505 return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, NULL);\r
a47463f2 506}\r
507\r
508/**\r
509 Initializes the valid bits mask and valid address mask for MTRRs.\r
510\r
511 This function initializes the valid bits mask and valid address mask for MTRRs.\r
512\r
513**/\r
514VOID\r
515InitializeMtrrMask (\r
516 VOID\r
517 )\r
518{\r
519 UINT32 RegEax;\r
520 UINT8 PhysicalAddressBits;\r
521\r
522 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
523\r
524 if (RegEax >= 0x80000008) {\r
525 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
526\r
527 PhysicalAddressBits = (UINT8) RegEax;\r
a47463f2 528 } else {\r
c894f83f 529 PhysicalAddressBits = 36;\r
a47463f2 530 }\r
c894f83f
ED
531\r
532 mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
533 mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
a47463f2 534}\r
535\r
536/**\r
430fbbe0 537 Gets GCD Mem Space type from MTRR Type.\r
a47463f2 538\r
430fbbe0 539 This function gets GCD Mem Space type from MTRR Type.\r
a47463f2 540\r
430fbbe0 541 @param MtrrAttributes MTRR memory type\r
a47463f2 542\r
543 @return GCD Mem Space type\r
544\r
545**/\r
546UINT64\r
547GetMemorySpaceAttributeFromMtrrType (\r
2c4b1bdc 548 IN UINT8 MtrrAttributes\r
a47463f2 549 )\r
550{\r
551 switch (MtrrAttributes) {\r
552 case MTRR_CACHE_UNCACHEABLE:\r
553 return EFI_MEMORY_UC;\r
554 case MTRR_CACHE_WRITE_COMBINING:\r
555 return EFI_MEMORY_WC;\r
556 case MTRR_CACHE_WRITE_THROUGH:\r
557 return EFI_MEMORY_WT;\r
558 case MTRR_CACHE_WRITE_PROTECTED:\r
559 return EFI_MEMORY_WP;\r
560 case MTRR_CACHE_WRITE_BACK:\r
561 return EFI_MEMORY_WB;\r
562 default:\r
563 return 0;\r
564 }\r
565}\r
566\r
567/**\r
568 Searches memory descriptors covered by given memory range.\r
569\r
570 This function searches into the Gcd Memory Space for descriptors\r
571 (from StartIndex to EndIndex) that contains the memory range\r
572 specified by BaseAddress and Length.\r
573\r
574 @param MemorySpaceMap Gcd Memory Space Map as array.\r
575 @param NumberOfDescriptors Number of descriptors in map.\r
576 @param BaseAddress BaseAddress for the requested range.\r
577 @param Length Length for the requested range.\r
578 @param StartIndex Start index into the Gcd Memory Space Map.\r
579 @param EndIndex End index into the Gcd Memory Space Map.\r
580\r
581 @retval EFI_SUCCESS Search successfully.\r
582 @retval EFI_NOT_FOUND The requested descriptors does not exist.\r
583\r
584**/\r
585EFI_STATUS\r
586SearchGcdMemorySpaces (\r
587 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
588 IN UINTN NumberOfDescriptors,\r
589 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
590 IN UINT64 Length,\r
591 OUT UINTN *StartIndex,\r
592 OUT UINTN *EndIndex\r
593 )\r
594{\r
595 UINTN Index;\r
596\r
597 *StartIndex = 0;\r
598 *EndIndex = 0;\r
599 for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
600 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r
601 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
602 *StartIndex = Index;\r
603 }\r
604 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r
605 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
606 *EndIndex = Index;\r
607 return EFI_SUCCESS;\r
608 }\r
609 }\r
610 return EFI_NOT_FOUND;\r
611}\r
612\r
613/**\r
614 Sets the attributes for a specified range in Gcd Memory Space Map.\r
615\r
616 This function sets the attributes for a specified range in\r
617 Gcd Memory Space Map.\r
618\r
619 @param MemorySpaceMap Gcd Memory Space Map as array\r
620 @param NumberOfDescriptors Number of descriptors in map\r
621 @param BaseAddress BaseAddress for the range\r
622 @param Length Length for the range\r
623 @param Attributes Attributes to set\r
624\r
625 @retval EFI_SUCCESS Memory attributes set successfully\r
626 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r
627\r
628**/\r
629EFI_STATUS\r
630SetGcdMemorySpaceAttributes (\r
631 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
632 IN UINTN NumberOfDescriptors,\r
633 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
634 IN UINT64 Length,\r
635 IN UINT64 Attributes\r
636 )\r
637{\r
638 EFI_STATUS Status;\r
639 UINTN Index;\r
640 UINTN StartIndex;\r
641 UINTN EndIndex;\r
642 EFI_PHYSICAL_ADDRESS RegionStart;\r
643 UINT64 RegionLength;\r
644\r
645 //\r
646 // Get all memory descriptors covered by the memory range\r
647 //\r
648 Status = SearchGcdMemorySpaces (\r
649 MemorySpaceMap,\r
650 NumberOfDescriptors,\r
651 BaseAddress,\r
652 Length,\r
653 &StartIndex,\r
654 &EndIndex\r
655 );\r
656 if (EFI_ERROR (Status)) {\r
657 return Status;\r
658 }\r
659\r
660 //\r
661 // Go through all related descriptors and set attributes accordingly\r
662 //\r
663 for (Index = StartIndex; Index <= EndIndex; Index++) {\r
664 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
665 continue;\r
666 }\r
667 //\r
668 // Calculate the start and end address of the overlapping range\r
669 //\r
670 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r
671 RegionStart = BaseAddress;\r
672 } else {\r
673 RegionStart = MemorySpaceMap[Index].BaseAddress;\r
674 }\r
675 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
676 RegionLength = BaseAddress + Length - RegionStart;\r
677 } else {\r
678 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
679 }\r
680 //\r
681 // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
682 //\r
683 gDS->SetMemorySpaceAttributes (\r
684 RegionStart,\r
685 RegionLength,\r
686 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r
687 );\r
688 }\r
689\r
690 return EFI_SUCCESS;\r
691}\r
692\r
693\r
694/**\r
695 Refreshes the GCD Memory Space attributes according to MTRRs.\r
696\r
697 This function refreshes the GCD Memory Space attributes according to MTRRs.\r
698\r
699**/\r
700VOID\r
c46bced2 701RefreshMemoryAttributesFromMtrr (\r
a47463f2 702 VOID\r
703 )\r
704{\r
705 EFI_STATUS Status;\r
706 UINTN Index;\r
707 UINTN SubIndex;\r
708 UINT64 RegValue;\r
709 EFI_PHYSICAL_ADDRESS BaseAddress;\r
710 UINT64 Length;\r
711 UINT64 Attributes;\r
712 UINT64 CurrentAttributes;\r
2c4b1bdc 713 UINT8 MtrrType;\r
a47463f2 714 UINTN NumberOfDescriptors;\r
715 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
716 UINT64 DefaultAttributes;\r
6640eb36 717 VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
a47463f2 718 MTRR_FIXED_SETTINGS MtrrFixedSettings;\r
3b9be416 719 UINT32 FirmwareVariableMtrrCount;\r
2c4b1bdc 720 UINT8 DefaultMemoryType;\r
3b9be416
JY
721\r
722 FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r
5bdfa4e5 723 ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
a47463f2 724\r
a47463f2 725 MemorySpaceMap = NULL;\r
726\r
727 //\r
728 // Initialize the valid bits mask and valid address mask for MTRRs\r
729 //\r
730 InitializeMtrrMask ();\r
731\r
732 //\r
733 // Get the memory attribute of variable MTRRs\r
734 //\r
735 MtrrGetMemoryAttributeInVariableMtrr (\r
736 mValidMtrrBitsMask,\r
737 mValidMtrrAddressMask,\r
738 VariableMtrr\r
739 );\r
740\r
741 //\r
742 // Get the memory space map from GCD\r
743 //\r
744 Status = gDS->GetMemorySpaceMap (\r
745 &NumberOfDescriptors,\r
746 &MemorySpaceMap\r
747 );\r
748 ASSERT_EFI_ERROR (Status);\r
749\r
2c4b1bdc 750 DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();\r
91ec7824 751 DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);\r
a47463f2 752\r
753 //\r
754 // Set default attributes to all spaces.\r
755 //\r
756 for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
757 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
758 continue;\r
759 }\r
760 gDS->SetMemorySpaceAttributes (\r
761 MemorySpaceMap[Index].BaseAddress,\r
762 MemorySpaceMap[Index].Length,\r
763 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |\r
764 (MemorySpaceMap[Index].Capabilities & DefaultAttributes)\r
765 );\r
766 }\r
767\r
768 //\r
769 // Go for variable MTRRs with WB attribute\r
770 //\r
3b9be416 771 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
a47463f2 772 if (VariableMtrr[Index].Valid &&\r
773 VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {\r
774 SetGcdMemorySpaceAttributes (\r
775 MemorySpaceMap,\r
776 NumberOfDescriptors,\r
777 VariableMtrr[Index].BaseAddress,\r
778 VariableMtrr[Index].Length,\r
779 EFI_MEMORY_WB\r
780 );\r
781 }\r
782 }\r
91ec7824 783\r
a47463f2 784 //\r
91ec7824 785 // Go for variable MTRRs with the attribute except for WB and UC attributes\r
a47463f2 786 //\r
3b9be416 787 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
d4605c23 788 if (VariableMtrr[Index].Valid &&\r
91ec7824 789 VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&\r
790 VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {\r
2c4b1bdc 791 Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);\r
a47463f2 792 SetGcdMemorySpaceAttributes (\r
793 MemorySpaceMap,\r
794 NumberOfDescriptors,\r
795 VariableMtrr[Index].BaseAddress,\r
796 VariableMtrr[Index].Length,\r
797 Attributes\r
798 );\r
799 }\r
800 }\r
801\r
91ec7824 802 //\r
803 // Go for variable MTRRs with UC attribute\r
804 //\r
805 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
806 if (VariableMtrr[Index].Valid &&\r
807 VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {\r
808 SetGcdMemorySpaceAttributes (\r
809 MemorySpaceMap,\r
810 NumberOfDescriptors,\r
811 VariableMtrr[Index].BaseAddress,\r
812 VariableMtrr[Index].Length,\r
813 EFI_MEMORY_UC\r
814 );\r
815 }\r
816 }\r
817\r
a47463f2 818 //\r
819 // Go for fixed MTRRs\r
820 //\r
821 Attributes = 0;\r
822 BaseAddress = 0;\r
823 Length = 0;\r
824 MtrrGetFixedMtrr (&MtrrFixedSettings);\r
825 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
826 RegValue = MtrrFixedSettings.Mtrr[Index];\r
827 //\r
828 // Check for continuous fixed MTRR sections\r
829 //\r
830 for (SubIndex = 0; SubIndex < 8; SubIndex++) {\r
2c4b1bdc 831 MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);\r
a47463f2 832 CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);\r
833 if (Length == 0) {\r
834 //\r
835 // A new MTRR attribute begins\r
836 //\r
837 Attributes = CurrentAttributes;\r
838 } else {\r
839 //\r
840 // If fixed MTRR attribute changed, then set memory attribute for previous atrribute\r
841 //\r
842 if (CurrentAttributes != Attributes) {\r
843 SetGcdMemorySpaceAttributes (\r
844 MemorySpaceMap,\r
845 NumberOfDescriptors,\r
846 BaseAddress,\r
847 Length,\r
848 Attributes\r
849 );\r
850 BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;\r
851 Length = 0;\r
852 Attributes = CurrentAttributes;\r
853 }\r
854 }\r
855 Length += mFixedMtrrTable[Index].Length;\r
856 }\r
857 }\r
858 //\r
859 // Handle the last fixed MTRR region\r
860 //\r
861 SetGcdMemorySpaceAttributes (\r
862 MemorySpaceMap,\r
863 NumberOfDescriptors,\r
864 BaseAddress,\r
865 Length,\r
866 Attributes\r
867 );\r
868\r
869 //\r
870 // Free memory space map allocated by GCD service GetMemorySpaceMap ()\r
871 //\r
872 if (MemorySpaceMap != NULL) {\r
873 FreePool (MemorySpaceMap);\r
874 }\r
c46bced2 875}\r
a47463f2 876\r
c46bced2
JW
877/**\r
878 Check if paging is enabled or not.\r
879**/\r
880BOOLEAN\r
881IsPagingAndPageAddressExtensionsEnabled (\r
882 VOID\r
883 )\r
884{\r
885 IA32_CR0 Cr0;\r
886 IA32_CR4 Cr4;\r
887\r
888 Cr0.UintN = AsmReadCr0 ();\r
889 Cr4.UintN = AsmReadCr4 ();\r
890\r
891 return ((Cr0.Bits.PG != 0) && (Cr4.Bits.PAE != 0));\r
892}\r
893\r
894/**\r
895 Refreshes the GCD Memory Space attributes according to MTRRs and Paging.\r
896\r
897 This function refreshes the GCD Memory Space attributes according to MTRRs\r
898 and page tables.\r
899\r
900**/\r
901VOID\r
902RefreshGcdMemoryAttributes (\r
903 VOID\r
904 )\r
905{\r
906 mIsFlushingGCD = TRUE;\r
907\r
908 if (IsMtrrSupported ()) {\r
909 RefreshMemoryAttributesFromMtrr ();\r
910 }\r
911\r
912 if (IsPagingAndPageAddressExtensionsEnabled ()) {\r
913 RefreshGcdMemoryAttributesFromPaging ();\r
914 }\r
c1cab54c 915\r
a47463f2 916 mIsFlushingGCD = FALSE;\r
917}\r
918\r
a47463f2 919/**\r
920 Initialize Interrupt Descriptor Table for interrupt handling.\r
921\r
922**/\r
a47463f2 923VOID\r
924InitInterruptDescriptorTable (\r
925 VOID\r
926 )\r
927{\r
e41aad15
JF
928 EFI_STATUS Status;\r
929 EFI_VECTOR_HANDOFF_INFO *VectorInfoList;\r
930 EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r
931\r
932 VectorInfo = NULL;\r
933 Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);\r
934 if (Status == EFI_SUCCESS && VectorInfoList != NULL) {\r
935 VectorInfo = VectorInfoList;\r
a47463f2 936 }\r
e41aad15
JF
937 Status = InitializeCpuInterruptHandlers (VectorInfo);\r
938 ASSERT_EFI_ERROR (Status);\r
a47463f2 939}\r
940\r
941\r
32394027 942/**\r
943 Callback function for idle events.\r
d4605c23 944\r
32394027 945 @param Event Event whose notification function is being invoked.\r
946 @param Context The pointer to the notification function's context,\r
947 which is implementation-dependent.\r
948\r
949**/\r
950VOID\r
951EFIAPI\r
952IdleLoopEventCallback (\r
953 IN EFI_EVENT Event,\r
954 IN VOID *Context\r
955 )\r
956{\r
957 CpuSleep ();\r
958}\r
959\r
410590f1
JF
960/**\r
961 Ensure the compatibility of a memory space descriptor with the MMIO aperture.\r
962\r
963 The memory space descriptor can come from the GCD memory space map, or it can\r
964 represent a gap between two neighboring memory space descriptors. In the\r
965 latter case, the GcdMemoryType field is expected to be\r
966 EfiGcdMemoryTypeNonExistent.\r
967\r
968 If the memory space descriptor already has type\r
969 EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the\r
970 required capabilities, then no action is taken -- it is by definition\r
971 compatible with the aperture.\r
972\r
973 Otherwise, the intersection of the memory space descriptor is calculated with\r
974 the aperture. If the intersection is the empty set (no overlap), no action is\r
975 taken; the memory space descriptor is compatible with the aperture.\r
976\r
977 Otherwise, the type of the descriptor is investigated again. If the type is\r
978 EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with\r
979 such a type), then an attempt is made to add the intersection as MMIO space\r
980 to the GCD memory space map, with the specified capabilities. This ensures\r
981 continuity for the aperture, and the descriptor is deemed compatible with the\r
982 aperture.\r
983\r
984 Otherwise, the memory space descriptor is incompatible with the MMIO\r
985 aperture.\r
986\r
987 @param[in] Base Base address of the aperture.\r
988 @param[in] Length Length of the aperture.\r
989 @param[in] Capabilities Capabilities required by the aperture.\r
990 @param[in] Descriptor The descriptor to ensure compatibility with the\r
991 aperture for.\r
992\r
993 @retval EFI_SUCCESS The descriptor is compatible. The GCD memory\r
994 space map may have been updated, for\r
995 continuity within the aperture.\r
996 @retval EFI_INVALID_PARAMETER The descriptor is incompatible.\r
997 @return Error codes from gDS->AddMemorySpace().\r
998**/\r
999EFI_STATUS\r
1000IntersectMemoryDescriptor (\r
1001 IN UINT64 Base,\r
1002 IN UINT64 Length,\r
1003 IN UINT64 Capabilities,\r
1004 IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor\r
1005 )\r
1006{\r
1007 UINT64 IntersectionBase;\r
1008 UINT64 IntersectionEnd;\r
1009 EFI_STATUS Status;\r
1010\r
1011 if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&\r
1012 (Descriptor->Capabilities & Capabilities) == Capabilities) {\r
1013 return EFI_SUCCESS;\r
1014 }\r
1015\r
1016 IntersectionBase = MAX (Base, Descriptor->BaseAddress);\r
1017 IntersectionEnd = MIN (Base + Length,\r
1018 Descriptor->BaseAddress + Descriptor->Length);\r
1019 if (IntersectionBase >= IntersectionEnd) {\r
1020 //\r
1021 // The descriptor and the aperture don't overlap.\r
1022 //\r
1023 return EFI_SUCCESS;\r
1024 }\r
1025\r
1026 if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
1027 Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,\r
1028 IntersectionBase, IntersectionEnd - IntersectionBase,\r
1029 Capabilities);\r
1030\r
af9bce40 1031 DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
410590f1
JF
1032 "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,\r
1033 IntersectionBase, IntersectionEnd, Status));\r
1034 return Status;\r
1035 }\r
1036\r
af9bce40 1037 DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r
410590f1
JF
1038 "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,\r
1039 Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,\r
1040 (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,\r
1041 Base, Base + Length, Capabilities));\r
1042 return EFI_INVALID_PARAMETER;\r
1043}\r
1044\r
1045/**\r
1046 Add MMIO space to GCD.\r
1047 The routine checks the GCD database and only adds those which are\r
1048 not added in the specified range to GCD.\r
1049\r
1050 @param Base Base address of the MMIO space.\r
1051 @param Length Length of the MMIO space.\r
1052 @param Capabilities Capabilities of the MMIO space.\r
1053\r
1054 @retval EFI_SUCCES The MMIO space was added successfully.\r
1055**/\r
1056EFI_STATUS\r
1057AddMemoryMappedIoSpace (\r
1058 IN UINT64 Base,\r
1059 IN UINT64 Length,\r
1060 IN UINT64 Capabilities\r
1061 )\r
1062{\r
1063 EFI_STATUS Status;\r
1064 UINTN Index;\r
1065 UINTN NumberOfDescriptors;\r
1066 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
1067\r
1068 Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
1069 if (EFI_ERROR (Status)) {\r
af9bce40 1070 DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",\r
410590f1
JF
1071 gEfiCallerBaseName, __FUNCTION__, Status));\r
1072 return Status;\r
1073 }\r
1074\r
1075 for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
1076 Status = IntersectMemoryDescriptor (Base, Length, Capabilities,\r
1077 &MemorySpaceMap[Index]);\r
1078 if (EFI_ERROR (Status)) {\r
1079 goto FreeMemorySpaceMap;\r
1080 }\r
1081 }\r
1082\r
1083 DEBUG_CODE (\r
1084 //\r
1085 // Make sure there are adjacent descriptors covering [Base, Base + Length).\r
1086 // It is possible that they have not been merged; merging can be prevented\r
1087 // by allocation and different capabilities.\r
1088 //\r
1089 UINT64 CheckBase;\r
1090 EFI_STATUS CheckStatus;\r
1091 EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r
1092\r
1093 for (CheckBase = Base;\r
1094 CheckBase < Base + Length;\r
1095 CheckBase = Descriptor.BaseAddress + Descriptor.Length) {\r
1096 CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);\r
1097 ASSERT_EFI_ERROR (CheckStatus);\r
1098 ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);\r
1099 ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);\r
1100 }\r
1101 );\r
1102\r
1103FreeMemorySpaceMap:\r
1104 FreePool (MemorySpaceMap);\r
1105\r
1106 return Status;\r
1107}\r
32394027 1108\r
14f92ded
JF
1109/**\r
1110 Add and allocate CPU local APIC memory mapped space. \r
1111\r
1112 @param[in]ImageHandle Image handle this driver.\r
1113\r
1114**/\r
1115VOID\r
1116AddLocalApicMemorySpace (\r
1117 IN EFI_HANDLE ImageHandle\r
1118 )\r
1119{\r
1120 EFI_STATUS Status;\r
1121 EFI_PHYSICAL_ADDRESS BaseAddress;\r
1122\r
1123 BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();\r
1124 Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);\r
1125 ASSERT_EFI_ERROR (Status);\r
1126\r
29c90f14
JF
1127 //\r
1128 // Try to allocate APIC memory mapped space, does not check return \r
1129 // status because it may be allocated by other driver, or DXE Core if\r
1130 // this range is built into Memory Allocation HOB.\r
1131 //\r
14f92ded
JF
1132 Status = gDS->AllocateMemorySpace (\r
1133 EfiGcdAllocateAddress,\r
1134 EfiGcdMemoryTypeMemoryMappedIo,\r
1135 0,\r
1136 SIZE_4KB,\r
1137 &BaseAddress,\r
1138 ImageHandle,\r
1139 NULL\r
1140 );\r
29c90f14
JF
1141 if (EFI_ERROR (Status)) {\r
1142 DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n",\r
1143 gEfiCallerBaseName, __FUNCTION__, Status));\r
1144 }\r
14f92ded
JF
1145}\r
1146\r
a47463f2 1147/**\r
1148 Initialize the state information for the CPU Architectural Protocol.\r
1149\r
1150 @param ImageHandle Image handle this driver.\r
1151 @param SystemTable Pointer to the System Table.\r
1152\r
1153 @retval EFI_SUCCESS Thread can be successfully created\r
1154 @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
1155 @retval EFI_DEVICE_ERROR Cannot create the thread\r
1156\r
1157**/\r
1158EFI_STATUS\r
1159EFIAPI\r
1160InitializeCpu (\r
1161 IN EFI_HANDLE ImageHandle,\r
1162 IN EFI_SYSTEM_TABLE *SystemTable\r
1163 )\r
1164{\r
1165 EFI_STATUS Status;\r
32394027 1166 EFI_EVENT IdleLoopEvent;\r
22292ed3
JY
1167 \r
1168 InitializePageTableLib();\r
a47463f2 1169\r
661cab5d 1170 InitializeFloatingPointUnits ();\r
1171\r
a47463f2 1172 //\r
1173 // Make sure interrupts are disabled\r
1174 //\r
1175 DisableInterrupts ();\r
1176\r
1177 //\r
1178 // Init GDT for DXE\r
1179 //\r
1180 InitGlobalDescriptorTable ();\r
1181\r
1182 //\r
1183 // Setup IDT pointer, IDT and interrupt entry points\r
1184 //\r
1185 InitInterruptDescriptorTable ();\r
1186\r
1187 //\r
1188 // Install CPU Architectural Protocol\r
1189 //\r
1190 Status = gBS->InstallMultipleProtocolInterfaces (\r
1191 &mCpuHandle,\r
1192 &gEfiCpuArchProtocolGuid, &gCpu,\r
1193 NULL\r
1194 );\r
1195 ASSERT_EFI_ERROR (Status);\r
1196\r
1197 //\r
1198 // Refresh GCD memory space map according to MTRR value.\r
1199 //\r
1200 RefreshGcdMemoryAttributes ();\r
1201\r
14f92ded
JF
1202 //\r
1203 // Add and allocate local APIC memory mapped space\r
1204 //\r
1205 AddLocalApicMemorySpace (ImageHandle);\r
1206\r
32394027 1207 //\r
1208 // Setup a callback for idle events\r
1209 //\r
1210 Status = gBS->CreateEventEx (\r
1211 EVT_NOTIFY_SIGNAL,\r
1212 TPL_NOTIFY,\r
1213 IdleLoopEventCallback,\r
1214 NULL,\r
1215 &gIdleLoopEventGuid,\r
1216 &IdleLoopEvent\r
1217 );\r
1218 ASSERT_EFI_ERROR (Status);\r
1219\r
6022e28c
JJ
1220 InitializeMpSupport ();\r
1221\r
a47463f2 1222 return Status;\r
1223}\r
1224\r