projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a47463f2 | 1 | /** @file\r |
| 7fadaacd | 2 | CPU DXE Module to produce CPU ARCH Protocol.\r |
| a47463f2 | 3 | \r |
| 22292ed3 | 4 | Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r |
| 01a1c0fc | 5 | This program and the accompanying materials\r |
| a47463f2 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #include "CpuDxe.h"\r | |
| 6022e28c | 16 | #include "CpuMp.h"\r |
| 22292ed3 JY |
17 | #include "CpuPageTable.h"\r |
| 18 | \r | |
| 19 | #define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)\r | |
| 20 | #define MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)\r | |
| a47463f2 | 21 | \r |
| 22 | //\r | |
| 23 | // Global Variables\r | |
| 24 | //\r | |
| a47463f2 | 25 | BOOLEAN InterruptState = FALSE;\r |
| 26 | EFI_HANDLE mCpuHandle = NULL;\r | |
| 27 | BOOLEAN mIsFlushingGCD;\r | |
| a47463f2 | 28 | UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r |
| 29 | UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r | |
| 7537f8c0 | 30 | UINT64 mTimerPeriod = 0;\r |
| a47463f2 | 31 | \r |
| 32 | FIXED_MTRR mFixedMtrrTable[] = {\r | |
| 33 | {\r | |
| 34 | MTRR_LIB_IA32_MTRR_FIX64K_00000,\r | |
| 35 | 0,\r | |
| 36 | 0x10000\r | |
| 37 | },\r | |
| 38 | {\r | |
| 39 | MTRR_LIB_IA32_MTRR_FIX16K_80000,\r | |
| 40 | 0x80000,\r | |
| 41 | 0x4000\r | |
| 42 | },\r | |
| 43 | {\r | |
| 44 | MTRR_LIB_IA32_MTRR_FIX16K_A0000,\r | |
| 45 | 0xA0000,\r | |
| 46 | 0x4000\r | |
| 47 | },\r | |
| 48 | {\r | |
| 49 | MTRR_LIB_IA32_MTRR_FIX4K_C0000,\r | |
| 50 | 0xC0000,\r | |
| 51 | 0x1000\r | |
| 52 | },\r | |
| 53 | {\r | |
| 54 | MTRR_LIB_IA32_MTRR_FIX4K_C8000,\r | |
| 55 | 0xC8000,\r | |
| 56 | 0x1000\r | |
| 57 | },\r | |
| 58 | {\r | |
| 59 | MTRR_LIB_IA32_MTRR_FIX4K_D0000,\r | |
| 60 | 0xD0000,\r | |
| 61 | 0x1000\r | |
| 62 | },\r | |
| 63 | {\r | |
| 64 | MTRR_LIB_IA32_MTRR_FIX4K_D8000,\r | |
| 65 | 0xD8000,\r | |
| 66 | 0x1000\r | |
| 67 | },\r | |
| 68 | {\r | |
| 69 | MTRR_LIB_IA32_MTRR_FIX4K_E0000,\r | |
| 70 | 0xE0000,\r | |
| 71 | 0x1000\r | |
| 72 | },\r | |
| 73 | {\r | |
| 74 | MTRR_LIB_IA32_MTRR_FIX4K_E8000,\r | |
| 75 | 0xE8000,\r | |
| 76 | 0x1000\r | |
| 77 | },\r | |
| 78 | {\r | |
| 79 | MTRR_LIB_IA32_MTRR_FIX4K_F0000,\r | |
| 80 | 0xF0000,\r | |
| 81 | 0x1000\r | |
| 82 | },\r | |
| 83 | {\r | |
| 84 | MTRR_LIB_IA32_MTRR_FIX4K_F8000,\r | |
| 85 | 0xF8000,\r | |
| 86 | 0x1000\r | |
| 87 | },\r | |
| 88 | };\r | |
| 89 | \r | |
| 90 | \r | |
| 91 | EFI_CPU_ARCH_PROTOCOL gCpu = {\r | |
| 92 | CpuFlushCpuDataCache,\r | |
| 93 | CpuEnableInterrupt,\r | |
| 94 | CpuDisableInterrupt,\r | |
| 95 | CpuGetInterruptState,\r | |
| 96 | CpuInit,\r | |
| 97 | CpuRegisterInterruptHandler,\r | |
| 98 | CpuGetTimerValue,\r | |
| 99 | CpuSetMemoryAttributes,\r | |
| 100 | 1, // NumberOfTimers\r | |
| 101 | 4 // DmaBufferAlignment\r | |
| 102 | };\r | |
| 103 | \r | |
| a47463f2 | 104 | //\r |
| 105 | // CPU Arch Protocol Functions\r | |
| 106 | //\r | |
| 107 | \r | |
| a47463f2 | 108 | /**\r |
| 109 | Flush CPU data cache. If the instruction cache is fully coherent\r | |
| 110 | with all DMA operations then function can just return EFI_SUCCESS.\r | |
| 111 | \r | |
| 112 | @param This Protocol instance structure\r | |
| 113 | @param Start Physical address to start flushing from.\r | |
| 114 | @param Length Number of bytes to flush. Round up to chipset\r | |
| 115 | granularity.\r | |
| 116 | @param FlushType Specifies the type of flush operation to perform.\r | |
| 117 | \r | |
| 118 | @retval EFI_SUCCESS If cache was flushed\r | |
| 119 | @retval EFI_UNSUPPORTED If flush type is not supported.\r | |
| 120 | @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r | |
| 121 | \r | |
| 122 | **/\r | |
| 123 | EFI_STATUS\r | |
| 124 | EFIAPI\r | |
| 125 | CpuFlushCpuDataCache (\r | |
| 126 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
| 127 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
| 128 | IN UINT64 Length,\r | |
| 129 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
| 130 | )\r | |
| 131 | {\r | |
| 132 | if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r | |
| 133 | AsmWbinvd ();\r | |
| 134 | return EFI_SUCCESS;\r | |
| 135 | } else if (FlushType == EfiCpuFlushTypeInvalidate) {\r | |
| 136 | AsmInvd ();\r | |
| 137 | return EFI_SUCCESS;\r | |
| 138 | } else {\r | |
| 139 | return EFI_UNSUPPORTED;\r | |
| 140 | }\r | |
| 141 | }\r | |
| 142 | \r | |
| 143 | \r | |
| 144 | /**\r | |
| 145 | Enables CPU interrupts.\r | |
| 146 | \r | |
| 147 | @param This Protocol instance structure\r | |
| 148 | \r | |
| 149 | @retval EFI_SUCCESS If interrupts were enabled in the CPU\r | |
| 150 | @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r | |
| 151 | \r | |
| 152 | **/\r | |
| 153 | EFI_STATUS\r | |
| 154 | EFIAPI\r | |
| 155 | CpuEnableInterrupt (\r | |
| 156 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
| 157 | )\r | |
| 158 | {\r | |
| 159 | EnableInterrupts ();\r | |
| 160 | \r | |
| 161 | InterruptState = TRUE;\r | |
| 162 | return EFI_SUCCESS;\r | |
| 163 | }\r | |
| 164 | \r | |
| 165 | \r | |
| 166 | /**\r | |
| 167 | Disables CPU interrupts.\r | |
| 168 | \r | |
| 169 | @param This Protocol instance structure\r | |
| 170 | \r | |
| 171 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
| 172 | @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r | |
| 173 | \r | |
| 174 | **/\r | |
| 175 | EFI_STATUS\r | |
| 176 | EFIAPI\r | |
| 177 | CpuDisableInterrupt (\r | |
| 178 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
| 179 | )\r | |
| 180 | {\r | |
| 181 | DisableInterrupts ();\r | |
| 182 | \r | |
| 183 | InterruptState = FALSE;\r | |
| 184 | return EFI_SUCCESS;\r | |
| 185 | }\r | |
| 186 | \r | |
| 187 | \r | |
| 188 | /**\r | |
| 189 | Return the state of interrupts.\r | |
| 190 | \r | |
| 191 | @param This Protocol instance structure\r | |
| 192 | @param State Pointer to the CPU's current interrupt state\r | |
| 193 | \r | |
| 194 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
| 195 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
| 196 | \r | |
| 197 | **/\r | |
| 198 | EFI_STATUS\r | |
| 199 | EFIAPI\r | |
| 200 | CpuGetInterruptState (\r | |
| 201 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
| 202 | OUT BOOLEAN *State\r | |
| 203 | )\r | |
| 204 | {\r | |
| 205 | if (State == NULL) {\r | |
| 206 | return EFI_INVALID_PARAMETER;\r | |
| 207 | }\r | |
| 208 | \r | |
| 209 | *State = InterruptState;\r | |
| 210 | return EFI_SUCCESS;\r | |
| 211 | }\r | |
| 212 | \r | |
| 213 | \r | |
| 214 | /**\r | |
| 215 | Generates an INIT to the CPU.\r | |
| 216 | \r | |
| 217 | @param This Protocol instance structure\r | |
| 218 | @param InitType Type of CPU INIT to perform\r | |
| 219 | \r | |
| 220 | @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r | |
| 221 | seen.\r | |
| 222 | @retval EFI_DEVICE_ERROR If CPU INIT failed.\r | |
| 223 | @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r | |
| 224 | \r | |
| 225 | **/\r | |
| 226 | EFI_STATUS\r | |
| 227 | EFIAPI\r | |
| 228 | CpuInit (\r | |
| 229 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
| 230 | IN EFI_CPU_INIT_TYPE InitType\r | |
| 231 | )\r | |
| 232 | {\r | |
| 233 | return EFI_UNSUPPORTED;\r | |
| 234 | }\r | |
| 235 | \r | |
| 236 | \r | |
| 237 | /**\r | |
| 238 | Registers a function to be called from the CPU interrupt handler.\r | |
| 239 | \r | |
| 240 | @param This Protocol instance structure\r | |
| 241 | @param InterruptType Defines which interrupt to hook. IA-32\r | |
| 242 | valid range is 0x00 through 0xFF\r | |
| 243 | @param InterruptHandler A pointer to a function of type\r | |
| 244 | EFI_CPU_INTERRUPT_HANDLER that is called\r | |
| 245 | when a processor interrupt occurs. A null\r | |
| 246 | pointer is an error condition.\r | |
| 247 | \r | |
| 248 | @retval EFI_SUCCESS If handler installed or uninstalled.\r | |
| 249 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r | |
| 250 | for InterruptType was previously installed.\r | |
| 251 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r | |
| 252 | InterruptType was not previously installed.\r | |
| 253 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r | |
| 254 | is not supported.\r | |
| 255 | \r | |
| 256 | **/\r | |
| 257 | EFI_STATUS\r | |
| 258 | EFIAPI\r | |
| 259 | CpuRegisterInterruptHandler (\r | |
| 260 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
| 261 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
| 262 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
| 263 | )\r | |
| 264 | {\r | |
| e41aad15 | 265 | return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);\r |
| a47463f2 | 266 | }\r |
| 267 | \r | |
| 268 | \r | |
| 269 | /**\r | |
| 270 | Returns a timer value from one of the CPU's internal timers. There is no\r | |
| 271 | inherent time interval between ticks but is a function of the CPU frequency.\r | |
| 272 | \r | |
| 273 | @param This - Protocol instance structure.\r | |
| 274 | @param TimerIndex - Specifies which CPU timer is requested.\r | |
| 275 | @param TimerValue - Pointer to the returned timer value.\r | |
| 276 | @param TimerPeriod - A pointer to the amount of time that passes\r | |
| 277 | in femtoseconds (10-15) for each increment\r | |
| 278 | of TimerValue. If TimerValue does not\r | |
| 279 | increment at a predictable rate, then 0 is\r | |
| 280 | returned. The amount of time that has\r | |
| 281 | passed between two calls to GetTimerValue()\r | |
| 282 | can be calculated with the formula\r | |
| 283 | (TimerValue2 - TimerValue1) * TimerPeriod.\r | |
| 284 | This parameter is optional and may be NULL.\r | |
| 285 | \r | |
| 286 | @retval EFI_SUCCESS - If the CPU timer count was returned.\r | |
| 287 | @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r | |
| 288 | @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r | |
| 289 | @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r | |
| 290 | \r | |
| 291 | **/\r | |
| 292 | EFI_STATUS\r | |
| 293 | EFIAPI\r | |
| 294 | CpuGetTimerValue (\r | |
| 295 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
| 296 | IN UINT32 TimerIndex,\r | |
| 297 | OUT UINT64 *TimerValue,\r | |
| 298 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
| 299 | )\r | |
| 300 | {\r | |
| 7537f8c0 JF |
301 | UINT64 BeginValue;\r |
| 302 | UINT64 EndValue;\r | |
| 303 | \r | |
| a47463f2 | 304 | if (TimerValue == NULL) {\r |
| 305 | return EFI_INVALID_PARAMETER;\r | |
| 306 | }\r | |
| 307 | \r | |
| 308 | if (TimerIndex != 0) {\r | |
| 309 | return EFI_INVALID_PARAMETER;\r | |
| 310 | }\r | |
| 311 | \r | |
| 312 | *TimerValue = AsmReadTsc ();\r | |
| 313 | \r | |
| 314 | if (TimerPeriod != NULL) {\r | |
| 7537f8c0 JF |
315 | if (mTimerPeriod == 0) {\r |
| 316 | //\r | |
| 317 | // Read time stamp counter before and after delay of 100 microseconds\r | |
| 318 | //\r | |
| 319 | BeginValue = AsmReadTsc ();\r | |
| 320 | MicroSecondDelay (100);\r | |
| 321 | EndValue = AsmReadTsc ();\r | |
| a47463f2 | 322 | //\r |
| 7537f8c0 | 323 | // Calculate the actual frequency\r |
| a47463f2 | 324 | //\r |
| 7537f8c0 JF |
325 | mTimerPeriod = DivU64x64Remainder (\r |
| 326 | MultU64x32 (\r | |
| 327 | 1000 * 1000 * 1000,\r | |
| 328 | 100\r | |
| 329 | ),\r | |
| 330 | EndValue - BeginValue,\r | |
| 331 | NULL\r | |
| 332 | );\r | |
| 333 | }\r | |
| 334 | *TimerPeriod = mTimerPeriod;\r | |
| a47463f2 | 335 | }\r |
| 336 | \r | |
| 337 | return EFI_SUCCESS;\r | |
| 338 | }\r | |
| 339 | \r | |
| 0b9f0dd6 JF |
340 | /**\r |
| 341 | A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to\r | |
| 342 | EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.\r | |
| 343 | \r | |
| 344 | @param[in] Buffer Pointer to an MTRR_SETTINGS object, to be passed to\r | |
| 345 | MtrrSetAllMtrrs().\r | |
| 346 | **/\r | |
| 347 | VOID\r | |
| 348 | EFIAPI\r | |
| 349 | SetMtrrsFromBuffer (\r | |
| 350 | IN VOID *Buffer\r | |
| 351 | )\r | |
| 352 | {\r | |
| 353 | MtrrSetAllMtrrs (Buffer);\r | |
| 354 | }\r | |
| a47463f2 | 355 | \r |
| 356 | /**\r | |
| 4ec21e8b | 357 | Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.\r |
| 358 | \r | |
| 359 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
| 360 | Length from their current attributes to the attributes specified by Attributes.\r | |
| 361 | \r | |
| 362 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
| 363 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
| 364 | @param Length The size in bytes of the memory region.\r | |
| 365 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
| 366 | \r | |
| 367 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
| 368 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
| 369 | BaseAddress and Length cannot be modified.\r | |
| 370 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
| 371 | Attributes specified an illegal combination of attributes that\r | |
| 372 | cannot be set together.\r | |
| 373 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
| 374 | the memory resource range.\r | |
| 375 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
| 376 | resource range specified by BaseAddress and Length.\r | |
| 377 | The bit mask of attributes is not support for the memory resource\r | |
| 378 | range specified by BaseAddress and Length.\r | |
| a47463f2 | 379 | \r |
| 380 | **/\r | |
| 381 | EFI_STATUS\r | |
| 382 | EFIAPI\r | |
| 383 | CpuSetMemoryAttributes (\r | |
| 384 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
| 385 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
| 386 | IN UINT64 Length,\r | |
| 387 | IN UINT64 Attributes\r | |
| 388 | )\r | |
| 389 | {\r | |
| 390 | RETURN_STATUS Status;\r | |
| 391 | MTRR_MEMORY_CACHE_TYPE CacheType;\r | |
| 94941c88 LE |
392 | EFI_STATUS MpStatus;\r |
| 393 | EFI_MP_SERVICES_PROTOCOL *MpService;\r | |
| 394 | MTRR_SETTINGS MtrrSettings;\r | |
| 22292ed3 JY |
395 | UINT64 CacheAttributes;\r |
| 396 | UINT64 MemoryAttributes;\r | |
| 397 | MTRR_MEMORY_CACHE_TYPE CurrentCacheType;\r | |
| 947a573a | 398 | \r |
| a47463f2 | 399 | //\r |
| 400 | // If this function is called because GCD SetMemorySpaceAttributes () is called\r | |
| 401 | // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory\r | |
| 402 | // map with MTRR values. So there is no need to modify MTRRs, just return immediately\r | |
| 403 | // to avoid unnecessary computing.\r | |
| 404 | //\r | |
| 405 | if (mIsFlushingGCD) {\r | |
| 79aca636 SEHM |
406 | DEBUG((EFI_D_INFO, " Flushing GCD\n"));\r |
| 407 | return EFI_SUCCESS;\r | |
| 408 | }\r | |
| a47463f2 | 409 | \r |
| a47463f2 | 410 | \r |
| 22292ed3 JY |
411 | CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;\r |
| 412 | MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;\r | |
| a47463f2 | 413 | \r |
| 22292ed3 JY |
414 | if (Attributes != (CacheAttributes | MemoryAttributes)) {\r |
| 415 | return EFI_INVALID_PARAMETER;\r | |
| 416 | }\r | |
| a47463f2 | 417 | \r |
| 22292ed3 JY |
418 | if (CacheAttributes != 0) {\r |
| 419 | if (!IsMtrrSupported ()) {\r | |
| 420 | return EFI_UNSUPPORTED;\r | |
| 421 | }\r | |
| a47463f2 | 422 | \r |
| 22292ed3 JY |
423 | switch (CacheAttributes) {\r |
| 424 | case EFI_MEMORY_UC:\r | |
| 425 | CacheType = CacheUncacheable;\r | |
| 426 | break;\r | |
| a47463f2 | 427 | \r |
| 22292ed3 JY |
428 | case EFI_MEMORY_WC:\r |
| 429 | CacheType = CacheWriteCombining;\r | |
| 430 | break;\r | |
| 4ec21e8b | 431 | \r |
| 22292ed3 JY |
432 | case EFI_MEMORY_WT:\r |
| 433 | CacheType = CacheWriteThrough;\r | |
| 434 | break;\r | |
| a47463f2 | 435 | \r |
| 22292ed3 JY |
436 | case EFI_MEMORY_WP:\r |
| 437 | CacheType = CacheWriteProtected;\r | |
| 438 | break;\r | |
| 439 | \r | |
| 440 | case EFI_MEMORY_WB:\r | |
| 441 | CacheType = CacheWriteBack;\r | |
| 442 | break;\r | |
| 443 | \r | |
| 444 | default:\r | |
| 445 | return EFI_INVALID_PARAMETER;\r | |
| 446 | }\r | |
| 447 | CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);\r | |
| 448 | if (CurrentCacheType != CacheType) {\r | |
| 449 | //\r | |
| 450 | // call MTRR libary function\r | |
| 451 | //\r | |
| 452 | Status = MtrrSetMemoryAttribute (\r | |
| 453 | BaseAddress,\r | |
| 454 | Length,\r | |
| 455 | CacheType\r | |
| 456 | );\r | |
| 457 | \r | |
| 458 | if (!RETURN_ERROR (Status)) {\r | |
| 459 | MpStatus = gBS->LocateProtocol (\r | |
| 460 | &gEfiMpServiceProtocolGuid,\r | |
| 461 | NULL,\r | |
| 462 | (VOID **)&MpService\r | |
| 463 | );\r | |
| 464 | //\r | |
| 465 | // Synchronize the update with all APs\r | |
| 466 | //\r | |
| 467 | if (!EFI_ERROR (MpStatus)) {\r | |
| 468 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
| 469 | MpStatus = MpService->StartupAllAPs (\r | |
| 470 | MpService, // This\r | |
| 471 | SetMtrrsFromBuffer, // Procedure\r | |
| 472 | FALSE, // SingleThread\r | |
| 473 | NULL, // WaitEvent\r | |
| 474 | 0, // TimeoutInMicrosecsond\r | |
| 475 | &MtrrSettings, // ProcedureArgument\r | |
| 476 | NULL // FailedCpuList\r | |
| 477 | );\r | |
| 478 | ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);\r | |
| 479 | }\r | |
| 480 | }\r | |
| 481 | if (EFI_ERROR(Status)) {\r | |
| 482 | return Status;\r | |
| 483 | }\r | |
| 94941c88 LE |
484 | }\r |
| 485 | }\r | |
| 22292ed3 JY |
486 | \r |
| 487 | //\r | |
| 488 | // Set memory attribute by page table\r | |
| 489 | //\r | |
| 490 | return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, AllocatePages);\r | |
| a47463f2 | 491 | }\r |
| 492 | \r | |
| 493 | /**\r | |
| 494 | Initializes the valid bits mask and valid address mask for MTRRs.\r | |
| 495 | \r | |
| 496 | This function initializes the valid bits mask and valid address mask for MTRRs.\r | |
| 497 | \r | |
| 498 | **/\r | |
| 499 | VOID\r | |
| 500 | InitializeMtrrMask (\r | |
| 501 | VOID\r | |
| 502 | )\r | |
| 503 | {\r | |
| 504 | UINT32 RegEax;\r | |
| 505 | UINT8 PhysicalAddressBits;\r | |
| 506 | \r | |
| 507 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
| 508 | \r | |
| 509 | if (RegEax >= 0x80000008) {\r | |
| 510 | AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r | |
| 511 | \r | |
| 512 | PhysicalAddressBits = (UINT8) RegEax;\r | |
| 513 | \r | |
| 514 | mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r | |
| 515 | mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r | |
| 516 | } else {\r | |
| 517 | mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r | |
| 518 | mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r | |
| 519 | }\r | |
| 520 | }\r | |
| 521 | \r | |
| 522 | /**\r | |
| 430fbbe0 | 523 | Gets GCD Mem Space type from MTRR Type.\r |
| a47463f2 | 524 | \r |
| 430fbbe0 | 525 | This function gets GCD Mem Space type from MTRR Type.\r |
| a47463f2 | 526 | \r |
| 430fbbe0 | 527 | @param MtrrAttributes MTRR memory type\r |
| a47463f2 | 528 | \r |
| 529 | @return GCD Mem Space type\r | |
| 530 | \r | |
| 531 | **/\r | |
| 532 | UINT64\r | |
| 533 | GetMemorySpaceAttributeFromMtrrType (\r | |
| 2c4b1bdc | 534 | IN UINT8 MtrrAttributes\r |
| a47463f2 | 535 | )\r |
| 536 | {\r | |
| 537 | switch (MtrrAttributes) {\r | |
| 538 | case MTRR_CACHE_UNCACHEABLE:\r | |
| 539 | return EFI_MEMORY_UC;\r | |
| 540 | case MTRR_CACHE_WRITE_COMBINING:\r | |
| 541 | return EFI_MEMORY_WC;\r | |
| 542 | case MTRR_CACHE_WRITE_THROUGH:\r | |
| 543 | return EFI_MEMORY_WT;\r | |
| 544 | case MTRR_CACHE_WRITE_PROTECTED:\r | |
| 545 | return EFI_MEMORY_WP;\r | |
| 546 | case MTRR_CACHE_WRITE_BACK:\r | |
| 547 | return EFI_MEMORY_WB;\r | |
| 548 | default:\r | |
| 549 | return 0;\r | |
| 550 | }\r | |
| 551 | }\r | |
| 552 | \r | |
| 553 | /**\r | |
| 554 | Searches memory descriptors covered by given memory range.\r | |
| 555 | \r | |
| 556 | This function searches into the Gcd Memory Space for descriptors\r | |
| 557 | (from StartIndex to EndIndex) that contains the memory range\r | |
| 558 | specified by BaseAddress and Length.\r | |
| 559 | \r | |
| 560 | @param MemorySpaceMap Gcd Memory Space Map as array.\r | |
| 561 | @param NumberOfDescriptors Number of descriptors in map.\r | |
| 562 | @param BaseAddress BaseAddress for the requested range.\r | |
| 563 | @param Length Length for the requested range.\r | |
| 564 | @param StartIndex Start index into the Gcd Memory Space Map.\r | |
| 565 | @param EndIndex End index into the Gcd Memory Space Map.\r | |
| 566 | \r | |
| 567 | @retval EFI_SUCCESS Search successfully.\r | |
| 568 | @retval EFI_NOT_FOUND The requested descriptors does not exist.\r | |
| 569 | \r | |
| 570 | **/\r | |
| 571 | EFI_STATUS\r | |
| 572 | SearchGcdMemorySpaces (\r | |
| 573 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
| 574 | IN UINTN NumberOfDescriptors,\r | |
| 575 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
| 576 | IN UINT64 Length,\r | |
| 577 | OUT UINTN *StartIndex,\r | |
| 578 | OUT UINTN *EndIndex\r | |
| 579 | )\r | |
| 580 | {\r | |
| 581 | UINTN Index;\r | |
| 582 | \r | |
| 583 | *StartIndex = 0;\r | |
| 584 | *EndIndex = 0;\r | |
| 585 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
| 586 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r | |
| 587 | BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
| 588 | *StartIndex = Index;\r | |
| 589 | }\r | |
| 590 | if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r | |
| 591 | BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
| 592 | *EndIndex = Index;\r | |
| 593 | return EFI_SUCCESS;\r | |
| 594 | }\r | |
| 595 | }\r | |
| 596 | return EFI_NOT_FOUND;\r | |
| 597 | }\r | |
| 598 | \r | |
| 599 | /**\r | |
| 600 | Sets the attributes for a specified range in Gcd Memory Space Map.\r | |
| 601 | \r | |
| 602 | This function sets the attributes for a specified range in\r | |
| 603 | Gcd Memory Space Map.\r | |
| 604 | \r | |
| 605 | @param MemorySpaceMap Gcd Memory Space Map as array\r | |
| 606 | @param NumberOfDescriptors Number of descriptors in map\r | |
| 607 | @param BaseAddress BaseAddress for the range\r | |
| 608 | @param Length Length for the range\r | |
| 609 | @param Attributes Attributes to set\r | |
| 610 | \r | |
| 611 | @retval EFI_SUCCESS Memory attributes set successfully\r | |
| 612 | @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r | |
| 613 | \r | |
| 614 | **/\r | |
| 615 | EFI_STATUS\r | |
| 616 | SetGcdMemorySpaceAttributes (\r | |
| 617 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
| 618 | IN UINTN NumberOfDescriptors,\r | |
| 619 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
| 620 | IN UINT64 Length,\r | |
| 621 | IN UINT64 Attributes\r | |
| 622 | )\r | |
| 623 | {\r | |
| 624 | EFI_STATUS Status;\r | |
| 625 | UINTN Index;\r | |
| 626 | UINTN StartIndex;\r | |
| 627 | UINTN EndIndex;\r | |
| 628 | EFI_PHYSICAL_ADDRESS RegionStart;\r | |
| 629 | UINT64 RegionLength;\r | |
| 630 | \r | |
| 631 | //\r | |
| 632 | // Get all memory descriptors covered by the memory range\r | |
| 633 | //\r | |
| 634 | Status = SearchGcdMemorySpaces (\r | |
| 635 | MemorySpaceMap,\r | |
| 636 | NumberOfDescriptors,\r | |
| 637 | BaseAddress,\r | |
| 638 | Length,\r | |
| 639 | &StartIndex,\r | |
| 640 | &EndIndex\r | |
| 641 | );\r | |
| 642 | if (EFI_ERROR (Status)) {\r | |
| 643 | return Status;\r | |
| 644 | }\r | |
| 645 | \r | |
| 646 | //\r | |
| 647 | // Go through all related descriptors and set attributes accordingly\r | |
| 648 | //\r | |
| 649 | for (Index = StartIndex; Index <= EndIndex; Index++) {\r | |
| 650 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
| 651 | continue;\r | |
| 652 | }\r | |
| 653 | //\r | |
| 654 | // Calculate the start and end address of the overlapping range\r | |
| 655 | //\r | |
| 656 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r | |
| 657 | RegionStart = BaseAddress;\r | |
| 658 | } else {\r | |
| 659 | RegionStart = MemorySpaceMap[Index].BaseAddress;\r | |
| 660 | }\r | |
| 661 | if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
| 662 | RegionLength = BaseAddress + Length - RegionStart;\r | |
| 663 | } else {\r | |
| 664 | RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r | |
| 665 | }\r | |
| 666 | //\r | |
| 667 | // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r | |
| 668 | //\r | |
| 669 | gDS->SetMemorySpaceAttributes (\r | |
| 670 | RegionStart,\r | |
| 671 | RegionLength,\r | |
| 672 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r | |
| 673 | );\r | |
| 674 | }\r | |
| 675 | \r | |
| 676 | return EFI_SUCCESS;\r | |
| 677 | }\r | |
| 678 | \r | |
| 679 | \r | |
| 680 | /**\r | |
| 681 | Refreshes the GCD Memory Space attributes according to MTRRs.\r | |
| 682 | \r | |
| 683 | This function refreshes the GCD Memory Space attributes according to MTRRs.\r | |
| 684 | \r | |
| 685 | **/\r | |
| 686 | VOID\r | |
| 687 | RefreshGcdMemoryAttributes (\r | |
| 688 | VOID\r | |
| 689 | )\r | |
| 690 | {\r | |
| 691 | EFI_STATUS Status;\r | |
| 692 | UINTN Index;\r | |
| 693 | UINTN SubIndex;\r | |
| 694 | UINT64 RegValue;\r | |
| 695 | EFI_PHYSICAL_ADDRESS BaseAddress;\r | |
| 696 | UINT64 Length;\r | |
| 697 | UINT64 Attributes;\r | |
| 698 | UINT64 CurrentAttributes;\r | |
| 2c4b1bdc | 699 | UINT8 MtrrType;\r |
| a47463f2 | 700 | UINTN NumberOfDescriptors;\r |
| 701 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
| 702 | UINT64 DefaultAttributes;\r | |
| 6640eb36 | 703 | VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r |
| a47463f2 | 704 | MTRR_FIXED_SETTINGS MtrrFixedSettings;\r |
| 3b9be416 | 705 | UINT32 FirmwareVariableMtrrCount;\r |
| 2c4b1bdc | 706 | UINT8 DefaultMemoryType;\r |
| 3b9be416 | 707 | \r |
| 947a573a | 708 | if (!IsMtrrSupported ()) {\r |
| 709 | return;\r | |
| 710 | }\r | |
| 711 | \r | |
| 3b9be416 | 712 | FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r |
| 5bdfa4e5 | 713 | ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r |
| a47463f2 | 714 | \r |
| 91ec7824 | 715 | mIsFlushingGCD = TRUE;\r |
| a47463f2 | 716 | MemorySpaceMap = NULL;\r |
| 717 | \r | |
| 718 | //\r | |
| 719 | // Initialize the valid bits mask and valid address mask for MTRRs\r | |
| 720 | //\r | |
| 721 | InitializeMtrrMask ();\r | |
| 722 | \r | |
| 723 | //\r | |
| 724 | // Get the memory attribute of variable MTRRs\r | |
| 725 | //\r | |
| 726 | MtrrGetMemoryAttributeInVariableMtrr (\r | |
| 727 | mValidMtrrBitsMask,\r | |
| 728 | mValidMtrrAddressMask,\r | |
| 729 | VariableMtrr\r | |
| 730 | );\r | |
| 731 | \r | |
| 732 | //\r | |
| 733 | // Get the memory space map from GCD\r | |
| 734 | //\r | |
| 735 | Status = gDS->GetMemorySpaceMap (\r | |
| 736 | &NumberOfDescriptors,\r | |
| 737 | &MemorySpaceMap\r | |
| 738 | );\r | |
| 739 | ASSERT_EFI_ERROR (Status);\r | |
| 740 | \r | |
| 2c4b1bdc | 741 | DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();\r |
| 91ec7824 | 742 | DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);\r |
| a47463f2 | 743 | \r |
| 744 | //\r | |
| 745 | // Set default attributes to all spaces.\r | |
| 746 | //\r | |
| 747 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
| 748 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
| 749 | continue;\r | |
| 750 | }\r | |
| 751 | gDS->SetMemorySpaceAttributes (\r | |
| 752 | MemorySpaceMap[Index].BaseAddress,\r | |
| 753 | MemorySpaceMap[Index].Length,\r | |
| 754 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |\r | |
| 755 | (MemorySpaceMap[Index].Capabilities & DefaultAttributes)\r | |
| 756 | );\r | |
| 757 | }\r | |
| 758 | \r | |
| 759 | //\r | |
| 760 | // Go for variable MTRRs with WB attribute\r | |
| 761 | //\r | |
| 3b9be416 | 762 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r |
| a47463f2 | 763 | if (VariableMtrr[Index].Valid &&\r |
| 764 | VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {\r | |
| 765 | SetGcdMemorySpaceAttributes (\r | |
| 766 | MemorySpaceMap,\r | |
| 767 | NumberOfDescriptors,\r | |
| 768 | VariableMtrr[Index].BaseAddress,\r | |
| 769 | VariableMtrr[Index].Length,\r | |
| 770 | EFI_MEMORY_WB\r | |
| 771 | );\r | |
| 772 | }\r | |
| 773 | }\r | |
| 91ec7824 | 774 | \r |
| a47463f2 | 775 | //\r |
| 91ec7824 | 776 | // Go for variable MTRRs with the attribute except for WB and UC attributes\r |
| a47463f2 | 777 | //\r |
| 3b9be416 | 778 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r |
| d4605c23 | 779 | if (VariableMtrr[Index].Valid &&\r |
| 91ec7824 | 780 | VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&\r |
| 781 | VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {\r | |
| 2c4b1bdc | 782 | Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);\r |
| a47463f2 | 783 | SetGcdMemorySpaceAttributes (\r |
| 784 | MemorySpaceMap,\r | |
| 785 | NumberOfDescriptors,\r | |
| 786 | VariableMtrr[Index].BaseAddress,\r | |
| 787 | VariableMtrr[Index].Length,\r | |
| 788 | Attributes\r | |
| 789 | );\r | |
| 790 | }\r | |
| 791 | }\r | |
| 792 | \r | |
| 91ec7824 | 793 | //\r |
| 794 | // Go for variable MTRRs with UC attribute\r | |
| 795 | //\r | |
| 796 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r | |
| 797 | if (VariableMtrr[Index].Valid &&\r | |
| 798 | VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {\r | |
| 799 | SetGcdMemorySpaceAttributes (\r | |
| 800 | MemorySpaceMap,\r | |
| 801 | NumberOfDescriptors,\r | |
| 802 | VariableMtrr[Index].BaseAddress,\r | |
| 803 | VariableMtrr[Index].Length,\r | |
| 804 | EFI_MEMORY_UC\r | |
| 805 | );\r | |
| 806 | }\r | |
| 807 | }\r | |
| 808 | \r | |
| a47463f2 | 809 | //\r |
| 810 | // Go for fixed MTRRs\r | |
| 811 | //\r | |
| 812 | Attributes = 0;\r | |
| 813 | BaseAddress = 0;\r | |
| 814 | Length = 0;\r | |
| 815 | MtrrGetFixedMtrr (&MtrrFixedSettings);\r | |
| 816 | for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r | |
| 817 | RegValue = MtrrFixedSettings.Mtrr[Index];\r | |
| 818 | //\r | |
| 819 | // Check for continuous fixed MTRR sections\r | |
| 820 | //\r | |
| 821 | for (SubIndex = 0; SubIndex < 8; SubIndex++) {\r | |
| 2c4b1bdc | 822 | MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);\r |
| a47463f2 | 823 | CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);\r |
| 824 | if (Length == 0) {\r | |
| 825 | //\r | |
| 826 | // A new MTRR attribute begins\r | |
| 827 | //\r | |
| 828 | Attributes = CurrentAttributes;\r | |
| 829 | } else {\r | |
| 830 | //\r | |
| 831 | // If fixed MTRR attribute changed, then set memory attribute for previous atrribute\r | |
| 832 | //\r | |
| 833 | if (CurrentAttributes != Attributes) {\r | |
| 834 | SetGcdMemorySpaceAttributes (\r | |
| 835 | MemorySpaceMap,\r | |
| 836 | NumberOfDescriptors,\r | |
| 837 | BaseAddress,\r | |
| 838 | Length,\r | |
| 839 | Attributes\r | |
| 840 | );\r | |
| 841 | BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;\r | |
| 842 | Length = 0;\r | |
| 843 | Attributes = CurrentAttributes;\r | |
| 844 | }\r | |
| 845 | }\r | |
| 846 | Length += mFixedMtrrTable[Index].Length;\r | |
| 847 | }\r | |
| 848 | }\r | |
| 849 | //\r | |
| 850 | // Handle the last fixed MTRR region\r | |
| 851 | //\r | |
| 852 | SetGcdMemorySpaceAttributes (\r | |
| 853 | MemorySpaceMap,\r | |
| 854 | NumberOfDescriptors,\r | |
| 855 | BaseAddress,\r | |
| 856 | Length,\r | |
| 857 | Attributes\r | |
| 858 | );\r | |
| 859 | \r | |
| 860 | //\r | |
| 861 | // Free memory space map allocated by GCD service GetMemorySpaceMap ()\r | |
| 862 | //\r | |
| 863 | if (MemorySpaceMap != NULL) {\r | |
| 864 | FreePool (MemorySpaceMap);\r | |
| 865 | }\r | |
| 866 | \r | |
| 867 | mIsFlushingGCD = FALSE;\r | |
| 868 | }\r | |
| 869 | \r | |
| a47463f2 | 870 | /**\r |
| 871 | Initialize Interrupt Descriptor Table for interrupt handling.\r | |
| 872 | \r | |
| 873 | **/\r | |
| a47463f2 | 874 | VOID\r |
| 875 | InitInterruptDescriptorTable (\r | |
| 876 | VOID\r | |
| 877 | )\r | |
| 878 | {\r | |
| e41aad15 JF |
879 | EFI_STATUS Status;\r |
| 880 | EFI_VECTOR_HANDOFF_INFO *VectorInfoList;\r | |
| 881 | EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r | |
| 882 | \r | |
| 883 | VectorInfo = NULL;\r | |
| 884 | Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);\r | |
| 885 | if (Status == EFI_SUCCESS && VectorInfoList != NULL) {\r | |
| 886 | VectorInfo = VectorInfoList;\r | |
| a47463f2 | 887 | }\r |
| e41aad15 JF |
888 | Status = InitializeCpuInterruptHandlers (VectorInfo);\r |
| 889 | ASSERT_EFI_ERROR (Status);\r | |
| a47463f2 | 890 | }\r |
| 891 | \r | |
| 892 | \r | |
| 32394027 | 893 | /**\r |
| 894 | Callback function for idle events.\r | |
| d4605c23 | 895 | \r |
| 32394027 | 896 | @param Event Event whose notification function is being invoked.\r |
| 897 | @param Context The pointer to the notification function's context,\r | |
| 898 | which is implementation-dependent.\r | |
| 899 | \r | |
| 900 | **/\r | |
| 901 | VOID\r | |
| 902 | EFIAPI\r | |
| 903 | IdleLoopEventCallback (\r | |
| 904 | IN EFI_EVENT Event,\r | |
| 905 | IN VOID *Context\r | |
| 906 | )\r | |
| 907 | {\r | |
| 908 | CpuSleep ();\r | |
| 909 | }\r | |
| 910 | \r | |
| 410590f1 JF |
911 | /**\r |
| 912 | Ensure the compatibility of a memory space descriptor with the MMIO aperture.\r | |
| 913 | \r | |
| 914 | The memory space descriptor can come from the GCD memory space map, or it can\r | |
| 915 | represent a gap between two neighboring memory space descriptors. In the\r | |
| 916 | latter case, the GcdMemoryType field is expected to be\r | |
| 917 | EfiGcdMemoryTypeNonExistent.\r | |
| 918 | \r | |
| 919 | If the memory space descriptor already has type\r | |
| 920 | EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the\r | |
| 921 | required capabilities, then no action is taken -- it is by definition\r | |
| 922 | compatible with the aperture.\r | |
| 923 | \r | |
| 924 | Otherwise, the intersection of the memory space descriptor is calculated with\r | |
| 925 | the aperture. If the intersection is the empty set (no overlap), no action is\r | |
| 926 | taken; the memory space descriptor is compatible with the aperture.\r | |
| 927 | \r | |
| 928 | Otherwise, the type of the descriptor is investigated again. If the type is\r | |
| 929 | EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with\r | |
| 930 | such a type), then an attempt is made to add the intersection as MMIO space\r | |
| 931 | to the GCD memory space map, with the specified capabilities. This ensures\r | |
| 932 | continuity for the aperture, and the descriptor is deemed compatible with the\r | |
| 933 | aperture.\r | |
| 934 | \r | |
| 935 | Otherwise, the memory space descriptor is incompatible with the MMIO\r | |
| 936 | aperture.\r | |
| 937 | \r | |
| 938 | @param[in] Base Base address of the aperture.\r | |
| 939 | @param[in] Length Length of the aperture.\r | |
| 940 | @param[in] Capabilities Capabilities required by the aperture.\r | |
| 941 | @param[in] Descriptor The descriptor to ensure compatibility with the\r | |
| 942 | aperture for.\r | |
| 943 | \r | |
| 944 | @retval EFI_SUCCESS The descriptor is compatible. The GCD memory\r | |
| 945 | space map may have been updated, for\r | |
| 946 | continuity within the aperture.\r | |
| 947 | @retval EFI_INVALID_PARAMETER The descriptor is incompatible.\r | |
| 948 | @return Error codes from gDS->AddMemorySpace().\r | |
| 949 | **/\r | |
| 950 | EFI_STATUS\r | |
| 951 | IntersectMemoryDescriptor (\r | |
| 952 | IN UINT64 Base,\r | |
| 953 | IN UINT64 Length,\r | |
| 954 | IN UINT64 Capabilities,\r | |
| 955 | IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor\r | |
| 956 | )\r | |
| 957 | {\r | |
| 958 | UINT64 IntersectionBase;\r | |
| 959 | UINT64 IntersectionEnd;\r | |
| 960 | EFI_STATUS Status;\r | |
| 961 | \r | |
| 962 | if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&\r | |
| 963 | (Descriptor->Capabilities & Capabilities) == Capabilities) {\r | |
| 964 | return EFI_SUCCESS;\r | |
| 965 | }\r | |
| 966 | \r | |
| 967 | IntersectionBase = MAX (Base, Descriptor->BaseAddress);\r | |
| 968 | IntersectionEnd = MIN (Base + Length,\r | |
| 969 | Descriptor->BaseAddress + Descriptor->Length);\r | |
| 970 | if (IntersectionBase >= IntersectionEnd) {\r | |
| 971 | //\r | |
| 972 | // The descriptor and the aperture don't overlap.\r | |
| 973 | //\r | |
| 974 | return EFI_SUCCESS;\r | |
| 975 | }\r | |
| 976 | \r | |
| 977 | if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
| 978 | Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,\r | |
| 979 | IntersectionBase, IntersectionEnd - IntersectionBase,\r | |
| 980 | Capabilities);\r | |
| 981 | \r | |
| 982 | DEBUG ((EFI_ERROR (Status) ? EFI_D_ERROR : EFI_D_VERBOSE,\r | |
| 983 | "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,\r | |
| 984 | IntersectionBase, IntersectionEnd, Status));\r | |
| 985 | return Status;\r | |
| 986 | }\r | |
| 987 | \r | |
| 988 | DEBUG ((EFI_D_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r | |
| 989 | "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,\r | |
| 990 | Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,\r | |
| 991 | (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,\r | |
| 992 | Base, Base + Length, Capabilities));\r | |
| 993 | return EFI_INVALID_PARAMETER;\r | |
| 994 | }\r | |
| 995 | \r | |
| 996 | /**\r | |
| 997 | Add MMIO space to GCD.\r | |
| 998 | The routine checks the GCD database and only adds those which are\r | |
| 999 | not added in the specified range to GCD.\r | |
| 1000 | \r | |
| 1001 | @param Base Base address of the MMIO space.\r | |
| 1002 | @param Length Length of the MMIO space.\r | |
| 1003 | @param Capabilities Capabilities of the MMIO space.\r | |
| 1004 | \r | |
| 1005 | @retval EFI_SUCCES The MMIO space was added successfully.\r | |
| 1006 | **/\r | |
| 1007 | EFI_STATUS\r | |
| 1008 | AddMemoryMappedIoSpace (\r | |
| 1009 | IN UINT64 Base,\r | |
| 1010 | IN UINT64 Length,\r | |
| 1011 | IN UINT64 Capabilities\r | |
| 1012 | )\r | |
| 1013 | {\r | |
| 1014 | EFI_STATUS Status;\r | |
| 1015 | UINTN Index;\r | |
| 1016 | UINTN NumberOfDescriptors;\r | |
| 1017 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
| 1018 | \r | |
| 1019 | Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r | |
| 1020 | if (EFI_ERROR (Status)) {\r | |
| 1021 | DEBUG ((EFI_D_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",\r | |
| 1022 | gEfiCallerBaseName, __FUNCTION__, Status));\r | |
| 1023 | return Status;\r | |
| 1024 | }\r | |
| 1025 | \r | |
| 1026 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
| 1027 | Status = IntersectMemoryDescriptor (Base, Length, Capabilities,\r | |
| 1028 | &MemorySpaceMap[Index]);\r | |
| 1029 | if (EFI_ERROR (Status)) {\r | |
| 1030 | goto FreeMemorySpaceMap;\r | |
| 1031 | }\r | |
| 1032 | }\r | |
| 1033 | \r | |
| 1034 | DEBUG_CODE (\r | |
| 1035 | //\r | |
| 1036 | // Make sure there are adjacent descriptors covering [Base, Base + Length).\r | |
| 1037 | // It is possible that they have not been merged; merging can be prevented\r | |
| 1038 | // by allocation and different capabilities.\r | |
| 1039 | //\r | |
| 1040 | UINT64 CheckBase;\r | |
| 1041 | EFI_STATUS CheckStatus;\r | |
| 1042 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r | |
| 1043 | \r | |
| 1044 | for (CheckBase = Base;\r | |
| 1045 | CheckBase < Base + Length;\r | |
| 1046 | CheckBase = Descriptor.BaseAddress + Descriptor.Length) {\r | |
| 1047 | CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);\r | |
| 1048 | ASSERT_EFI_ERROR (CheckStatus);\r | |
| 1049 | ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);\r | |
| 1050 | ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);\r | |
| 1051 | }\r | |
| 1052 | );\r | |
| 1053 | \r | |
| 1054 | FreeMemorySpaceMap:\r | |
| 1055 | FreePool (MemorySpaceMap);\r | |
| 1056 | \r | |
| 1057 | return Status;\r | |
| 1058 | }\r | |
| 32394027 | 1059 | \r |
| 14f92ded JF |
1060 | /**\r |
| 1061 | Add and allocate CPU local APIC memory mapped space. \r | |
| 1062 | \r | |
| 1063 | @param[in]ImageHandle Image handle this driver.\r | |
| 1064 | \r | |
| 1065 | **/\r | |
| 1066 | VOID\r | |
| 1067 | AddLocalApicMemorySpace (\r | |
| 1068 | IN EFI_HANDLE ImageHandle\r | |
| 1069 | )\r | |
| 1070 | {\r | |
| 1071 | EFI_STATUS Status;\r | |
| 1072 | EFI_PHYSICAL_ADDRESS BaseAddress;\r | |
| 1073 | \r | |
| 1074 | BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();\r | |
| 1075 | Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);\r | |
| 1076 | ASSERT_EFI_ERROR (Status);\r | |
| 1077 | \r | |
| 1078 | Status = gDS->AllocateMemorySpace (\r | |
| 1079 | EfiGcdAllocateAddress,\r | |
| 1080 | EfiGcdMemoryTypeMemoryMappedIo,\r | |
| 1081 | 0,\r | |
| 1082 | SIZE_4KB,\r | |
| 1083 | &BaseAddress,\r | |
| 1084 | ImageHandle,\r | |
| 1085 | NULL\r | |
| 1086 | );\r | |
| 1087 | ASSERT_EFI_ERROR (Status);\r | |
| 1088 | }\r | |
| 1089 | \r | |
| a47463f2 | 1090 | /**\r |
| 1091 | Initialize the state information for the CPU Architectural Protocol.\r | |
| 1092 | \r | |
| 1093 | @param ImageHandle Image handle this driver.\r | |
| 1094 | @param SystemTable Pointer to the System Table.\r | |
| 1095 | \r | |
| 1096 | @retval EFI_SUCCESS Thread can be successfully created\r | |
| 1097 | @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r | |
| 1098 | @retval EFI_DEVICE_ERROR Cannot create the thread\r | |
| 1099 | \r | |
| 1100 | **/\r | |
| 1101 | EFI_STATUS\r | |
| 1102 | EFIAPI\r | |
| 1103 | InitializeCpu (\r | |
| 1104 | IN EFI_HANDLE ImageHandle,\r | |
| 1105 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
| 1106 | )\r | |
| 1107 | {\r | |
| 1108 | EFI_STATUS Status;\r | |
| 32394027 | 1109 | EFI_EVENT IdleLoopEvent;\r |
| 22292ed3 JY |
1110 | \r |
| 1111 | InitializePageTableLib();\r | |
| a47463f2 | 1112 | \r |
| 661cab5d | 1113 | InitializeFloatingPointUnits ();\r |
| 1114 | \r | |
| a47463f2 | 1115 | //\r |
| 1116 | // Make sure interrupts are disabled\r | |
| 1117 | //\r | |
| 1118 | DisableInterrupts ();\r | |
| 1119 | \r | |
| 1120 | //\r | |
| 1121 | // Init GDT for DXE\r | |
| 1122 | //\r | |
| 1123 | InitGlobalDescriptorTable ();\r | |
| 1124 | \r | |
| 1125 | //\r | |
| 1126 | // Setup IDT pointer, IDT and interrupt entry points\r | |
| 1127 | //\r | |
| 1128 | InitInterruptDescriptorTable ();\r | |
| 1129 | \r | |
| d4605c23 EB |
1130 | //\r |
| 1131 | // Enable the local APIC for Virtual Wire Mode.\r | |
| 1132 | //\r | |
| 1133 | ProgramVirtualWireMode ();\r | |
| 1134 | \r | |
| a47463f2 | 1135 | //\r |
| 1136 | // Install CPU Architectural Protocol\r | |
| 1137 | //\r | |
| 1138 | Status = gBS->InstallMultipleProtocolInterfaces (\r | |
| 1139 | &mCpuHandle,\r | |
| 1140 | &gEfiCpuArchProtocolGuid, &gCpu,\r | |
| 1141 | NULL\r | |
| 1142 | );\r | |
| 1143 | ASSERT_EFI_ERROR (Status);\r | |
| 1144 | \r | |
| 1145 | //\r | |
| 1146 | // Refresh GCD memory space map according to MTRR value.\r | |
| 1147 | //\r | |
| 1148 | RefreshGcdMemoryAttributes ();\r | |
| 1149 | \r | |
| 14f92ded JF |
1150 | //\r |
| 1151 | // Add and allocate local APIC memory mapped space\r | |
| 1152 | //\r | |
| 1153 | AddLocalApicMemorySpace (ImageHandle);\r | |
| 1154 | \r | |
| 32394027 | 1155 | //\r |
| 1156 | // Setup a callback for idle events\r | |
| 1157 | //\r | |
| 1158 | Status = gBS->CreateEventEx (\r | |
| 1159 | EVT_NOTIFY_SIGNAL,\r | |
| 1160 | TPL_NOTIFY,\r | |
| 1161 | IdleLoopEventCallback,\r | |
| 1162 | NULL,\r | |
| 1163 | &gIdleLoopEventGuid,\r | |
| 1164 | &IdleLoopEvent\r | |
| 1165 | );\r | |
| 1166 | ASSERT_EFI_ERROR (Status);\r | |
| 1167 | \r | |
| 6022e28c JJ |
1168 | InitializeMpSupport ();\r |
| 1169 | \r | |
| a47463f2 | 1170 | return Status;\r |
| 1171 | }\r | |
| 1172 | \r |