Add DEBUG() macros for DEBUG_CACHE to MTRR Library show all changes memory caches...
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuDxe.c
CommitLineData
a47463f2 1/** @file\r
2 CPU DXE Module.\r
3\r
f877f300 4 Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>\r
01a1c0fc 5 This program and the accompanying materials\r
a47463f2 6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#include "CpuDxe.h"\r
16\r
17//\r
18// Global Variables\r
19//\r
20IA32_IDT_GATE_DESCRIPTOR gIdtTable[INTERRUPT_VECTOR_NUMBER] = { 0 };\r
21\r
22EFI_CPU_INTERRUPT_HANDLER ExternalVectorTable[0x100];\r
23BOOLEAN InterruptState = FALSE;\r
24EFI_HANDLE mCpuHandle = NULL;\r
25BOOLEAN mIsFlushingGCD;\r
26UINT8 mDefaultMemoryType = MTRR_CACHE_WRITE_BACK;\r
27UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
28UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r
29\r
30FIXED_MTRR mFixedMtrrTable[] = {\r
31 {\r
32 MTRR_LIB_IA32_MTRR_FIX64K_00000,\r
33 0,\r
34 0x10000\r
35 },\r
36 {\r
37 MTRR_LIB_IA32_MTRR_FIX16K_80000,\r
38 0x80000,\r
39 0x4000\r
40 },\r
41 {\r
42 MTRR_LIB_IA32_MTRR_FIX16K_A0000,\r
43 0xA0000,\r
44 0x4000\r
45 },\r
46 {\r
47 MTRR_LIB_IA32_MTRR_FIX4K_C0000,\r
48 0xC0000,\r
49 0x1000\r
50 },\r
51 {\r
52 MTRR_LIB_IA32_MTRR_FIX4K_C8000,\r
53 0xC8000,\r
54 0x1000\r
55 },\r
56 {\r
57 MTRR_LIB_IA32_MTRR_FIX4K_D0000,\r
58 0xD0000,\r
59 0x1000\r
60 },\r
61 {\r
62 MTRR_LIB_IA32_MTRR_FIX4K_D8000,\r
63 0xD8000,\r
64 0x1000\r
65 },\r
66 {\r
67 MTRR_LIB_IA32_MTRR_FIX4K_E0000,\r
68 0xE0000,\r
69 0x1000\r
70 },\r
71 {\r
72 MTRR_LIB_IA32_MTRR_FIX4K_E8000,\r
73 0xE8000,\r
74 0x1000\r
75 },\r
76 {\r
77 MTRR_LIB_IA32_MTRR_FIX4K_F0000,\r
78 0xF0000,\r
79 0x1000\r
80 },\r
81 {\r
82 MTRR_LIB_IA32_MTRR_FIX4K_F8000,\r
83 0xF8000,\r
84 0x1000\r
85 },\r
86};\r
87\r
88\r
89EFI_CPU_ARCH_PROTOCOL gCpu = {\r
90 CpuFlushCpuDataCache,\r
91 CpuEnableInterrupt,\r
92 CpuDisableInterrupt,\r
93 CpuGetInterruptState,\r
94 CpuInit,\r
95 CpuRegisterInterruptHandler,\r
96 CpuGetTimerValue,\r
97 CpuSetMemoryAttributes,\r
98 1, // NumberOfTimers\r
99 4 // DmaBufferAlignment\r
100};\r
101\r
102//\r
103// Error code flag indicating whether or not an error code will be\r
104// pushed on the stack if an exception occurs.\r
105//\r
106// 1 means an error code will be pushed, otherwise 0\r
107//\r
108// bit 0 - exception 0\r
109// bit 1 - exception 1\r
110// etc.\r
111//\r
112UINT32 mErrorCodeFlag = 0x00027d00;\r
113\r
557b970a 114//\r
115// Local function prototypes\r
116//\r
1e51d595
ED
117\r
118/**\r
119 Set Interrupt Descriptor Table Handler Address.\r
120\r
121 @param Index The Index of the interrupt descriptor table handle.\r
122 @param Handler Handler address.\r
123\r
124**/\r
557b970a 125VOID\r
126SetInterruptDescriptorTableHandlerAddress (\r
127 IN UINTN Index,\r
128 IN VOID *Handler OPTIONAL\r
129 );\r
130\r
a47463f2 131//\r
132// CPU Arch Protocol Functions\r
133//\r
134\r
135\r
136/**\r
137 Common exception handler.\r
138\r
139 @param InterruptType Exception type\r
140 @param SystemContext EFI_SYSTEM_CONTEXT\r
141\r
142**/\r
143VOID\r
144EFIAPI\r
145CommonExceptionHandler (\r
146 IN EFI_EXCEPTION_TYPE InterruptType,\r
147 IN EFI_SYSTEM_CONTEXT SystemContext\r
148 )\r
149{\r
150#if defined (MDE_CPU_IA32)\r
151 DEBUG ((\r
152 EFI_D_ERROR,\r
153 "!!!! IA32 Exception Type - %08x !!!!\n",\r
154 InterruptType\r
155 ));\r
430fbbe0 156 if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {\r
a47463f2 157 DEBUG ((\r
158 EFI_D_ERROR,\r
159 "ExceptionData - %08x\n",\r
160 SystemContext.SystemContextIa32->ExceptionData\r
161 ));\r
162 }\r
163 DEBUG ((\r
164 EFI_D_ERROR,\r
165 "CS - %04x, EIP - %08x, EFL - %08x, SS - %04x\n",\r
166 SystemContext.SystemContextIa32->Cs,\r
167 SystemContext.SystemContextIa32->Eip,\r
168 SystemContext.SystemContextIa32->Eflags,\r
169 SystemContext.SystemContextIa32->Ss\r
170 ));\r
171 DEBUG ((\r
172 EFI_D_ERROR,\r
173 "DS - %04x, ES - %04x, FS - %04x, GS - %04x\n",\r
174 SystemContext.SystemContextIa32->Ds,\r
175 SystemContext.SystemContextIa32->Es,\r
176 SystemContext.SystemContextIa32->Fs,\r
177 SystemContext.SystemContextIa32->Gs\r
178 ));\r
179 DEBUG ((\r
180 EFI_D_ERROR,\r
181 "EAX - %08x, EBX - %08x, ECX - %08x, EDX - %08x\n",\r
182 SystemContext.SystemContextIa32->Eax,\r
183 SystemContext.SystemContextIa32->Ebx,\r
184 SystemContext.SystemContextIa32->Ecx,\r
185 SystemContext.SystemContextIa32->Edx\r
186 ));\r
187 DEBUG ((\r
188 EFI_D_ERROR,\r
189 "ESP - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",\r
190 SystemContext.SystemContextIa32->Esp,\r
191 SystemContext.SystemContextIa32->Ebp,\r
192 SystemContext.SystemContextIa32->Esi,\r
193 SystemContext.SystemContextIa32->Edi\r
194 ));\r
195 DEBUG ((\r
196 EFI_D_ERROR,\r
197 "GDT - %08x LIM - %04x, IDT - %08x LIM - %04x\n",\r
198 SystemContext.SystemContextIa32->Gdtr[0],\r
199 SystemContext.SystemContextIa32->Gdtr[1],\r
200 SystemContext.SystemContextIa32->Idtr[0],\r
201 SystemContext.SystemContextIa32->Idtr[1]\r
202 ));\r
203 DEBUG ((\r
204 EFI_D_ERROR,\r
205 "LDT - %08x, TR - %08x\n",\r
206 SystemContext.SystemContextIa32->Ldtr,\r
207 SystemContext.SystemContextIa32->Tr\r
208 ));\r
209 DEBUG ((\r
210 EFI_D_ERROR,\r
211 "CR0 - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",\r
212 SystemContext.SystemContextIa32->Cr0,\r
213 SystemContext.SystemContextIa32->Cr2,\r
214 SystemContext.SystemContextIa32->Cr3,\r
215 SystemContext.SystemContextIa32->Cr4\r
216 ));\r
217 DEBUG ((\r
218 EFI_D_ERROR,\r
219 "DR0 - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",\r
220 SystemContext.SystemContextIa32->Dr0,\r
221 SystemContext.SystemContextIa32->Dr1,\r
222 SystemContext.SystemContextIa32->Dr2,\r
223 SystemContext.SystemContextIa32->Dr3\r
224 ));\r
225 DEBUG ((\r
226 EFI_D_ERROR,\r
227 "DR6 - %08x, DR7 - %08x\n",\r
228 SystemContext.SystemContextIa32->Dr6,\r
229 SystemContext.SystemContextIa32->Dr7\r
230 ));\r
231#elif defined (MDE_CPU_X64)\r
232 DEBUG ((\r
233 EFI_D_ERROR,\r
234 "!!!! X64 Exception Type - %016lx !!!!\n",\r
235 (UINT64)InterruptType\r
236 ));\r
430fbbe0 237 if ((mErrorCodeFlag & (1 << InterruptType)) != 0) {\r
a47463f2 238 DEBUG ((\r
239 EFI_D_ERROR,\r
240 "ExceptionData - %016lx\n",\r
241 SystemContext.SystemContextX64->ExceptionData\r
242 ));\r
243 }\r
244 DEBUG ((\r
245 EFI_D_ERROR,\r
246 "RIP - %016lx, RFL - %016lx\n",\r
247 SystemContext.SystemContextX64->Rip,\r
248 SystemContext.SystemContextX64->Rflags\r
249 ));\r
250 DEBUG ((\r
251 EFI_D_ERROR,\r
252 "RAX - %016lx, RCX - %016lx, RDX - %016lx\n",\r
253 SystemContext.SystemContextX64->Rax,\r
254 SystemContext.SystemContextX64->Rcx,\r
255 SystemContext.SystemContextX64->Rdx\r
256 ));\r
257 DEBUG ((\r
258 EFI_D_ERROR,\r
259 "RBX - %016lx, RSP - %016lx, RBP - %016lx\n",\r
260 SystemContext.SystemContextX64->Rbx,\r
261 SystemContext.SystemContextX64->Rsp,\r
262 SystemContext.SystemContextX64->Rbp\r
263 ));\r
264 DEBUG ((\r
265 EFI_D_ERROR,\r
266 "RSI - %016lx, RDI - %016lx\n",\r
267 SystemContext.SystemContextX64->Rsi,\r
268 SystemContext.SystemContextX64->Rdi\r
269 ));\r
270 DEBUG ((\r
271 EFI_D_ERROR,\r
272 "R8 - %016lx, R9 - %016lx, R10 - %016lx\n",\r
273 SystemContext.SystemContextX64->R8,\r
274 SystemContext.SystemContextX64->R9,\r
275 SystemContext.SystemContextX64->R10\r
276 ));\r
277 DEBUG ((\r
278 EFI_D_ERROR,\r
279 "R11 - %016lx, R12 - %016lx, R13 - %016lx\n",\r
280 SystemContext.SystemContextX64->R11,\r
281 SystemContext.SystemContextX64->R12,\r
282 SystemContext.SystemContextX64->R13\r
283 ));\r
284 DEBUG ((\r
285 EFI_D_ERROR,\r
286 "R14 - %016lx, R15 - %016lx\n",\r
287 SystemContext.SystemContextX64->R14,\r
288 SystemContext.SystemContextX64->R15\r
289 ));\r
290 DEBUG ((\r
291 EFI_D_ERROR,\r
292 "CS - %04lx, DS - %04lx, ES - %04lx, FS - %04lx, GS - %04lx, SS - %04lx\n",\r
293 SystemContext.SystemContextX64->Cs,\r
294 SystemContext.SystemContextX64->Ds,\r
295 SystemContext.SystemContextX64->Es,\r
296 SystemContext.SystemContextX64->Fs,\r
297 SystemContext.SystemContextX64->Gs,\r
298 SystemContext.SystemContextX64->Ss\r
299 ));\r
300 DEBUG ((\r
301 EFI_D_ERROR,\r
302 "GDT - %016lx; %04lx, IDT - %016lx; %04lx\n",\r
303 SystemContext.SystemContextX64->Gdtr[0],\r
304 SystemContext.SystemContextX64->Gdtr[1],\r
305 SystemContext.SystemContextX64->Idtr[0],\r
306 SystemContext.SystemContextX64->Idtr[1]\r
307 ));\r
308 DEBUG ((\r
309 EFI_D_ERROR,\r
310 "LDT - %016lx, TR - %016lx\n",\r
311 SystemContext.SystemContextX64->Ldtr,\r
312 SystemContext.SystemContextX64->Tr\r
313 ));\r
314 DEBUG ((\r
315 EFI_D_ERROR,\r
316 "CR0 - %016lx, CR2 - %016lx, CR3 - %016lx\n",\r
317 SystemContext.SystemContextX64->Cr0,\r
318 SystemContext.SystemContextX64->Cr2,\r
319 SystemContext.SystemContextX64->Cr3\r
320 ));\r
321 DEBUG ((\r
322 EFI_D_ERROR,\r
323 "CR4 - %016lx, CR8 - %016lx\n",\r
324 SystemContext.SystemContextX64->Cr4,\r
325 SystemContext.SystemContextX64->Cr8\r
326 ));\r
327 DEBUG ((\r
328 EFI_D_ERROR,\r
329 "DR0 - %016lx, DR1 - %016lx, DR2 - %016lx\n",\r
330 SystemContext.SystemContextX64->Dr0,\r
331 SystemContext.SystemContextX64->Dr1,\r
332 SystemContext.SystemContextX64->Dr2\r
333 ));\r
334 DEBUG ((\r
335 EFI_D_ERROR,\r
336 "DR3 - %016lx, DR6 - %016lx, DR7 - %016lx\n",\r
337 SystemContext.SystemContextX64->Dr3,\r
338 SystemContext.SystemContextX64->Dr6,\r
339 SystemContext.SystemContextX64->Dr7\r
340 ));\r
341#else\r
342#error CPU type not supported for exception information dump!\r
343#endif\r
344\r
345 //\r
346 // Hang the system with CpuSleep so the processor will enter a lower power\r
347 // state.\r
348 //\r
349 while (TRUE) {\r
350 CpuSleep ();\r
351 };\r
352}\r
353\r
354\r
355/**\r
356 Flush CPU data cache. If the instruction cache is fully coherent\r
357 with all DMA operations then function can just return EFI_SUCCESS.\r
358\r
359 @param This Protocol instance structure\r
360 @param Start Physical address to start flushing from.\r
361 @param Length Number of bytes to flush. Round up to chipset\r
362 granularity.\r
363 @param FlushType Specifies the type of flush operation to perform.\r
364\r
365 @retval EFI_SUCCESS If cache was flushed\r
366 @retval EFI_UNSUPPORTED If flush type is not supported.\r
367 @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r
368\r
369**/\r
370EFI_STATUS\r
371EFIAPI\r
372CpuFlushCpuDataCache (\r
373 IN EFI_CPU_ARCH_PROTOCOL *This,\r
374 IN EFI_PHYSICAL_ADDRESS Start,\r
375 IN UINT64 Length,\r
376 IN EFI_CPU_FLUSH_TYPE FlushType\r
377 )\r
378{\r
379 if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r
380 AsmWbinvd ();\r
381 return EFI_SUCCESS;\r
382 } else if (FlushType == EfiCpuFlushTypeInvalidate) {\r
383 AsmInvd ();\r
384 return EFI_SUCCESS;\r
385 } else {\r
386 return EFI_UNSUPPORTED;\r
387 }\r
388}\r
389\r
390\r
391/**\r
392 Enables CPU interrupts.\r
393\r
394 @param This Protocol instance structure\r
395\r
396 @retval EFI_SUCCESS If interrupts were enabled in the CPU\r
397 @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r
398\r
399**/\r
400EFI_STATUS\r
401EFIAPI\r
402CpuEnableInterrupt (\r
403 IN EFI_CPU_ARCH_PROTOCOL *This\r
404 )\r
405{\r
406 EnableInterrupts ();\r
407\r
408 InterruptState = TRUE;\r
409 return EFI_SUCCESS;\r
410}\r
411\r
412\r
413/**\r
414 Disables CPU interrupts.\r
415\r
416 @param This Protocol instance structure\r
417\r
418 @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
419 @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r
420\r
421**/\r
422EFI_STATUS\r
423EFIAPI\r
424CpuDisableInterrupt (\r
425 IN EFI_CPU_ARCH_PROTOCOL *This\r
426 )\r
427{\r
428 DisableInterrupts ();\r
429\r
430 InterruptState = FALSE;\r
431 return EFI_SUCCESS;\r
432}\r
433\r
434\r
435/**\r
436 Return the state of interrupts.\r
437\r
438 @param This Protocol instance structure\r
439 @param State Pointer to the CPU's current interrupt state\r
440\r
441 @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r
442 @retval EFI_INVALID_PARAMETER State is NULL.\r
443\r
444**/\r
445EFI_STATUS\r
446EFIAPI\r
447CpuGetInterruptState (\r
448 IN EFI_CPU_ARCH_PROTOCOL *This,\r
449 OUT BOOLEAN *State\r
450 )\r
451{\r
452 if (State == NULL) {\r
453 return EFI_INVALID_PARAMETER;\r
454 }\r
455\r
456 *State = InterruptState;\r
457 return EFI_SUCCESS;\r
458}\r
459\r
460\r
461/**\r
462 Generates an INIT to the CPU.\r
463\r
464 @param This Protocol instance structure\r
465 @param InitType Type of CPU INIT to perform\r
466\r
467 @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r
468 seen.\r
469 @retval EFI_DEVICE_ERROR If CPU INIT failed.\r
470 @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r
471\r
472**/\r
473EFI_STATUS\r
474EFIAPI\r
475CpuInit (\r
476 IN EFI_CPU_ARCH_PROTOCOL *This,\r
477 IN EFI_CPU_INIT_TYPE InitType\r
478 )\r
479{\r
480 return EFI_UNSUPPORTED;\r
481}\r
482\r
483\r
484/**\r
485 Registers a function to be called from the CPU interrupt handler.\r
486\r
487 @param This Protocol instance structure\r
488 @param InterruptType Defines which interrupt to hook. IA-32\r
489 valid range is 0x00 through 0xFF\r
490 @param InterruptHandler A pointer to a function of type\r
491 EFI_CPU_INTERRUPT_HANDLER that is called\r
492 when a processor interrupt occurs. A null\r
493 pointer is an error condition.\r
494\r
495 @retval EFI_SUCCESS If handler installed or uninstalled.\r
496 @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r
497 for InterruptType was previously installed.\r
498 @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r
499 InterruptType was not previously installed.\r
500 @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r
501 is not supported.\r
502\r
503**/\r
504EFI_STATUS\r
505EFIAPI\r
506CpuRegisterInterruptHandler (\r
507 IN EFI_CPU_ARCH_PROTOCOL *This,\r
508 IN EFI_EXCEPTION_TYPE InterruptType,\r
509 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
510 )\r
511{\r
512 if (InterruptType < 0 || InterruptType > 0xff) {\r
513 return EFI_UNSUPPORTED;\r
514 }\r
515\r
516 if (InterruptHandler == NULL && ExternalVectorTable[InterruptType] == NULL) {\r
517 return EFI_INVALID_PARAMETER;\r
518 }\r
519\r
520 if (InterruptHandler != NULL && ExternalVectorTable[InterruptType] != NULL) {\r
521 return EFI_ALREADY_STARTED;\r
522 }\r
523\r
c52acd89 524 SetInterruptDescriptorTableHandlerAddress ((UINTN)InterruptType, NULL);\r
a47463f2 525 ExternalVectorTable[InterruptType] = InterruptHandler;\r
526 return EFI_SUCCESS;\r
527}\r
528\r
529\r
530/**\r
531 Returns a timer value from one of the CPU's internal timers. There is no\r
532 inherent time interval between ticks but is a function of the CPU frequency.\r
533\r
534 @param This - Protocol instance structure.\r
535 @param TimerIndex - Specifies which CPU timer is requested.\r
536 @param TimerValue - Pointer to the returned timer value.\r
537 @param TimerPeriod - A pointer to the amount of time that passes\r
538 in femtoseconds (10-15) for each increment\r
539 of TimerValue. If TimerValue does not\r
540 increment at a predictable rate, then 0 is\r
541 returned. The amount of time that has\r
542 passed between two calls to GetTimerValue()\r
543 can be calculated with the formula\r
544 (TimerValue2 - TimerValue1) * TimerPeriod.\r
545 This parameter is optional and may be NULL.\r
546\r
547 @retval EFI_SUCCESS - If the CPU timer count was returned.\r
548 @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r
549 @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r
550 @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r
551\r
552**/\r
553EFI_STATUS\r
554EFIAPI\r
555CpuGetTimerValue (\r
556 IN EFI_CPU_ARCH_PROTOCOL *This,\r
557 IN UINT32 TimerIndex,\r
558 OUT UINT64 *TimerValue,\r
559 OUT UINT64 *TimerPeriod OPTIONAL\r
560 )\r
561{\r
562 if (TimerValue == NULL) {\r
563 return EFI_INVALID_PARAMETER;\r
564 }\r
565\r
566 if (TimerIndex != 0) {\r
567 return EFI_INVALID_PARAMETER;\r
568 }\r
569\r
570 *TimerValue = AsmReadTsc ();\r
571\r
572 if (TimerPeriod != NULL) {\r
573 //\r
574 // BugBug: Hard coded. Don't know how to do this generically\r
575 //\r
576 *TimerPeriod = 1000000000;\r
577 }\r
578\r
579 return EFI_SUCCESS;\r
580}\r
581\r
582\r
583/**\r
584 Set memory cacheability attributes for given range of memeory.\r
585\r
586 @param This Protocol instance structure\r
587 @param BaseAddress Specifies the start address of the\r
588 memory range\r
589 @param Length Specifies the length of the memory range\r
590 @param Attributes The memory cacheability for the memory range\r
591\r
592 @retval EFI_SUCCESS If the cacheability of that memory range is\r
593 set successfully\r
594 @retval EFI_UNSUPPORTED If the desired operation cannot be done\r
595 @retval EFI_INVALID_PARAMETER The input parameter is not correct,\r
596 such as Length = 0\r
597\r
598**/\r
599EFI_STATUS\r
600EFIAPI\r
601CpuSetMemoryAttributes (\r
602 IN EFI_CPU_ARCH_PROTOCOL *This,\r
603 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
604 IN UINT64 Length,\r
605 IN UINT64 Attributes\r
606 )\r
607{\r
608 RETURN_STATUS Status;\r
609 MTRR_MEMORY_CACHE_TYPE CacheType;\r
610\r
947a573a 611 if (!IsMtrrSupported ()) {\r
612 return EFI_UNSUPPORTED;\r
613 }\r
614\r
a47463f2 615 //\r
616 // If this function is called because GCD SetMemorySpaceAttributes () is called\r
617 // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory\r
618 // map with MTRR values. So there is no need to modify MTRRs, just return immediately\r
619 // to avoid unnecessary computing.\r
620 //\r
621 if (mIsFlushingGCD) {\r
622 DEBUG((EFI_D_ERROR, " Flushing GCD\n"));\r
623 return EFI_SUCCESS;\r
624 }\r
625\r
626 switch (Attributes) {\r
627 case EFI_MEMORY_UC:\r
628 CacheType = CacheUncacheable;\r
629 break;\r
630\r
631 case EFI_MEMORY_WC:\r
632 CacheType = CacheWriteCombining;\r
633 break;\r
634\r
635 case EFI_MEMORY_WT:\r
636 CacheType = CacheWriteThrough;\r
637 break;\r
638\r
639 case EFI_MEMORY_WP:\r
640 CacheType = CacheWriteProtected;\r
641 break;\r
642\r
643 case EFI_MEMORY_WB:\r
644 CacheType = CacheWriteBack;\r
645 break;\r
646\r
647 default:\r
648 return EFI_UNSUPPORTED;\r
649 }\r
650 //\r
651 // call MTRR libary function\r
652 //\r
f877f300 653 Status = MtrrSetMemoryAttribute (\r
a47463f2 654 BaseAddress,\r
655 Length,\r
656 CacheType\r
657 );\r
658\r
a47463f2 659 return (EFI_STATUS) Status;\r
660}\r
661\r
662/**\r
663 Initializes the valid bits mask and valid address mask for MTRRs.\r
664\r
665 This function initializes the valid bits mask and valid address mask for MTRRs.\r
666\r
667**/\r
668VOID\r
669InitializeMtrrMask (\r
670 VOID\r
671 )\r
672{\r
673 UINT32 RegEax;\r
674 UINT8 PhysicalAddressBits;\r
675\r
676 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
677\r
678 if (RegEax >= 0x80000008) {\r
679 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
680\r
681 PhysicalAddressBits = (UINT8) RegEax;\r
682\r
683 mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r
684 mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r
685 } else {\r
686 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;\r
687 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;\r
688 }\r
689}\r
690\r
691/**\r
430fbbe0 692 Gets GCD Mem Space type from MTRR Type.\r
a47463f2 693\r
430fbbe0 694 This function gets GCD Mem Space type from MTRR Type.\r
a47463f2 695\r
430fbbe0 696 @param MtrrAttributes MTRR memory type\r
a47463f2 697\r
698 @return GCD Mem Space type\r
699\r
700**/\r
701UINT64\r
702GetMemorySpaceAttributeFromMtrrType (\r
703 IN UINT8 MtrrAttributes\r
704 )\r
705{\r
706 switch (MtrrAttributes) {\r
707 case MTRR_CACHE_UNCACHEABLE:\r
708 return EFI_MEMORY_UC;\r
709 case MTRR_CACHE_WRITE_COMBINING:\r
710 return EFI_MEMORY_WC;\r
711 case MTRR_CACHE_WRITE_THROUGH:\r
712 return EFI_MEMORY_WT;\r
713 case MTRR_CACHE_WRITE_PROTECTED:\r
714 return EFI_MEMORY_WP;\r
715 case MTRR_CACHE_WRITE_BACK:\r
716 return EFI_MEMORY_WB;\r
717 default:\r
718 return 0;\r
719 }\r
720}\r
721\r
722/**\r
723 Searches memory descriptors covered by given memory range.\r
724\r
725 This function searches into the Gcd Memory Space for descriptors\r
726 (from StartIndex to EndIndex) that contains the memory range\r
727 specified by BaseAddress and Length.\r
728\r
729 @param MemorySpaceMap Gcd Memory Space Map as array.\r
730 @param NumberOfDescriptors Number of descriptors in map.\r
731 @param BaseAddress BaseAddress for the requested range.\r
732 @param Length Length for the requested range.\r
733 @param StartIndex Start index into the Gcd Memory Space Map.\r
734 @param EndIndex End index into the Gcd Memory Space Map.\r
735\r
736 @retval EFI_SUCCESS Search successfully.\r
737 @retval EFI_NOT_FOUND The requested descriptors does not exist.\r
738\r
739**/\r
740EFI_STATUS\r
741SearchGcdMemorySpaces (\r
742 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
743 IN UINTN NumberOfDescriptors,\r
744 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
745 IN UINT64 Length,\r
746 OUT UINTN *StartIndex,\r
747 OUT UINTN *EndIndex\r
748 )\r
749{\r
750 UINTN Index;\r
751\r
752 *StartIndex = 0;\r
753 *EndIndex = 0;\r
754 for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
755 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r
756 BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
757 *StartIndex = Index;\r
758 }\r
759 if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r
760 BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
761 *EndIndex = Index;\r
762 return EFI_SUCCESS;\r
763 }\r
764 }\r
765 return EFI_NOT_FOUND;\r
766}\r
767\r
768/**\r
769 Sets the attributes for a specified range in Gcd Memory Space Map.\r
770\r
771 This function sets the attributes for a specified range in\r
772 Gcd Memory Space Map.\r
773\r
774 @param MemorySpaceMap Gcd Memory Space Map as array\r
775 @param NumberOfDescriptors Number of descriptors in map\r
776 @param BaseAddress BaseAddress for the range\r
777 @param Length Length for the range\r
778 @param Attributes Attributes to set\r
779\r
780 @retval EFI_SUCCESS Memory attributes set successfully\r
781 @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r
782\r
783**/\r
784EFI_STATUS\r
785SetGcdMemorySpaceAttributes (\r
786 IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r
787 IN UINTN NumberOfDescriptors,\r
788 IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
789 IN UINT64 Length,\r
790 IN UINT64 Attributes\r
791 )\r
792{\r
793 EFI_STATUS Status;\r
794 UINTN Index;\r
795 UINTN StartIndex;\r
796 UINTN EndIndex;\r
797 EFI_PHYSICAL_ADDRESS RegionStart;\r
798 UINT64 RegionLength;\r
799\r
800 //\r
801 // Get all memory descriptors covered by the memory range\r
802 //\r
803 Status = SearchGcdMemorySpaces (\r
804 MemorySpaceMap,\r
805 NumberOfDescriptors,\r
806 BaseAddress,\r
807 Length,\r
808 &StartIndex,\r
809 &EndIndex\r
810 );\r
811 if (EFI_ERROR (Status)) {\r
812 return Status;\r
813 }\r
814\r
815 //\r
816 // Go through all related descriptors and set attributes accordingly\r
817 //\r
818 for (Index = StartIndex; Index <= EndIndex; Index++) {\r
819 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
820 continue;\r
821 }\r
822 //\r
823 // Calculate the start and end address of the overlapping range\r
824 //\r
825 if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r
826 RegionStart = BaseAddress;\r
827 } else {\r
828 RegionStart = MemorySpaceMap[Index].BaseAddress;\r
829 }\r
830 if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
831 RegionLength = BaseAddress + Length - RegionStart;\r
832 } else {\r
833 RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
834 }\r
835 //\r
836 // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
837 //\r
838 gDS->SetMemorySpaceAttributes (\r
839 RegionStart,\r
840 RegionLength,\r
841 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r
842 );\r
843 }\r
844\r
845 return EFI_SUCCESS;\r
846}\r
847\r
848\r
849/**\r
850 Refreshes the GCD Memory Space attributes according to MTRRs.\r
851\r
852 This function refreshes the GCD Memory Space attributes according to MTRRs.\r
853\r
854**/\r
855VOID\r
856RefreshGcdMemoryAttributes (\r
857 VOID\r
858 )\r
859{\r
860 EFI_STATUS Status;\r
861 UINTN Index;\r
862 UINTN SubIndex;\r
863 UINT64 RegValue;\r
864 EFI_PHYSICAL_ADDRESS BaseAddress;\r
865 UINT64 Length;\r
866 UINT64 Attributes;\r
867 UINT64 CurrentAttributes;\r
868 UINT8 MtrrType;\r
869 UINTN NumberOfDescriptors;\r
870 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
871 UINT64 DefaultAttributes;\r
6640eb36 872 VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
a47463f2 873 MTRR_FIXED_SETTINGS MtrrFixedSettings;\r
3b9be416 874 UINT32 FirmwareVariableMtrrCount;\r
3b9be416 875\r
947a573a 876 if (!IsMtrrSupported ()) {\r
877 return;\r
878 }\r
879\r
3b9be416 880 FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r
5bdfa4e5 881 ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
a47463f2 882\r
883// mIsFlushingGCD = TRUE;\r
884 mIsFlushingGCD = FALSE;\r
885 MemorySpaceMap = NULL;\r
886\r
887 //\r
888 // Initialize the valid bits mask and valid address mask for MTRRs\r
889 //\r
890 InitializeMtrrMask ();\r
891\r
892 //\r
893 // Get the memory attribute of variable MTRRs\r
894 //\r
895 MtrrGetMemoryAttributeInVariableMtrr (\r
896 mValidMtrrBitsMask,\r
897 mValidMtrrAddressMask,\r
898 VariableMtrr\r
899 );\r
900\r
901 //\r
902 // Get the memory space map from GCD\r
903 //\r
904 Status = gDS->GetMemorySpaceMap (\r
905 &NumberOfDescriptors,\r
906 &MemorySpaceMap\r
907 );\r
908 ASSERT_EFI_ERROR (Status);\r
909\r
910 DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (mDefaultMemoryType);\r
911\r
912 //\r
913 // Set default attributes to all spaces.\r
914 //\r
915 for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
916 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
917 continue;\r
918 }\r
919 gDS->SetMemorySpaceAttributes (\r
920 MemorySpaceMap[Index].BaseAddress,\r
921 MemorySpaceMap[Index].Length,\r
922 (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |\r
923 (MemorySpaceMap[Index].Capabilities & DefaultAttributes)\r
924 );\r
925 }\r
926\r
927 //\r
928 // Go for variable MTRRs with WB attribute\r
929 //\r
3b9be416 930 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
a47463f2 931 if (VariableMtrr[Index].Valid &&\r
932 VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {\r
933 SetGcdMemorySpaceAttributes (\r
934 MemorySpaceMap,\r
935 NumberOfDescriptors,\r
936 VariableMtrr[Index].BaseAddress,\r
937 VariableMtrr[Index].Length,\r
938 EFI_MEMORY_WB\r
939 );\r
940 }\r
941 }\r
942 //\r
943 // Go for variable MTRRs with Non-WB attribute\r
944 //\r
3b9be416 945 for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
a47463f2 946 if (VariableMtrr[Index].Valid &&\r
947 VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) {\r
948 Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);\r
949 SetGcdMemorySpaceAttributes (\r
950 MemorySpaceMap,\r
951 NumberOfDescriptors,\r
952 VariableMtrr[Index].BaseAddress,\r
953 VariableMtrr[Index].Length,\r
954 Attributes\r
955 );\r
956 }\r
957 }\r
958\r
959 //\r
960 // Go for fixed MTRRs\r
961 //\r
962 Attributes = 0;\r
963 BaseAddress = 0;\r
964 Length = 0;\r
965 MtrrGetFixedMtrr (&MtrrFixedSettings);\r
966 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
967 RegValue = MtrrFixedSettings.Mtrr[Index];\r
968 //\r
969 // Check for continuous fixed MTRR sections\r
970 //\r
971 for (SubIndex = 0; SubIndex < 8; SubIndex++) {\r
972 MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);\r
973 CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);\r
974 if (Length == 0) {\r
975 //\r
976 // A new MTRR attribute begins\r
977 //\r
978 Attributes = CurrentAttributes;\r
979 } else {\r
980 //\r
981 // If fixed MTRR attribute changed, then set memory attribute for previous atrribute\r
982 //\r
983 if (CurrentAttributes != Attributes) {\r
984 SetGcdMemorySpaceAttributes (\r
985 MemorySpaceMap,\r
986 NumberOfDescriptors,\r
987 BaseAddress,\r
988 Length,\r
989 Attributes\r
990 );\r
991 BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;\r
992 Length = 0;\r
993 Attributes = CurrentAttributes;\r
994 }\r
995 }\r
996 Length += mFixedMtrrTable[Index].Length;\r
997 }\r
998 }\r
999 //\r
1000 // Handle the last fixed MTRR region\r
1001 //\r
1002 SetGcdMemorySpaceAttributes (\r
1003 MemorySpaceMap,\r
1004 NumberOfDescriptors,\r
1005 BaseAddress,\r
1006 Length,\r
1007 Attributes\r
1008 );\r
1009\r
1010 //\r
1011 // Free memory space map allocated by GCD service GetMemorySpaceMap ()\r
1012 //\r
1013 if (MemorySpaceMap != NULL) {\r
1014 FreePool (MemorySpaceMap);\r
1015 }\r
1016\r
1017 mIsFlushingGCD = FALSE;\r
1018}\r
1019\r
1e51d595
ED
1020/**\r
1021 Set Interrupt Descriptor Table Handler Address.\r
1022\r
1023 @param Index The Index of the interrupt descriptor table handle.\r
1024 @param Handler Handler address.\r
a47463f2 1025\r
1e51d595 1026**/\r
557b970a 1027VOID\r
1028SetInterruptDescriptorTableHandlerAddress (\r
1029 IN UINTN Index,\r
1030 IN VOID *Handler OPTIONAL\r
1031 )\r
1032{\r
1033 UINTN UintnHandler;\r
1034\r
1035 if (Handler != NULL) {\r
1036 UintnHandler = (UINTN) Handler;\r
1037 } else {\r
1038 UintnHandler = ((UINTN) AsmIdtVector00) + (8 * Index);\r
1039 }\r
1040\r
1041 gIdtTable[Index].Bits.OffsetLow = (UINT16)UintnHandler;\r
1042 gIdtTable[Index].Bits.Reserved_0 = 0;\r
1043 gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
1044 gIdtTable[Index].Bits.OffsetHigh = (UINT16)(UintnHandler >> 16);\r
1045#if defined (MDE_CPU_X64)\r
1046 gIdtTable[Index].Bits.OffsetUpper = (UINT32)(UintnHandler >> 32);\r
1047 gIdtTable[Index].Bits.Reserved_1 = 0;\r
1048#endif\r
1049}\r
1050\r
1051\r
a47463f2 1052/**\r
1053 Initialize Interrupt Descriptor Table for interrupt handling.\r
1054\r
1055**/\r
a47463f2 1056VOID\r
1057InitInterruptDescriptorTable (\r
1058 VOID\r
1059 )\r
1060{\r
557b970a 1061 EFI_STATUS Status;\r
1062 IA32_DESCRIPTOR OldIdtPtr;\r
1063 IA32_IDT_GATE_DESCRIPTOR *OldIdt;\r
1064 UINTN OldIdtSize;\r
1065 VOID *IdtPtrAlignmentBuffer;\r
1066 IA32_DESCRIPTOR *IdtPtr;\r
1067 UINTN Index;\r
1068 UINT16 CurrentCs;\r
1069 VOID *IntHandler;\r
a47463f2 1070\r
1071 SetMem (ExternalVectorTable, sizeof(ExternalVectorTable), 0);\r
1072\r
1073 //\r
557b970a 1074 // Get original IDT address and size.\r
a47463f2 1075 //\r
557b970a 1076 AsmReadIdtr ((IA32_DESCRIPTOR *) &OldIdtPtr);\r
1077\r
1078 if ((OldIdtPtr.Base != 0) && ((OldIdtPtr.Limit & 7) == 7)) {\r
1079 OldIdt = (IA32_IDT_GATE_DESCRIPTOR*) OldIdtPtr.Base;\r
304a39b7 1080 OldIdtSize = (OldIdtPtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);\r
557b970a 1081 } else {\r
1082 OldIdt = NULL;\r
1083 OldIdtSize = 0;\r
a47463f2 1084 }\r
1085\r
0564ae5e 1086 //\r
557b970a 1087 // Intialize IDT\r
0564ae5e 1088 //\r
557b970a 1089 CurrentCs = AsmReadCs();\r
1090 for (Index = 0; Index < INTERRUPT_VECTOR_NUMBER; Index ++) {\r
1091 //\r
1092 // If the old IDT had a handler for this interrupt, then\r
1093 // preserve it.\r
1094 //\r
1095 if (Index < OldIdtSize) {\r
1096 IntHandler = \r
1097 (VOID*) (\r
1098 OldIdt[Index].Bits.OffsetLow +\r
1099 (OldIdt[Index].Bits.OffsetHigh << 16)\r
1100#if defined (MDE_CPU_X64)\r
1101 + (((UINTN) OldIdt[Index].Bits.OffsetUpper) << 32)\r
1102#endif\r
1103 );\r
1104 } else {\r
1105 IntHandler = NULL;\r
1106 }\r
0564ae5e 1107\r
557b970a 1108 gIdtTable[Index].Bits.Selector = CurrentCs;\r
1109 gIdtTable[Index].Bits.Reserved_0 = 0;\r
1110 gIdtTable[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
1111 SetInterruptDescriptorTableHandlerAddress (Index, IntHandler);\r
0564ae5e 1112 }\r
557b970a 1113\r
a47463f2 1114 //\r
1115 // Load IDT Pointer\r
1116 //\r
1117 IdtPtrAlignmentBuffer = AllocatePool (sizeof (*IdtPtr) + 16);\r
1118 IdtPtr = ALIGN_POINTER (IdtPtrAlignmentBuffer, 16);\r
1119 IdtPtr->Base = (UINT32)(((UINTN)(VOID*) gIdtTable) & (BASE_4GB-1));\r
5b7e61a0 1120 IdtPtr->Limit = (UINT16) (sizeof (gIdtTable) - 1);\r
ea99e00d 1121\r
a47463f2 1122 AsmWriteIdtr (IdtPtr);\r
ea99e00d 1123\r
a47463f2 1124 FreePool (IdtPtrAlignmentBuffer);\r
1125\r
1126 //\r
1127 // Initialize Exception Handlers\r
1128 //\r
1129 for (Index = 0; Index < 32; Index++) {\r
1130 Status = CpuRegisterInterruptHandler (&gCpu, Index, CommonExceptionHandler);\r
1131 ASSERT_EFI_ERROR (Status);\r
1132 }\r
1133\r
1134 //\r
1135 // Set the pointer to the array of C based exception handling routines.\r
1136 //\r
1137 InitializeExternalVectorTablePtr (ExternalVectorTable);\r
1138\r
1139}\r
1140\r
1141\r
1142/**\r
1143 Initialize the state information for the CPU Architectural Protocol.\r
1144\r
1145 @param ImageHandle Image handle this driver.\r
1146 @param SystemTable Pointer to the System Table.\r
1147\r
1148 @retval EFI_SUCCESS Thread can be successfully created\r
1149 @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
1150 @retval EFI_DEVICE_ERROR Cannot create the thread\r
1151\r
1152**/\r
1153EFI_STATUS\r
1154EFIAPI\r
1155InitializeCpu (\r
1156 IN EFI_HANDLE ImageHandle,\r
1157 IN EFI_SYSTEM_TABLE *SystemTable\r
1158 )\r
1159{\r
1160 EFI_STATUS Status;\r
1161\r
1162 //\r
1163 // Make sure interrupts are disabled\r
1164 //\r
1165 DisableInterrupts ();\r
1166\r
1167 //\r
1168 // Init GDT for DXE\r
1169 //\r
1170 InitGlobalDescriptorTable ();\r
1171\r
1172 //\r
1173 // Setup IDT pointer, IDT and interrupt entry points\r
1174 //\r
1175 InitInterruptDescriptorTable ();\r
1176\r
1177 //\r
1178 // Install CPU Architectural Protocol\r
1179 //\r
1180 Status = gBS->InstallMultipleProtocolInterfaces (\r
1181 &mCpuHandle,\r
1182 &gEfiCpuArchProtocolGuid, &gCpu,\r
1183 NULL\r
1184 );\r
1185 ASSERT_EFI_ERROR (Status);\r
1186\r
1187 //\r
1188 // Refresh GCD memory space map according to MTRR value.\r
1189 //\r
1190 RefreshGcdMemoryAttributes ();\r
1191\r
1192 return Status;\r
1193}\r
1194\r